1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 25 #include "mt7530.h" 26 27 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) 28 { 29 return container_of(pcs, struct mt753x_pcs, pcs); 30 } 31 32 /* String, offset, and register size in bytes if different from 4 bytes */ 33 static const struct mt7530_mib_desc mt7530_mib[] = { 34 MIB_DESC(1, 0x00, "TxDrop"), 35 MIB_DESC(1, 0x04, "TxCrcErr"), 36 MIB_DESC(1, 0x08, "TxUnicast"), 37 MIB_DESC(1, 0x0c, "TxMulticast"), 38 MIB_DESC(1, 0x10, "TxBroadcast"), 39 MIB_DESC(1, 0x14, "TxCollision"), 40 MIB_DESC(1, 0x18, "TxSingleCollision"), 41 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 42 MIB_DESC(1, 0x20, "TxDeferred"), 43 MIB_DESC(1, 0x24, "TxLateCollision"), 44 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 45 MIB_DESC(1, 0x2c, "TxPause"), 46 MIB_DESC(1, 0x30, "TxPktSz64"), 47 MIB_DESC(1, 0x34, "TxPktSz65To127"), 48 MIB_DESC(1, 0x38, "TxPktSz128To255"), 49 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 50 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 51 MIB_DESC(1, 0x44, "Tx1024ToMax"), 52 MIB_DESC(2, 0x48, "TxBytes"), 53 MIB_DESC(1, 0x60, "RxDrop"), 54 MIB_DESC(1, 0x64, "RxFiltering"), 55 MIB_DESC(1, 0x68, "RxUnicast"), 56 MIB_DESC(1, 0x6c, "RxMulticast"), 57 MIB_DESC(1, 0x70, "RxBroadcast"), 58 MIB_DESC(1, 0x74, "RxAlignErr"), 59 MIB_DESC(1, 0x78, "RxCrcErr"), 60 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 61 MIB_DESC(1, 0x80, "RxFragErr"), 62 MIB_DESC(1, 0x84, "RxOverSzErr"), 63 MIB_DESC(1, 0x88, "RxJabberErr"), 64 MIB_DESC(1, 0x8c, "RxPause"), 65 MIB_DESC(1, 0x90, "RxPktSz64"), 66 MIB_DESC(1, 0x94, "RxPktSz65To127"), 67 MIB_DESC(1, 0x98, "RxPktSz128To255"), 68 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 69 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 70 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 71 MIB_DESC(2, 0xa8, "RxBytes"), 72 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 73 MIB_DESC(1, 0xb4, "RxIngressDrop"), 74 MIB_DESC(1, 0xb8, "RxArlDrop"), 75 }; 76 77 /* Since phy_device has not yet been created and 78 * phy_{read,write}_mmd_indirect is not available, we provide our own 79 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers 80 * to complete this function. 81 */ 82 static int 83 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 84 { 85 struct mii_bus *bus = priv->bus; 86 int value, ret; 87 88 /* Write the desired MMD Devad */ 89 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 90 if (ret < 0) 91 goto err; 92 93 /* Write the desired MMD register address */ 94 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 95 if (ret < 0) 96 goto err; 97 98 /* Select the Function : DATA with no post increment */ 99 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 100 if (ret < 0) 101 goto err; 102 103 /* Read the content of the MMD's selected register */ 104 value = bus->read(bus, 0, MII_MMD_DATA); 105 106 return value; 107 err: 108 dev_err(&bus->dev, "failed to read mmd register\n"); 109 110 return ret; 111 } 112 113 static int 114 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 115 int devad, u32 data) 116 { 117 struct mii_bus *bus = priv->bus; 118 int ret; 119 120 /* Write the desired MMD Devad */ 121 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 122 if (ret < 0) 123 goto err; 124 125 /* Write the desired MMD register address */ 126 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 127 if (ret < 0) 128 goto err; 129 130 /* Select the Function : DATA with no post increment */ 131 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 132 if (ret < 0) 133 goto err; 134 135 /* Write the data into MMD's selected register */ 136 ret = bus->write(bus, 0, MII_MMD_DATA, data); 137 err: 138 if (ret < 0) 139 dev_err(&bus->dev, 140 "failed to write mmd register\n"); 141 return ret; 142 } 143 144 static void 145 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 146 { 147 struct mii_bus *bus = priv->bus; 148 149 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 150 151 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 152 153 mutex_unlock(&bus->mdio_lock); 154 } 155 156 static void 157 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 158 { 159 struct mii_bus *bus = priv->bus; 160 u32 val; 161 162 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 163 164 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 165 val &= ~mask; 166 val |= set; 167 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 168 169 mutex_unlock(&bus->mdio_lock); 170 } 171 172 static void 173 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 174 { 175 core_rmw(priv, reg, 0, val); 176 } 177 178 static void 179 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 180 { 181 core_rmw(priv, reg, val, 0); 182 } 183 184 static int 185 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 186 { 187 struct mii_bus *bus = priv->bus; 188 u16 page, r, lo, hi; 189 int ret; 190 191 page = (reg >> 6) & 0x3ff; 192 r = (reg >> 2) & 0xf; 193 lo = val & 0xffff; 194 hi = val >> 16; 195 196 /* MT7530 uses 31 as the pseudo port */ 197 ret = bus->write(bus, 0x1f, 0x1f, page); 198 if (ret < 0) 199 goto err; 200 201 ret = bus->write(bus, 0x1f, r, lo); 202 if (ret < 0) 203 goto err; 204 205 ret = bus->write(bus, 0x1f, 0x10, hi); 206 err: 207 if (ret < 0) 208 dev_err(&bus->dev, 209 "failed to write mt7530 register\n"); 210 return ret; 211 } 212 213 static u32 214 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 215 { 216 struct mii_bus *bus = priv->bus; 217 u16 page, r, lo, hi; 218 int ret; 219 220 page = (reg >> 6) & 0x3ff; 221 r = (reg >> 2) & 0xf; 222 223 /* MT7530 uses 31 as the pseudo port */ 224 ret = bus->write(bus, 0x1f, 0x1f, page); 225 if (ret < 0) { 226 dev_err(&bus->dev, 227 "failed to read mt7530 register\n"); 228 return ret; 229 } 230 231 lo = bus->read(bus, 0x1f, r); 232 hi = bus->read(bus, 0x1f, 0x10); 233 234 return (hi << 16) | (lo & 0xffff); 235 } 236 237 static void 238 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 239 { 240 struct mii_bus *bus = priv->bus; 241 242 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 243 244 mt7530_mii_write(priv, reg, val); 245 246 mutex_unlock(&bus->mdio_lock); 247 } 248 249 static u32 250 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 251 { 252 return mt7530_mii_read(p->priv, p->reg); 253 } 254 255 static u32 256 _mt7530_read(struct mt7530_dummy_poll *p) 257 { 258 struct mii_bus *bus = p->priv->bus; 259 u32 val; 260 261 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 262 263 val = mt7530_mii_read(p->priv, p->reg); 264 265 mutex_unlock(&bus->mdio_lock); 266 267 return val; 268 } 269 270 static u32 271 mt7530_read(struct mt7530_priv *priv, u32 reg) 272 { 273 struct mt7530_dummy_poll p; 274 275 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 276 return _mt7530_read(&p); 277 } 278 279 static void 280 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 281 u32 mask, u32 set) 282 { 283 struct mii_bus *bus = priv->bus; 284 u32 val; 285 286 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 287 288 val = mt7530_mii_read(priv, reg); 289 val &= ~mask; 290 val |= set; 291 mt7530_mii_write(priv, reg, val); 292 293 mutex_unlock(&bus->mdio_lock); 294 } 295 296 static void 297 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 298 { 299 mt7530_rmw(priv, reg, 0, val); 300 } 301 302 static void 303 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 304 { 305 mt7530_rmw(priv, reg, val, 0); 306 } 307 308 static int 309 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 310 { 311 u32 val; 312 int ret; 313 struct mt7530_dummy_poll p; 314 315 /* Set the command operating upon the MAC address entries */ 316 val = ATC_BUSY | ATC_MAT(0) | cmd; 317 mt7530_write(priv, MT7530_ATC, val); 318 319 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 320 ret = readx_poll_timeout(_mt7530_read, &p, val, 321 !(val & ATC_BUSY), 20, 20000); 322 if (ret < 0) { 323 dev_err(priv->dev, "reset timeout\n"); 324 return ret; 325 } 326 327 /* Additional sanity for read command if the specified 328 * entry is invalid 329 */ 330 val = mt7530_read(priv, MT7530_ATC); 331 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 332 return -EINVAL; 333 334 if (rsp) 335 *rsp = val; 336 337 return 0; 338 } 339 340 static void 341 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 342 { 343 u32 reg[3]; 344 int i; 345 346 /* Read from ARL table into an array */ 347 for (i = 0; i < 3; i++) { 348 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 349 350 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 351 __func__, __LINE__, i, reg[i]); 352 } 353 354 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 355 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 356 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 357 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 358 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 359 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 360 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 361 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 362 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 363 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 364 } 365 366 static void 367 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 368 u8 port_mask, const u8 *mac, 369 u8 aging, u8 type) 370 { 371 u32 reg[3] = { 0 }; 372 int i; 373 374 reg[1] |= vid & CVID_MASK; 375 reg[1] |= ATA2_IVL; 376 reg[1] |= ATA2_FID(FID_BRIDGED); 377 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 378 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 379 /* STATIC_ENT indicate that entry is static wouldn't 380 * be aged out and STATIC_EMP specified as erasing an 381 * entry 382 */ 383 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 384 reg[1] |= mac[5] << MAC_BYTE_5; 385 reg[1] |= mac[4] << MAC_BYTE_4; 386 reg[0] |= mac[3] << MAC_BYTE_3; 387 reg[0] |= mac[2] << MAC_BYTE_2; 388 reg[0] |= mac[1] << MAC_BYTE_1; 389 reg[0] |= mac[0] << MAC_BYTE_0; 390 391 /* Write array into the ARL table */ 392 for (i = 0; i < 3; i++) 393 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 394 } 395 396 /* Setup TX circuit including relevant PAD and driving */ 397 static int 398 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 399 { 400 struct mt7530_priv *priv = ds->priv; 401 u32 ncpo1, ssc_delta, trgint, i, xtal; 402 403 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 404 405 if (xtal == HWTRAP_XTAL_20MHZ) { 406 dev_err(priv->dev, 407 "%s: MT7530 with a 20MHz XTAL is not supported!\n", 408 __func__); 409 return -EINVAL; 410 } 411 412 switch (interface) { 413 case PHY_INTERFACE_MODE_RGMII: 414 trgint = 0; 415 /* PLL frequency: 125MHz */ 416 ncpo1 = 0x0c80; 417 break; 418 case PHY_INTERFACE_MODE_TRGMII: 419 trgint = 1; 420 if (priv->id == ID_MT7621) { 421 /* PLL frequency: 150MHz: 1.2GBit */ 422 if (xtal == HWTRAP_XTAL_40MHZ) 423 ncpo1 = 0x0780; 424 if (xtal == HWTRAP_XTAL_25MHZ) 425 ncpo1 = 0x0a00; 426 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 427 if (xtal == HWTRAP_XTAL_40MHZ) 428 ncpo1 = 0x0c80; 429 if (xtal == HWTRAP_XTAL_25MHZ) 430 ncpo1 = 0x1400; 431 } 432 break; 433 default: 434 dev_err(priv->dev, "xMII interface %d not supported\n", 435 interface); 436 return -EINVAL; 437 } 438 439 if (xtal == HWTRAP_XTAL_25MHZ) 440 ssc_delta = 0x57; 441 else 442 ssc_delta = 0x87; 443 444 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 445 P6_INTF_MODE(trgint)); 446 447 /* Lower Tx Driving for TRGMII path */ 448 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) 449 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 450 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 451 452 /* Disable MT7530 core and TRGMII Tx clocks */ 453 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, 454 REG_GSWCK_EN | REG_TRGMIICK_EN); 455 456 /* Setup core clock for MT7530 */ 457 /* Disable PLL */ 458 core_write(priv, CORE_GSWPLL_GRP1, 0); 459 460 /* Set core clock into 500Mhz */ 461 core_write(priv, CORE_GSWPLL_GRP2, 462 RG_GSWPLL_POSDIV_500M(1) | 463 RG_GSWPLL_FBKDIV_500M(25)); 464 465 /* Enable PLL */ 466 core_write(priv, CORE_GSWPLL_GRP1, 467 RG_GSWPLL_EN_PRE | 468 RG_GSWPLL_POSDIV_200M(2) | 469 RG_GSWPLL_FBKDIV_200M(32)); 470 471 /* Setup the MT7530 TRGMII Tx Clock */ 472 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 473 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 474 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 475 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 476 core_write(priv, CORE_PLL_GROUP4, 477 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 478 RG_SYSPLL_BIAS_LPF_EN); 479 core_write(priv, CORE_PLL_GROUP2, 480 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 481 RG_SYSPLL_POSDIV(1)); 482 core_write(priv, CORE_PLL_GROUP7, 483 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 484 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 485 486 /* Enable MT7530 core and TRGMII Tx clocks */ 487 core_set(priv, CORE_TRGMII_GSW_CLK_CG, 488 REG_GSWCK_EN | REG_TRGMIICK_EN); 489 490 if (!trgint) 491 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 492 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 493 RD_TAP_MASK, RD_TAP(16)); 494 return 0; 495 } 496 497 static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) 498 { 499 u32 val; 500 501 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 502 503 return (val & PAD_DUAL_SGMII_EN) != 0; 504 } 505 506 static int 507 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 508 { 509 struct mt7530_priv *priv = ds->priv; 510 u32 top_sig; 511 u32 hwstrap; 512 u32 xtal; 513 u32 val; 514 515 if (mt7531_dual_sgmii_supported(priv)) 516 return 0; 517 518 val = mt7530_read(priv, MT7531_CREV); 519 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 520 hwstrap = mt7530_read(priv, MT7531_HWTRAP); 521 if ((val & CHIP_REV_M) > 0) 522 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : 523 HWTRAP_XTAL_FSEL_25MHZ; 524 else 525 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; 526 527 /* Step 1 : Disable MT7531 COREPLL */ 528 val = mt7530_read(priv, MT7531_PLLGP_EN); 529 val &= ~EN_COREPLL; 530 mt7530_write(priv, MT7531_PLLGP_EN, val); 531 532 /* Step 2: switch to XTAL output */ 533 val = mt7530_read(priv, MT7531_PLLGP_EN); 534 val |= SW_CLKSW; 535 mt7530_write(priv, MT7531_PLLGP_EN, val); 536 537 val = mt7530_read(priv, MT7531_PLLGP_CR0); 538 val &= ~RG_COREPLL_EN; 539 mt7530_write(priv, MT7531_PLLGP_CR0, val); 540 541 /* Step 3: disable PLLGP and enable program PLLGP */ 542 val = mt7530_read(priv, MT7531_PLLGP_EN); 543 val |= SW_PLLGP; 544 mt7530_write(priv, MT7531_PLLGP_EN, val); 545 546 /* Step 4: program COREPLL output frequency to 500MHz */ 547 val = mt7530_read(priv, MT7531_PLLGP_CR0); 548 val &= ~RG_COREPLL_POSDIV_M; 549 val |= 2 << RG_COREPLL_POSDIV_S; 550 mt7530_write(priv, MT7531_PLLGP_CR0, val); 551 usleep_range(25, 35); 552 553 switch (xtal) { 554 case HWTRAP_XTAL_FSEL_25MHZ: 555 val = mt7530_read(priv, MT7531_PLLGP_CR0); 556 val &= ~RG_COREPLL_SDM_PCW_M; 557 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 558 mt7530_write(priv, MT7531_PLLGP_CR0, val); 559 break; 560 case HWTRAP_XTAL_FSEL_40MHZ: 561 val = mt7530_read(priv, MT7531_PLLGP_CR0); 562 val &= ~RG_COREPLL_SDM_PCW_M; 563 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 564 mt7530_write(priv, MT7531_PLLGP_CR0, val); 565 break; 566 } 567 568 /* Set feedback divide ratio update signal to high */ 569 val = mt7530_read(priv, MT7531_PLLGP_CR0); 570 val |= RG_COREPLL_SDM_PCW_CHG; 571 mt7530_write(priv, MT7531_PLLGP_CR0, val); 572 /* Wait for at least 16 XTAL clocks */ 573 usleep_range(10, 20); 574 575 /* Step 5: set feedback divide ratio update signal to low */ 576 val = mt7530_read(priv, MT7531_PLLGP_CR0); 577 val &= ~RG_COREPLL_SDM_PCW_CHG; 578 mt7530_write(priv, MT7531_PLLGP_CR0, val); 579 580 /* Enable 325M clock for SGMII */ 581 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 582 583 /* Enable 250SSC clock for RGMII */ 584 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 585 586 /* Step 6: Enable MT7531 PLL */ 587 val = mt7530_read(priv, MT7531_PLLGP_CR0); 588 val |= RG_COREPLL_EN; 589 mt7530_write(priv, MT7531_PLLGP_CR0, val); 590 591 val = mt7530_read(priv, MT7531_PLLGP_EN); 592 val |= EN_COREPLL; 593 mt7530_write(priv, MT7531_PLLGP_EN, val); 594 usleep_range(25, 35); 595 596 return 0; 597 } 598 599 static void 600 mt7530_mib_reset(struct dsa_switch *ds) 601 { 602 struct mt7530_priv *priv = ds->priv; 603 604 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 605 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 606 } 607 608 static int mt7530_phy_read(struct mt7530_priv *priv, int port, int regnum) 609 { 610 return mdiobus_read_nested(priv->bus, port, regnum); 611 } 612 613 static int mt7530_phy_write(struct mt7530_priv *priv, int port, int regnum, 614 u16 val) 615 { 616 return mdiobus_write_nested(priv->bus, port, regnum, val); 617 } 618 619 static int 620 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 621 int regnum) 622 { 623 struct mii_bus *bus = priv->bus; 624 struct mt7530_dummy_poll p; 625 u32 reg, val; 626 int ret; 627 628 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 629 630 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 631 632 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 633 !(val & MT7531_PHY_ACS_ST), 20, 100000); 634 if (ret < 0) { 635 dev_err(priv->dev, "poll timeout\n"); 636 goto out; 637 } 638 639 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 640 MT7531_MDIO_DEV_ADDR(devad) | regnum; 641 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 642 643 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 644 !(val & MT7531_PHY_ACS_ST), 20, 100000); 645 if (ret < 0) { 646 dev_err(priv->dev, "poll timeout\n"); 647 goto out; 648 } 649 650 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 651 MT7531_MDIO_DEV_ADDR(devad); 652 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 653 654 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 655 !(val & MT7531_PHY_ACS_ST), 20, 100000); 656 if (ret < 0) { 657 dev_err(priv->dev, "poll timeout\n"); 658 goto out; 659 } 660 661 ret = val & MT7531_MDIO_RW_DATA_MASK; 662 out: 663 mutex_unlock(&bus->mdio_lock); 664 665 return ret; 666 } 667 668 static int 669 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 670 int regnum, u32 data) 671 { 672 struct mii_bus *bus = priv->bus; 673 struct mt7530_dummy_poll p; 674 u32 val, reg; 675 int ret; 676 677 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 678 679 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 680 681 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 682 !(val & MT7531_PHY_ACS_ST), 20, 100000); 683 if (ret < 0) { 684 dev_err(priv->dev, "poll timeout\n"); 685 goto out; 686 } 687 688 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 689 MT7531_MDIO_DEV_ADDR(devad) | regnum; 690 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 691 692 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 693 !(val & MT7531_PHY_ACS_ST), 20, 100000); 694 if (ret < 0) { 695 dev_err(priv->dev, "poll timeout\n"); 696 goto out; 697 } 698 699 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 700 MT7531_MDIO_DEV_ADDR(devad) | data; 701 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 702 703 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 704 !(val & MT7531_PHY_ACS_ST), 20, 100000); 705 if (ret < 0) { 706 dev_err(priv->dev, "poll timeout\n"); 707 goto out; 708 } 709 710 out: 711 mutex_unlock(&bus->mdio_lock); 712 713 return ret; 714 } 715 716 static int 717 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 718 { 719 struct mii_bus *bus = priv->bus; 720 struct mt7530_dummy_poll p; 721 int ret; 722 u32 val; 723 724 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 725 726 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 727 728 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 729 !(val & MT7531_PHY_ACS_ST), 20, 100000); 730 if (ret < 0) { 731 dev_err(priv->dev, "poll timeout\n"); 732 goto out; 733 } 734 735 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 736 MT7531_MDIO_REG_ADDR(regnum); 737 738 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 739 740 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 741 !(val & MT7531_PHY_ACS_ST), 20, 100000); 742 if (ret < 0) { 743 dev_err(priv->dev, "poll timeout\n"); 744 goto out; 745 } 746 747 ret = val & MT7531_MDIO_RW_DATA_MASK; 748 out: 749 mutex_unlock(&bus->mdio_lock); 750 751 return ret; 752 } 753 754 static int 755 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 756 u16 data) 757 { 758 struct mii_bus *bus = priv->bus; 759 struct mt7530_dummy_poll p; 760 int ret; 761 u32 reg; 762 763 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 764 765 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 766 767 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 768 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 769 if (ret < 0) { 770 dev_err(priv->dev, "poll timeout\n"); 771 goto out; 772 } 773 774 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 775 MT7531_MDIO_REG_ADDR(regnum) | data; 776 777 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 778 779 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 780 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 781 if (ret < 0) { 782 dev_err(priv->dev, "poll timeout\n"); 783 goto out; 784 } 785 786 out: 787 mutex_unlock(&bus->mdio_lock); 788 789 return ret; 790 } 791 792 static int 793 mt7531_ind_phy_read(struct mt7530_priv *priv, int port, int regnum) 794 { 795 int devad; 796 int ret; 797 798 if (regnum & MII_ADDR_C45) { 799 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; 800 ret = mt7531_ind_c45_phy_read(priv, port, devad, 801 regnum & MII_REGADDR_C45_MASK); 802 } else { 803 ret = mt7531_ind_c22_phy_read(priv, port, regnum); 804 } 805 806 return ret; 807 } 808 809 static int 810 mt7531_ind_phy_write(struct mt7530_priv *priv, int port, int regnum, 811 u16 data) 812 { 813 int devad; 814 int ret; 815 816 if (regnum & MII_ADDR_C45) { 817 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; 818 ret = mt7531_ind_c45_phy_write(priv, port, devad, 819 regnum & MII_REGADDR_C45_MASK, 820 data); 821 } else { 822 ret = mt7531_ind_c22_phy_write(priv, port, regnum, data); 823 } 824 825 return ret; 826 } 827 828 static int 829 mt753x_phy_read(struct mii_bus *bus, int port, int regnum) 830 { 831 struct mt7530_priv *priv = bus->priv; 832 833 return priv->info->phy_read(priv, port, regnum); 834 } 835 836 static int 837 mt753x_phy_write(struct mii_bus *bus, int port, int regnum, u16 val) 838 { 839 struct mt7530_priv *priv = bus->priv; 840 841 return priv->info->phy_write(priv, port, regnum, val); 842 } 843 844 static void 845 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 846 uint8_t *data) 847 { 848 int i; 849 850 if (stringset != ETH_SS_STATS) 851 return; 852 853 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 854 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 855 ETH_GSTRING_LEN); 856 } 857 858 static void 859 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 860 uint64_t *data) 861 { 862 struct mt7530_priv *priv = ds->priv; 863 const struct mt7530_mib_desc *mib; 864 u32 reg, i; 865 u64 hi; 866 867 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 868 mib = &mt7530_mib[i]; 869 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 870 871 data[i] = mt7530_read(priv, reg); 872 if (mib->size == 2) { 873 hi = mt7530_read(priv, reg + 4); 874 data[i] |= hi << 32; 875 } 876 } 877 } 878 879 static int 880 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 881 { 882 if (sset != ETH_SS_STATS) 883 return 0; 884 885 return ARRAY_SIZE(mt7530_mib); 886 } 887 888 static int 889 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 890 { 891 struct mt7530_priv *priv = ds->priv; 892 unsigned int secs = msecs / 1000; 893 unsigned int tmp_age_count; 894 unsigned int error = -1; 895 unsigned int age_count; 896 unsigned int age_unit; 897 898 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 899 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 900 return -ERANGE; 901 902 /* iterate through all possible age_count to find the closest pair */ 903 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 904 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 905 906 if (tmp_age_unit <= AGE_UNIT_MAX) { 907 unsigned int tmp_error = secs - 908 (tmp_age_count + 1) * (tmp_age_unit + 1); 909 910 /* found a closer pair */ 911 if (error > tmp_error) { 912 error = tmp_error; 913 age_count = tmp_age_count; 914 age_unit = tmp_age_unit; 915 } 916 917 /* found the exact match, so break the loop */ 918 if (!error) 919 break; 920 } 921 } 922 923 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 924 925 return 0; 926 } 927 928 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 929 { 930 struct mt7530_priv *priv = ds->priv; 931 u8 tx_delay = 0; 932 int val; 933 934 mutex_lock(&priv->reg_mutex); 935 936 val = mt7530_read(priv, MT7530_MHWTRAP); 937 938 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 939 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 940 941 switch (priv->p5_intf_sel) { 942 case P5_INTF_SEL_PHY_P0: 943 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 944 val |= MHWTRAP_PHY0_SEL; 945 fallthrough; 946 case P5_INTF_SEL_PHY_P4: 947 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 948 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 949 950 /* Setup the MAC by default for the cpu port */ 951 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 952 break; 953 case P5_INTF_SEL_GMAC5: 954 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 955 val &= ~MHWTRAP_P5_DIS; 956 break; 957 case P5_DISABLED: 958 interface = PHY_INTERFACE_MODE_NA; 959 break; 960 default: 961 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", 962 priv->p5_intf_sel); 963 goto unlock_exit; 964 } 965 966 /* Setup RGMII settings */ 967 if (phy_interface_mode_is_rgmii(interface)) { 968 val |= MHWTRAP_P5_RGMII_MODE; 969 970 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 971 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 972 973 /* Don't set delay in DSA mode */ 974 if (!dsa_is_dsa_port(priv->ds, 5) && 975 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 976 interface == PHY_INTERFACE_MODE_RGMII_ID)) 977 tx_delay = 4; /* n * 0.5 ns */ 978 979 /* P5 RGMII TX Clock Control: delay x */ 980 mt7530_write(priv, MT7530_P5RGMIITXCR, 981 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 982 983 /* reduce P5 RGMII Tx driving, 8mA */ 984 mt7530_write(priv, MT7530_IO_DRV_CR, 985 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 986 } 987 988 mt7530_write(priv, MT7530_MHWTRAP, val); 989 990 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 991 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 992 993 priv->p5_interface = interface; 994 995 unlock_exit: 996 mutex_unlock(&priv->reg_mutex); 997 } 998 999 static int 1000 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 1001 { 1002 struct mt7530_priv *priv = ds->priv; 1003 int ret; 1004 1005 /* Setup max capability of CPU port at first */ 1006 if (priv->info->cpu_port_config) { 1007 ret = priv->info->cpu_port_config(ds, port); 1008 if (ret) 1009 return ret; 1010 } 1011 1012 /* Enable Mediatek header mode on the cpu port */ 1013 mt7530_write(priv, MT7530_PVC_P(port), 1014 PORT_SPEC_TAG); 1015 1016 /* Disable flooding by default */ 1017 mt7530_rmw(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK, 1018 BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port))); 1019 1020 /* Set CPU port number */ 1021 if (priv->id == ID_MT7621) 1022 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 1023 1024 /* CPU port gets connected to all user ports of 1025 * the switch. 1026 */ 1027 mt7530_write(priv, MT7530_PCR_P(port), 1028 PCR_MATRIX(dsa_user_ports(priv->ds))); 1029 1030 /* Set to fallback mode for independent VLAN learning */ 1031 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1032 MT7530_PORT_FALLBACK_MODE); 1033 1034 return 0; 1035 } 1036 1037 static int 1038 mt7530_port_enable(struct dsa_switch *ds, int port, 1039 struct phy_device *phy) 1040 { 1041 struct dsa_port *dp = dsa_to_port(ds, port); 1042 struct mt7530_priv *priv = ds->priv; 1043 1044 mutex_lock(&priv->reg_mutex); 1045 1046 /* Allow the user port gets connected to the cpu port and also 1047 * restore the port matrix if the port is the member of a certain 1048 * bridge. 1049 */ 1050 if (dsa_port_is_user(dp)) { 1051 struct dsa_port *cpu_dp = dp->cpu_dp; 1052 1053 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); 1054 } 1055 priv->ports[port].enable = true; 1056 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1057 priv->ports[port].pm); 1058 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1059 1060 mutex_unlock(&priv->reg_mutex); 1061 1062 return 0; 1063 } 1064 1065 static void 1066 mt7530_port_disable(struct dsa_switch *ds, int port) 1067 { 1068 struct mt7530_priv *priv = ds->priv; 1069 1070 mutex_lock(&priv->reg_mutex); 1071 1072 /* Clear up all port matrix which could be restored in the next 1073 * enablement for the port. 1074 */ 1075 priv->ports[port].enable = false; 1076 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1077 PCR_MATRIX_CLR); 1078 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1079 1080 mutex_unlock(&priv->reg_mutex); 1081 } 1082 1083 static int 1084 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1085 { 1086 struct mt7530_priv *priv = ds->priv; 1087 struct mii_bus *bus = priv->bus; 1088 int length; 1089 u32 val; 1090 1091 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1092 * largest MTU of the slave ports. Because the switch only has a global 1093 * RX length register, only allowing CPU port here is enough. 1094 */ 1095 if (!dsa_is_cpu_port(ds, port)) 1096 return 0; 1097 1098 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 1099 1100 val = mt7530_mii_read(priv, MT7530_GMACCR); 1101 val &= ~MAX_RX_PKT_LEN_MASK; 1102 1103 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1104 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1105 if (length <= 1522) { 1106 val |= MAX_RX_PKT_LEN_1522; 1107 } else if (length <= 1536) { 1108 val |= MAX_RX_PKT_LEN_1536; 1109 } else if (length <= 1552) { 1110 val |= MAX_RX_PKT_LEN_1552; 1111 } else { 1112 val &= ~MAX_RX_JUMBO_MASK; 1113 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1114 val |= MAX_RX_PKT_LEN_JUMBO; 1115 } 1116 1117 mt7530_mii_write(priv, MT7530_GMACCR, val); 1118 1119 mutex_unlock(&bus->mdio_lock); 1120 1121 return 0; 1122 } 1123 1124 static int 1125 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1126 { 1127 return MT7530_MAX_MTU; 1128 } 1129 1130 static void 1131 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1132 { 1133 struct mt7530_priv *priv = ds->priv; 1134 u32 stp_state; 1135 1136 switch (state) { 1137 case BR_STATE_DISABLED: 1138 stp_state = MT7530_STP_DISABLED; 1139 break; 1140 case BR_STATE_BLOCKING: 1141 stp_state = MT7530_STP_BLOCKING; 1142 break; 1143 case BR_STATE_LISTENING: 1144 stp_state = MT7530_STP_LISTENING; 1145 break; 1146 case BR_STATE_LEARNING: 1147 stp_state = MT7530_STP_LEARNING; 1148 break; 1149 case BR_STATE_FORWARDING: 1150 default: 1151 stp_state = MT7530_STP_FORWARDING; 1152 break; 1153 } 1154 1155 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1156 FID_PST(FID_BRIDGED, stp_state)); 1157 } 1158 1159 static int 1160 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1161 struct switchdev_brport_flags flags, 1162 struct netlink_ext_ack *extack) 1163 { 1164 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1165 BR_BCAST_FLOOD)) 1166 return -EINVAL; 1167 1168 return 0; 1169 } 1170 1171 static int 1172 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1173 struct switchdev_brport_flags flags, 1174 struct netlink_ext_ack *extack) 1175 { 1176 struct mt7530_priv *priv = ds->priv; 1177 1178 if (flags.mask & BR_LEARNING) 1179 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1180 flags.val & BR_LEARNING ? 0 : SA_DIS); 1181 1182 if (flags.mask & BR_FLOOD) 1183 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), 1184 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1185 1186 if (flags.mask & BR_MCAST_FLOOD) 1187 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1188 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1189 1190 if (flags.mask & BR_BCAST_FLOOD) 1191 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), 1192 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1193 1194 return 0; 1195 } 1196 1197 static int 1198 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1199 struct dsa_bridge bridge, bool *tx_fwd_offload, 1200 struct netlink_ext_ack *extack) 1201 { 1202 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1203 struct dsa_port *cpu_dp = dp->cpu_dp; 1204 u32 port_bitmap = BIT(cpu_dp->index); 1205 struct mt7530_priv *priv = ds->priv; 1206 1207 mutex_lock(&priv->reg_mutex); 1208 1209 dsa_switch_for_each_user_port(other_dp, ds) { 1210 int other_port = other_dp->index; 1211 1212 if (dp == other_dp) 1213 continue; 1214 1215 /* Add this port to the port matrix of the other ports in the 1216 * same bridge. If the port is disabled, port matrix is kept 1217 * and not being setup until the port becomes enabled. 1218 */ 1219 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1220 continue; 1221 1222 if (priv->ports[other_port].enable) 1223 mt7530_set(priv, MT7530_PCR_P(other_port), 1224 PCR_MATRIX(BIT(port))); 1225 priv->ports[other_port].pm |= PCR_MATRIX(BIT(port)); 1226 1227 port_bitmap |= BIT(other_port); 1228 } 1229 1230 /* Add the all other ports to this port matrix. */ 1231 if (priv->ports[port].enable) 1232 mt7530_rmw(priv, MT7530_PCR_P(port), 1233 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1234 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1235 1236 /* Set to fallback mode for independent VLAN learning */ 1237 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1238 MT7530_PORT_FALLBACK_MODE); 1239 1240 mutex_unlock(&priv->reg_mutex); 1241 1242 return 0; 1243 } 1244 1245 static void 1246 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1247 { 1248 struct mt7530_priv *priv = ds->priv; 1249 bool all_user_ports_removed = true; 1250 int i; 1251 1252 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1253 * bridge. Don't set standalone ports to fallback mode. 1254 */ 1255 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) 1256 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1257 MT7530_PORT_FALLBACK_MODE); 1258 1259 mt7530_rmw(priv, MT7530_PVC_P(port), 1260 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1261 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1262 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1263 MT7530_VLAN_ACC_ALL); 1264 1265 /* Set PVID to 0 */ 1266 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1267 G0_PORT_VID_DEF); 1268 1269 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1270 if (dsa_is_user_port(ds, i) && 1271 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1272 all_user_ports_removed = false; 1273 break; 1274 } 1275 } 1276 1277 /* CPU port also does the same thing until all user ports belonging to 1278 * the CPU port get out of VLAN filtering mode. 1279 */ 1280 if (all_user_ports_removed) { 1281 struct dsa_port *dp = dsa_to_port(ds, port); 1282 struct dsa_port *cpu_dp = dp->cpu_dp; 1283 1284 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), 1285 PCR_MATRIX(dsa_user_ports(priv->ds))); 1286 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG 1287 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1288 } 1289 } 1290 1291 static void 1292 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1293 { 1294 struct mt7530_priv *priv = ds->priv; 1295 1296 /* Trapped into security mode allows packet forwarding through VLAN 1297 * table lookup. 1298 */ 1299 if (dsa_is_user_port(ds, port)) { 1300 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1301 MT7530_PORT_SECURITY_MODE); 1302 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1303 G0_PORT_VID(priv->ports[port].pvid)); 1304 1305 /* Only accept tagged frames if PVID is not set */ 1306 if (!priv->ports[port].pvid) 1307 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1308 MT7530_VLAN_ACC_TAGGED); 1309 } 1310 1311 /* Set the port as a user port which is to be able to recognize VID 1312 * from incoming packets before fetching entry within the VLAN table. 1313 */ 1314 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1315 VLAN_ATTR(MT7530_VLAN_USER) | 1316 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1317 } 1318 1319 static void 1320 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1321 struct dsa_bridge bridge) 1322 { 1323 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1324 struct dsa_port *cpu_dp = dp->cpu_dp; 1325 struct mt7530_priv *priv = ds->priv; 1326 1327 mutex_lock(&priv->reg_mutex); 1328 1329 dsa_switch_for_each_user_port(other_dp, ds) { 1330 int other_port = other_dp->index; 1331 1332 if (dp == other_dp) 1333 continue; 1334 1335 /* Remove this port from the port matrix of the other ports 1336 * in the same bridge. If the port is disabled, port matrix 1337 * is kept and not being setup until the port becomes enabled. 1338 */ 1339 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1340 continue; 1341 1342 if (priv->ports[other_port].enable) 1343 mt7530_clear(priv, MT7530_PCR_P(other_port), 1344 PCR_MATRIX(BIT(port))); 1345 priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port)); 1346 } 1347 1348 /* Set the cpu port to be the only one in the port matrix of 1349 * this port. 1350 */ 1351 if (priv->ports[port].enable) 1352 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1353 PCR_MATRIX(BIT(cpu_dp->index))); 1354 priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index)); 1355 1356 /* When a port is removed from the bridge, the port would be set up 1357 * back to the default as is at initial boot which is a VLAN-unaware 1358 * port. 1359 */ 1360 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1361 MT7530_PORT_MATRIX_MODE); 1362 1363 mutex_unlock(&priv->reg_mutex); 1364 } 1365 1366 static int 1367 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1368 const unsigned char *addr, u16 vid, 1369 struct dsa_db db) 1370 { 1371 struct mt7530_priv *priv = ds->priv; 1372 int ret; 1373 u8 port_mask = BIT(port); 1374 1375 mutex_lock(&priv->reg_mutex); 1376 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1377 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1378 mutex_unlock(&priv->reg_mutex); 1379 1380 return ret; 1381 } 1382 1383 static int 1384 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1385 const unsigned char *addr, u16 vid, 1386 struct dsa_db db) 1387 { 1388 struct mt7530_priv *priv = ds->priv; 1389 int ret; 1390 u8 port_mask = BIT(port); 1391 1392 mutex_lock(&priv->reg_mutex); 1393 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1394 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1395 mutex_unlock(&priv->reg_mutex); 1396 1397 return ret; 1398 } 1399 1400 static int 1401 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1402 dsa_fdb_dump_cb_t *cb, void *data) 1403 { 1404 struct mt7530_priv *priv = ds->priv; 1405 struct mt7530_fdb _fdb = { 0 }; 1406 int cnt = MT7530_NUM_FDB_RECORDS; 1407 int ret = 0; 1408 u32 rsp = 0; 1409 1410 mutex_lock(&priv->reg_mutex); 1411 1412 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1413 if (ret < 0) 1414 goto err; 1415 1416 do { 1417 if (rsp & ATC_SRCH_HIT) { 1418 mt7530_fdb_read(priv, &_fdb); 1419 if (_fdb.port_mask & BIT(port)) { 1420 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1421 data); 1422 if (ret < 0) 1423 break; 1424 } 1425 } 1426 } while (--cnt && 1427 !(rsp & ATC_SRCH_END) && 1428 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1429 err: 1430 mutex_unlock(&priv->reg_mutex); 1431 1432 return 0; 1433 } 1434 1435 static int 1436 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1437 const struct switchdev_obj_port_mdb *mdb, 1438 struct dsa_db db) 1439 { 1440 struct mt7530_priv *priv = ds->priv; 1441 const u8 *addr = mdb->addr; 1442 u16 vid = mdb->vid; 1443 u8 port_mask = 0; 1444 int ret; 1445 1446 mutex_lock(&priv->reg_mutex); 1447 1448 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1449 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1450 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1451 & PORT_MAP_MASK; 1452 1453 port_mask |= BIT(port); 1454 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1455 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1456 1457 mutex_unlock(&priv->reg_mutex); 1458 1459 return ret; 1460 } 1461 1462 static int 1463 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1464 const struct switchdev_obj_port_mdb *mdb, 1465 struct dsa_db db) 1466 { 1467 struct mt7530_priv *priv = ds->priv; 1468 const u8 *addr = mdb->addr; 1469 u16 vid = mdb->vid; 1470 u8 port_mask = 0; 1471 int ret; 1472 1473 mutex_lock(&priv->reg_mutex); 1474 1475 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1476 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1477 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1478 & PORT_MAP_MASK; 1479 1480 port_mask &= ~BIT(port); 1481 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1482 port_mask ? STATIC_ENT : STATIC_EMP); 1483 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1484 1485 mutex_unlock(&priv->reg_mutex); 1486 1487 return ret; 1488 } 1489 1490 static int 1491 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1492 { 1493 struct mt7530_dummy_poll p; 1494 u32 val; 1495 int ret; 1496 1497 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1498 mt7530_write(priv, MT7530_VTCR, val); 1499 1500 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1501 ret = readx_poll_timeout(_mt7530_read, &p, val, 1502 !(val & VTCR_BUSY), 20, 20000); 1503 if (ret < 0) { 1504 dev_err(priv->dev, "poll timeout\n"); 1505 return ret; 1506 } 1507 1508 val = mt7530_read(priv, MT7530_VTCR); 1509 if (val & VTCR_INVALID) { 1510 dev_err(priv->dev, "read VTCR invalid\n"); 1511 return -EINVAL; 1512 } 1513 1514 return 0; 1515 } 1516 1517 static int 1518 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1519 struct netlink_ext_ack *extack) 1520 { 1521 struct dsa_port *dp = dsa_to_port(ds, port); 1522 struct dsa_port *cpu_dp = dp->cpu_dp; 1523 1524 if (vlan_filtering) { 1525 /* The port is being kept as VLAN-unaware port when bridge is 1526 * set up with vlan_filtering not being set, Otherwise, the 1527 * port and the corresponding CPU port is required the setup 1528 * for becoming a VLAN-aware port. 1529 */ 1530 mt7530_port_set_vlan_aware(ds, port); 1531 mt7530_port_set_vlan_aware(ds, cpu_dp->index); 1532 } else { 1533 mt7530_port_set_vlan_unaware(ds, port); 1534 } 1535 1536 return 0; 1537 } 1538 1539 static void 1540 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1541 struct mt7530_hw_vlan_entry *entry) 1542 { 1543 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); 1544 u8 new_members; 1545 u32 val; 1546 1547 new_members = entry->old_members | BIT(entry->port); 1548 1549 /* Validate the entry with independent learning, create egress tag per 1550 * VLAN and joining the port as one of the port members. 1551 */ 1552 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1553 VLAN_VALID; 1554 mt7530_write(priv, MT7530_VAWD1, val); 1555 1556 /* Decide whether adding tag or not for those outgoing packets from the 1557 * port inside the VLAN. 1558 * CPU port is always taken as a tagged port for serving more than one 1559 * VLANs across and also being applied with egress type stack mode for 1560 * that VLAN tags would be appended after hardware special tag used as 1561 * DSA tag. 1562 */ 1563 if (dsa_port_is_cpu(dp)) 1564 val = MT7530_VLAN_EGRESS_STACK; 1565 else if (entry->untagged) 1566 val = MT7530_VLAN_EGRESS_UNTAG; 1567 else 1568 val = MT7530_VLAN_EGRESS_TAG; 1569 mt7530_rmw(priv, MT7530_VAWD2, 1570 ETAG_CTRL_P_MASK(entry->port), 1571 ETAG_CTRL_P(entry->port, val)); 1572 } 1573 1574 static void 1575 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1576 struct mt7530_hw_vlan_entry *entry) 1577 { 1578 u8 new_members; 1579 u32 val; 1580 1581 new_members = entry->old_members & ~BIT(entry->port); 1582 1583 val = mt7530_read(priv, MT7530_VAWD1); 1584 if (!(val & VLAN_VALID)) { 1585 dev_err(priv->dev, 1586 "Cannot be deleted due to invalid entry\n"); 1587 return; 1588 } 1589 1590 if (new_members) { 1591 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1592 VLAN_VALID; 1593 mt7530_write(priv, MT7530_VAWD1, val); 1594 } else { 1595 mt7530_write(priv, MT7530_VAWD1, 0); 1596 mt7530_write(priv, MT7530_VAWD2, 0); 1597 } 1598 } 1599 1600 static void 1601 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1602 struct mt7530_hw_vlan_entry *entry, 1603 mt7530_vlan_op vlan_op) 1604 { 1605 u32 val; 1606 1607 /* Fetch entry */ 1608 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1609 1610 val = mt7530_read(priv, MT7530_VAWD1); 1611 1612 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1613 1614 /* Manipulate entry */ 1615 vlan_op(priv, entry); 1616 1617 /* Flush result to hardware */ 1618 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1619 } 1620 1621 static int 1622 mt7530_setup_vlan0(struct mt7530_priv *priv) 1623 { 1624 u32 val; 1625 1626 /* Validate the entry with independent learning, keep the original 1627 * ingress tag attribute. 1628 */ 1629 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1630 VLAN_VALID; 1631 mt7530_write(priv, MT7530_VAWD1, val); 1632 1633 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1634 } 1635 1636 static int 1637 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1638 const struct switchdev_obj_port_vlan *vlan, 1639 struct netlink_ext_ack *extack) 1640 { 1641 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1642 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1643 struct mt7530_hw_vlan_entry new_entry; 1644 struct mt7530_priv *priv = ds->priv; 1645 1646 mutex_lock(&priv->reg_mutex); 1647 1648 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1649 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1650 1651 if (pvid) { 1652 priv->ports[port].pvid = vlan->vid; 1653 1654 /* Accept all frames if PVID is set */ 1655 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1656 MT7530_VLAN_ACC_ALL); 1657 1658 /* Only configure PVID if VLAN filtering is enabled */ 1659 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1660 mt7530_rmw(priv, MT7530_PPBV1_P(port), 1661 G0_PORT_VID_MASK, 1662 G0_PORT_VID(vlan->vid)); 1663 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 1664 /* This VLAN is overwritten without PVID, so unset it */ 1665 priv->ports[port].pvid = G0_PORT_VID_DEF; 1666 1667 /* Only accept tagged frames if the port is VLAN-aware */ 1668 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1669 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1670 MT7530_VLAN_ACC_TAGGED); 1671 1672 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1673 G0_PORT_VID_DEF); 1674 } 1675 1676 mutex_unlock(&priv->reg_mutex); 1677 1678 return 0; 1679 } 1680 1681 static int 1682 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1683 const struct switchdev_obj_port_vlan *vlan) 1684 { 1685 struct mt7530_hw_vlan_entry target_entry; 1686 struct mt7530_priv *priv = ds->priv; 1687 1688 mutex_lock(&priv->reg_mutex); 1689 1690 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1691 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1692 mt7530_hw_vlan_del); 1693 1694 /* PVID is being restored to the default whenever the PVID port 1695 * is being removed from the VLAN. 1696 */ 1697 if (priv->ports[port].pvid == vlan->vid) { 1698 priv->ports[port].pvid = G0_PORT_VID_DEF; 1699 1700 /* Only accept tagged frames if the port is VLAN-aware */ 1701 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1702 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1703 MT7530_VLAN_ACC_TAGGED); 1704 1705 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1706 G0_PORT_VID_DEF); 1707 } 1708 1709 1710 mutex_unlock(&priv->reg_mutex); 1711 1712 return 0; 1713 } 1714 1715 static int mt753x_mirror_port_get(unsigned int id, u32 val) 1716 { 1717 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : 1718 MIRROR_PORT(val); 1719 } 1720 1721 static int mt753x_mirror_port_set(unsigned int id, u32 val) 1722 { 1723 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : 1724 MIRROR_PORT(val); 1725 } 1726 1727 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1728 struct dsa_mall_mirror_tc_entry *mirror, 1729 bool ingress, struct netlink_ext_ack *extack) 1730 { 1731 struct mt7530_priv *priv = ds->priv; 1732 int monitor_port; 1733 u32 val; 1734 1735 /* Check for existent entry */ 1736 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1737 return -EEXIST; 1738 1739 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1740 1741 /* MT7530 only supports one monitor port */ 1742 monitor_port = mt753x_mirror_port_get(priv->id, val); 1743 if (val & MT753X_MIRROR_EN(priv->id) && 1744 monitor_port != mirror->to_local_port) 1745 return -EEXIST; 1746 1747 val |= MT753X_MIRROR_EN(priv->id); 1748 val &= ~MT753X_MIRROR_MASK(priv->id); 1749 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); 1750 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1751 1752 val = mt7530_read(priv, MT7530_PCR_P(port)); 1753 if (ingress) { 1754 val |= PORT_RX_MIR; 1755 priv->mirror_rx |= BIT(port); 1756 } else { 1757 val |= PORT_TX_MIR; 1758 priv->mirror_tx |= BIT(port); 1759 } 1760 mt7530_write(priv, MT7530_PCR_P(port), val); 1761 1762 return 0; 1763 } 1764 1765 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1766 struct dsa_mall_mirror_tc_entry *mirror) 1767 { 1768 struct mt7530_priv *priv = ds->priv; 1769 u32 val; 1770 1771 val = mt7530_read(priv, MT7530_PCR_P(port)); 1772 if (mirror->ingress) { 1773 val &= ~PORT_RX_MIR; 1774 priv->mirror_rx &= ~BIT(port); 1775 } else { 1776 val &= ~PORT_TX_MIR; 1777 priv->mirror_tx &= ~BIT(port); 1778 } 1779 mt7530_write(priv, MT7530_PCR_P(port), val); 1780 1781 if (!priv->mirror_rx && !priv->mirror_tx) { 1782 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1783 val &= ~MT753X_MIRROR_EN(priv->id); 1784 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1785 } 1786 } 1787 1788 static enum dsa_tag_protocol 1789 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1790 enum dsa_tag_protocol mp) 1791 { 1792 return DSA_TAG_PROTO_MTK; 1793 } 1794 1795 #ifdef CONFIG_GPIOLIB 1796 static inline u32 1797 mt7530_gpio_to_bit(unsigned int offset) 1798 { 1799 /* Map GPIO offset to register bit 1800 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1801 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1802 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1803 * [14:12] port 3 LED 0..2 as GPIO 9..11 1804 * [18:16] port 4 LED 0..2 as GPIO 12..14 1805 */ 1806 return BIT(offset + offset / 3); 1807 } 1808 1809 static int 1810 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1811 { 1812 struct mt7530_priv *priv = gpiochip_get_data(gc); 1813 u32 bit = mt7530_gpio_to_bit(offset); 1814 1815 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1816 } 1817 1818 static void 1819 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1820 { 1821 struct mt7530_priv *priv = gpiochip_get_data(gc); 1822 u32 bit = mt7530_gpio_to_bit(offset); 1823 1824 if (value) 1825 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1826 else 1827 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1828 } 1829 1830 static int 1831 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1832 { 1833 struct mt7530_priv *priv = gpiochip_get_data(gc); 1834 u32 bit = mt7530_gpio_to_bit(offset); 1835 1836 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1837 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1838 } 1839 1840 static int 1841 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1842 { 1843 struct mt7530_priv *priv = gpiochip_get_data(gc); 1844 u32 bit = mt7530_gpio_to_bit(offset); 1845 1846 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 1847 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 1848 1849 return 0; 1850 } 1851 1852 static int 1853 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 1854 { 1855 struct mt7530_priv *priv = gpiochip_get_data(gc); 1856 u32 bit = mt7530_gpio_to_bit(offset); 1857 1858 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 1859 1860 if (value) 1861 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1862 else 1863 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1864 1865 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 1866 1867 return 0; 1868 } 1869 1870 static int 1871 mt7530_setup_gpio(struct mt7530_priv *priv) 1872 { 1873 struct device *dev = priv->dev; 1874 struct gpio_chip *gc; 1875 1876 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1877 if (!gc) 1878 return -ENOMEM; 1879 1880 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 1881 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 1882 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 1883 1884 gc->label = "mt7530"; 1885 gc->parent = dev; 1886 gc->owner = THIS_MODULE; 1887 gc->get_direction = mt7530_gpio_get_direction; 1888 gc->direction_input = mt7530_gpio_direction_input; 1889 gc->direction_output = mt7530_gpio_direction_output; 1890 gc->get = mt7530_gpio_get; 1891 gc->set = mt7530_gpio_set; 1892 gc->base = -1; 1893 gc->ngpio = 15; 1894 gc->can_sleep = true; 1895 1896 return devm_gpiochip_add_data(dev, gc, priv); 1897 } 1898 #endif /* CONFIG_GPIOLIB */ 1899 1900 static irqreturn_t 1901 mt7530_irq_thread_fn(int irq, void *dev_id) 1902 { 1903 struct mt7530_priv *priv = dev_id; 1904 bool handled = false; 1905 u32 val; 1906 int p; 1907 1908 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 1909 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); 1910 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); 1911 mutex_unlock(&priv->bus->mdio_lock); 1912 1913 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1914 if (BIT(p) & val) { 1915 unsigned int irq; 1916 1917 irq = irq_find_mapping(priv->irq_domain, p); 1918 handle_nested_irq(irq); 1919 handled = true; 1920 } 1921 } 1922 1923 return IRQ_RETVAL(handled); 1924 } 1925 1926 static void 1927 mt7530_irq_mask(struct irq_data *d) 1928 { 1929 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1930 1931 priv->irq_enable &= ~BIT(d->hwirq); 1932 } 1933 1934 static void 1935 mt7530_irq_unmask(struct irq_data *d) 1936 { 1937 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1938 1939 priv->irq_enable |= BIT(d->hwirq); 1940 } 1941 1942 static void 1943 mt7530_irq_bus_lock(struct irq_data *d) 1944 { 1945 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1946 1947 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 1948 } 1949 1950 static void 1951 mt7530_irq_bus_sync_unlock(struct irq_data *d) 1952 { 1953 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1954 1955 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 1956 mutex_unlock(&priv->bus->mdio_lock); 1957 } 1958 1959 static struct irq_chip mt7530_irq_chip = { 1960 .name = KBUILD_MODNAME, 1961 .irq_mask = mt7530_irq_mask, 1962 .irq_unmask = mt7530_irq_unmask, 1963 .irq_bus_lock = mt7530_irq_bus_lock, 1964 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, 1965 }; 1966 1967 static int 1968 mt7530_irq_map(struct irq_domain *domain, unsigned int irq, 1969 irq_hw_number_t hwirq) 1970 { 1971 irq_set_chip_data(irq, domain->host_data); 1972 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); 1973 irq_set_nested_thread(irq, true); 1974 irq_set_noprobe(irq); 1975 1976 return 0; 1977 } 1978 1979 static const struct irq_domain_ops mt7530_irq_domain_ops = { 1980 .map = mt7530_irq_map, 1981 .xlate = irq_domain_xlate_onecell, 1982 }; 1983 1984 static void 1985 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 1986 { 1987 struct dsa_switch *ds = priv->ds; 1988 int p; 1989 1990 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1991 if (BIT(p) & ds->phys_mii_mask) { 1992 unsigned int irq; 1993 1994 irq = irq_create_mapping(priv->irq_domain, p); 1995 ds->slave_mii_bus->irq[p] = irq; 1996 } 1997 } 1998 } 1999 2000 static int 2001 mt7530_setup_irq(struct mt7530_priv *priv) 2002 { 2003 struct device *dev = priv->dev; 2004 struct device_node *np = dev->of_node; 2005 int ret; 2006 2007 if (!of_property_read_bool(np, "interrupt-controller")) { 2008 dev_info(dev, "no interrupt support\n"); 2009 return 0; 2010 } 2011 2012 priv->irq = of_irq_get(np, 0); 2013 if (priv->irq <= 0) { 2014 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); 2015 return priv->irq ? : -EINVAL; 2016 } 2017 2018 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2019 &mt7530_irq_domain_ops, priv); 2020 if (!priv->irq_domain) { 2021 dev_err(dev, "failed to create IRQ domain\n"); 2022 return -ENOMEM; 2023 } 2024 2025 /* This register must be set for MT7530 to properly fire interrupts */ 2026 if (priv->id != ID_MT7531) 2027 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 2028 2029 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, 2030 IRQF_ONESHOT, KBUILD_MODNAME, priv); 2031 if (ret) { 2032 irq_domain_remove(priv->irq_domain); 2033 dev_err(dev, "failed to request IRQ: %d\n", ret); 2034 return ret; 2035 } 2036 2037 return 0; 2038 } 2039 2040 static void 2041 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2042 { 2043 int p; 2044 2045 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2046 if (BIT(p) & priv->ds->phys_mii_mask) { 2047 unsigned int irq; 2048 2049 irq = irq_find_mapping(priv->irq_domain, p); 2050 irq_dispose_mapping(irq); 2051 } 2052 } 2053 } 2054 2055 static void 2056 mt7530_free_irq_common(struct mt7530_priv *priv) 2057 { 2058 free_irq(priv->irq, priv); 2059 irq_domain_remove(priv->irq_domain); 2060 } 2061 2062 static void 2063 mt7530_free_irq(struct mt7530_priv *priv) 2064 { 2065 mt7530_free_mdio_irq(priv); 2066 mt7530_free_irq_common(priv); 2067 } 2068 2069 static int 2070 mt7530_setup_mdio(struct mt7530_priv *priv) 2071 { 2072 struct dsa_switch *ds = priv->ds; 2073 struct device *dev = priv->dev; 2074 struct mii_bus *bus; 2075 static int idx; 2076 int ret; 2077 2078 bus = devm_mdiobus_alloc(dev); 2079 if (!bus) 2080 return -ENOMEM; 2081 2082 ds->slave_mii_bus = bus; 2083 bus->priv = priv; 2084 bus->name = KBUILD_MODNAME "-mii"; 2085 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2086 bus->read = mt753x_phy_read; 2087 bus->write = mt753x_phy_write; 2088 bus->parent = dev; 2089 bus->phy_mask = ~ds->phys_mii_mask; 2090 2091 if (priv->irq) 2092 mt7530_setup_mdio_irq(priv); 2093 2094 ret = devm_mdiobus_register(dev, bus); 2095 if (ret) { 2096 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2097 if (priv->irq) 2098 mt7530_free_mdio_irq(priv); 2099 } 2100 2101 return ret; 2102 } 2103 2104 static int 2105 mt7530_setup(struct dsa_switch *ds) 2106 { 2107 struct mt7530_priv *priv = ds->priv; 2108 struct device_node *dn = NULL; 2109 struct device_node *phy_node; 2110 struct device_node *mac_np; 2111 struct mt7530_dummy_poll p; 2112 phy_interface_t interface; 2113 struct dsa_port *cpu_dp; 2114 u32 id, val; 2115 int ret, i; 2116 2117 /* The parent node of master netdev which holds the common system 2118 * controller also is the container for two GMACs nodes representing 2119 * as two netdev instances. 2120 */ 2121 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2122 dn = cpu_dp->master->dev.of_node->parent; 2123 /* It doesn't matter which CPU port is found first, 2124 * their masters should share the same parent OF node 2125 */ 2126 break; 2127 } 2128 2129 if (!dn) { 2130 dev_err(ds->dev, "parent OF node of DSA master not found"); 2131 return -EINVAL; 2132 } 2133 2134 ds->assisted_learning_on_cpu_port = true; 2135 ds->mtu_enforcement_ingress = true; 2136 2137 if (priv->id == ID_MT7530) { 2138 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2139 ret = regulator_enable(priv->core_pwr); 2140 if (ret < 0) { 2141 dev_err(priv->dev, 2142 "Failed to enable core power: %d\n", ret); 2143 return ret; 2144 } 2145 2146 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2147 ret = regulator_enable(priv->io_pwr); 2148 if (ret < 0) { 2149 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2150 ret); 2151 return ret; 2152 } 2153 } 2154 2155 /* Reset whole chip through gpio pin or memory-mapped registers for 2156 * different type of hardware 2157 */ 2158 if (priv->mcm) { 2159 reset_control_assert(priv->rstc); 2160 usleep_range(1000, 1100); 2161 reset_control_deassert(priv->rstc); 2162 } else { 2163 gpiod_set_value_cansleep(priv->reset, 0); 2164 usleep_range(1000, 1100); 2165 gpiod_set_value_cansleep(priv->reset, 1); 2166 } 2167 2168 /* Waiting for MT7530 got to stable */ 2169 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2170 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2171 20, 1000000); 2172 if (ret < 0) { 2173 dev_err(priv->dev, "reset timeout\n"); 2174 return ret; 2175 } 2176 2177 id = mt7530_read(priv, MT7530_CREV); 2178 id >>= CHIP_NAME_SHIFT; 2179 if (id != MT7530_ID) { 2180 dev_err(priv->dev, "chip %x can't be supported\n", id); 2181 return -ENODEV; 2182 } 2183 2184 /* Reset the switch through internal reset */ 2185 mt7530_write(priv, MT7530_SYS_CTRL, 2186 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2187 SYS_CTRL_REG_RST); 2188 2189 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */ 2190 val = mt7530_read(priv, MT7530_MHWTRAP); 2191 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 2192 val |= MHWTRAP_MANUAL; 2193 mt7530_write(priv, MT7530_MHWTRAP, val); 2194 2195 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2196 2197 /* Enable and reset MIB counters */ 2198 mt7530_mib_reset(ds); 2199 2200 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2201 /* Disable forwarding by default on all ports */ 2202 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2203 PCR_MATRIX_CLR); 2204 2205 /* Disable learning by default on all ports */ 2206 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2207 2208 if (dsa_is_cpu_port(ds, i)) { 2209 ret = mt753x_cpu_port_enable(ds, i); 2210 if (ret) 2211 return ret; 2212 } else { 2213 mt7530_port_disable(ds, i); 2214 2215 /* Set default PVID to 0 on all user ports */ 2216 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2217 G0_PORT_VID_DEF); 2218 } 2219 /* Enable consistent egress tag */ 2220 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2221 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2222 } 2223 2224 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2225 ret = mt7530_setup_vlan0(priv); 2226 if (ret) 2227 return ret; 2228 2229 /* Setup port 5 */ 2230 priv->p5_intf_sel = P5_DISABLED; 2231 interface = PHY_INTERFACE_MODE_NA; 2232 2233 if (!dsa_is_unused_port(ds, 5)) { 2234 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2235 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); 2236 if (ret && ret != -ENODEV) 2237 return ret; 2238 } else { 2239 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ 2240 for_each_child_of_node(dn, mac_np) { 2241 if (!of_device_is_compatible(mac_np, 2242 "mediatek,eth-mac")) 2243 continue; 2244 2245 ret = of_property_read_u32(mac_np, "reg", &id); 2246 if (ret < 0 || id != 1) 2247 continue; 2248 2249 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2250 if (!phy_node) 2251 continue; 2252 2253 if (phy_node->parent == priv->dev->of_node->parent) { 2254 ret = of_get_phy_mode(mac_np, &interface); 2255 if (ret && ret != -ENODEV) { 2256 of_node_put(mac_np); 2257 of_node_put(phy_node); 2258 return ret; 2259 } 2260 id = of_mdio_parse_addr(ds->dev, phy_node); 2261 if (id == 0) 2262 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 2263 if (id == 4) 2264 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 2265 } 2266 of_node_put(mac_np); 2267 of_node_put(phy_node); 2268 break; 2269 } 2270 } 2271 2272 #ifdef CONFIG_GPIOLIB 2273 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2274 ret = mt7530_setup_gpio(priv); 2275 if (ret) 2276 return ret; 2277 } 2278 #endif /* CONFIG_GPIOLIB */ 2279 2280 mt7530_setup_port5(ds, interface); 2281 2282 /* Flush the FDB table */ 2283 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2284 if (ret < 0) 2285 return ret; 2286 2287 return 0; 2288 } 2289 2290 static int 2291 mt7531_setup(struct dsa_switch *ds) 2292 { 2293 struct mt7530_priv *priv = ds->priv; 2294 struct mt7530_dummy_poll p; 2295 struct dsa_port *cpu_dp; 2296 u32 val, id; 2297 int ret, i; 2298 2299 /* Reset whole chip through gpio pin or memory-mapped registers for 2300 * different type of hardware 2301 */ 2302 if (priv->mcm) { 2303 reset_control_assert(priv->rstc); 2304 usleep_range(1000, 1100); 2305 reset_control_deassert(priv->rstc); 2306 } else { 2307 gpiod_set_value_cansleep(priv->reset, 0); 2308 usleep_range(1000, 1100); 2309 gpiod_set_value_cansleep(priv->reset, 1); 2310 } 2311 2312 /* Waiting for MT7530 got to stable */ 2313 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2314 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2315 20, 1000000); 2316 if (ret < 0) { 2317 dev_err(priv->dev, "reset timeout\n"); 2318 return ret; 2319 } 2320 2321 id = mt7530_read(priv, MT7531_CREV); 2322 id >>= CHIP_NAME_SHIFT; 2323 2324 if (id != MT7531_ID) { 2325 dev_err(priv->dev, "chip %x can't be supported\n", id); 2326 return -ENODEV; 2327 } 2328 2329 /* Reset the switch through internal reset */ 2330 mt7530_write(priv, MT7530_SYS_CTRL, 2331 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2332 SYS_CTRL_REG_RST); 2333 2334 if (mt7531_dual_sgmii_supported(priv)) { 2335 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; 2336 2337 /* Let ds->slave_mii_bus be able to access external phy. */ 2338 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2339 MT7531_EXT_P_MDC_11); 2340 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2341 MT7531_EXT_P_MDIO_12); 2342 } else { 2343 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2344 } 2345 dev_dbg(ds->dev, "P5 support %s interface\n", 2346 p5_intf_modes(priv->p5_intf_sel)); 2347 2348 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2349 MT7531_GPIO0_INTERRUPT); 2350 2351 /* Let phylink decide the interface later. */ 2352 priv->p5_interface = PHY_INTERFACE_MODE_NA; 2353 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2354 2355 /* Enable PHY core PLL, since phy_device has not yet been created 2356 * provided for phy_[read,write]_mmd_indirect is called, we provide 2357 * our own mt7531_ind_mmd_phy_[read,write] to complete this 2358 * function. 2359 */ 2360 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, 2361 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2362 val |= MT7531_PHY_PLL_BYPASS_MODE; 2363 val &= ~MT7531_PHY_PLL_OFF; 2364 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, 2365 CORE_PLL_GROUP4, val); 2366 2367 /* BPDU to CPU port */ 2368 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2369 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, 2370 BIT(cpu_dp->index)); 2371 break; 2372 } 2373 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, 2374 MT753X_BPDU_CPU_ONLY); 2375 2376 /* Enable and reset MIB counters */ 2377 mt7530_mib_reset(ds); 2378 2379 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2380 /* Disable forwarding by default on all ports */ 2381 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2382 PCR_MATRIX_CLR); 2383 2384 /* Disable learning by default on all ports */ 2385 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2386 2387 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2388 2389 if (dsa_is_cpu_port(ds, i)) { 2390 ret = mt753x_cpu_port_enable(ds, i); 2391 if (ret) 2392 return ret; 2393 } else { 2394 mt7530_port_disable(ds, i); 2395 2396 /* Set default PVID to 0 on all user ports */ 2397 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2398 G0_PORT_VID_DEF); 2399 } 2400 2401 /* Enable consistent egress tag */ 2402 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2403 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2404 } 2405 2406 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2407 ret = mt7530_setup_vlan0(priv); 2408 if (ret) 2409 return ret; 2410 2411 ds->assisted_learning_on_cpu_port = true; 2412 ds->mtu_enforcement_ingress = true; 2413 2414 /* Flush the FDB table */ 2415 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2416 if (ret < 0) 2417 return ret; 2418 2419 return 0; 2420 } 2421 2422 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 2423 struct phylink_config *config) 2424 { 2425 switch (port) { 2426 case 0 ... 4: /* Internal phy */ 2427 __set_bit(PHY_INTERFACE_MODE_GMII, 2428 config->supported_interfaces); 2429 break; 2430 2431 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2432 phy_interface_set_rgmii(config->supported_interfaces); 2433 __set_bit(PHY_INTERFACE_MODE_MII, 2434 config->supported_interfaces); 2435 __set_bit(PHY_INTERFACE_MODE_GMII, 2436 config->supported_interfaces); 2437 break; 2438 2439 case 6: /* 1st cpu port */ 2440 __set_bit(PHY_INTERFACE_MODE_RGMII, 2441 config->supported_interfaces); 2442 __set_bit(PHY_INTERFACE_MODE_TRGMII, 2443 config->supported_interfaces); 2444 break; 2445 } 2446 } 2447 2448 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) 2449 { 2450 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); 2451 } 2452 2453 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, 2454 struct phylink_config *config) 2455 { 2456 struct mt7530_priv *priv = ds->priv; 2457 2458 switch (port) { 2459 case 0 ... 4: /* Internal phy */ 2460 __set_bit(PHY_INTERFACE_MODE_GMII, 2461 config->supported_interfaces); 2462 break; 2463 2464 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ 2465 if (mt7531_is_rgmii_port(priv, port)) { 2466 phy_interface_set_rgmii(config->supported_interfaces); 2467 break; 2468 } 2469 fallthrough; 2470 2471 case 6: /* 1st cpu port supports sgmii/8023z only */ 2472 __set_bit(PHY_INTERFACE_MODE_SGMII, 2473 config->supported_interfaces); 2474 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2475 config->supported_interfaces); 2476 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2477 config->supported_interfaces); 2478 2479 config->mac_capabilities |= MAC_2500FD; 2480 break; 2481 } 2482 } 2483 2484 static int 2485 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) 2486 { 2487 struct mt7530_priv *priv = ds->priv; 2488 2489 return priv->info->pad_setup(ds, state->interface); 2490 } 2491 2492 static int 2493 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2494 phy_interface_t interface) 2495 { 2496 struct mt7530_priv *priv = ds->priv; 2497 2498 /* Only need to setup port5. */ 2499 if (port != 5) 2500 return 0; 2501 2502 mt7530_setup_port5(priv->ds, interface); 2503 2504 return 0; 2505 } 2506 2507 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 2508 phy_interface_t interface, 2509 struct phy_device *phydev) 2510 { 2511 u32 val; 2512 2513 if (!mt7531_is_rgmii_port(priv, port)) { 2514 dev_err(priv->dev, "RGMII mode is not available for port %d\n", 2515 port); 2516 return -EINVAL; 2517 } 2518 2519 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2520 val |= GP_CLK_EN; 2521 val &= ~GP_MODE_MASK; 2522 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2523 val &= ~CLK_SKEW_IN_MASK; 2524 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2525 val &= ~CLK_SKEW_OUT_MASK; 2526 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2527 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2528 2529 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2530 if (!phydev || phy_driver_is_genphy(phydev)) { 2531 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2532 switch (interface) { 2533 case PHY_INTERFACE_MODE_RGMII: 2534 val |= TXCLK_NO_REVERSE; 2535 val |= RXCLK_NO_DELAY; 2536 break; 2537 case PHY_INTERFACE_MODE_RGMII_RXID: 2538 val |= TXCLK_NO_REVERSE; 2539 break; 2540 case PHY_INTERFACE_MODE_RGMII_TXID: 2541 val |= RXCLK_NO_DELAY; 2542 break; 2543 case PHY_INTERFACE_MODE_RGMII_ID: 2544 break; 2545 default: 2546 return -EINVAL; 2547 } 2548 } 2549 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2550 2551 return 0; 2552 } 2553 2554 static void mt7531_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode, 2555 phy_interface_t interface, int speed, int duplex) 2556 { 2557 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2558 int port = pcs_to_mt753x_pcs(pcs)->port; 2559 unsigned int val; 2560 2561 /* For adjusting speed and duplex of SGMII force mode. */ 2562 if (interface != PHY_INTERFACE_MODE_SGMII || 2563 phylink_autoneg_inband(mode)) 2564 return; 2565 2566 /* SGMII force mode setting */ 2567 val = mt7530_read(priv, MT7531_SGMII_MODE(port)); 2568 val &= ~MT7531_SGMII_IF_MODE_MASK; 2569 2570 switch (speed) { 2571 case SPEED_10: 2572 val |= MT7531_SGMII_FORCE_SPEED_10; 2573 break; 2574 case SPEED_100: 2575 val |= MT7531_SGMII_FORCE_SPEED_100; 2576 break; 2577 case SPEED_1000: 2578 val |= MT7531_SGMII_FORCE_SPEED_1000; 2579 break; 2580 } 2581 2582 /* MT7531 SGMII 1G force mode can only work in full duplex mode, 2583 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2584 * 2585 * The speed check is unnecessary as the MAC capabilities apply 2586 * this restriction. --rmk 2587 */ 2588 if ((speed == SPEED_10 || speed == SPEED_100) && 2589 duplex != DUPLEX_FULL) 2590 val |= MT7531_SGMII_FORCE_HALF_DUPLEX; 2591 2592 mt7530_write(priv, MT7531_SGMII_MODE(port), val); 2593 } 2594 2595 static bool mt753x_is_mac_port(u32 port) 2596 { 2597 return (port == 5 || port == 6); 2598 } 2599 2600 static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port, 2601 phy_interface_t interface) 2602 { 2603 u32 val; 2604 2605 if (!mt753x_is_mac_port(port)) 2606 return -EINVAL; 2607 2608 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2609 MT7531_SGMII_PHYA_PWD); 2610 2611 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port)); 2612 val &= ~MT7531_RG_TPHY_SPEED_MASK; 2613 /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B 2614 * encoding. 2615 */ 2616 val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ? 2617 MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G; 2618 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val); 2619 2620 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2621 2622 /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex 2623 * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2624 */ 2625 mt7530_rmw(priv, MT7531_SGMII_MODE(port), 2626 MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS, 2627 MT7531_SGMII_FORCE_SPEED_1000); 2628 2629 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2630 2631 return 0; 2632 } 2633 2634 static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port, 2635 phy_interface_t interface) 2636 { 2637 if (!mt753x_is_mac_port(port)) 2638 return -EINVAL; 2639 2640 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2641 MT7531_SGMII_PHYA_PWD); 2642 2643 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), 2644 MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G); 2645 2646 mt7530_set(priv, MT7531_SGMII_MODE(port), 2647 MT7531_SGMII_REMOTE_FAULT_DIS | 2648 MT7531_SGMII_SPEED_DUPLEX_AN); 2649 2650 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port), 2651 MT7531_SGMII_TX_CONFIG_MASK, 1); 2652 2653 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2654 2655 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART); 2656 2657 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2658 2659 return 0; 2660 } 2661 2662 static void mt7531_pcs_an_restart(struct phylink_pcs *pcs) 2663 { 2664 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2665 int port = pcs_to_mt753x_pcs(pcs)->port; 2666 u32 val; 2667 2668 /* Only restart AN when AN is enabled */ 2669 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2670 if (val & MT7531_SGMII_AN_ENABLE) { 2671 val |= MT7531_SGMII_AN_RESTART; 2672 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val); 2673 } 2674 } 2675 2676 static int 2677 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2678 phy_interface_t interface) 2679 { 2680 struct mt7530_priv *priv = ds->priv; 2681 struct phy_device *phydev; 2682 struct dsa_port *dp; 2683 2684 if (!mt753x_is_mac_port(port)) { 2685 dev_err(priv->dev, "port %d is not a MAC port\n", port); 2686 return -EINVAL; 2687 } 2688 2689 switch (interface) { 2690 case PHY_INTERFACE_MODE_RGMII: 2691 case PHY_INTERFACE_MODE_RGMII_ID: 2692 case PHY_INTERFACE_MODE_RGMII_RXID: 2693 case PHY_INTERFACE_MODE_RGMII_TXID: 2694 dp = dsa_to_port(ds, port); 2695 phydev = dp->slave->phydev; 2696 return mt7531_rgmii_setup(priv, port, interface, phydev); 2697 case PHY_INTERFACE_MODE_SGMII: 2698 return mt7531_sgmii_setup_mode_an(priv, port, interface); 2699 case PHY_INTERFACE_MODE_NA: 2700 case PHY_INTERFACE_MODE_1000BASEX: 2701 case PHY_INTERFACE_MODE_2500BASEX: 2702 if (phylink_autoneg_inband(mode)) 2703 return -EINVAL; 2704 2705 return mt7531_sgmii_setup_mode_force(priv, port, interface); 2706 default: 2707 return -EINVAL; 2708 } 2709 2710 return -EINVAL; 2711 } 2712 2713 static int 2714 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2715 const struct phylink_link_state *state) 2716 { 2717 struct mt7530_priv *priv = ds->priv; 2718 2719 return priv->info->mac_port_config(ds, port, mode, state->interface); 2720 } 2721 2722 static struct phylink_pcs * 2723 mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port, 2724 phy_interface_t interface) 2725 { 2726 struct mt7530_priv *priv = ds->priv; 2727 2728 switch (interface) { 2729 case PHY_INTERFACE_MODE_TRGMII: 2730 case PHY_INTERFACE_MODE_SGMII: 2731 case PHY_INTERFACE_MODE_1000BASEX: 2732 case PHY_INTERFACE_MODE_2500BASEX: 2733 return &priv->pcs[port].pcs; 2734 2735 default: 2736 return NULL; 2737 } 2738 } 2739 2740 static void 2741 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2742 const struct phylink_link_state *state) 2743 { 2744 struct mt7530_priv *priv = ds->priv; 2745 u32 mcr_cur, mcr_new; 2746 2747 switch (port) { 2748 case 0 ... 4: /* Internal phy */ 2749 if (state->interface != PHY_INTERFACE_MODE_GMII) 2750 goto unsupported; 2751 break; 2752 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2753 if (priv->p5_interface == state->interface) 2754 break; 2755 2756 if (mt753x_mac_config(ds, port, mode, state) < 0) 2757 goto unsupported; 2758 2759 if (priv->p5_intf_sel != P5_DISABLED) 2760 priv->p5_interface = state->interface; 2761 break; 2762 case 6: /* 1st cpu port */ 2763 if (priv->p6_interface == state->interface) 2764 break; 2765 2766 mt753x_pad_setup(ds, state); 2767 2768 if (mt753x_mac_config(ds, port, mode, state) < 0) 2769 goto unsupported; 2770 2771 priv->p6_interface = state->interface; 2772 break; 2773 default: 2774 unsupported: 2775 dev_err(ds->dev, "%s: unsupported %s port: %i\n", 2776 __func__, phy_modes(state->interface), port); 2777 return; 2778 } 2779 2780 if (phylink_autoneg_inband(mode) && 2781 state->interface != PHY_INTERFACE_MODE_SGMII) { 2782 dev_err(ds->dev, "%s: in-band negotiation unsupported\n", 2783 __func__); 2784 return; 2785 } 2786 2787 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); 2788 mcr_new = mcr_cur; 2789 mcr_new &= ~PMCR_LINK_SETTINGS_MASK; 2790 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | 2791 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); 2792 2793 /* Are we connected to external phy */ 2794 if (port == 5 && dsa_is_user_port(ds, 5)) 2795 mcr_new |= PMCR_EXT_PHY; 2796 2797 if (mcr_new != mcr_cur) 2798 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); 2799 } 2800 2801 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, 2802 unsigned int mode, 2803 phy_interface_t interface) 2804 { 2805 struct mt7530_priv *priv = ds->priv; 2806 2807 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 2808 } 2809 2810 static void mt753x_phylink_pcs_link_up(struct phylink_pcs *pcs, 2811 unsigned int mode, 2812 phy_interface_t interface, 2813 int speed, int duplex) 2814 { 2815 if (pcs->ops->pcs_link_up) 2816 pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex); 2817 } 2818 2819 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, 2820 unsigned int mode, 2821 phy_interface_t interface, 2822 struct phy_device *phydev, 2823 int speed, int duplex, 2824 bool tx_pause, bool rx_pause) 2825 { 2826 struct mt7530_priv *priv = ds->priv; 2827 u32 mcr; 2828 2829 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; 2830 2831 /* MT753x MAC works in 1G full duplex mode for all up-clocked 2832 * variants. 2833 */ 2834 if (interface == PHY_INTERFACE_MODE_TRGMII || 2835 (phy_interface_mode_is_8023z(interface))) { 2836 speed = SPEED_1000; 2837 duplex = DUPLEX_FULL; 2838 } 2839 2840 switch (speed) { 2841 case SPEED_1000: 2842 mcr |= PMCR_FORCE_SPEED_1000; 2843 break; 2844 case SPEED_100: 2845 mcr |= PMCR_FORCE_SPEED_100; 2846 break; 2847 } 2848 if (duplex == DUPLEX_FULL) { 2849 mcr |= PMCR_FORCE_FDX; 2850 if (tx_pause) 2851 mcr |= PMCR_TX_FC_EN; 2852 if (rx_pause) 2853 mcr |= PMCR_RX_FC_EN; 2854 } 2855 2856 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) { 2857 switch (speed) { 2858 case SPEED_1000: 2859 mcr |= PMCR_FORCE_EEE1G; 2860 break; 2861 case SPEED_100: 2862 mcr |= PMCR_FORCE_EEE100; 2863 break; 2864 } 2865 } 2866 2867 mt7530_set(priv, MT7530_PMCR_P(port), mcr); 2868 } 2869 2870 static int 2871 mt7531_cpu_port_config(struct dsa_switch *ds, int port) 2872 { 2873 struct mt7530_priv *priv = ds->priv; 2874 phy_interface_t interface; 2875 int speed; 2876 int ret; 2877 2878 switch (port) { 2879 case 5: 2880 if (mt7531_is_rgmii_port(priv, port)) 2881 interface = PHY_INTERFACE_MODE_RGMII; 2882 else 2883 interface = PHY_INTERFACE_MODE_2500BASEX; 2884 2885 priv->p5_interface = interface; 2886 break; 2887 case 6: 2888 interface = PHY_INTERFACE_MODE_2500BASEX; 2889 2890 mt7531_pad_setup(ds, interface); 2891 2892 priv->p6_interface = interface; 2893 break; 2894 default: 2895 return -EINVAL; 2896 } 2897 2898 if (interface == PHY_INTERFACE_MODE_2500BASEX) 2899 speed = SPEED_2500; 2900 else 2901 speed = SPEED_1000; 2902 2903 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); 2904 if (ret) 2905 return ret; 2906 mt7530_write(priv, MT7530_PMCR_P(port), 2907 PMCR_CPU_PORT_SETTING(priv->id)); 2908 mt753x_phylink_pcs_link_up(&priv->pcs[port].pcs, MLO_AN_FIXED, 2909 interface, speed, DUPLEX_FULL); 2910 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, 2911 speed, DUPLEX_FULL, true, true); 2912 2913 return 0; 2914 } 2915 2916 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, 2917 struct phylink_config *config) 2918 { 2919 struct mt7530_priv *priv = ds->priv; 2920 2921 /* This switch only supports full-duplex at 1Gbps */ 2922 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2923 MAC_10 | MAC_100 | MAC_1000FD; 2924 2925 /* This driver does not make use of the speed, duplex, pause or the 2926 * advertisement in its mac_config, so it is safe to mark this driver 2927 * as non-legacy. 2928 */ 2929 config->legacy_pre_march2020 = false; 2930 2931 priv->info->mac_port_get_caps(ds, port, config); 2932 } 2933 2934 static int mt753x_pcs_validate(struct phylink_pcs *pcs, 2935 unsigned long *supported, 2936 const struct phylink_link_state *state) 2937 { 2938 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */ 2939 if (state->interface == PHY_INTERFACE_MODE_TRGMII || 2940 phy_interface_mode_is_8023z(state->interface)) 2941 phylink_clear(supported, Autoneg); 2942 2943 return 0; 2944 } 2945 2946 static void mt7530_pcs_get_state(struct phylink_pcs *pcs, 2947 struct phylink_link_state *state) 2948 { 2949 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2950 int port = pcs_to_mt753x_pcs(pcs)->port; 2951 u32 pmsr; 2952 2953 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2954 2955 state->link = (pmsr & PMSR_LINK); 2956 state->an_complete = state->link; 2957 state->duplex = !!(pmsr & PMSR_DPX); 2958 2959 switch (pmsr & PMSR_SPEED_MASK) { 2960 case PMSR_SPEED_10: 2961 state->speed = SPEED_10; 2962 break; 2963 case PMSR_SPEED_100: 2964 state->speed = SPEED_100; 2965 break; 2966 case PMSR_SPEED_1000: 2967 state->speed = SPEED_1000; 2968 break; 2969 default: 2970 state->speed = SPEED_UNKNOWN; 2971 break; 2972 } 2973 2974 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 2975 if (pmsr & PMSR_RX_FC) 2976 state->pause |= MLO_PAUSE_RX; 2977 if (pmsr & PMSR_TX_FC) 2978 state->pause |= MLO_PAUSE_TX; 2979 } 2980 2981 static int 2982 mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port, 2983 struct phylink_link_state *state) 2984 { 2985 u32 status, val; 2986 u16 config_reg; 2987 2988 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2989 state->link = !!(status & MT7531_SGMII_LINK_STATUS); 2990 if (state->interface == PHY_INTERFACE_MODE_SGMII && 2991 (status & MT7531_SGMII_AN_ENABLE)) { 2992 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port)); 2993 config_reg = val >> 16; 2994 2995 switch (config_reg & LPA_SGMII_SPD_MASK) { 2996 case LPA_SGMII_1000: 2997 state->speed = SPEED_1000; 2998 break; 2999 case LPA_SGMII_100: 3000 state->speed = SPEED_100; 3001 break; 3002 case LPA_SGMII_10: 3003 state->speed = SPEED_10; 3004 break; 3005 default: 3006 dev_err(priv->dev, "invalid sgmii PHY speed\n"); 3007 state->link = false; 3008 return -EINVAL; 3009 } 3010 3011 if (config_reg & LPA_SGMII_FULL_DUPLEX) 3012 state->duplex = DUPLEX_FULL; 3013 else 3014 state->duplex = DUPLEX_HALF; 3015 } 3016 3017 return 0; 3018 } 3019 3020 static void mt7531_pcs_get_state(struct phylink_pcs *pcs, 3021 struct phylink_link_state *state) 3022 { 3023 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 3024 int port = pcs_to_mt753x_pcs(pcs)->port; 3025 3026 if (state->interface == PHY_INTERFACE_MODE_SGMII) 3027 mt7531_sgmii_pcs_get_state_an(priv, port, state); 3028 else 3029 state->link = false; 3030 } 3031 3032 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode, 3033 phy_interface_t interface, 3034 const unsigned long *advertising, 3035 bool permit_pause_to_mac) 3036 { 3037 return 0; 3038 } 3039 3040 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) 3041 { 3042 } 3043 3044 static const struct phylink_pcs_ops mt7530_pcs_ops = { 3045 .pcs_validate = mt753x_pcs_validate, 3046 .pcs_get_state = mt7530_pcs_get_state, 3047 .pcs_config = mt753x_pcs_config, 3048 .pcs_an_restart = mt7530_pcs_an_restart, 3049 }; 3050 3051 static const struct phylink_pcs_ops mt7531_pcs_ops = { 3052 .pcs_validate = mt753x_pcs_validate, 3053 .pcs_get_state = mt7531_pcs_get_state, 3054 .pcs_config = mt753x_pcs_config, 3055 .pcs_an_restart = mt7531_pcs_an_restart, 3056 .pcs_link_up = mt7531_pcs_link_up, 3057 }; 3058 3059 static int 3060 mt753x_setup(struct dsa_switch *ds) 3061 { 3062 struct mt7530_priv *priv = ds->priv; 3063 int i, ret; 3064 3065 /* Initialise the PCS devices */ 3066 for (i = 0; i < priv->ds->num_ports; i++) { 3067 priv->pcs[i].pcs.ops = priv->info->pcs_ops; 3068 priv->pcs[i].priv = priv; 3069 priv->pcs[i].port = i; 3070 } 3071 3072 ret = priv->info->sw_setup(ds); 3073 if (ret) 3074 return ret; 3075 3076 ret = mt7530_setup_irq(priv); 3077 if (ret) 3078 return ret; 3079 3080 ret = mt7530_setup_mdio(priv); 3081 if (ret && priv->irq) 3082 mt7530_free_irq_common(priv); 3083 3084 return ret; 3085 } 3086 3087 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, 3088 struct ethtool_eee *e) 3089 { 3090 struct mt7530_priv *priv = ds->priv; 3091 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); 3092 3093 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); 3094 e->tx_lpi_timer = GET_LPI_THRESH(eeecr); 3095 3096 return 0; 3097 } 3098 3099 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3100 struct ethtool_eee *e) 3101 { 3102 struct mt7530_priv *priv = ds->priv; 3103 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN; 3104 3105 if (e->tx_lpi_timer > 0xFFF) 3106 return -EINVAL; 3107 3108 set = SET_LPI_THRESH(e->tx_lpi_timer); 3109 if (!e->tx_lpi_enabled) 3110 /* Force LPI Mode without a delay */ 3111 set |= LPI_MODE_EN; 3112 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); 3113 3114 return 0; 3115 } 3116 3117 static const struct dsa_switch_ops mt7530_switch_ops = { 3118 .get_tag_protocol = mtk_get_tag_protocol, 3119 .setup = mt753x_setup, 3120 .get_strings = mt7530_get_strings, 3121 .get_ethtool_stats = mt7530_get_ethtool_stats, 3122 .get_sset_count = mt7530_get_sset_count, 3123 .set_ageing_time = mt7530_set_ageing_time, 3124 .port_enable = mt7530_port_enable, 3125 .port_disable = mt7530_port_disable, 3126 .port_change_mtu = mt7530_port_change_mtu, 3127 .port_max_mtu = mt7530_port_max_mtu, 3128 .port_stp_state_set = mt7530_stp_state_set, 3129 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3130 .port_bridge_flags = mt7530_port_bridge_flags, 3131 .port_bridge_join = mt7530_port_bridge_join, 3132 .port_bridge_leave = mt7530_port_bridge_leave, 3133 .port_fdb_add = mt7530_port_fdb_add, 3134 .port_fdb_del = mt7530_port_fdb_del, 3135 .port_fdb_dump = mt7530_port_fdb_dump, 3136 .port_mdb_add = mt7530_port_mdb_add, 3137 .port_mdb_del = mt7530_port_mdb_del, 3138 .port_vlan_filtering = mt7530_port_vlan_filtering, 3139 .port_vlan_add = mt7530_port_vlan_add, 3140 .port_vlan_del = mt7530_port_vlan_del, 3141 .port_mirror_add = mt753x_port_mirror_add, 3142 .port_mirror_del = mt753x_port_mirror_del, 3143 .phylink_get_caps = mt753x_phylink_get_caps, 3144 .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs, 3145 .phylink_mac_config = mt753x_phylink_mac_config, 3146 .phylink_mac_link_down = mt753x_phylink_mac_link_down, 3147 .phylink_mac_link_up = mt753x_phylink_mac_link_up, 3148 .get_mac_eee = mt753x_get_mac_eee, 3149 .set_mac_eee = mt753x_set_mac_eee, 3150 }; 3151 3152 static const struct mt753x_info mt753x_table[] = { 3153 [ID_MT7621] = { 3154 .id = ID_MT7621, 3155 .pcs_ops = &mt7530_pcs_ops, 3156 .sw_setup = mt7530_setup, 3157 .phy_read = mt7530_phy_read, 3158 .phy_write = mt7530_phy_write, 3159 .pad_setup = mt7530_pad_clk_setup, 3160 .mac_port_get_caps = mt7530_mac_port_get_caps, 3161 .mac_port_config = mt7530_mac_config, 3162 }, 3163 [ID_MT7530] = { 3164 .id = ID_MT7530, 3165 .pcs_ops = &mt7530_pcs_ops, 3166 .sw_setup = mt7530_setup, 3167 .phy_read = mt7530_phy_read, 3168 .phy_write = mt7530_phy_write, 3169 .pad_setup = mt7530_pad_clk_setup, 3170 .mac_port_get_caps = mt7530_mac_port_get_caps, 3171 .mac_port_config = mt7530_mac_config, 3172 }, 3173 [ID_MT7531] = { 3174 .id = ID_MT7531, 3175 .pcs_ops = &mt7531_pcs_ops, 3176 .sw_setup = mt7531_setup, 3177 .phy_read = mt7531_ind_phy_read, 3178 .phy_write = mt7531_ind_phy_write, 3179 .pad_setup = mt7531_pad_setup, 3180 .cpu_port_config = mt7531_cpu_port_config, 3181 .mac_port_get_caps = mt7531_mac_port_get_caps, 3182 .mac_port_config = mt7531_mac_config, 3183 }, 3184 }; 3185 3186 static const struct of_device_id mt7530_of_match[] = { 3187 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], }, 3188 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], }, 3189 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], }, 3190 { /* sentinel */ }, 3191 }; 3192 MODULE_DEVICE_TABLE(of, mt7530_of_match); 3193 3194 static int 3195 mt7530_probe(struct mdio_device *mdiodev) 3196 { 3197 struct mt7530_priv *priv; 3198 struct device_node *dn; 3199 3200 dn = mdiodev->dev.of_node; 3201 3202 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 3203 if (!priv) 3204 return -ENOMEM; 3205 3206 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); 3207 if (!priv->ds) 3208 return -ENOMEM; 3209 3210 priv->ds->dev = &mdiodev->dev; 3211 priv->ds->num_ports = MT7530_NUM_PORTS; 3212 3213 /* Use medatek,mcm property to distinguish hardware type that would 3214 * casues a little bit differences on power-on sequence. 3215 */ 3216 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); 3217 if (priv->mcm) { 3218 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); 3219 3220 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); 3221 if (IS_ERR(priv->rstc)) { 3222 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 3223 return PTR_ERR(priv->rstc); 3224 } 3225 } 3226 3227 /* Get the hardware identifier from the devicetree node. 3228 * We will need it for some of the clock and regulator setup. 3229 */ 3230 priv->info = of_device_get_match_data(&mdiodev->dev); 3231 if (!priv->info) 3232 return -EINVAL; 3233 3234 /* Sanity check if these required device operations are filled 3235 * properly. 3236 */ 3237 if (!priv->info->sw_setup || !priv->info->pad_setup || 3238 !priv->info->phy_read || !priv->info->phy_write || 3239 !priv->info->mac_port_get_caps || 3240 !priv->info->mac_port_config) 3241 return -EINVAL; 3242 3243 priv->id = priv->info->id; 3244 3245 if (priv->id == ID_MT7530) { 3246 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); 3247 if (IS_ERR(priv->core_pwr)) 3248 return PTR_ERR(priv->core_pwr); 3249 3250 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); 3251 if (IS_ERR(priv->io_pwr)) 3252 return PTR_ERR(priv->io_pwr); 3253 } 3254 3255 /* Not MCM that indicates switch works as the remote standalone 3256 * integrated circuit so the GPIO pin would be used to complete 3257 * the reset, otherwise memory-mapped register accessing used 3258 * through syscon provides in the case of MCM. 3259 */ 3260 if (!priv->mcm) { 3261 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", 3262 GPIOD_OUT_LOW); 3263 if (IS_ERR(priv->reset)) { 3264 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 3265 return PTR_ERR(priv->reset); 3266 } 3267 } 3268 3269 priv->bus = mdiodev->bus; 3270 priv->dev = &mdiodev->dev; 3271 priv->ds->priv = priv; 3272 priv->ds->ops = &mt7530_switch_ops; 3273 mutex_init(&priv->reg_mutex); 3274 dev_set_drvdata(&mdiodev->dev, priv); 3275 3276 return dsa_register_switch(priv->ds); 3277 } 3278 3279 static void 3280 mt7530_remove(struct mdio_device *mdiodev) 3281 { 3282 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 3283 int ret = 0; 3284 3285 if (!priv) 3286 return; 3287 3288 ret = regulator_disable(priv->core_pwr); 3289 if (ret < 0) 3290 dev_err(priv->dev, 3291 "Failed to disable core power: %d\n", ret); 3292 3293 ret = regulator_disable(priv->io_pwr); 3294 if (ret < 0) 3295 dev_err(priv->dev, "Failed to disable io pwr: %d\n", 3296 ret); 3297 3298 if (priv->irq) 3299 mt7530_free_irq(priv); 3300 3301 dsa_unregister_switch(priv->ds); 3302 mutex_destroy(&priv->reg_mutex); 3303 3304 dev_set_drvdata(&mdiodev->dev, NULL); 3305 } 3306 3307 static void mt7530_shutdown(struct mdio_device *mdiodev) 3308 { 3309 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 3310 3311 if (!priv) 3312 return; 3313 3314 dsa_switch_shutdown(priv->ds); 3315 3316 dev_set_drvdata(&mdiodev->dev, NULL); 3317 } 3318 3319 static struct mdio_driver mt7530_mdio_driver = { 3320 .probe = mt7530_probe, 3321 .remove = mt7530_remove, 3322 .shutdown = mt7530_shutdown, 3323 .mdiodrv.driver = { 3324 .name = "mt7530", 3325 .of_match_table = mt7530_of_match, 3326 }, 3327 }; 3328 3329 mdio_module_driver(mt7530_mdio_driver); 3330 3331 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3332 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3333 MODULE_LICENSE("GPL"); 3334