1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 25 #include "mt7530.h" 26 27 /* String, offset, and register size in bytes if different from 4 bytes */ 28 static const struct mt7530_mib_desc mt7530_mib[] = { 29 MIB_DESC(1, 0x00, "TxDrop"), 30 MIB_DESC(1, 0x04, "TxCrcErr"), 31 MIB_DESC(1, 0x08, "TxUnicast"), 32 MIB_DESC(1, 0x0c, "TxMulticast"), 33 MIB_DESC(1, 0x10, "TxBroadcast"), 34 MIB_DESC(1, 0x14, "TxCollision"), 35 MIB_DESC(1, 0x18, "TxSingleCollision"), 36 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 37 MIB_DESC(1, 0x20, "TxDeferred"), 38 MIB_DESC(1, 0x24, "TxLateCollision"), 39 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 40 MIB_DESC(1, 0x2c, "TxPause"), 41 MIB_DESC(1, 0x30, "TxPktSz64"), 42 MIB_DESC(1, 0x34, "TxPktSz65To127"), 43 MIB_DESC(1, 0x38, "TxPktSz128To255"), 44 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 45 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 46 MIB_DESC(1, 0x44, "Tx1024ToMax"), 47 MIB_DESC(2, 0x48, "TxBytes"), 48 MIB_DESC(1, 0x60, "RxDrop"), 49 MIB_DESC(1, 0x64, "RxFiltering"), 50 MIB_DESC(1, 0x6c, "RxMulticast"), 51 MIB_DESC(1, 0x70, "RxBroadcast"), 52 MIB_DESC(1, 0x74, "RxAlignErr"), 53 MIB_DESC(1, 0x78, "RxCrcErr"), 54 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 55 MIB_DESC(1, 0x80, "RxFragErr"), 56 MIB_DESC(1, 0x84, "RxOverSzErr"), 57 MIB_DESC(1, 0x88, "RxJabberErr"), 58 MIB_DESC(1, 0x8c, "RxPause"), 59 MIB_DESC(1, 0x90, "RxPktSz64"), 60 MIB_DESC(1, 0x94, "RxPktSz65To127"), 61 MIB_DESC(1, 0x98, "RxPktSz128To255"), 62 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 63 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 64 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 65 MIB_DESC(2, 0xa8, "RxBytes"), 66 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 67 MIB_DESC(1, 0xb4, "RxIngressDrop"), 68 MIB_DESC(1, 0xb8, "RxArlDrop"), 69 }; 70 71 /* Since phy_device has not yet been created and 72 * phy_{read,write}_mmd_indirect is not available, we provide our own 73 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers 74 * to complete this function. 75 */ 76 static int 77 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 78 { 79 struct mii_bus *bus = priv->bus; 80 int value, ret; 81 82 /* Write the desired MMD Devad */ 83 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 84 if (ret < 0) 85 goto err; 86 87 /* Write the desired MMD register address */ 88 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 89 if (ret < 0) 90 goto err; 91 92 /* Select the Function : DATA with no post increment */ 93 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 94 if (ret < 0) 95 goto err; 96 97 /* Read the content of the MMD's selected register */ 98 value = bus->read(bus, 0, MII_MMD_DATA); 99 100 return value; 101 err: 102 dev_err(&bus->dev, "failed to read mmd register\n"); 103 104 return ret; 105 } 106 107 static int 108 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 109 int devad, u32 data) 110 { 111 struct mii_bus *bus = priv->bus; 112 int ret; 113 114 /* Write the desired MMD Devad */ 115 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 116 if (ret < 0) 117 goto err; 118 119 /* Write the desired MMD register address */ 120 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 121 if (ret < 0) 122 goto err; 123 124 /* Select the Function : DATA with no post increment */ 125 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 126 if (ret < 0) 127 goto err; 128 129 /* Write the data into MMD's selected register */ 130 ret = bus->write(bus, 0, MII_MMD_DATA, data); 131 err: 132 if (ret < 0) 133 dev_err(&bus->dev, 134 "failed to write mmd register\n"); 135 return ret; 136 } 137 138 static void 139 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 140 { 141 struct mii_bus *bus = priv->bus; 142 143 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 144 145 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 146 147 mutex_unlock(&bus->mdio_lock); 148 } 149 150 static void 151 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 152 { 153 struct mii_bus *bus = priv->bus; 154 u32 val; 155 156 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 157 158 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 159 val &= ~mask; 160 val |= set; 161 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 162 163 mutex_unlock(&bus->mdio_lock); 164 } 165 166 static void 167 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 168 { 169 core_rmw(priv, reg, 0, val); 170 } 171 172 static void 173 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 174 { 175 core_rmw(priv, reg, val, 0); 176 } 177 178 static int 179 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 180 { 181 struct mii_bus *bus = priv->bus; 182 u16 page, r, lo, hi; 183 int ret; 184 185 page = (reg >> 6) & 0x3ff; 186 r = (reg >> 2) & 0xf; 187 lo = val & 0xffff; 188 hi = val >> 16; 189 190 /* MT7530 uses 31 as the pseudo port */ 191 ret = bus->write(bus, 0x1f, 0x1f, page); 192 if (ret < 0) 193 goto err; 194 195 ret = bus->write(bus, 0x1f, r, lo); 196 if (ret < 0) 197 goto err; 198 199 ret = bus->write(bus, 0x1f, 0x10, hi); 200 err: 201 if (ret < 0) 202 dev_err(&bus->dev, 203 "failed to write mt7530 register\n"); 204 return ret; 205 } 206 207 static u32 208 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 209 { 210 struct mii_bus *bus = priv->bus; 211 u16 page, r, lo, hi; 212 int ret; 213 214 page = (reg >> 6) & 0x3ff; 215 r = (reg >> 2) & 0xf; 216 217 /* MT7530 uses 31 as the pseudo port */ 218 ret = bus->write(bus, 0x1f, 0x1f, page); 219 if (ret < 0) { 220 dev_err(&bus->dev, 221 "failed to read mt7530 register\n"); 222 return ret; 223 } 224 225 lo = bus->read(bus, 0x1f, r); 226 hi = bus->read(bus, 0x1f, 0x10); 227 228 return (hi << 16) | (lo & 0xffff); 229 } 230 231 static void 232 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 233 { 234 struct mii_bus *bus = priv->bus; 235 236 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 237 238 mt7530_mii_write(priv, reg, val); 239 240 mutex_unlock(&bus->mdio_lock); 241 } 242 243 static u32 244 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 245 { 246 return mt7530_mii_read(p->priv, p->reg); 247 } 248 249 static u32 250 _mt7530_read(struct mt7530_dummy_poll *p) 251 { 252 struct mii_bus *bus = p->priv->bus; 253 u32 val; 254 255 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 256 257 val = mt7530_mii_read(p->priv, p->reg); 258 259 mutex_unlock(&bus->mdio_lock); 260 261 return val; 262 } 263 264 static u32 265 mt7530_read(struct mt7530_priv *priv, u32 reg) 266 { 267 struct mt7530_dummy_poll p; 268 269 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 270 return _mt7530_read(&p); 271 } 272 273 static void 274 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 275 u32 mask, u32 set) 276 { 277 struct mii_bus *bus = priv->bus; 278 u32 val; 279 280 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 281 282 val = mt7530_mii_read(priv, reg); 283 val &= ~mask; 284 val |= set; 285 mt7530_mii_write(priv, reg, val); 286 287 mutex_unlock(&bus->mdio_lock); 288 } 289 290 static void 291 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 292 { 293 mt7530_rmw(priv, reg, 0, val); 294 } 295 296 static void 297 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 298 { 299 mt7530_rmw(priv, reg, val, 0); 300 } 301 302 static int 303 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 304 { 305 u32 val; 306 int ret; 307 struct mt7530_dummy_poll p; 308 309 /* Set the command operating upon the MAC address entries */ 310 val = ATC_BUSY | ATC_MAT(0) | cmd; 311 mt7530_write(priv, MT7530_ATC, val); 312 313 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 314 ret = readx_poll_timeout(_mt7530_read, &p, val, 315 !(val & ATC_BUSY), 20, 20000); 316 if (ret < 0) { 317 dev_err(priv->dev, "reset timeout\n"); 318 return ret; 319 } 320 321 /* Additional sanity for read command if the specified 322 * entry is invalid 323 */ 324 val = mt7530_read(priv, MT7530_ATC); 325 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 326 return -EINVAL; 327 328 if (rsp) 329 *rsp = val; 330 331 return 0; 332 } 333 334 static void 335 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 336 { 337 u32 reg[3]; 338 int i; 339 340 /* Read from ARL table into an array */ 341 for (i = 0; i < 3; i++) { 342 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 343 344 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 345 __func__, __LINE__, i, reg[i]); 346 } 347 348 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 349 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 350 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 351 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 352 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 353 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 354 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 355 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 356 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 357 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 358 } 359 360 static void 361 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 362 u8 port_mask, const u8 *mac, 363 u8 aging, u8 type) 364 { 365 u32 reg[3] = { 0 }; 366 int i; 367 368 reg[1] |= vid & CVID_MASK; 369 if (vid > 1) 370 reg[1] |= ATA2_IVL; 371 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 372 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 373 /* STATIC_ENT indicate that entry is static wouldn't 374 * be aged out and STATIC_EMP specified as erasing an 375 * entry 376 */ 377 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 378 reg[1] |= mac[5] << MAC_BYTE_5; 379 reg[1] |= mac[4] << MAC_BYTE_4; 380 reg[0] |= mac[3] << MAC_BYTE_3; 381 reg[0] |= mac[2] << MAC_BYTE_2; 382 reg[0] |= mac[1] << MAC_BYTE_1; 383 reg[0] |= mac[0] << MAC_BYTE_0; 384 385 /* Write array into the ARL table */ 386 for (i = 0; i < 3; i++) 387 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 388 } 389 390 /* Setup TX circuit including relevant PAD and driving */ 391 static int 392 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 393 { 394 struct mt7530_priv *priv = ds->priv; 395 u32 ncpo1, ssc_delta, trgint, i, xtal; 396 397 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 398 399 if (xtal == HWTRAP_XTAL_20MHZ) { 400 dev_err(priv->dev, 401 "%s: MT7530 with a 20MHz XTAL is not supported!\n", 402 __func__); 403 return -EINVAL; 404 } 405 406 switch (interface) { 407 case PHY_INTERFACE_MODE_RGMII: 408 trgint = 0; 409 /* PLL frequency: 125MHz */ 410 ncpo1 = 0x0c80; 411 break; 412 case PHY_INTERFACE_MODE_TRGMII: 413 trgint = 1; 414 if (priv->id == ID_MT7621) { 415 /* PLL frequency: 150MHz: 1.2GBit */ 416 if (xtal == HWTRAP_XTAL_40MHZ) 417 ncpo1 = 0x0780; 418 if (xtal == HWTRAP_XTAL_25MHZ) 419 ncpo1 = 0x0a00; 420 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 421 if (xtal == HWTRAP_XTAL_40MHZ) 422 ncpo1 = 0x0c80; 423 if (xtal == HWTRAP_XTAL_25MHZ) 424 ncpo1 = 0x1400; 425 } 426 break; 427 default: 428 dev_err(priv->dev, "xMII interface %d not supported\n", 429 interface); 430 return -EINVAL; 431 } 432 433 if (xtal == HWTRAP_XTAL_25MHZ) 434 ssc_delta = 0x57; 435 else 436 ssc_delta = 0x87; 437 438 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 439 P6_INTF_MODE(trgint)); 440 441 /* Lower Tx Driving for TRGMII path */ 442 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) 443 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 444 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 445 446 /* Disable MT7530 core and TRGMII Tx clocks */ 447 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, 448 REG_GSWCK_EN | REG_TRGMIICK_EN); 449 450 /* Setup core clock for MT7530 */ 451 /* Disable PLL */ 452 core_write(priv, CORE_GSWPLL_GRP1, 0); 453 454 /* Set core clock into 500Mhz */ 455 core_write(priv, CORE_GSWPLL_GRP2, 456 RG_GSWPLL_POSDIV_500M(1) | 457 RG_GSWPLL_FBKDIV_500M(25)); 458 459 /* Enable PLL */ 460 core_write(priv, CORE_GSWPLL_GRP1, 461 RG_GSWPLL_EN_PRE | 462 RG_GSWPLL_POSDIV_200M(2) | 463 RG_GSWPLL_FBKDIV_200M(32)); 464 465 /* Setup the MT7530 TRGMII Tx Clock */ 466 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 467 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 468 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 469 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 470 core_write(priv, CORE_PLL_GROUP4, 471 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 472 RG_SYSPLL_BIAS_LPF_EN); 473 core_write(priv, CORE_PLL_GROUP2, 474 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 475 RG_SYSPLL_POSDIV(1)); 476 core_write(priv, CORE_PLL_GROUP7, 477 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 478 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 479 480 /* Enable MT7530 core and TRGMII Tx clocks */ 481 core_set(priv, CORE_TRGMII_GSW_CLK_CG, 482 REG_GSWCK_EN | REG_TRGMIICK_EN); 483 484 if (!trgint) 485 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 486 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 487 RD_TAP_MASK, RD_TAP(16)); 488 return 0; 489 } 490 491 static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) 492 { 493 u32 val; 494 495 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 496 497 return (val & PAD_DUAL_SGMII_EN) != 0; 498 } 499 500 static int 501 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 502 { 503 struct mt7530_priv *priv = ds->priv; 504 u32 top_sig; 505 u32 hwstrap; 506 u32 xtal; 507 u32 val; 508 509 if (mt7531_dual_sgmii_supported(priv)) 510 return 0; 511 512 val = mt7530_read(priv, MT7531_CREV); 513 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 514 hwstrap = mt7530_read(priv, MT7531_HWTRAP); 515 if ((val & CHIP_REV_M) > 0) 516 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : 517 HWTRAP_XTAL_FSEL_25MHZ; 518 else 519 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; 520 521 /* Step 1 : Disable MT7531 COREPLL */ 522 val = mt7530_read(priv, MT7531_PLLGP_EN); 523 val &= ~EN_COREPLL; 524 mt7530_write(priv, MT7531_PLLGP_EN, val); 525 526 /* Step 2: switch to XTAL output */ 527 val = mt7530_read(priv, MT7531_PLLGP_EN); 528 val |= SW_CLKSW; 529 mt7530_write(priv, MT7531_PLLGP_EN, val); 530 531 val = mt7530_read(priv, MT7531_PLLGP_CR0); 532 val &= ~RG_COREPLL_EN; 533 mt7530_write(priv, MT7531_PLLGP_CR0, val); 534 535 /* Step 3: disable PLLGP and enable program PLLGP */ 536 val = mt7530_read(priv, MT7531_PLLGP_EN); 537 val |= SW_PLLGP; 538 mt7530_write(priv, MT7531_PLLGP_EN, val); 539 540 /* Step 4: program COREPLL output frequency to 500MHz */ 541 val = mt7530_read(priv, MT7531_PLLGP_CR0); 542 val &= ~RG_COREPLL_POSDIV_M; 543 val |= 2 << RG_COREPLL_POSDIV_S; 544 mt7530_write(priv, MT7531_PLLGP_CR0, val); 545 usleep_range(25, 35); 546 547 switch (xtal) { 548 case HWTRAP_XTAL_FSEL_25MHZ: 549 val = mt7530_read(priv, MT7531_PLLGP_CR0); 550 val &= ~RG_COREPLL_SDM_PCW_M; 551 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 552 mt7530_write(priv, MT7531_PLLGP_CR0, val); 553 break; 554 case HWTRAP_XTAL_FSEL_40MHZ: 555 val = mt7530_read(priv, MT7531_PLLGP_CR0); 556 val &= ~RG_COREPLL_SDM_PCW_M; 557 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 558 mt7530_write(priv, MT7531_PLLGP_CR0, val); 559 break; 560 } 561 562 /* Set feedback divide ratio update signal to high */ 563 val = mt7530_read(priv, MT7531_PLLGP_CR0); 564 val |= RG_COREPLL_SDM_PCW_CHG; 565 mt7530_write(priv, MT7531_PLLGP_CR0, val); 566 /* Wait for at least 16 XTAL clocks */ 567 usleep_range(10, 20); 568 569 /* Step 5: set feedback divide ratio update signal to low */ 570 val = mt7530_read(priv, MT7531_PLLGP_CR0); 571 val &= ~RG_COREPLL_SDM_PCW_CHG; 572 mt7530_write(priv, MT7531_PLLGP_CR0, val); 573 574 /* Enable 325M clock for SGMII */ 575 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 576 577 /* Enable 250SSC clock for RGMII */ 578 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 579 580 /* Step 6: Enable MT7531 PLL */ 581 val = mt7530_read(priv, MT7531_PLLGP_CR0); 582 val |= RG_COREPLL_EN; 583 mt7530_write(priv, MT7531_PLLGP_CR0, val); 584 585 val = mt7530_read(priv, MT7531_PLLGP_EN); 586 val |= EN_COREPLL; 587 mt7530_write(priv, MT7531_PLLGP_EN, val); 588 usleep_range(25, 35); 589 590 return 0; 591 } 592 593 static void 594 mt7530_mib_reset(struct dsa_switch *ds) 595 { 596 struct mt7530_priv *priv = ds->priv; 597 598 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 599 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 600 } 601 602 static int mt7530_phy_read(struct mt7530_priv *priv, int port, int regnum) 603 { 604 return mdiobus_read_nested(priv->bus, port, regnum); 605 } 606 607 static int mt7530_phy_write(struct mt7530_priv *priv, int port, int regnum, 608 u16 val) 609 { 610 return mdiobus_write_nested(priv->bus, port, regnum, val); 611 } 612 613 static int 614 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 615 int regnum) 616 { 617 struct mii_bus *bus = priv->bus; 618 struct mt7530_dummy_poll p; 619 u32 reg, val; 620 int ret; 621 622 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 623 624 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 625 626 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 627 !(val & MT7531_PHY_ACS_ST), 20, 100000); 628 if (ret < 0) { 629 dev_err(priv->dev, "poll timeout\n"); 630 goto out; 631 } 632 633 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 634 MT7531_MDIO_DEV_ADDR(devad) | regnum; 635 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 636 637 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 638 !(val & MT7531_PHY_ACS_ST), 20, 100000); 639 if (ret < 0) { 640 dev_err(priv->dev, "poll timeout\n"); 641 goto out; 642 } 643 644 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 645 MT7531_MDIO_DEV_ADDR(devad); 646 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 647 648 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 649 !(val & MT7531_PHY_ACS_ST), 20, 100000); 650 if (ret < 0) { 651 dev_err(priv->dev, "poll timeout\n"); 652 goto out; 653 } 654 655 ret = val & MT7531_MDIO_RW_DATA_MASK; 656 out: 657 mutex_unlock(&bus->mdio_lock); 658 659 return ret; 660 } 661 662 static int 663 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 664 int regnum, u32 data) 665 { 666 struct mii_bus *bus = priv->bus; 667 struct mt7530_dummy_poll p; 668 u32 val, reg; 669 int ret; 670 671 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 672 673 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 674 675 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 676 !(val & MT7531_PHY_ACS_ST), 20, 100000); 677 if (ret < 0) { 678 dev_err(priv->dev, "poll timeout\n"); 679 goto out; 680 } 681 682 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 683 MT7531_MDIO_DEV_ADDR(devad) | regnum; 684 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 685 686 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 687 !(val & MT7531_PHY_ACS_ST), 20, 100000); 688 if (ret < 0) { 689 dev_err(priv->dev, "poll timeout\n"); 690 goto out; 691 } 692 693 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 694 MT7531_MDIO_DEV_ADDR(devad) | data; 695 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 696 697 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 698 !(val & MT7531_PHY_ACS_ST), 20, 100000); 699 if (ret < 0) { 700 dev_err(priv->dev, "poll timeout\n"); 701 goto out; 702 } 703 704 out: 705 mutex_unlock(&bus->mdio_lock); 706 707 return ret; 708 } 709 710 static int 711 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 712 { 713 struct mii_bus *bus = priv->bus; 714 struct mt7530_dummy_poll p; 715 int ret; 716 u32 val; 717 718 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 719 720 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 721 722 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 723 !(val & MT7531_PHY_ACS_ST), 20, 100000); 724 if (ret < 0) { 725 dev_err(priv->dev, "poll timeout\n"); 726 goto out; 727 } 728 729 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 730 MT7531_MDIO_REG_ADDR(regnum); 731 732 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 733 734 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 735 !(val & MT7531_PHY_ACS_ST), 20, 100000); 736 if (ret < 0) { 737 dev_err(priv->dev, "poll timeout\n"); 738 goto out; 739 } 740 741 ret = val & MT7531_MDIO_RW_DATA_MASK; 742 out: 743 mutex_unlock(&bus->mdio_lock); 744 745 return ret; 746 } 747 748 static int 749 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 750 u16 data) 751 { 752 struct mii_bus *bus = priv->bus; 753 struct mt7530_dummy_poll p; 754 int ret; 755 u32 reg; 756 757 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 758 759 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 760 761 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 762 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 763 if (ret < 0) { 764 dev_err(priv->dev, "poll timeout\n"); 765 goto out; 766 } 767 768 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 769 MT7531_MDIO_REG_ADDR(regnum) | data; 770 771 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 772 773 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 774 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 775 if (ret < 0) { 776 dev_err(priv->dev, "poll timeout\n"); 777 goto out; 778 } 779 780 out: 781 mutex_unlock(&bus->mdio_lock); 782 783 return ret; 784 } 785 786 static int 787 mt7531_ind_phy_read(struct mt7530_priv *priv, int port, int regnum) 788 { 789 int devad; 790 int ret; 791 792 if (regnum & MII_ADDR_C45) { 793 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; 794 ret = mt7531_ind_c45_phy_read(priv, port, devad, 795 regnum & MII_REGADDR_C45_MASK); 796 } else { 797 ret = mt7531_ind_c22_phy_read(priv, port, regnum); 798 } 799 800 return ret; 801 } 802 803 static int 804 mt7531_ind_phy_write(struct mt7530_priv *priv, int port, int regnum, 805 u16 data) 806 { 807 int devad; 808 int ret; 809 810 if (regnum & MII_ADDR_C45) { 811 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; 812 ret = mt7531_ind_c45_phy_write(priv, port, devad, 813 regnum & MII_REGADDR_C45_MASK, 814 data); 815 } else { 816 ret = mt7531_ind_c22_phy_write(priv, port, regnum, data); 817 } 818 819 return ret; 820 } 821 822 static int 823 mt753x_phy_read(struct mii_bus *bus, int port, int regnum) 824 { 825 struct mt7530_priv *priv = bus->priv; 826 827 return priv->info->phy_read(priv, port, regnum); 828 } 829 830 static int 831 mt753x_phy_write(struct mii_bus *bus, int port, int regnum, u16 val) 832 { 833 struct mt7530_priv *priv = bus->priv; 834 835 return priv->info->phy_write(priv, port, regnum, val); 836 } 837 838 static void 839 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 840 uint8_t *data) 841 { 842 int i; 843 844 if (stringset != ETH_SS_STATS) 845 return; 846 847 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 848 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 849 ETH_GSTRING_LEN); 850 } 851 852 static void 853 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 854 uint64_t *data) 855 { 856 struct mt7530_priv *priv = ds->priv; 857 const struct mt7530_mib_desc *mib; 858 u32 reg, i; 859 u64 hi; 860 861 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 862 mib = &mt7530_mib[i]; 863 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 864 865 data[i] = mt7530_read(priv, reg); 866 if (mib->size == 2) { 867 hi = mt7530_read(priv, reg + 4); 868 data[i] |= hi << 32; 869 } 870 } 871 } 872 873 static int 874 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 875 { 876 if (sset != ETH_SS_STATS) 877 return 0; 878 879 return ARRAY_SIZE(mt7530_mib); 880 } 881 882 static int 883 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 884 { 885 struct mt7530_priv *priv = ds->priv; 886 unsigned int secs = msecs / 1000; 887 unsigned int tmp_age_count; 888 unsigned int error = -1; 889 unsigned int age_count; 890 unsigned int age_unit; 891 892 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 893 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 894 return -ERANGE; 895 896 /* iterate through all possible age_count to find the closest pair */ 897 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 898 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 899 900 if (tmp_age_unit <= AGE_UNIT_MAX) { 901 unsigned int tmp_error = secs - 902 (tmp_age_count + 1) * (tmp_age_unit + 1); 903 904 /* found a closer pair */ 905 if (error > tmp_error) { 906 error = tmp_error; 907 age_count = tmp_age_count; 908 age_unit = tmp_age_unit; 909 } 910 911 /* found the exact match, so break the loop */ 912 if (!error) 913 break; 914 } 915 } 916 917 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 918 919 return 0; 920 } 921 922 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 923 { 924 struct mt7530_priv *priv = ds->priv; 925 u8 tx_delay = 0; 926 int val; 927 928 mutex_lock(&priv->reg_mutex); 929 930 val = mt7530_read(priv, MT7530_MHWTRAP); 931 932 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 933 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 934 935 switch (priv->p5_intf_sel) { 936 case P5_INTF_SEL_PHY_P0: 937 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 938 val |= MHWTRAP_PHY0_SEL; 939 fallthrough; 940 case P5_INTF_SEL_PHY_P4: 941 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 942 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 943 944 /* Setup the MAC by default for the cpu port */ 945 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 946 break; 947 case P5_INTF_SEL_GMAC5: 948 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 949 val &= ~MHWTRAP_P5_DIS; 950 break; 951 case P5_DISABLED: 952 interface = PHY_INTERFACE_MODE_NA; 953 break; 954 default: 955 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", 956 priv->p5_intf_sel); 957 goto unlock_exit; 958 } 959 960 /* Setup RGMII settings */ 961 if (phy_interface_mode_is_rgmii(interface)) { 962 val |= MHWTRAP_P5_RGMII_MODE; 963 964 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 965 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 966 967 /* Don't set delay in DSA mode */ 968 if (!dsa_is_dsa_port(priv->ds, 5) && 969 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 970 interface == PHY_INTERFACE_MODE_RGMII_ID)) 971 tx_delay = 4; /* n * 0.5 ns */ 972 973 /* P5 RGMII TX Clock Control: delay x */ 974 mt7530_write(priv, MT7530_P5RGMIITXCR, 975 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 976 977 /* reduce P5 RGMII Tx driving, 8mA */ 978 mt7530_write(priv, MT7530_IO_DRV_CR, 979 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 980 } 981 982 mt7530_write(priv, MT7530_MHWTRAP, val); 983 984 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 985 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 986 987 priv->p5_interface = interface; 988 989 unlock_exit: 990 mutex_unlock(&priv->reg_mutex); 991 } 992 993 static int 994 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 995 { 996 struct mt7530_priv *priv = ds->priv; 997 int ret; 998 999 /* Setup max capability of CPU port at first */ 1000 if (priv->info->cpu_port_config) { 1001 ret = priv->info->cpu_port_config(ds, port); 1002 if (ret) 1003 return ret; 1004 } 1005 1006 /* Enable Mediatek header mode on the cpu port */ 1007 mt7530_write(priv, MT7530_PVC_P(port), 1008 PORT_SPEC_TAG); 1009 1010 /* Disable flooding by default */ 1011 mt7530_rmw(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK, 1012 BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port))); 1013 1014 /* Set CPU port number */ 1015 if (priv->id == ID_MT7621) 1016 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 1017 1018 /* CPU port gets connected to all user ports of 1019 * the switch. 1020 */ 1021 mt7530_write(priv, MT7530_PCR_P(port), 1022 PCR_MATRIX(dsa_user_ports(priv->ds))); 1023 1024 return 0; 1025 } 1026 1027 static int 1028 mt7530_port_enable(struct dsa_switch *ds, int port, 1029 struct phy_device *phy) 1030 { 1031 struct mt7530_priv *priv = ds->priv; 1032 1033 if (!dsa_is_user_port(ds, port)) 1034 return 0; 1035 1036 mutex_lock(&priv->reg_mutex); 1037 1038 /* Allow the user port gets connected to the cpu port and also 1039 * restore the port matrix if the port is the member of a certain 1040 * bridge. 1041 */ 1042 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); 1043 priv->ports[port].enable = true; 1044 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1045 priv->ports[port].pm); 1046 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1047 1048 mutex_unlock(&priv->reg_mutex); 1049 1050 return 0; 1051 } 1052 1053 static void 1054 mt7530_port_disable(struct dsa_switch *ds, int port) 1055 { 1056 struct mt7530_priv *priv = ds->priv; 1057 1058 if (!dsa_is_user_port(ds, port)) 1059 return; 1060 1061 mutex_lock(&priv->reg_mutex); 1062 1063 /* Clear up all port matrix which could be restored in the next 1064 * enablement for the port. 1065 */ 1066 priv->ports[port].enable = false; 1067 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1068 PCR_MATRIX_CLR); 1069 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1070 1071 mutex_unlock(&priv->reg_mutex); 1072 } 1073 1074 static int 1075 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1076 { 1077 struct mt7530_priv *priv = ds->priv; 1078 struct mii_bus *bus = priv->bus; 1079 int length; 1080 u32 val; 1081 1082 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1083 * largest MTU of the slave ports. Because the switch only has a global 1084 * RX length register, only allowing CPU port here is enough. 1085 */ 1086 if (!dsa_is_cpu_port(ds, port)) 1087 return 0; 1088 1089 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 1090 1091 val = mt7530_mii_read(priv, MT7530_GMACCR); 1092 val &= ~MAX_RX_PKT_LEN_MASK; 1093 1094 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1095 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1096 if (length <= 1522) { 1097 val |= MAX_RX_PKT_LEN_1522; 1098 } else if (length <= 1536) { 1099 val |= MAX_RX_PKT_LEN_1536; 1100 } else if (length <= 1552) { 1101 val |= MAX_RX_PKT_LEN_1552; 1102 } else { 1103 val &= ~MAX_RX_JUMBO_MASK; 1104 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1105 val |= MAX_RX_PKT_LEN_JUMBO; 1106 } 1107 1108 mt7530_mii_write(priv, MT7530_GMACCR, val); 1109 1110 mutex_unlock(&bus->mdio_lock); 1111 1112 return 0; 1113 } 1114 1115 static int 1116 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1117 { 1118 return MT7530_MAX_MTU; 1119 } 1120 1121 static void 1122 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1123 { 1124 struct mt7530_priv *priv = ds->priv; 1125 u32 stp_state; 1126 1127 switch (state) { 1128 case BR_STATE_DISABLED: 1129 stp_state = MT7530_STP_DISABLED; 1130 break; 1131 case BR_STATE_BLOCKING: 1132 stp_state = MT7530_STP_BLOCKING; 1133 break; 1134 case BR_STATE_LISTENING: 1135 stp_state = MT7530_STP_LISTENING; 1136 break; 1137 case BR_STATE_LEARNING: 1138 stp_state = MT7530_STP_LEARNING; 1139 break; 1140 case BR_STATE_FORWARDING: 1141 default: 1142 stp_state = MT7530_STP_FORWARDING; 1143 break; 1144 } 1145 1146 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state); 1147 } 1148 1149 static int 1150 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1151 struct switchdev_brport_flags flags, 1152 struct netlink_ext_ack *extack) 1153 { 1154 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1155 BR_BCAST_FLOOD)) 1156 return -EINVAL; 1157 1158 return 0; 1159 } 1160 1161 static int 1162 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1163 struct switchdev_brport_flags flags, 1164 struct netlink_ext_ack *extack) 1165 { 1166 struct mt7530_priv *priv = ds->priv; 1167 1168 if (flags.mask & BR_LEARNING) 1169 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1170 flags.val & BR_LEARNING ? 0 : SA_DIS); 1171 1172 if (flags.mask & BR_FLOOD) 1173 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), 1174 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1175 1176 if (flags.mask & BR_MCAST_FLOOD) 1177 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1178 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1179 1180 if (flags.mask & BR_BCAST_FLOOD) 1181 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), 1182 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1183 1184 return 0; 1185 } 1186 1187 static int 1188 mt7530_port_set_mrouter(struct dsa_switch *ds, int port, bool mrouter, 1189 struct netlink_ext_ack *extack) 1190 { 1191 struct mt7530_priv *priv = ds->priv; 1192 1193 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1194 mrouter ? UNM_FFP(BIT(port)) : 0); 1195 1196 return 0; 1197 } 1198 1199 static int 1200 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1201 struct net_device *bridge) 1202 { 1203 struct mt7530_priv *priv = ds->priv; 1204 u32 port_bitmap = BIT(MT7530_CPU_PORT); 1205 int i; 1206 1207 mutex_lock(&priv->reg_mutex); 1208 1209 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1210 /* Add this port to the port matrix of the other ports in the 1211 * same bridge. If the port is disabled, port matrix is kept 1212 * and not being setup until the port becomes enabled. 1213 */ 1214 if (dsa_is_user_port(ds, i) && i != port) { 1215 if (dsa_to_port(ds, i)->bridge_dev != bridge) 1216 continue; 1217 if (priv->ports[i].enable) 1218 mt7530_set(priv, MT7530_PCR_P(i), 1219 PCR_MATRIX(BIT(port))); 1220 priv->ports[i].pm |= PCR_MATRIX(BIT(port)); 1221 1222 port_bitmap |= BIT(i); 1223 } 1224 } 1225 1226 /* Add the all other ports to this port matrix. */ 1227 if (priv->ports[port].enable) 1228 mt7530_rmw(priv, MT7530_PCR_P(port), 1229 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1230 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1231 1232 mutex_unlock(&priv->reg_mutex); 1233 1234 return 0; 1235 } 1236 1237 static void 1238 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1239 { 1240 struct mt7530_priv *priv = ds->priv; 1241 bool all_user_ports_removed = true; 1242 int i; 1243 1244 /* When a port is removed from the bridge, the port would be set up 1245 * back to the default as is at initial boot which is a VLAN-unaware 1246 * port. 1247 */ 1248 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1249 MT7530_PORT_MATRIX_MODE); 1250 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1251 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1252 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1253 1254 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1255 if (dsa_is_user_port(ds, i) && 1256 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1257 all_user_ports_removed = false; 1258 break; 1259 } 1260 } 1261 1262 /* CPU port also does the same thing until all user ports belonging to 1263 * the CPU port get out of VLAN filtering mode. 1264 */ 1265 if (all_user_ports_removed) { 1266 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT), 1267 PCR_MATRIX(dsa_user_ports(priv->ds))); 1268 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG 1269 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1270 } 1271 } 1272 1273 static void 1274 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1275 { 1276 struct mt7530_priv *priv = ds->priv; 1277 1278 /* Trapped into security mode allows packet forwarding through VLAN 1279 * table lookup. CPU port is set to fallback mode to let untagged 1280 * frames pass through. 1281 */ 1282 if (dsa_is_cpu_port(ds, port)) 1283 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1284 MT7530_PORT_FALLBACK_MODE); 1285 else 1286 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1287 MT7530_PORT_SECURITY_MODE); 1288 1289 /* Set the port as a user port which is to be able to recognize VID 1290 * from incoming packets before fetching entry within the VLAN table. 1291 */ 1292 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1293 VLAN_ATTR(MT7530_VLAN_USER) | 1294 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1295 } 1296 1297 static void 1298 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1299 struct net_device *bridge) 1300 { 1301 struct mt7530_priv *priv = ds->priv; 1302 int i; 1303 1304 mutex_lock(&priv->reg_mutex); 1305 1306 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1307 /* Remove this port from the port matrix of the other ports 1308 * in the same bridge. If the port is disabled, port matrix 1309 * is kept and not being setup until the port becomes enabled. 1310 * And the other port's port matrix cannot be broken when the 1311 * other port is still a VLAN-aware port. 1312 */ 1313 if (dsa_is_user_port(ds, i) && i != port && 1314 !dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1315 if (dsa_to_port(ds, i)->bridge_dev != bridge) 1316 continue; 1317 if (priv->ports[i].enable) 1318 mt7530_clear(priv, MT7530_PCR_P(i), 1319 PCR_MATRIX(BIT(port))); 1320 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port)); 1321 } 1322 } 1323 1324 /* Set the cpu port to be the only one in the port matrix of 1325 * this port. 1326 */ 1327 if (priv->ports[port].enable) 1328 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1329 PCR_MATRIX(BIT(MT7530_CPU_PORT))); 1330 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); 1331 1332 mutex_unlock(&priv->reg_mutex); 1333 } 1334 1335 static int 1336 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1337 const unsigned char *addr, u16 vid) 1338 { 1339 struct mt7530_priv *priv = ds->priv; 1340 int ret; 1341 u8 port_mask = BIT(port); 1342 1343 mutex_lock(&priv->reg_mutex); 1344 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1345 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1346 mutex_unlock(&priv->reg_mutex); 1347 1348 return ret; 1349 } 1350 1351 static int 1352 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1353 const unsigned char *addr, u16 vid) 1354 { 1355 struct mt7530_priv *priv = ds->priv; 1356 int ret; 1357 u8 port_mask = BIT(port); 1358 1359 mutex_lock(&priv->reg_mutex); 1360 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1361 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1362 mutex_unlock(&priv->reg_mutex); 1363 1364 return ret; 1365 } 1366 1367 static int 1368 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1369 dsa_fdb_dump_cb_t *cb, void *data) 1370 { 1371 struct mt7530_priv *priv = ds->priv; 1372 struct mt7530_fdb _fdb = { 0 }; 1373 int cnt = MT7530_NUM_FDB_RECORDS; 1374 int ret = 0; 1375 u32 rsp = 0; 1376 1377 mutex_lock(&priv->reg_mutex); 1378 1379 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1380 if (ret < 0) 1381 goto err; 1382 1383 do { 1384 if (rsp & ATC_SRCH_HIT) { 1385 mt7530_fdb_read(priv, &_fdb); 1386 if (_fdb.port_mask & BIT(port)) { 1387 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1388 data); 1389 if (ret < 0) 1390 break; 1391 } 1392 } 1393 } while (--cnt && 1394 !(rsp & ATC_SRCH_END) && 1395 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1396 err: 1397 mutex_unlock(&priv->reg_mutex); 1398 1399 return 0; 1400 } 1401 1402 static int 1403 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1404 const struct switchdev_obj_port_mdb *mdb) 1405 { 1406 struct mt7530_priv *priv = ds->priv; 1407 const u8 *addr = mdb->addr; 1408 u16 vid = mdb->vid; 1409 u8 port_mask = 0; 1410 int ret; 1411 1412 mutex_lock(&priv->reg_mutex); 1413 1414 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1415 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1416 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1417 & PORT_MAP_MASK; 1418 1419 port_mask |= BIT(port); 1420 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1421 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1422 1423 mutex_unlock(&priv->reg_mutex); 1424 1425 return ret; 1426 } 1427 1428 static int 1429 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1430 const struct switchdev_obj_port_mdb *mdb) 1431 { 1432 struct mt7530_priv *priv = ds->priv; 1433 const u8 *addr = mdb->addr; 1434 u16 vid = mdb->vid; 1435 u8 port_mask = 0; 1436 int ret; 1437 1438 mutex_lock(&priv->reg_mutex); 1439 1440 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1441 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1442 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1443 & PORT_MAP_MASK; 1444 1445 port_mask &= ~BIT(port); 1446 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1447 port_mask ? STATIC_ENT : STATIC_EMP); 1448 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1449 1450 mutex_unlock(&priv->reg_mutex); 1451 1452 return ret; 1453 } 1454 1455 static int 1456 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1457 { 1458 struct mt7530_dummy_poll p; 1459 u32 val; 1460 int ret; 1461 1462 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1463 mt7530_write(priv, MT7530_VTCR, val); 1464 1465 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1466 ret = readx_poll_timeout(_mt7530_read, &p, val, 1467 !(val & VTCR_BUSY), 20, 20000); 1468 if (ret < 0) { 1469 dev_err(priv->dev, "poll timeout\n"); 1470 return ret; 1471 } 1472 1473 val = mt7530_read(priv, MT7530_VTCR); 1474 if (val & VTCR_INVALID) { 1475 dev_err(priv->dev, "read VTCR invalid\n"); 1476 return -EINVAL; 1477 } 1478 1479 return 0; 1480 } 1481 1482 static int 1483 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1484 struct netlink_ext_ack *extack) 1485 { 1486 if (vlan_filtering) { 1487 /* The port is being kept as VLAN-unaware port when bridge is 1488 * set up with vlan_filtering not being set, Otherwise, the 1489 * port and the corresponding CPU port is required the setup 1490 * for becoming a VLAN-aware port. 1491 */ 1492 mt7530_port_set_vlan_aware(ds, port); 1493 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT); 1494 } else { 1495 mt7530_port_set_vlan_unaware(ds, port); 1496 } 1497 1498 return 0; 1499 } 1500 1501 static void 1502 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1503 struct mt7530_hw_vlan_entry *entry) 1504 { 1505 u8 new_members; 1506 u32 val; 1507 1508 new_members = entry->old_members | BIT(entry->port) | 1509 BIT(MT7530_CPU_PORT); 1510 1511 /* Validate the entry with independent learning, create egress tag per 1512 * VLAN and joining the port as one of the port members. 1513 */ 1514 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID; 1515 mt7530_write(priv, MT7530_VAWD1, val); 1516 1517 /* Decide whether adding tag or not for those outgoing packets from the 1518 * port inside the VLAN. 1519 */ 1520 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG : 1521 MT7530_VLAN_EGRESS_TAG; 1522 mt7530_rmw(priv, MT7530_VAWD2, 1523 ETAG_CTRL_P_MASK(entry->port), 1524 ETAG_CTRL_P(entry->port, val)); 1525 1526 /* CPU port is always taken as a tagged port for serving more than one 1527 * VLANs across and also being applied with egress type stack mode for 1528 * that VLAN tags would be appended after hardware special tag used as 1529 * DSA tag. 1530 */ 1531 mt7530_rmw(priv, MT7530_VAWD2, 1532 ETAG_CTRL_P_MASK(MT7530_CPU_PORT), 1533 ETAG_CTRL_P(MT7530_CPU_PORT, 1534 MT7530_VLAN_EGRESS_STACK)); 1535 } 1536 1537 static void 1538 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1539 struct mt7530_hw_vlan_entry *entry) 1540 { 1541 u8 new_members; 1542 u32 val; 1543 1544 new_members = entry->old_members & ~BIT(entry->port); 1545 1546 val = mt7530_read(priv, MT7530_VAWD1); 1547 if (!(val & VLAN_VALID)) { 1548 dev_err(priv->dev, 1549 "Cannot be deleted due to invalid entry\n"); 1550 return; 1551 } 1552 1553 /* If certain member apart from CPU port is still alive in the VLAN, 1554 * the entry would be kept valid. Otherwise, the entry is got to be 1555 * disabled. 1556 */ 1557 if (new_members && new_members != BIT(MT7530_CPU_PORT)) { 1558 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1559 VLAN_VALID; 1560 mt7530_write(priv, MT7530_VAWD1, val); 1561 } else { 1562 mt7530_write(priv, MT7530_VAWD1, 0); 1563 mt7530_write(priv, MT7530_VAWD2, 0); 1564 } 1565 } 1566 1567 static void 1568 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1569 struct mt7530_hw_vlan_entry *entry, 1570 mt7530_vlan_op vlan_op) 1571 { 1572 u32 val; 1573 1574 /* Fetch entry */ 1575 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1576 1577 val = mt7530_read(priv, MT7530_VAWD1); 1578 1579 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1580 1581 /* Manipulate entry */ 1582 vlan_op(priv, entry); 1583 1584 /* Flush result to hardware */ 1585 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1586 } 1587 1588 static int 1589 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1590 const struct switchdev_obj_port_vlan *vlan, 1591 struct netlink_ext_ack *extack) 1592 { 1593 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1594 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1595 struct mt7530_hw_vlan_entry new_entry; 1596 struct mt7530_priv *priv = ds->priv; 1597 1598 mutex_lock(&priv->reg_mutex); 1599 1600 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1601 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1602 1603 if (pvid) { 1604 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1605 G0_PORT_VID(vlan->vid)); 1606 priv->ports[port].pvid = vlan->vid; 1607 } 1608 1609 mutex_unlock(&priv->reg_mutex); 1610 1611 return 0; 1612 } 1613 1614 static int 1615 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1616 const struct switchdev_obj_port_vlan *vlan) 1617 { 1618 struct mt7530_hw_vlan_entry target_entry; 1619 struct mt7530_priv *priv = ds->priv; 1620 u16 pvid; 1621 1622 mutex_lock(&priv->reg_mutex); 1623 1624 pvid = priv->ports[port].pvid; 1625 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1626 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1627 mt7530_hw_vlan_del); 1628 1629 /* PVID is being restored to the default whenever the PVID port 1630 * is being removed from the VLAN. 1631 */ 1632 if (pvid == vlan->vid) 1633 pvid = G0_PORT_VID_DEF; 1634 1635 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid); 1636 priv->ports[port].pvid = pvid; 1637 1638 mutex_unlock(&priv->reg_mutex); 1639 1640 return 0; 1641 } 1642 1643 static int mt753x_mirror_port_get(unsigned int id, u32 val) 1644 { 1645 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : 1646 MIRROR_PORT(val); 1647 } 1648 1649 static int mt753x_mirror_port_set(unsigned int id, u32 val) 1650 { 1651 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : 1652 MIRROR_PORT(val); 1653 } 1654 1655 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1656 struct dsa_mall_mirror_tc_entry *mirror, 1657 bool ingress) 1658 { 1659 struct mt7530_priv *priv = ds->priv; 1660 int monitor_port; 1661 u32 val; 1662 1663 /* Check for existent entry */ 1664 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1665 return -EEXIST; 1666 1667 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1668 1669 /* MT7530 only supports one monitor port */ 1670 monitor_port = mt753x_mirror_port_get(priv->id, val); 1671 if (val & MT753X_MIRROR_EN(priv->id) && 1672 monitor_port != mirror->to_local_port) 1673 return -EEXIST; 1674 1675 val |= MT753X_MIRROR_EN(priv->id); 1676 val &= ~MT753X_MIRROR_MASK(priv->id); 1677 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); 1678 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1679 1680 val = mt7530_read(priv, MT7530_PCR_P(port)); 1681 if (ingress) { 1682 val |= PORT_RX_MIR; 1683 priv->mirror_rx |= BIT(port); 1684 } else { 1685 val |= PORT_TX_MIR; 1686 priv->mirror_tx |= BIT(port); 1687 } 1688 mt7530_write(priv, MT7530_PCR_P(port), val); 1689 1690 return 0; 1691 } 1692 1693 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1694 struct dsa_mall_mirror_tc_entry *mirror) 1695 { 1696 struct mt7530_priv *priv = ds->priv; 1697 u32 val; 1698 1699 val = mt7530_read(priv, MT7530_PCR_P(port)); 1700 if (mirror->ingress) { 1701 val &= ~PORT_RX_MIR; 1702 priv->mirror_rx &= ~BIT(port); 1703 } else { 1704 val &= ~PORT_TX_MIR; 1705 priv->mirror_tx &= ~BIT(port); 1706 } 1707 mt7530_write(priv, MT7530_PCR_P(port), val); 1708 1709 if (!priv->mirror_rx && !priv->mirror_tx) { 1710 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1711 val &= ~MT753X_MIRROR_EN(priv->id); 1712 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1713 } 1714 } 1715 1716 static enum dsa_tag_protocol 1717 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1718 enum dsa_tag_protocol mp) 1719 { 1720 return DSA_TAG_PROTO_MTK; 1721 } 1722 1723 #ifdef CONFIG_GPIOLIB 1724 static inline u32 1725 mt7530_gpio_to_bit(unsigned int offset) 1726 { 1727 /* Map GPIO offset to register bit 1728 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1729 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1730 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1731 * [14:12] port 3 LED 0..2 as GPIO 9..11 1732 * [18:16] port 4 LED 0..2 as GPIO 12..14 1733 */ 1734 return BIT(offset + offset / 3); 1735 } 1736 1737 static int 1738 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1739 { 1740 struct mt7530_priv *priv = gpiochip_get_data(gc); 1741 u32 bit = mt7530_gpio_to_bit(offset); 1742 1743 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1744 } 1745 1746 static void 1747 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1748 { 1749 struct mt7530_priv *priv = gpiochip_get_data(gc); 1750 u32 bit = mt7530_gpio_to_bit(offset); 1751 1752 if (value) 1753 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1754 else 1755 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1756 } 1757 1758 static int 1759 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1760 { 1761 struct mt7530_priv *priv = gpiochip_get_data(gc); 1762 u32 bit = mt7530_gpio_to_bit(offset); 1763 1764 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1765 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1766 } 1767 1768 static int 1769 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1770 { 1771 struct mt7530_priv *priv = gpiochip_get_data(gc); 1772 u32 bit = mt7530_gpio_to_bit(offset); 1773 1774 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 1775 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 1776 1777 return 0; 1778 } 1779 1780 static int 1781 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 1782 { 1783 struct mt7530_priv *priv = gpiochip_get_data(gc); 1784 u32 bit = mt7530_gpio_to_bit(offset); 1785 1786 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 1787 1788 if (value) 1789 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1790 else 1791 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1792 1793 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 1794 1795 return 0; 1796 } 1797 1798 static int 1799 mt7530_setup_gpio(struct mt7530_priv *priv) 1800 { 1801 struct device *dev = priv->dev; 1802 struct gpio_chip *gc; 1803 1804 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1805 if (!gc) 1806 return -ENOMEM; 1807 1808 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 1809 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 1810 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 1811 1812 gc->label = "mt7530"; 1813 gc->parent = dev; 1814 gc->owner = THIS_MODULE; 1815 gc->get_direction = mt7530_gpio_get_direction; 1816 gc->direction_input = mt7530_gpio_direction_input; 1817 gc->direction_output = mt7530_gpio_direction_output; 1818 gc->get = mt7530_gpio_get; 1819 gc->set = mt7530_gpio_set; 1820 gc->base = -1; 1821 gc->ngpio = 15; 1822 gc->can_sleep = true; 1823 1824 return devm_gpiochip_add_data(dev, gc, priv); 1825 } 1826 #endif /* CONFIG_GPIOLIB */ 1827 1828 static irqreturn_t 1829 mt7530_irq_thread_fn(int irq, void *dev_id) 1830 { 1831 struct mt7530_priv *priv = dev_id; 1832 bool handled = false; 1833 u32 val; 1834 int p; 1835 1836 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 1837 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); 1838 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); 1839 mutex_unlock(&priv->bus->mdio_lock); 1840 1841 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1842 if (BIT(p) & val) { 1843 unsigned int irq; 1844 1845 irq = irq_find_mapping(priv->irq_domain, p); 1846 handle_nested_irq(irq); 1847 handled = true; 1848 } 1849 } 1850 1851 return IRQ_RETVAL(handled); 1852 } 1853 1854 static void 1855 mt7530_irq_mask(struct irq_data *d) 1856 { 1857 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1858 1859 priv->irq_enable &= ~BIT(d->hwirq); 1860 } 1861 1862 static void 1863 mt7530_irq_unmask(struct irq_data *d) 1864 { 1865 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1866 1867 priv->irq_enable |= BIT(d->hwirq); 1868 } 1869 1870 static void 1871 mt7530_irq_bus_lock(struct irq_data *d) 1872 { 1873 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1874 1875 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 1876 } 1877 1878 static void 1879 mt7530_irq_bus_sync_unlock(struct irq_data *d) 1880 { 1881 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1882 1883 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 1884 mutex_unlock(&priv->bus->mdio_lock); 1885 } 1886 1887 static struct irq_chip mt7530_irq_chip = { 1888 .name = KBUILD_MODNAME, 1889 .irq_mask = mt7530_irq_mask, 1890 .irq_unmask = mt7530_irq_unmask, 1891 .irq_bus_lock = mt7530_irq_bus_lock, 1892 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, 1893 }; 1894 1895 static int 1896 mt7530_irq_map(struct irq_domain *domain, unsigned int irq, 1897 irq_hw_number_t hwirq) 1898 { 1899 irq_set_chip_data(irq, domain->host_data); 1900 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); 1901 irq_set_nested_thread(irq, true); 1902 irq_set_noprobe(irq); 1903 1904 return 0; 1905 } 1906 1907 static const struct irq_domain_ops mt7530_irq_domain_ops = { 1908 .map = mt7530_irq_map, 1909 .xlate = irq_domain_xlate_onecell, 1910 }; 1911 1912 static void 1913 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 1914 { 1915 struct dsa_switch *ds = priv->ds; 1916 int p; 1917 1918 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1919 if (BIT(p) & ds->phys_mii_mask) { 1920 unsigned int irq; 1921 1922 irq = irq_create_mapping(priv->irq_domain, p); 1923 ds->slave_mii_bus->irq[p] = irq; 1924 } 1925 } 1926 } 1927 1928 static int 1929 mt7530_setup_irq(struct mt7530_priv *priv) 1930 { 1931 struct device *dev = priv->dev; 1932 struct device_node *np = dev->of_node; 1933 int ret; 1934 1935 if (!of_property_read_bool(np, "interrupt-controller")) { 1936 dev_info(dev, "no interrupt support\n"); 1937 return 0; 1938 } 1939 1940 priv->irq = of_irq_get(np, 0); 1941 if (priv->irq <= 0) { 1942 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); 1943 return priv->irq ? : -EINVAL; 1944 } 1945 1946 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 1947 &mt7530_irq_domain_ops, priv); 1948 if (!priv->irq_domain) { 1949 dev_err(dev, "failed to create IRQ domain\n"); 1950 return -ENOMEM; 1951 } 1952 1953 /* This register must be set for MT7530 to properly fire interrupts */ 1954 if (priv->id != ID_MT7531) 1955 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 1956 1957 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, 1958 IRQF_ONESHOT, KBUILD_MODNAME, priv); 1959 if (ret) { 1960 irq_domain_remove(priv->irq_domain); 1961 dev_err(dev, "failed to request IRQ: %d\n", ret); 1962 return ret; 1963 } 1964 1965 return 0; 1966 } 1967 1968 static void 1969 mt7530_free_mdio_irq(struct mt7530_priv *priv) 1970 { 1971 int p; 1972 1973 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1974 if (BIT(p) & priv->ds->phys_mii_mask) { 1975 unsigned int irq; 1976 1977 irq = irq_find_mapping(priv->irq_domain, p); 1978 irq_dispose_mapping(irq); 1979 } 1980 } 1981 } 1982 1983 static void 1984 mt7530_free_irq_common(struct mt7530_priv *priv) 1985 { 1986 free_irq(priv->irq, priv); 1987 irq_domain_remove(priv->irq_domain); 1988 } 1989 1990 static void 1991 mt7530_free_irq(struct mt7530_priv *priv) 1992 { 1993 mt7530_free_mdio_irq(priv); 1994 mt7530_free_irq_common(priv); 1995 } 1996 1997 static int 1998 mt7530_setup_mdio(struct mt7530_priv *priv) 1999 { 2000 struct dsa_switch *ds = priv->ds; 2001 struct device *dev = priv->dev; 2002 struct mii_bus *bus; 2003 static int idx; 2004 int ret; 2005 2006 bus = devm_mdiobus_alloc(dev); 2007 if (!bus) 2008 return -ENOMEM; 2009 2010 ds->slave_mii_bus = bus; 2011 bus->priv = priv; 2012 bus->name = KBUILD_MODNAME "-mii"; 2013 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2014 bus->read = mt753x_phy_read; 2015 bus->write = mt753x_phy_write; 2016 bus->parent = dev; 2017 bus->phy_mask = ~ds->phys_mii_mask; 2018 2019 if (priv->irq) 2020 mt7530_setup_mdio_irq(priv); 2021 2022 ret = mdiobus_register(bus); 2023 if (ret) { 2024 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2025 if (priv->irq) 2026 mt7530_free_mdio_irq(priv); 2027 } 2028 2029 return ret; 2030 } 2031 2032 static int 2033 mt7530_setup(struct dsa_switch *ds) 2034 { 2035 struct mt7530_priv *priv = ds->priv; 2036 struct device_node *phy_node; 2037 struct device_node *mac_np; 2038 struct mt7530_dummy_poll p; 2039 phy_interface_t interface; 2040 struct device_node *dn; 2041 u32 id, val; 2042 int ret, i; 2043 2044 /* The parent node of master netdev which holds the common system 2045 * controller also is the container for two GMACs nodes representing 2046 * as two netdev instances. 2047 */ 2048 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent; 2049 ds->mtu_enforcement_ingress = true; 2050 2051 if (priv->id == ID_MT7530) { 2052 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2053 ret = regulator_enable(priv->core_pwr); 2054 if (ret < 0) { 2055 dev_err(priv->dev, 2056 "Failed to enable core power: %d\n", ret); 2057 return ret; 2058 } 2059 2060 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2061 ret = regulator_enable(priv->io_pwr); 2062 if (ret < 0) { 2063 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2064 ret); 2065 return ret; 2066 } 2067 } 2068 2069 /* Reset whole chip through gpio pin or memory-mapped registers for 2070 * different type of hardware 2071 */ 2072 if (priv->mcm) { 2073 reset_control_assert(priv->rstc); 2074 usleep_range(1000, 1100); 2075 reset_control_deassert(priv->rstc); 2076 } else { 2077 gpiod_set_value_cansleep(priv->reset, 0); 2078 usleep_range(1000, 1100); 2079 gpiod_set_value_cansleep(priv->reset, 1); 2080 } 2081 2082 /* Waiting for MT7530 got to stable */ 2083 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2084 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2085 20, 1000000); 2086 if (ret < 0) { 2087 dev_err(priv->dev, "reset timeout\n"); 2088 return ret; 2089 } 2090 2091 id = mt7530_read(priv, MT7530_CREV); 2092 id >>= CHIP_NAME_SHIFT; 2093 if (id != MT7530_ID) { 2094 dev_err(priv->dev, "chip %x can't be supported\n", id); 2095 return -ENODEV; 2096 } 2097 2098 /* Reset the switch through internal reset */ 2099 mt7530_write(priv, MT7530_SYS_CTRL, 2100 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2101 SYS_CTRL_REG_RST); 2102 2103 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */ 2104 val = mt7530_read(priv, MT7530_MHWTRAP); 2105 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 2106 val |= MHWTRAP_MANUAL; 2107 mt7530_write(priv, MT7530_MHWTRAP, val); 2108 2109 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2110 2111 /* Enable and reset MIB counters */ 2112 mt7530_mib_reset(ds); 2113 2114 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2115 /* Disable forwarding by default on all ports */ 2116 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2117 PCR_MATRIX_CLR); 2118 2119 if (dsa_is_cpu_port(ds, i)) { 2120 ret = mt753x_cpu_port_enable(ds, i); 2121 if (ret) 2122 return ret; 2123 } else { 2124 mt7530_port_disable(ds, i); 2125 2126 /* Disable learning by default on all user ports */ 2127 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2128 } 2129 /* Enable consistent egress tag */ 2130 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2131 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2132 } 2133 2134 /* Setup port 5 */ 2135 priv->p5_intf_sel = P5_DISABLED; 2136 interface = PHY_INTERFACE_MODE_NA; 2137 2138 if (!dsa_is_unused_port(ds, 5)) { 2139 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2140 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); 2141 if (ret && ret != -ENODEV) 2142 return ret; 2143 } else { 2144 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ 2145 for_each_child_of_node(dn, mac_np) { 2146 if (!of_device_is_compatible(mac_np, 2147 "mediatek,eth-mac")) 2148 continue; 2149 2150 ret = of_property_read_u32(mac_np, "reg", &id); 2151 if (ret < 0 || id != 1) 2152 continue; 2153 2154 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2155 if (!phy_node) 2156 continue; 2157 2158 if (phy_node->parent == priv->dev->of_node->parent) { 2159 ret = of_get_phy_mode(mac_np, &interface); 2160 if (ret && ret != -ENODEV) { 2161 of_node_put(mac_np); 2162 return ret; 2163 } 2164 id = of_mdio_parse_addr(ds->dev, phy_node); 2165 if (id == 0) 2166 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 2167 if (id == 4) 2168 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 2169 } 2170 of_node_put(mac_np); 2171 of_node_put(phy_node); 2172 break; 2173 } 2174 } 2175 2176 #ifdef CONFIG_GPIOLIB 2177 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2178 ret = mt7530_setup_gpio(priv); 2179 if (ret) 2180 return ret; 2181 } 2182 #endif /* CONFIG_GPIOLIB */ 2183 2184 mt7530_setup_port5(ds, interface); 2185 2186 /* Flush the FDB table */ 2187 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2188 if (ret < 0) 2189 return ret; 2190 2191 return 0; 2192 } 2193 2194 static int 2195 mt7531_setup(struct dsa_switch *ds) 2196 { 2197 struct mt7530_priv *priv = ds->priv; 2198 struct mt7530_dummy_poll p; 2199 u32 val, id; 2200 int ret, i; 2201 2202 /* Reset whole chip through gpio pin or memory-mapped registers for 2203 * different type of hardware 2204 */ 2205 if (priv->mcm) { 2206 reset_control_assert(priv->rstc); 2207 usleep_range(1000, 1100); 2208 reset_control_deassert(priv->rstc); 2209 } else { 2210 gpiod_set_value_cansleep(priv->reset, 0); 2211 usleep_range(1000, 1100); 2212 gpiod_set_value_cansleep(priv->reset, 1); 2213 } 2214 2215 /* Waiting for MT7530 got to stable */ 2216 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2217 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2218 20, 1000000); 2219 if (ret < 0) { 2220 dev_err(priv->dev, "reset timeout\n"); 2221 return ret; 2222 } 2223 2224 id = mt7530_read(priv, MT7531_CREV); 2225 id >>= CHIP_NAME_SHIFT; 2226 2227 if (id != MT7531_ID) { 2228 dev_err(priv->dev, "chip %x can't be supported\n", id); 2229 return -ENODEV; 2230 } 2231 2232 /* Reset the switch through internal reset */ 2233 mt7530_write(priv, MT7530_SYS_CTRL, 2234 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2235 SYS_CTRL_REG_RST); 2236 2237 if (mt7531_dual_sgmii_supported(priv)) { 2238 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; 2239 2240 /* Let ds->slave_mii_bus be able to access external phy. */ 2241 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2242 MT7531_EXT_P_MDC_11); 2243 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2244 MT7531_EXT_P_MDIO_12); 2245 } else { 2246 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2247 } 2248 dev_dbg(ds->dev, "P5 support %s interface\n", 2249 p5_intf_modes(priv->p5_intf_sel)); 2250 2251 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2252 MT7531_GPIO0_INTERRUPT); 2253 2254 /* Let phylink decide the interface later. */ 2255 priv->p5_interface = PHY_INTERFACE_MODE_NA; 2256 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2257 2258 /* Enable PHY core PLL, since phy_device has not yet been created 2259 * provided for phy_[read,write]_mmd_indirect is called, we provide 2260 * our own mt7531_ind_mmd_phy_[read,write] to complete this 2261 * function. 2262 */ 2263 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, 2264 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2265 val |= MT7531_PHY_PLL_BYPASS_MODE; 2266 val &= ~MT7531_PHY_PLL_OFF; 2267 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, 2268 CORE_PLL_GROUP4, val); 2269 2270 /* BPDU to CPU port */ 2271 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, 2272 BIT(MT7530_CPU_PORT)); 2273 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, 2274 MT753X_BPDU_CPU_ONLY); 2275 2276 /* Enable and reset MIB counters */ 2277 mt7530_mib_reset(ds); 2278 2279 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2280 /* Disable forwarding by default on all ports */ 2281 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2282 PCR_MATRIX_CLR); 2283 2284 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2285 2286 if (dsa_is_cpu_port(ds, i)) { 2287 ret = mt753x_cpu_port_enable(ds, i); 2288 if (ret) 2289 return ret; 2290 } else { 2291 mt7530_port_disable(ds, i); 2292 2293 /* Disable learning by default on all user ports */ 2294 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2295 } 2296 2297 /* Enable consistent egress tag */ 2298 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2299 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2300 } 2301 2302 ds->mtu_enforcement_ingress = true; 2303 2304 /* Flush the FDB table */ 2305 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2306 if (ret < 0) 2307 return ret; 2308 2309 return 0; 2310 } 2311 2312 static bool 2313 mt7530_phy_mode_supported(struct dsa_switch *ds, int port, 2314 const struct phylink_link_state *state) 2315 { 2316 struct mt7530_priv *priv = ds->priv; 2317 2318 switch (port) { 2319 case 0 ... 4: /* Internal phy */ 2320 if (state->interface != PHY_INTERFACE_MODE_GMII) 2321 return false; 2322 break; 2323 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2324 if (!phy_interface_mode_is_rgmii(state->interface) && 2325 state->interface != PHY_INTERFACE_MODE_MII && 2326 state->interface != PHY_INTERFACE_MODE_GMII) 2327 return false; 2328 break; 2329 case 6: /* 1st cpu port */ 2330 if (state->interface != PHY_INTERFACE_MODE_RGMII && 2331 state->interface != PHY_INTERFACE_MODE_TRGMII) 2332 return false; 2333 break; 2334 default: 2335 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, 2336 port); 2337 return false; 2338 } 2339 2340 return true; 2341 } 2342 2343 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) 2344 { 2345 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); 2346 } 2347 2348 static bool 2349 mt7531_phy_mode_supported(struct dsa_switch *ds, int port, 2350 const struct phylink_link_state *state) 2351 { 2352 struct mt7530_priv *priv = ds->priv; 2353 2354 switch (port) { 2355 case 0 ... 4: /* Internal phy */ 2356 if (state->interface != PHY_INTERFACE_MODE_GMII) 2357 return false; 2358 break; 2359 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ 2360 if (mt7531_is_rgmii_port(priv, port)) 2361 return phy_interface_mode_is_rgmii(state->interface); 2362 fallthrough; 2363 case 6: /* 1st cpu port supports sgmii/8023z only */ 2364 if (state->interface != PHY_INTERFACE_MODE_SGMII && 2365 !phy_interface_mode_is_8023z(state->interface)) 2366 return false; 2367 break; 2368 default: 2369 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, 2370 port); 2371 return false; 2372 } 2373 2374 return true; 2375 } 2376 2377 static bool 2378 mt753x_phy_mode_supported(struct dsa_switch *ds, int port, 2379 const struct phylink_link_state *state) 2380 { 2381 struct mt7530_priv *priv = ds->priv; 2382 2383 return priv->info->phy_mode_supported(ds, port, state); 2384 } 2385 2386 static int 2387 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) 2388 { 2389 struct mt7530_priv *priv = ds->priv; 2390 2391 return priv->info->pad_setup(ds, state->interface); 2392 } 2393 2394 static int 2395 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2396 phy_interface_t interface) 2397 { 2398 struct mt7530_priv *priv = ds->priv; 2399 2400 /* Only need to setup port5. */ 2401 if (port != 5) 2402 return 0; 2403 2404 mt7530_setup_port5(priv->ds, interface); 2405 2406 return 0; 2407 } 2408 2409 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 2410 phy_interface_t interface, 2411 struct phy_device *phydev) 2412 { 2413 u32 val; 2414 2415 if (!mt7531_is_rgmii_port(priv, port)) { 2416 dev_err(priv->dev, "RGMII mode is not available for port %d\n", 2417 port); 2418 return -EINVAL; 2419 } 2420 2421 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2422 val |= GP_CLK_EN; 2423 val &= ~GP_MODE_MASK; 2424 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2425 val &= ~CLK_SKEW_IN_MASK; 2426 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2427 val &= ~CLK_SKEW_OUT_MASK; 2428 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2429 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2430 2431 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2432 if (!phydev || phy_driver_is_genphy(phydev)) { 2433 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2434 switch (interface) { 2435 case PHY_INTERFACE_MODE_RGMII: 2436 val |= TXCLK_NO_REVERSE; 2437 val |= RXCLK_NO_DELAY; 2438 break; 2439 case PHY_INTERFACE_MODE_RGMII_RXID: 2440 val |= TXCLK_NO_REVERSE; 2441 break; 2442 case PHY_INTERFACE_MODE_RGMII_TXID: 2443 val |= RXCLK_NO_DELAY; 2444 break; 2445 case PHY_INTERFACE_MODE_RGMII_ID: 2446 break; 2447 default: 2448 return -EINVAL; 2449 } 2450 } 2451 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2452 2453 return 0; 2454 } 2455 2456 static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port, 2457 unsigned long *supported) 2458 { 2459 /* Port5 supports ethier RGMII or SGMII. 2460 * Port6 supports SGMII only. 2461 */ 2462 switch (port) { 2463 case 5: 2464 if (mt7531_is_rgmii_port(priv, port)) 2465 break; 2466 fallthrough; 2467 case 6: 2468 phylink_set(supported, 1000baseX_Full); 2469 phylink_set(supported, 2500baseX_Full); 2470 phylink_set(supported, 2500baseT_Full); 2471 } 2472 } 2473 2474 static void 2475 mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port, 2476 unsigned int mode, phy_interface_t interface, 2477 int speed, int duplex) 2478 { 2479 struct mt7530_priv *priv = ds->priv; 2480 unsigned int val; 2481 2482 /* For adjusting speed and duplex of SGMII force mode. */ 2483 if (interface != PHY_INTERFACE_MODE_SGMII || 2484 phylink_autoneg_inband(mode)) 2485 return; 2486 2487 /* SGMII force mode setting */ 2488 val = mt7530_read(priv, MT7531_SGMII_MODE(port)); 2489 val &= ~MT7531_SGMII_IF_MODE_MASK; 2490 2491 switch (speed) { 2492 case SPEED_10: 2493 val |= MT7531_SGMII_FORCE_SPEED_10; 2494 break; 2495 case SPEED_100: 2496 val |= MT7531_SGMII_FORCE_SPEED_100; 2497 break; 2498 case SPEED_1000: 2499 val |= MT7531_SGMII_FORCE_SPEED_1000; 2500 break; 2501 } 2502 2503 /* MT7531 SGMII 1G force mode can only work in full duplex mode, 2504 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2505 */ 2506 if ((speed == SPEED_10 || speed == SPEED_100) && 2507 duplex != DUPLEX_FULL) 2508 val |= MT7531_SGMII_FORCE_HALF_DUPLEX; 2509 2510 mt7530_write(priv, MT7531_SGMII_MODE(port), val); 2511 } 2512 2513 static bool mt753x_is_mac_port(u32 port) 2514 { 2515 return (port == 5 || port == 6); 2516 } 2517 2518 static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port, 2519 phy_interface_t interface) 2520 { 2521 u32 val; 2522 2523 if (!mt753x_is_mac_port(port)) 2524 return -EINVAL; 2525 2526 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2527 MT7531_SGMII_PHYA_PWD); 2528 2529 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port)); 2530 val &= ~MT7531_RG_TPHY_SPEED_MASK; 2531 /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B 2532 * encoding. 2533 */ 2534 val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ? 2535 MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G; 2536 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val); 2537 2538 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2539 2540 /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex 2541 * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2542 */ 2543 mt7530_rmw(priv, MT7531_SGMII_MODE(port), 2544 MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS, 2545 MT7531_SGMII_FORCE_SPEED_1000); 2546 2547 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2548 2549 return 0; 2550 } 2551 2552 static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port, 2553 phy_interface_t interface) 2554 { 2555 if (!mt753x_is_mac_port(port)) 2556 return -EINVAL; 2557 2558 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2559 MT7531_SGMII_PHYA_PWD); 2560 2561 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), 2562 MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G); 2563 2564 mt7530_set(priv, MT7531_SGMII_MODE(port), 2565 MT7531_SGMII_REMOTE_FAULT_DIS | 2566 MT7531_SGMII_SPEED_DUPLEX_AN); 2567 2568 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port), 2569 MT7531_SGMII_TX_CONFIG_MASK, 1); 2570 2571 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2572 2573 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART); 2574 2575 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2576 2577 return 0; 2578 } 2579 2580 static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port) 2581 { 2582 struct mt7530_priv *priv = ds->priv; 2583 u32 val; 2584 2585 /* Only restart AN when AN is enabled */ 2586 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2587 if (val & MT7531_SGMII_AN_ENABLE) { 2588 val |= MT7531_SGMII_AN_RESTART; 2589 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val); 2590 } 2591 } 2592 2593 static int 2594 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2595 phy_interface_t interface) 2596 { 2597 struct mt7530_priv *priv = ds->priv; 2598 struct phy_device *phydev; 2599 struct dsa_port *dp; 2600 2601 if (!mt753x_is_mac_port(port)) { 2602 dev_err(priv->dev, "port %d is not a MAC port\n", port); 2603 return -EINVAL; 2604 } 2605 2606 switch (interface) { 2607 case PHY_INTERFACE_MODE_RGMII: 2608 case PHY_INTERFACE_MODE_RGMII_ID: 2609 case PHY_INTERFACE_MODE_RGMII_RXID: 2610 case PHY_INTERFACE_MODE_RGMII_TXID: 2611 dp = dsa_to_port(ds, port); 2612 phydev = dp->slave->phydev; 2613 return mt7531_rgmii_setup(priv, port, interface, phydev); 2614 case PHY_INTERFACE_MODE_SGMII: 2615 return mt7531_sgmii_setup_mode_an(priv, port, interface); 2616 case PHY_INTERFACE_MODE_NA: 2617 case PHY_INTERFACE_MODE_1000BASEX: 2618 case PHY_INTERFACE_MODE_2500BASEX: 2619 if (phylink_autoneg_inband(mode)) 2620 return -EINVAL; 2621 2622 return mt7531_sgmii_setup_mode_force(priv, port, interface); 2623 default: 2624 return -EINVAL; 2625 } 2626 2627 return -EINVAL; 2628 } 2629 2630 static int 2631 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2632 const struct phylink_link_state *state) 2633 { 2634 struct mt7530_priv *priv = ds->priv; 2635 2636 return priv->info->mac_port_config(ds, port, mode, state->interface); 2637 } 2638 2639 static void 2640 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2641 const struct phylink_link_state *state) 2642 { 2643 struct mt7530_priv *priv = ds->priv; 2644 u32 mcr_cur, mcr_new; 2645 2646 if (!mt753x_phy_mode_supported(ds, port, state)) 2647 goto unsupported; 2648 2649 switch (port) { 2650 case 0 ... 4: /* Internal phy */ 2651 if (state->interface != PHY_INTERFACE_MODE_GMII) 2652 goto unsupported; 2653 break; 2654 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2655 if (priv->p5_interface == state->interface) 2656 break; 2657 2658 if (mt753x_mac_config(ds, port, mode, state) < 0) 2659 goto unsupported; 2660 2661 if (priv->p5_intf_sel != P5_DISABLED) 2662 priv->p5_interface = state->interface; 2663 break; 2664 case 6: /* 1st cpu port */ 2665 if (priv->p6_interface == state->interface) 2666 break; 2667 2668 mt753x_pad_setup(ds, state); 2669 2670 if (mt753x_mac_config(ds, port, mode, state) < 0) 2671 goto unsupported; 2672 2673 priv->p6_interface = state->interface; 2674 break; 2675 default: 2676 unsupported: 2677 dev_err(ds->dev, "%s: unsupported %s port: %i\n", 2678 __func__, phy_modes(state->interface), port); 2679 return; 2680 } 2681 2682 if (phylink_autoneg_inband(mode) && 2683 state->interface != PHY_INTERFACE_MODE_SGMII) { 2684 dev_err(ds->dev, "%s: in-band negotiation unsupported\n", 2685 __func__); 2686 return; 2687 } 2688 2689 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); 2690 mcr_new = mcr_cur; 2691 mcr_new &= ~PMCR_LINK_SETTINGS_MASK; 2692 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | 2693 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); 2694 2695 /* Are we connected to external phy */ 2696 if (port == 5 && dsa_is_user_port(ds, 5)) 2697 mcr_new |= PMCR_EXT_PHY; 2698 2699 if (mcr_new != mcr_cur) 2700 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); 2701 } 2702 2703 static void 2704 mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port) 2705 { 2706 struct mt7530_priv *priv = ds->priv; 2707 2708 if (!priv->info->mac_pcs_an_restart) 2709 return; 2710 2711 priv->info->mac_pcs_an_restart(ds, port); 2712 } 2713 2714 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, 2715 unsigned int mode, 2716 phy_interface_t interface) 2717 { 2718 struct mt7530_priv *priv = ds->priv; 2719 2720 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 2721 } 2722 2723 static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port, 2724 unsigned int mode, phy_interface_t interface, 2725 int speed, int duplex) 2726 { 2727 struct mt7530_priv *priv = ds->priv; 2728 2729 if (!priv->info->mac_pcs_link_up) 2730 return; 2731 2732 priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex); 2733 } 2734 2735 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, 2736 unsigned int mode, 2737 phy_interface_t interface, 2738 struct phy_device *phydev, 2739 int speed, int duplex, 2740 bool tx_pause, bool rx_pause) 2741 { 2742 struct mt7530_priv *priv = ds->priv; 2743 u32 mcr; 2744 2745 mt753x_mac_pcs_link_up(ds, port, mode, interface, speed, duplex); 2746 2747 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; 2748 2749 /* MT753x MAC works in 1G full duplex mode for all up-clocked 2750 * variants. 2751 */ 2752 if (interface == PHY_INTERFACE_MODE_TRGMII || 2753 (phy_interface_mode_is_8023z(interface))) { 2754 speed = SPEED_1000; 2755 duplex = DUPLEX_FULL; 2756 } 2757 2758 switch (speed) { 2759 case SPEED_1000: 2760 mcr |= PMCR_FORCE_SPEED_1000; 2761 break; 2762 case SPEED_100: 2763 mcr |= PMCR_FORCE_SPEED_100; 2764 break; 2765 } 2766 if (duplex == DUPLEX_FULL) { 2767 mcr |= PMCR_FORCE_FDX; 2768 if (tx_pause) 2769 mcr |= PMCR_TX_FC_EN; 2770 if (rx_pause) 2771 mcr |= PMCR_RX_FC_EN; 2772 } 2773 2774 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, 0) >= 0) { 2775 switch (speed) { 2776 case SPEED_1000: 2777 mcr |= PMCR_FORCE_EEE1G; 2778 break; 2779 case SPEED_100: 2780 mcr |= PMCR_FORCE_EEE100; 2781 break; 2782 } 2783 } 2784 2785 mt7530_set(priv, MT7530_PMCR_P(port), mcr); 2786 } 2787 2788 static int 2789 mt7531_cpu_port_config(struct dsa_switch *ds, int port) 2790 { 2791 struct mt7530_priv *priv = ds->priv; 2792 phy_interface_t interface; 2793 int speed; 2794 int ret; 2795 2796 switch (port) { 2797 case 5: 2798 if (mt7531_is_rgmii_port(priv, port)) 2799 interface = PHY_INTERFACE_MODE_RGMII; 2800 else 2801 interface = PHY_INTERFACE_MODE_2500BASEX; 2802 2803 priv->p5_interface = interface; 2804 break; 2805 case 6: 2806 interface = PHY_INTERFACE_MODE_2500BASEX; 2807 2808 mt7531_pad_setup(ds, interface); 2809 2810 priv->p6_interface = interface; 2811 break; 2812 default: 2813 return -EINVAL; 2814 } 2815 2816 if (interface == PHY_INTERFACE_MODE_2500BASEX) 2817 speed = SPEED_2500; 2818 else 2819 speed = SPEED_1000; 2820 2821 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); 2822 if (ret) 2823 return ret; 2824 mt7530_write(priv, MT7530_PMCR_P(port), 2825 PMCR_CPU_PORT_SETTING(priv->id)); 2826 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, 2827 speed, DUPLEX_FULL, true, true); 2828 2829 return 0; 2830 } 2831 2832 static void 2833 mt7530_mac_port_validate(struct dsa_switch *ds, int port, 2834 unsigned long *supported) 2835 { 2836 if (port == 5) 2837 phylink_set(supported, 1000baseX_Full); 2838 } 2839 2840 static void mt7531_mac_port_validate(struct dsa_switch *ds, int port, 2841 unsigned long *supported) 2842 { 2843 struct mt7530_priv *priv = ds->priv; 2844 2845 mt7531_sgmii_validate(priv, port, supported); 2846 } 2847 2848 static void 2849 mt753x_phylink_validate(struct dsa_switch *ds, int port, 2850 unsigned long *supported, 2851 struct phylink_link_state *state) 2852 { 2853 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 2854 struct mt7530_priv *priv = ds->priv; 2855 2856 if (state->interface != PHY_INTERFACE_MODE_NA && 2857 !mt753x_phy_mode_supported(ds, port, state)) { 2858 linkmode_zero(supported); 2859 return; 2860 } 2861 2862 phylink_set_port_modes(mask); 2863 2864 if (state->interface != PHY_INTERFACE_MODE_TRGMII || 2865 !phy_interface_mode_is_8023z(state->interface)) { 2866 phylink_set(mask, 10baseT_Half); 2867 phylink_set(mask, 10baseT_Full); 2868 phylink_set(mask, 100baseT_Half); 2869 phylink_set(mask, 100baseT_Full); 2870 phylink_set(mask, Autoneg); 2871 } 2872 2873 /* This switch only supports 1G full-duplex. */ 2874 if (state->interface != PHY_INTERFACE_MODE_MII) 2875 phylink_set(mask, 1000baseT_Full); 2876 2877 priv->info->mac_port_validate(ds, port, mask); 2878 2879 phylink_set(mask, Pause); 2880 phylink_set(mask, Asym_Pause); 2881 2882 linkmode_and(supported, supported, mask); 2883 linkmode_and(state->advertising, state->advertising, mask); 2884 2885 /* We can only operate at 2500BaseX or 1000BaseX. If requested 2886 * to advertise both, only report advertising at 2500BaseX. 2887 */ 2888 phylink_helper_basex_speed(state); 2889 } 2890 2891 static int 2892 mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port, 2893 struct phylink_link_state *state) 2894 { 2895 struct mt7530_priv *priv = ds->priv; 2896 u32 pmsr; 2897 2898 if (port < 0 || port >= MT7530_NUM_PORTS) 2899 return -EINVAL; 2900 2901 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2902 2903 state->link = (pmsr & PMSR_LINK); 2904 state->an_complete = state->link; 2905 state->duplex = !!(pmsr & PMSR_DPX); 2906 2907 switch (pmsr & PMSR_SPEED_MASK) { 2908 case PMSR_SPEED_10: 2909 state->speed = SPEED_10; 2910 break; 2911 case PMSR_SPEED_100: 2912 state->speed = SPEED_100; 2913 break; 2914 case PMSR_SPEED_1000: 2915 state->speed = SPEED_1000; 2916 break; 2917 default: 2918 state->speed = SPEED_UNKNOWN; 2919 break; 2920 } 2921 2922 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 2923 if (pmsr & PMSR_RX_FC) 2924 state->pause |= MLO_PAUSE_RX; 2925 if (pmsr & PMSR_TX_FC) 2926 state->pause |= MLO_PAUSE_TX; 2927 2928 return 1; 2929 } 2930 2931 static int 2932 mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port, 2933 struct phylink_link_state *state) 2934 { 2935 u32 status, val; 2936 u16 config_reg; 2937 2938 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2939 state->link = !!(status & MT7531_SGMII_LINK_STATUS); 2940 if (state->interface == PHY_INTERFACE_MODE_SGMII && 2941 (status & MT7531_SGMII_AN_ENABLE)) { 2942 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port)); 2943 config_reg = val >> 16; 2944 2945 switch (config_reg & LPA_SGMII_SPD_MASK) { 2946 case LPA_SGMII_1000: 2947 state->speed = SPEED_1000; 2948 break; 2949 case LPA_SGMII_100: 2950 state->speed = SPEED_100; 2951 break; 2952 case LPA_SGMII_10: 2953 state->speed = SPEED_10; 2954 break; 2955 default: 2956 dev_err(priv->dev, "invalid sgmii PHY speed\n"); 2957 state->link = false; 2958 return -EINVAL; 2959 } 2960 2961 if (config_reg & LPA_SGMII_FULL_DUPLEX) 2962 state->duplex = DUPLEX_FULL; 2963 else 2964 state->duplex = DUPLEX_HALF; 2965 } 2966 2967 return 0; 2968 } 2969 2970 static int 2971 mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port, 2972 struct phylink_link_state *state) 2973 { 2974 struct mt7530_priv *priv = ds->priv; 2975 2976 if (state->interface == PHY_INTERFACE_MODE_SGMII) 2977 return mt7531_sgmii_pcs_get_state_an(priv, port, state); 2978 2979 return -EOPNOTSUPP; 2980 } 2981 2982 static int 2983 mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port, 2984 struct phylink_link_state *state) 2985 { 2986 struct mt7530_priv *priv = ds->priv; 2987 2988 return priv->info->mac_port_get_state(ds, port, state); 2989 } 2990 2991 static int 2992 mt753x_setup(struct dsa_switch *ds) 2993 { 2994 struct mt7530_priv *priv = ds->priv; 2995 int ret = priv->info->sw_setup(ds); 2996 2997 if (ret) 2998 return ret; 2999 3000 ret = mt7530_setup_irq(priv); 3001 if (ret) 3002 return ret; 3003 3004 ret = mt7530_setup_mdio(priv); 3005 if (ret && priv->irq) 3006 mt7530_free_irq_common(priv); 3007 3008 return ret; 3009 } 3010 3011 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, 3012 struct ethtool_eee *e) 3013 { 3014 struct mt7530_priv *priv = ds->priv; 3015 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); 3016 3017 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); 3018 e->tx_lpi_timer = GET_LPI_THRESH(eeecr); 3019 3020 return 0; 3021 } 3022 3023 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3024 struct ethtool_eee *e) 3025 { 3026 struct mt7530_priv *priv = ds->priv; 3027 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN; 3028 3029 if (e->tx_lpi_timer > 0xFFF) 3030 return -EINVAL; 3031 3032 set = SET_LPI_THRESH(e->tx_lpi_timer); 3033 if (!e->tx_lpi_enabled) 3034 /* Force LPI Mode without a delay */ 3035 set |= LPI_MODE_EN; 3036 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); 3037 3038 return 0; 3039 } 3040 3041 static const struct dsa_switch_ops mt7530_switch_ops = { 3042 .get_tag_protocol = mtk_get_tag_protocol, 3043 .setup = mt753x_setup, 3044 .get_strings = mt7530_get_strings, 3045 .get_ethtool_stats = mt7530_get_ethtool_stats, 3046 .get_sset_count = mt7530_get_sset_count, 3047 .set_ageing_time = mt7530_set_ageing_time, 3048 .port_enable = mt7530_port_enable, 3049 .port_disable = mt7530_port_disable, 3050 .port_change_mtu = mt7530_port_change_mtu, 3051 .port_max_mtu = mt7530_port_max_mtu, 3052 .port_stp_state_set = mt7530_stp_state_set, 3053 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3054 .port_bridge_flags = mt7530_port_bridge_flags, 3055 .port_set_mrouter = mt7530_port_set_mrouter, 3056 .port_bridge_join = mt7530_port_bridge_join, 3057 .port_bridge_leave = mt7530_port_bridge_leave, 3058 .port_fdb_add = mt7530_port_fdb_add, 3059 .port_fdb_del = mt7530_port_fdb_del, 3060 .port_fdb_dump = mt7530_port_fdb_dump, 3061 .port_mdb_add = mt7530_port_mdb_add, 3062 .port_mdb_del = mt7530_port_mdb_del, 3063 .port_vlan_filtering = mt7530_port_vlan_filtering, 3064 .port_vlan_add = mt7530_port_vlan_add, 3065 .port_vlan_del = mt7530_port_vlan_del, 3066 .port_mirror_add = mt753x_port_mirror_add, 3067 .port_mirror_del = mt753x_port_mirror_del, 3068 .phylink_validate = mt753x_phylink_validate, 3069 .phylink_mac_link_state = mt753x_phylink_mac_link_state, 3070 .phylink_mac_config = mt753x_phylink_mac_config, 3071 .phylink_mac_an_restart = mt753x_phylink_mac_an_restart, 3072 .phylink_mac_link_down = mt753x_phylink_mac_link_down, 3073 .phylink_mac_link_up = mt753x_phylink_mac_link_up, 3074 .get_mac_eee = mt753x_get_mac_eee, 3075 .set_mac_eee = mt753x_set_mac_eee, 3076 }; 3077 3078 static const struct mt753x_info mt753x_table[] = { 3079 [ID_MT7621] = { 3080 .id = ID_MT7621, 3081 .sw_setup = mt7530_setup, 3082 .phy_read = mt7530_phy_read, 3083 .phy_write = mt7530_phy_write, 3084 .pad_setup = mt7530_pad_clk_setup, 3085 .phy_mode_supported = mt7530_phy_mode_supported, 3086 .mac_port_validate = mt7530_mac_port_validate, 3087 .mac_port_get_state = mt7530_phylink_mac_link_state, 3088 .mac_port_config = mt7530_mac_config, 3089 }, 3090 [ID_MT7530] = { 3091 .id = ID_MT7530, 3092 .sw_setup = mt7530_setup, 3093 .phy_read = mt7530_phy_read, 3094 .phy_write = mt7530_phy_write, 3095 .pad_setup = mt7530_pad_clk_setup, 3096 .phy_mode_supported = mt7530_phy_mode_supported, 3097 .mac_port_validate = mt7530_mac_port_validate, 3098 .mac_port_get_state = mt7530_phylink_mac_link_state, 3099 .mac_port_config = mt7530_mac_config, 3100 }, 3101 [ID_MT7531] = { 3102 .id = ID_MT7531, 3103 .sw_setup = mt7531_setup, 3104 .phy_read = mt7531_ind_phy_read, 3105 .phy_write = mt7531_ind_phy_write, 3106 .pad_setup = mt7531_pad_setup, 3107 .cpu_port_config = mt7531_cpu_port_config, 3108 .phy_mode_supported = mt7531_phy_mode_supported, 3109 .mac_port_validate = mt7531_mac_port_validate, 3110 .mac_port_get_state = mt7531_phylink_mac_link_state, 3111 .mac_port_config = mt7531_mac_config, 3112 .mac_pcs_an_restart = mt7531_sgmii_restart_an, 3113 .mac_pcs_link_up = mt7531_sgmii_link_up_force, 3114 }, 3115 }; 3116 3117 static const struct of_device_id mt7530_of_match[] = { 3118 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], }, 3119 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], }, 3120 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], }, 3121 { /* sentinel */ }, 3122 }; 3123 MODULE_DEVICE_TABLE(of, mt7530_of_match); 3124 3125 static int 3126 mt7530_probe(struct mdio_device *mdiodev) 3127 { 3128 struct mt7530_priv *priv; 3129 struct device_node *dn; 3130 3131 dn = mdiodev->dev.of_node; 3132 3133 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 3134 if (!priv) 3135 return -ENOMEM; 3136 3137 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); 3138 if (!priv->ds) 3139 return -ENOMEM; 3140 3141 priv->ds->dev = &mdiodev->dev; 3142 priv->ds->num_ports = DSA_MAX_PORTS; 3143 3144 /* Use medatek,mcm property to distinguish hardware type that would 3145 * casues a little bit differences on power-on sequence. 3146 */ 3147 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); 3148 if (priv->mcm) { 3149 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); 3150 3151 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); 3152 if (IS_ERR(priv->rstc)) { 3153 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 3154 return PTR_ERR(priv->rstc); 3155 } 3156 } 3157 3158 /* Get the hardware identifier from the devicetree node. 3159 * We will need it for some of the clock and regulator setup. 3160 */ 3161 priv->info = of_device_get_match_data(&mdiodev->dev); 3162 if (!priv->info) 3163 return -EINVAL; 3164 3165 /* Sanity check if these required device operations are filled 3166 * properly. 3167 */ 3168 if (!priv->info->sw_setup || !priv->info->pad_setup || 3169 !priv->info->phy_read || !priv->info->phy_write || 3170 !priv->info->phy_mode_supported || 3171 !priv->info->mac_port_validate || 3172 !priv->info->mac_port_get_state || !priv->info->mac_port_config) 3173 return -EINVAL; 3174 3175 priv->id = priv->info->id; 3176 3177 if (priv->id == ID_MT7530) { 3178 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); 3179 if (IS_ERR(priv->core_pwr)) 3180 return PTR_ERR(priv->core_pwr); 3181 3182 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); 3183 if (IS_ERR(priv->io_pwr)) 3184 return PTR_ERR(priv->io_pwr); 3185 } 3186 3187 /* Not MCM that indicates switch works as the remote standalone 3188 * integrated circuit so the GPIO pin would be used to complete 3189 * the reset, otherwise memory-mapped register accessing used 3190 * through syscon provides in the case of MCM. 3191 */ 3192 if (!priv->mcm) { 3193 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", 3194 GPIOD_OUT_LOW); 3195 if (IS_ERR(priv->reset)) { 3196 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 3197 return PTR_ERR(priv->reset); 3198 } 3199 } 3200 3201 priv->bus = mdiodev->bus; 3202 priv->dev = &mdiodev->dev; 3203 priv->ds->priv = priv; 3204 priv->ds->ops = &mt7530_switch_ops; 3205 mutex_init(&priv->reg_mutex); 3206 dev_set_drvdata(&mdiodev->dev, priv); 3207 3208 return dsa_register_switch(priv->ds); 3209 } 3210 3211 static void 3212 mt7530_remove(struct mdio_device *mdiodev) 3213 { 3214 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 3215 int ret = 0; 3216 3217 ret = regulator_disable(priv->core_pwr); 3218 if (ret < 0) 3219 dev_err(priv->dev, 3220 "Failed to disable core power: %d\n", ret); 3221 3222 ret = regulator_disable(priv->io_pwr); 3223 if (ret < 0) 3224 dev_err(priv->dev, "Failed to disable io pwr: %d\n", 3225 ret); 3226 3227 if (priv->irq) 3228 mt7530_free_irq(priv); 3229 3230 dsa_unregister_switch(priv->ds); 3231 mutex_destroy(&priv->reg_mutex); 3232 } 3233 3234 static struct mdio_driver mt7530_mdio_driver = { 3235 .probe = mt7530_probe, 3236 .remove = mt7530_remove, 3237 .mdiodrv.driver = { 3238 .name = "mt7530", 3239 .of_match_table = mt7530_of_match, 3240 }, 3241 }; 3242 3243 mdio_module_driver(mt7530_mdio_driver); 3244 3245 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3246 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3247 MODULE_LICENSE("GPL"); 3248