1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 25 #include "mt7530.h" 26 27 /* String, offset, and register size in bytes if different from 4 bytes */ 28 static const struct mt7530_mib_desc mt7530_mib[] = { 29 MIB_DESC(1, 0x00, "TxDrop"), 30 MIB_DESC(1, 0x04, "TxCrcErr"), 31 MIB_DESC(1, 0x08, "TxUnicast"), 32 MIB_DESC(1, 0x0c, "TxMulticast"), 33 MIB_DESC(1, 0x10, "TxBroadcast"), 34 MIB_DESC(1, 0x14, "TxCollision"), 35 MIB_DESC(1, 0x18, "TxSingleCollision"), 36 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 37 MIB_DESC(1, 0x20, "TxDeferred"), 38 MIB_DESC(1, 0x24, "TxLateCollision"), 39 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 40 MIB_DESC(1, 0x2c, "TxPause"), 41 MIB_DESC(1, 0x30, "TxPktSz64"), 42 MIB_DESC(1, 0x34, "TxPktSz65To127"), 43 MIB_DESC(1, 0x38, "TxPktSz128To255"), 44 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 45 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 46 MIB_DESC(1, 0x44, "Tx1024ToMax"), 47 MIB_DESC(2, 0x48, "TxBytes"), 48 MIB_DESC(1, 0x60, "RxDrop"), 49 MIB_DESC(1, 0x64, "RxFiltering"), 50 MIB_DESC(1, 0x68, "RxUnicast"), 51 MIB_DESC(1, 0x6c, "RxMulticast"), 52 MIB_DESC(1, 0x70, "RxBroadcast"), 53 MIB_DESC(1, 0x74, "RxAlignErr"), 54 MIB_DESC(1, 0x78, "RxCrcErr"), 55 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 56 MIB_DESC(1, 0x80, "RxFragErr"), 57 MIB_DESC(1, 0x84, "RxOverSzErr"), 58 MIB_DESC(1, 0x88, "RxJabberErr"), 59 MIB_DESC(1, 0x8c, "RxPause"), 60 MIB_DESC(1, 0x90, "RxPktSz64"), 61 MIB_DESC(1, 0x94, "RxPktSz65To127"), 62 MIB_DESC(1, 0x98, "RxPktSz128To255"), 63 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 64 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 65 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 66 MIB_DESC(2, 0xa8, "RxBytes"), 67 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 68 MIB_DESC(1, 0xb4, "RxIngressDrop"), 69 MIB_DESC(1, 0xb8, "RxArlDrop"), 70 }; 71 72 /* Since phy_device has not yet been created and 73 * phy_{read,write}_mmd_indirect is not available, we provide our own 74 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers 75 * to complete this function. 76 */ 77 static int 78 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 79 { 80 struct mii_bus *bus = priv->bus; 81 int value, ret; 82 83 /* Write the desired MMD Devad */ 84 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 85 if (ret < 0) 86 goto err; 87 88 /* Write the desired MMD register address */ 89 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 90 if (ret < 0) 91 goto err; 92 93 /* Select the Function : DATA with no post increment */ 94 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 95 if (ret < 0) 96 goto err; 97 98 /* Read the content of the MMD's selected register */ 99 value = bus->read(bus, 0, MII_MMD_DATA); 100 101 return value; 102 err: 103 dev_err(&bus->dev, "failed to read mmd register\n"); 104 105 return ret; 106 } 107 108 static int 109 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 110 int devad, u32 data) 111 { 112 struct mii_bus *bus = priv->bus; 113 int ret; 114 115 /* Write the desired MMD Devad */ 116 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 117 if (ret < 0) 118 goto err; 119 120 /* Write the desired MMD register address */ 121 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 122 if (ret < 0) 123 goto err; 124 125 /* Select the Function : DATA with no post increment */ 126 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 127 if (ret < 0) 128 goto err; 129 130 /* Write the data into MMD's selected register */ 131 ret = bus->write(bus, 0, MII_MMD_DATA, data); 132 err: 133 if (ret < 0) 134 dev_err(&bus->dev, 135 "failed to write mmd register\n"); 136 return ret; 137 } 138 139 static void 140 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 141 { 142 struct mii_bus *bus = priv->bus; 143 144 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 145 146 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 147 148 mutex_unlock(&bus->mdio_lock); 149 } 150 151 static void 152 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 153 { 154 struct mii_bus *bus = priv->bus; 155 u32 val; 156 157 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 158 159 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 160 val &= ~mask; 161 val |= set; 162 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 163 164 mutex_unlock(&bus->mdio_lock); 165 } 166 167 static void 168 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 169 { 170 core_rmw(priv, reg, 0, val); 171 } 172 173 static void 174 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 175 { 176 core_rmw(priv, reg, val, 0); 177 } 178 179 static int 180 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 181 { 182 struct mii_bus *bus = priv->bus; 183 u16 page, r, lo, hi; 184 int ret; 185 186 page = (reg >> 6) & 0x3ff; 187 r = (reg >> 2) & 0xf; 188 lo = val & 0xffff; 189 hi = val >> 16; 190 191 /* MT7530 uses 31 as the pseudo port */ 192 ret = bus->write(bus, 0x1f, 0x1f, page); 193 if (ret < 0) 194 goto err; 195 196 ret = bus->write(bus, 0x1f, r, lo); 197 if (ret < 0) 198 goto err; 199 200 ret = bus->write(bus, 0x1f, 0x10, hi); 201 err: 202 if (ret < 0) 203 dev_err(&bus->dev, 204 "failed to write mt7530 register\n"); 205 return ret; 206 } 207 208 static u32 209 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 210 { 211 struct mii_bus *bus = priv->bus; 212 u16 page, r, lo, hi; 213 int ret; 214 215 page = (reg >> 6) & 0x3ff; 216 r = (reg >> 2) & 0xf; 217 218 /* MT7530 uses 31 as the pseudo port */ 219 ret = bus->write(bus, 0x1f, 0x1f, page); 220 if (ret < 0) { 221 dev_err(&bus->dev, 222 "failed to read mt7530 register\n"); 223 return ret; 224 } 225 226 lo = bus->read(bus, 0x1f, r); 227 hi = bus->read(bus, 0x1f, 0x10); 228 229 return (hi << 16) | (lo & 0xffff); 230 } 231 232 static void 233 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 234 { 235 struct mii_bus *bus = priv->bus; 236 237 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 238 239 mt7530_mii_write(priv, reg, val); 240 241 mutex_unlock(&bus->mdio_lock); 242 } 243 244 static u32 245 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 246 { 247 return mt7530_mii_read(p->priv, p->reg); 248 } 249 250 static u32 251 _mt7530_read(struct mt7530_dummy_poll *p) 252 { 253 struct mii_bus *bus = p->priv->bus; 254 u32 val; 255 256 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 257 258 val = mt7530_mii_read(p->priv, p->reg); 259 260 mutex_unlock(&bus->mdio_lock); 261 262 return val; 263 } 264 265 static u32 266 mt7530_read(struct mt7530_priv *priv, u32 reg) 267 { 268 struct mt7530_dummy_poll p; 269 270 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 271 return _mt7530_read(&p); 272 } 273 274 static void 275 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 276 u32 mask, u32 set) 277 { 278 struct mii_bus *bus = priv->bus; 279 u32 val; 280 281 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 282 283 val = mt7530_mii_read(priv, reg); 284 val &= ~mask; 285 val |= set; 286 mt7530_mii_write(priv, reg, val); 287 288 mutex_unlock(&bus->mdio_lock); 289 } 290 291 static void 292 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 293 { 294 mt7530_rmw(priv, reg, 0, val); 295 } 296 297 static void 298 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 299 { 300 mt7530_rmw(priv, reg, val, 0); 301 } 302 303 static int 304 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 305 { 306 u32 val; 307 int ret; 308 struct mt7530_dummy_poll p; 309 310 /* Set the command operating upon the MAC address entries */ 311 val = ATC_BUSY | ATC_MAT(0) | cmd; 312 mt7530_write(priv, MT7530_ATC, val); 313 314 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 315 ret = readx_poll_timeout(_mt7530_read, &p, val, 316 !(val & ATC_BUSY), 20, 20000); 317 if (ret < 0) { 318 dev_err(priv->dev, "reset timeout\n"); 319 return ret; 320 } 321 322 /* Additional sanity for read command if the specified 323 * entry is invalid 324 */ 325 val = mt7530_read(priv, MT7530_ATC); 326 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 327 return -EINVAL; 328 329 if (rsp) 330 *rsp = val; 331 332 return 0; 333 } 334 335 static void 336 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 337 { 338 u32 reg[3]; 339 int i; 340 341 /* Read from ARL table into an array */ 342 for (i = 0; i < 3; i++) { 343 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 344 345 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 346 __func__, __LINE__, i, reg[i]); 347 } 348 349 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 350 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 351 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 352 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 353 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 354 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 355 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 356 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 357 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 358 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 359 } 360 361 static void 362 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 363 u8 port_mask, const u8 *mac, 364 u8 aging, u8 type) 365 { 366 u32 reg[3] = { 0 }; 367 int i; 368 369 reg[1] |= vid & CVID_MASK; 370 reg[1] |= ATA2_IVL; 371 reg[1] |= ATA2_FID(FID_BRIDGED); 372 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 373 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 374 /* STATIC_ENT indicate that entry is static wouldn't 375 * be aged out and STATIC_EMP specified as erasing an 376 * entry 377 */ 378 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 379 reg[1] |= mac[5] << MAC_BYTE_5; 380 reg[1] |= mac[4] << MAC_BYTE_4; 381 reg[0] |= mac[3] << MAC_BYTE_3; 382 reg[0] |= mac[2] << MAC_BYTE_2; 383 reg[0] |= mac[1] << MAC_BYTE_1; 384 reg[0] |= mac[0] << MAC_BYTE_0; 385 386 /* Write array into the ARL table */ 387 for (i = 0; i < 3; i++) 388 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 389 } 390 391 /* Setup TX circuit including relevant PAD and driving */ 392 static int 393 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 394 { 395 struct mt7530_priv *priv = ds->priv; 396 u32 ncpo1, ssc_delta, trgint, i, xtal; 397 398 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 399 400 if (xtal == HWTRAP_XTAL_20MHZ) { 401 dev_err(priv->dev, 402 "%s: MT7530 with a 20MHz XTAL is not supported!\n", 403 __func__); 404 return -EINVAL; 405 } 406 407 switch (interface) { 408 case PHY_INTERFACE_MODE_RGMII: 409 trgint = 0; 410 /* PLL frequency: 125MHz */ 411 ncpo1 = 0x0c80; 412 break; 413 case PHY_INTERFACE_MODE_TRGMII: 414 trgint = 1; 415 if (priv->id == ID_MT7621) { 416 /* PLL frequency: 150MHz: 1.2GBit */ 417 if (xtal == HWTRAP_XTAL_40MHZ) 418 ncpo1 = 0x0780; 419 if (xtal == HWTRAP_XTAL_25MHZ) 420 ncpo1 = 0x0a00; 421 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 422 if (xtal == HWTRAP_XTAL_40MHZ) 423 ncpo1 = 0x0c80; 424 if (xtal == HWTRAP_XTAL_25MHZ) 425 ncpo1 = 0x1400; 426 } 427 break; 428 default: 429 dev_err(priv->dev, "xMII interface %d not supported\n", 430 interface); 431 return -EINVAL; 432 } 433 434 if (xtal == HWTRAP_XTAL_25MHZ) 435 ssc_delta = 0x57; 436 else 437 ssc_delta = 0x87; 438 439 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 440 P6_INTF_MODE(trgint)); 441 442 /* Lower Tx Driving for TRGMII path */ 443 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) 444 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 445 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 446 447 /* Disable MT7530 core and TRGMII Tx clocks */ 448 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, 449 REG_GSWCK_EN | REG_TRGMIICK_EN); 450 451 /* Setup core clock for MT7530 */ 452 /* Disable PLL */ 453 core_write(priv, CORE_GSWPLL_GRP1, 0); 454 455 /* Set core clock into 500Mhz */ 456 core_write(priv, CORE_GSWPLL_GRP2, 457 RG_GSWPLL_POSDIV_500M(1) | 458 RG_GSWPLL_FBKDIV_500M(25)); 459 460 /* Enable PLL */ 461 core_write(priv, CORE_GSWPLL_GRP1, 462 RG_GSWPLL_EN_PRE | 463 RG_GSWPLL_POSDIV_200M(2) | 464 RG_GSWPLL_FBKDIV_200M(32)); 465 466 /* Setup the MT7530 TRGMII Tx Clock */ 467 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 468 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 469 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 470 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 471 core_write(priv, CORE_PLL_GROUP4, 472 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 473 RG_SYSPLL_BIAS_LPF_EN); 474 core_write(priv, CORE_PLL_GROUP2, 475 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 476 RG_SYSPLL_POSDIV(1)); 477 core_write(priv, CORE_PLL_GROUP7, 478 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 479 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 480 481 /* Enable MT7530 core and TRGMII Tx clocks */ 482 core_set(priv, CORE_TRGMII_GSW_CLK_CG, 483 REG_GSWCK_EN | REG_TRGMIICK_EN); 484 485 if (!trgint) 486 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 487 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 488 RD_TAP_MASK, RD_TAP(16)); 489 return 0; 490 } 491 492 static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) 493 { 494 u32 val; 495 496 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 497 498 return (val & PAD_DUAL_SGMII_EN) != 0; 499 } 500 501 static int 502 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 503 { 504 struct mt7530_priv *priv = ds->priv; 505 u32 top_sig; 506 u32 hwstrap; 507 u32 xtal; 508 u32 val; 509 510 if (mt7531_dual_sgmii_supported(priv)) 511 return 0; 512 513 val = mt7530_read(priv, MT7531_CREV); 514 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 515 hwstrap = mt7530_read(priv, MT7531_HWTRAP); 516 if ((val & CHIP_REV_M) > 0) 517 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : 518 HWTRAP_XTAL_FSEL_25MHZ; 519 else 520 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; 521 522 /* Step 1 : Disable MT7531 COREPLL */ 523 val = mt7530_read(priv, MT7531_PLLGP_EN); 524 val &= ~EN_COREPLL; 525 mt7530_write(priv, MT7531_PLLGP_EN, val); 526 527 /* Step 2: switch to XTAL output */ 528 val = mt7530_read(priv, MT7531_PLLGP_EN); 529 val |= SW_CLKSW; 530 mt7530_write(priv, MT7531_PLLGP_EN, val); 531 532 val = mt7530_read(priv, MT7531_PLLGP_CR0); 533 val &= ~RG_COREPLL_EN; 534 mt7530_write(priv, MT7531_PLLGP_CR0, val); 535 536 /* Step 3: disable PLLGP and enable program PLLGP */ 537 val = mt7530_read(priv, MT7531_PLLGP_EN); 538 val |= SW_PLLGP; 539 mt7530_write(priv, MT7531_PLLGP_EN, val); 540 541 /* Step 4: program COREPLL output frequency to 500MHz */ 542 val = mt7530_read(priv, MT7531_PLLGP_CR0); 543 val &= ~RG_COREPLL_POSDIV_M; 544 val |= 2 << RG_COREPLL_POSDIV_S; 545 mt7530_write(priv, MT7531_PLLGP_CR0, val); 546 usleep_range(25, 35); 547 548 switch (xtal) { 549 case HWTRAP_XTAL_FSEL_25MHZ: 550 val = mt7530_read(priv, MT7531_PLLGP_CR0); 551 val &= ~RG_COREPLL_SDM_PCW_M; 552 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 553 mt7530_write(priv, MT7531_PLLGP_CR0, val); 554 break; 555 case HWTRAP_XTAL_FSEL_40MHZ: 556 val = mt7530_read(priv, MT7531_PLLGP_CR0); 557 val &= ~RG_COREPLL_SDM_PCW_M; 558 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 559 mt7530_write(priv, MT7531_PLLGP_CR0, val); 560 break; 561 } 562 563 /* Set feedback divide ratio update signal to high */ 564 val = mt7530_read(priv, MT7531_PLLGP_CR0); 565 val |= RG_COREPLL_SDM_PCW_CHG; 566 mt7530_write(priv, MT7531_PLLGP_CR0, val); 567 /* Wait for at least 16 XTAL clocks */ 568 usleep_range(10, 20); 569 570 /* Step 5: set feedback divide ratio update signal to low */ 571 val = mt7530_read(priv, MT7531_PLLGP_CR0); 572 val &= ~RG_COREPLL_SDM_PCW_CHG; 573 mt7530_write(priv, MT7531_PLLGP_CR0, val); 574 575 /* Enable 325M clock for SGMII */ 576 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 577 578 /* Enable 250SSC clock for RGMII */ 579 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 580 581 /* Step 6: Enable MT7531 PLL */ 582 val = mt7530_read(priv, MT7531_PLLGP_CR0); 583 val |= RG_COREPLL_EN; 584 mt7530_write(priv, MT7531_PLLGP_CR0, val); 585 586 val = mt7530_read(priv, MT7531_PLLGP_EN); 587 val |= EN_COREPLL; 588 mt7530_write(priv, MT7531_PLLGP_EN, val); 589 usleep_range(25, 35); 590 591 return 0; 592 } 593 594 static void 595 mt7530_mib_reset(struct dsa_switch *ds) 596 { 597 struct mt7530_priv *priv = ds->priv; 598 599 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 600 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 601 } 602 603 static int mt7530_phy_read(struct mt7530_priv *priv, int port, int regnum) 604 { 605 return mdiobus_read_nested(priv->bus, port, regnum); 606 } 607 608 static int mt7530_phy_write(struct mt7530_priv *priv, int port, int regnum, 609 u16 val) 610 { 611 return mdiobus_write_nested(priv->bus, port, regnum, val); 612 } 613 614 static int 615 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 616 int regnum) 617 { 618 struct mii_bus *bus = priv->bus; 619 struct mt7530_dummy_poll p; 620 u32 reg, val; 621 int ret; 622 623 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 624 625 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 626 627 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 628 !(val & MT7531_PHY_ACS_ST), 20, 100000); 629 if (ret < 0) { 630 dev_err(priv->dev, "poll timeout\n"); 631 goto out; 632 } 633 634 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 635 MT7531_MDIO_DEV_ADDR(devad) | regnum; 636 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 637 638 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 639 !(val & MT7531_PHY_ACS_ST), 20, 100000); 640 if (ret < 0) { 641 dev_err(priv->dev, "poll timeout\n"); 642 goto out; 643 } 644 645 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 646 MT7531_MDIO_DEV_ADDR(devad); 647 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 648 649 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 650 !(val & MT7531_PHY_ACS_ST), 20, 100000); 651 if (ret < 0) { 652 dev_err(priv->dev, "poll timeout\n"); 653 goto out; 654 } 655 656 ret = val & MT7531_MDIO_RW_DATA_MASK; 657 out: 658 mutex_unlock(&bus->mdio_lock); 659 660 return ret; 661 } 662 663 static int 664 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 665 int regnum, u32 data) 666 { 667 struct mii_bus *bus = priv->bus; 668 struct mt7530_dummy_poll p; 669 u32 val, reg; 670 int ret; 671 672 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 673 674 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 675 676 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 677 !(val & MT7531_PHY_ACS_ST), 20, 100000); 678 if (ret < 0) { 679 dev_err(priv->dev, "poll timeout\n"); 680 goto out; 681 } 682 683 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 684 MT7531_MDIO_DEV_ADDR(devad) | regnum; 685 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 686 687 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 688 !(val & MT7531_PHY_ACS_ST), 20, 100000); 689 if (ret < 0) { 690 dev_err(priv->dev, "poll timeout\n"); 691 goto out; 692 } 693 694 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 695 MT7531_MDIO_DEV_ADDR(devad) | data; 696 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 697 698 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 699 !(val & MT7531_PHY_ACS_ST), 20, 100000); 700 if (ret < 0) { 701 dev_err(priv->dev, "poll timeout\n"); 702 goto out; 703 } 704 705 out: 706 mutex_unlock(&bus->mdio_lock); 707 708 return ret; 709 } 710 711 static int 712 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 713 { 714 struct mii_bus *bus = priv->bus; 715 struct mt7530_dummy_poll p; 716 int ret; 717 u32 val; 718 719 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 720 721 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 722 723 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 724 !(val & MT7531_PHY_ACS_ST), 20, 100000); 725 if (ret < 0) { 726 dev_err(priv->dev, "poll timeout\n"); 727 goto out; 728 } 729 730 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 731 MT7531_MDIO_REG_ADDR(regnum); 732 733 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 734 735 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 736 !(val & MT7531_PHY_ACS_ST), 20, 100000); 737 if (ret < 0) { 738 dev_err(priv->dev, "poll timeout\n"); 739 goto out; 740 } 741 742 ret = val & MT7531_MDIO_RW_DATA_MASK; 743 out: 744 mutex_unlock(&bus->mdio_lock); 745 746 return ret; 747 } 748 749 static int 750 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 751 u16 data) 752 { 753 struct mii_bus *bus = priv->bus; 754 struct mt7530_dummy_poll p; 755 int ret; 756 u32 reg; 757 758 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 759 760 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 761 762 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 763 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 764 if (ret < 0) { 765 dev_err(priv->dev, "poll timeout\n"); 766 goto out; 767 } 768 769 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 770 MT7531_MDIO_REG_ADDR(regnum) | data; 771 772 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 773 774 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 775 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 776 if (ret < 0) { 777 dev_err(priv->dev, "poll timeout\n"); 778 goto out; 779 } 780 781 out: 782 mutex_unlock(&bus->mdio_lock); 783 784 return ret; 785 } 786 787 static int 788 mt7531_ind_phy_read(struct mt7530_priv *priv, int port, int regnum) 789 { 790 int devad; 791 int ret; 792 793 if (regnum & MII_ADDR_C45) { 794 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; 795 ret = mt7531_ind_c45_phy_read(priv, port, devad, 796 regnum & MII_REGADDR_C45_MASK); 797 } else { 798 ret = mt7531_ind_c22_phy_read(priv, port, regnum); 799 } 800 801 return ret; 802 } 803 804 static int 805 mt7531_ind_phy_write(struct mt7530_priv *priv, int port, int regnum, 806 u16 data) 807 { 808 int devad; 809 int ret; 810 811 if (regnum & MII_ADDR_C45) { 812 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; 813 ret = mt7531_ind_c45_phy_write(priv, port, devad, 814 regnum & MII_REGADDR_C45_MASK, 815 data); 816 } else { 817 ret = mt7531_ind_c22_phy_write(priv, port, regnum, data); 818 } 819 820 return ret; 821 } 822 823 static int 824 mt753x_phy_read(struct mii_bus *bus, int port, int regnum) 825 { 826 struct mt7530_priv *priv = bus->priv; 827 828 return priv->info->phy_read(priv, port, regnum); 829 } 830 831 static int 832 mt753x_phy_write(struct mii_bus *bus, int port, int regnum, u16 val) 833 { 834 struct mt7530_priv *priv = bus->priv; 835 836 return priv->info->phy_write(priv, port, regnum, val); 837 } 838 839 static void 840 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 841 uint8_t *data) 842 { 843 int i; 844 845 if (stringset != ETH_SS_STATS) 846 return; 847 848 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 849 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 850 ETH_GSTRING_LEN); 851 } 852 853 static void 854 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 855 uint64_t *data) 856 { 857 struct mt7530_priv *priv = ds->priv; 858 const struct mt7530_mib_desc *mib; 859 u32 reg, i; 860 u64 hi; 861 862 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 863 mib = &mt7530_mib[i]; 864 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 865 866 data[i] = mt7530_read(priv, reg); 867 if (mib->size == 2) { 868 hi = mt7530_read(priv, reg + 4); 869 data[i] |= hi << 32; 870 } 871 } 872 } 873 874 static int 875 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 876 { 877 if (sset != ETH_SS_STATS) 878 return 0; 879 880 return ARRAY_SIZE(mt7530_mib); 881 } 882 883 static int 884 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 885 { 886 struct mt7530_priv *priv = ds->priv; 887 unsigned int secs = msecs / 1000; 888 unsigned int tmp_age_count; 889 unsigned int error = -1; 890 unsigned int age_count; 891 unsigned int age_unit; 892 893 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 894 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 895 return -ERANGE; 896 897 /* iterate through all possible age_count to find the closest pair */ 898 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 899 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 900 901 if (tmp_age_unit <= AGE_UNIT_MAX) { 902 unsigned int tmp_error = secs - 903 (tmp_age_count + 1) * (tmp_age_unit + 1); 904 905 /* found a closer pair */ 906 if (error > tmp_error) { 907 error = tmp_error; 908 age_count = tmp_age_count; 909 age_unit = tmp_age_unit; 910 } 911 912 /* found the exact match, so break the loop */ 913 if (!error) 914 break; 915 } 916 } 917 918 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 919 920 return 0; 921 } 922 923 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 924 { 925 struct mt7530_priv *priv = ds->priv; 926 u8 tx_delay = 0; 927 int val; 928 929 mutex_lock(&priv->reg_mutex); 930 931 val = mt7530_read(priv, MT7530_MHWTRAP); 932 933 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 934 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 935 936 switch (priv->p5_intf_sel) { 937 case P5_INTF_SEL_PHY_P0: 938 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 939 val |= MHWTRAP_PHY0_SEL; 940 fallthrough; 941 case P5_INTF_SEL_PHY_P4: 942 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 943 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 944 945 /* Setup the MAC by default for the cpu port */ 946 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 947 break; 948 case P5_INTF_SEL_GMAC5: 949 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 950 val &= ~MHWTRAP_P5_DIS; 951 break; 952 case P5_DISABLED: 953 interface = PHY_INTERFACE_MODE_NA; 954 break; 955 default: 956 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", 957 priv->p5_intf_sel); 958 goto unlock_exit; 959 } 960 961 /* Setup RGMII settings */ 962 if (phy_interface_mode_is_rgmii(interface)) { 963 val |= MHWTRAP_P5_RGMII_MODE; 964 965 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 966 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 967 968 /* Don't set delay in DSA mode */ 969 if (!dsa_is_dsa_port(priv->ds, 5) && 970 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 971 interface == PHY_INTERFACE_MODE_RGMII_ID)) 972 tx_delay = 4; /* n * 0.5 ns */ 973 974 /* P5 RGMII TX Clock Control: delay x */ 975 mt7530_write(priv, MT7530_P5RGMIITXCR, 976 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 977 978 /* reduce P5 RGMII Tx driving, 8mA */ 979 mt7530_write(priv, MT7530_IO_DRV_CR, 980 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 981 } 982 983 mt7530_write(priv, MT7530_MHWTRAP, val); 984 985 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 986 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 987 988 priv->p5_interface = interface; 989 990 unlock_exit: 991 mutex_unlock(&priv->reg_mutex); 992 } 993 994 static int 995 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 996 { 997 struct mt7530_priv *priv = ds->priv; 998 int ret; 999 1000 /* Setup max capability of CPU port at first */ 1001 if (priv->info->cpu_port_config) { 1002 ret = priv->info->cpu_port_config(ds, port); 1003 if (ret) 1004 return ret; 1005 } 1006 1007 /* Enable Mediatek header mode on the cpu port */ 1008 mt7530_write(priv, MT7530_PVC_P(port), 1009 PORT_SPEC_TAG); 1010 1011 /* Disable flooding by default */ 1012 mt7530_rmw(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK, 1013 BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port))); 1014 1015 /* Set CPU port number */ 1016 if (priv->id == ID_MT7621) 1017 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 1018 1019 /* CPU port gets connected to all user ports of 1020 * the switch. 1021 */ 1022 mt7530_write(priv, MT7530_PCR_P(port), 1023 PCR_MATRIX(dsa_user_ports(priv->ds))); 1024 1025 /* Set to fallback mode for independent VLAN learning */ 1026 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1027 MT7530_PORT_FALLBACK_MODE); 1028 1029 return 0; 1030 } 1031 1032 static int 1033 mt7530_port_enable(struct dsa_switch *ds, int port, 1034 struct phy_device *phy) 1035 { 1036 struct mt7530_priv *priv = ds->priv; 1037 1038 mutex_lock(&priv->reg_mutex); 1039 1040 /* Allow the user port gets connected to the cpu port and also 1041 * restore the port matrix if the port is the member of a certain 1042 * bridge. 1043 */ 1044 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); 1045 priv->ports[port].enable = true; 1046 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1047 priv->ports[port].pm); 1048 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1049 1050 mutex_unlock(&priv->reg_mutex); 1051 1052 return 0; 1053 } 1054 1055 static void 1056 mt7530_port_disable(struct dsa_switch *ds, int port) 1057 { 1058 struct mt7530_priv *priv = ds->priv; 1059 1060 mutex_lock(&priv->reg_mutex); 1061 1062 /* Clear up all port matrix which could be restored in the next 1063 * enablement for the port. 1064 */ 1065 priv->ports[port].enable = false; 1066 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1067 PCR_MATRIX_CLR); 1068 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1069 1070 mutex_unlock(&priv->reg_mutex); 1071 } 1072 1073 static int 1074 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1075 { 1076 struct mt7530_priv *priv = ds->priv; 1077 struct mii_bus *bus = priv->bus; 1078 int length; 1079 u32 val; 1080 1081 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1082 * largest MTU of the slave ports. Because the switch only has a global 1083 * RX length register, only allowing CPU port here is enough. 1084 */ 1085 if (!dsa_is_cpu_port(ds, port)) 1086 return 0; 1087 1088 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 1089 1090 val = mt7530_mii_read(priv, MT7530_GMACCR); 1091 val &= ~MAX_RX_PKT_LEN_MASK; 1092 1093 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1094 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1095 if (length <= 1522) { 1096 val |= MAX_RX_PKT_LEN_1522; 1097 } else if (length <= 1536) { 1098 val |= MAX_RX_PKT_LEN_1536; 1099 } else if (length <= 1552) { 1100 val |= MAX_RX_PKT_LEN_1552; 1101 } else { 1102 val &= ~MAX_RX_JUMBO_MASK; 1103 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1104 val |= MAX_RX_PKT_LEN_JUMBO; 1105 } 1106 1107 mt7530_mii_write(priv, MT7530_GMACCR, val); 1108 1109 mutex_unlock(&bus->mdio_lock); 1110 1111 return 0; 1112 } 1113 1114 static int 1115 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1116 { 1117 return MT7530_MAX_MTU; 1118 } 1119 1120 static void 1121 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1122 { 1123 struct mt7530_priv *priv = ds->priv; 1124 u32 stp_state; 1125 1126 switch (state) { 1127 case BR_STATE_DISABLED: 1128 stp_state = MT7530_STP_DISABLED; 1129 break; 1130 case BR_STATE_BLOCKING: 1131 stp_state = MT7530_STP_BLOCKING; 1132 break; 1133 case BR_STATE_LISTENING: 1134 stp_state = MT7530_STP_LISTENING; 1135 break; 1136 case BR_STATE_LEARNING: 1137 stp_state = MT7530_STP_LEARNING; 1138 break; 1139 case BR_STATE_FORWARDING: 1140 default: 1141 stp_state = MT7530_STP_FORWARDING; 1142 break; 1143 } 1144 1145 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1146 FID_PST(FID_BRIDGED, stp_state)); 1147 } 1148 1149 static int 1150 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1151 struct switchdev_brport_flags flags, 1152 struct netlink_ext_ack *extack) 1153 { 1154 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1155 BR_BCAST_FLOOD)) 1156 return -EINVAL; 1157 1158 return 0; 1159 } 1160 1161 static int 1162 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1163 struct switchdev_brport_flags flags, 1164 struct netlink_ext_ack *extack) 1165 { 1166 struct mt7530_priv *priv = ds->priv; 1167 1168 if (flags.mask & BR_LEARNING) 1169 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1170 flags.val & BR_LEARNING ? 0 : SA_DIS); 1171 1172 if (flags.mask & BR_FLOOD) 1173 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), 1174 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1175 1176 if (flags.mask & BR_MCAST_FLOOD) 1177 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1178 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1179 1180 if (flags.mask & BR_BCAST_FLOOD) 1181 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), 1182 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1183 1184 return 0; 1185 } 1186 1187 static int 1188 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1189 struct dsa_bridge bridge, bool *tx_fwd_offload, 1190 struct netlink_ext_ack *extack) 1191 { 1192 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1193 u32 port_bitmap = BIT(MT7530_CPU_PORT); 1194 struct mt7530_priv *priv = ds->priv; 1195 1196 mutex_lock(&priv->reg_mutex); 1197 1198 dsa_switch_for_each_user_port(other_dp, ds) { 1199 int other_port = other_dp->index; 1200 1201 if (dp == other_dp) 1202 continue; 1203 1204 /* Add this port to the port matrix of the other ports in the 1205 * same bridge. If the port is disabled, port matrix is kept 1206 * and not being setup until the port becomes enabled. 1207 */ 1208 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1209 continue; 1210 1211 if (priv->ports[other_port].enable) 1212 mt7530_set(priv, MT7530_PCR_P(other_port), 1213 PCR_MATRIX(BIT(port))); 1214 priv->ports[other_port].pm |= PCR_MATRIX(BIT(port)); 1215 1216 port_bitmap |= BIT(other_port); 1217 } 1218 1219 /* Add the all other ports to this port matrix. */ 1220 if (priv->ports[port].enable) 1221 mt7530_rmw(priv, MT7530_PCR_P(port), 1222 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1223 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1224 1225 /* Set to fallback mode for independent VLAN learning */ 1226 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1227 MT7530_PORT_FALLBACK_MODE); 1228 1229 mutex_unlock(&priv->reg_mutex); 1230 1231 return 0; 1232 } 1233 1234 static void 1235 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1236 { 1237 struct mt7530_priv *priv = ds->priv; 1238 bool all_user_ports_removed = true; 1239 int i; 1240 1241 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1242 * bridge. Don't set standalone ports to fallback mode. 1243 */ 1244 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) 1245 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1246 MT7530_PORT_FALLBACK_MODE); 1247 1248 mt7530_rmw(priv, MT7530_PVC_P(port), 1249 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1250 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1251 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1252 MT7530_VLAN_ACC_ALL); 1253 1254 /* Set PVID to 0 */ 1255 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1256 G0_PORT_VID_DEF); 1257 1258 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1259 if (dsa_is_user_port(ds, i) && 1260 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1261 all_user_ports_removed = false; 1262 break; 1263 } 1264 } 1265 1266 /* CPU port also does the same thing until all user ports belonging to 1267 * the CPU port get out of VLAN filtering mode. 1268 */ 1269 if (all_user_ports_removed) { 1270 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT), 1271 PCR_MATRIX(dsa_user_ports(priv->ds))); 1272 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG 1273 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1274 } 1275 } 1276 1277 static void 1278 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1279 { 1280 struct mt7530_priv *priv = ds->priv; 1281 1282 /* Trapped into security mode allows packet forwarding through VLAN 1283 * table lookup. 1284 */ 1285 if (dsa_is_user_port(ds, port)) { 1286 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1287 MT7530_PORT_SECURITY_MODE); 1288 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1289 G0_PORT_VID(priv->ports[port].pvid)); 1290 1291 /* Only accept tagged frames if PVID is not set */ 1292 if (!priv->ports[port].pvid) 1293 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1294 MT7530_VLAN_ACC_TAGGED); 1295 } 1296 1297 /* Set the port as a user port which is to be able to recognize VID 1298 * from incoming packets before fetching entry within the VLAN table. 1299 */ 1300 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1301 VLAN_ATTR(MT7530_VLAN_USER) | 1302 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1303 } 1304 1305 static void 1306 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1307 struct dsa_bridge bridge) 1308 { 1309 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1310 struct mt7530_priv *priv = ds->priv; 1311 1312 mutex_lock(&priv->reg_mutex); 1313 1314 dsa_switch_for_each_user_port(other_dp, ds) { 1315 int other_port = other_dp->index; 1316 1317 if (dp == other_dp) 1318 continue; 1319 1320 /* Remove this port from the port matrix of the other ports 1321 * in the same bridge. If the port is disabled, port matrix 1322 * is kept and not being setup until the port becomes enabled. 1323 */ 1324 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1325 continue; 1326 1327 if (priv->ports[other_port].enable) 1328 mt7530_clear(priv, MT7530_PCR_P(other_port), 1329 PCR_MATRIX(BIT(port))); 1330 priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port)); 1331 } 1332 1333 /* Set the cpu port to be the only one in the port matrix of 1334 * this port. 1335 */ 1336 if (priv->ports[port].enable) 1337 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1338 PCR_MATRIX(BIT(MT7530_CPU_PORT))); 1339 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); 1340 1341 /* When a port is removed from the bridge, the port would be set up 1342 * back to the default as is at initial boot which is a VLAN-unaware 1343 * port. 1344 */ 1345 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1346 MT7530_PORT_MATRIX_MODE); 1347 1348 mutex_unlock(&priv->reg_mutex); 1349 } 1350 1351 static int 1352 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1353 const unsigned char *addr, u16 vid, 1354 struct dsa_db db) 1355 { 1356 struct mt7530_priv *priv = ds->priv; 1357 int ret; 1358 u8 port_mask = BIT(port); 1359 1360 mutex_lock(&priv->reg_mutex); 1361 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1362 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1363 mutex_unlock(&priv->reg_mutex); 1364 1365 return ret; 1366 } 1367 1368 static int 1369 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1370 const unsigned char *addr, u16 vid, 1371 struct dsa_db db) 1372 { 1373 struct mt7530_priv *priv = ds->priv; 1374 int ret; 1375 u8 port_mask = BIT(port); 1376 1377 mutex_lock(&priv->reg_mutex); 1378 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1379 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1380 mutex_unlock(&priv->reg_mutex); 1381 1382 return ret; 1383 } 1384 1385 static int 1386 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1387 dsa_fdb_dump_cb_t *cb, void *data) 1388 { 1389 struct mt7530_priv *priv = ds->priv; 1390 struct mt7530_fdb _fdb = { 0 }; 1391 int cnt = MT7530_NUM_FDB_RECORDS; 1392 int ret = 0; 1393 u32 rsp = 0; 1394 1395 mutex_lock(&priv->reg_mutex); 1396 1397 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1398 if (ret < 0) 1399 goto err; 1400 1401 do { 1402 if (rsp & ATC_SRCH_HIT) { 1403 mt7530_fdb_read(priv, &_fdb); 1404 if (_fdb.port_mask & BIT(port)) { 1405 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1406 data); 1407 if (ret < 0) 1408 break; 1409 } 1410 } 1411 } while (--cnt && 1412 !(rsp & ATC_SRCH_END) && 1413 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1414 err: 1415 mutex_unlock(&priv->reg_mutex); 1416 1417 return 0; 1418 } 1419 1420 static int 1421 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1422 const struct switchdev_obj_port_mdb *mdb, 1423 struct dsa_db db) 1424 { 1425 struct mt7530_priv *priv = ds->priv; 1426 const u8 *addr = mdb->addr; 1427 u16 vid = mdb->vid; 1428 u8 port_mask = 0; 1429 int ret; 1430 1431 mutex_lock(&priv->reg_mutex); 1432 1433 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1434 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1435 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1436 & PORT_MAP_MASK; 1437 1438 port_mask |= BIT(port); 1439 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1440 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1441 1442 mutex_unlock(&priv->reg_mutex); 1443 1444 return ret; 1445 } 1446 1447 static int 1448 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1449 const struct switchdev_obj_port_mdb *mdb, 1450 struct dsa_db db) 1451 { 1452 struct mt7530_priv *priv = ds->priv; 1453 const u8 *addr = mdb->addr; 1454 u16 vid = mdb->vid; 1455 u8 port_mask = 0; 1456 int ret; 1457 1458 mutex_lock(&priv->reg_mutex); 1459 1460 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1461 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1462 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1463 & PORT_MAP_MASK; 1464 1465 port_mask &= ~BIT(port); 1466 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1467 port_mask ? STATIC_ENT : STATIC_EMP); 1468 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1469 1470 mutex_unlock(&priv->reg_mutex); 1471 1472 return ret; 1473 } 1474 1475 static int 1476 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1477 { 1478 struct mt7530_dummy_poll p; 1479 u32 val; 1480 int ret; 1481 1482 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1483 mt7530_write(priv, MT7530_VTCR, val); 1484 1485 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1486 ret = readx_poll_timeout(_mt7530_read, &p, val, 1487 !(val & VTCR_BUSY), 20, 20000); 1488 if (ret < 0) { 1489 dev_err(priv->dev, "poll timeout\n"); 1490 return ret; 1491 } 1492 1493 val = mt7530_read(priv, MT7530_VTCR); 1494 if (val & VTCR_INVALID) { 1495 dev_err(priv->dev, "read VTCR invalid\n"); 1496 return -EINVAL; 1497 } 1498 1499 return 0; 1500 } 1501 1502 static int 1503 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1504 struct netlink_ext_ack *extack) 1505 { 1506 if (vlan_filtering) { 1507 /* The port is being kept as VLAN-unaware port when bridge is 1508 * set up with vlan_filtering not being set, Otherwise, the 1509 * port and the corresponding CPU port is required the setup 1510 * for becoming a VLAN-aware port. 1511 */ 1512 mt7530_port_set_vlan_aware(ds, port); 1513 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT); 1514 } else { 1515 mt7530_port_set_vlan_unaware(ds, port); 1516 } 1517 1518 return 0; 1519 } 1520 1521 static void 1522 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1523 struct mt7530_hw_vlan_entry *entry) 1524 { 1525 u8 new_members; 1526 u32 val; 1527 1528 new_members = entry->old_members | BIT(entry->port) | 1529 BIT(MT7530_CPU_PORT); 1530 1531 /* Validate the entry with independent learning, create egress tag per 1532 * VLAN and joining the port as one of the port members. 1533 */ 1534 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1535 VLAN_VALID; 1536 mt7530_write(priv, MT7530_VAWD1, val); 1537 1538 /* Decide whether adding tag or not for those outgoing packets from the 1539 * port inside the VLAN. 1540 */ 1541 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG : 1542 MT7530_VLAN_EGRESS_TAG; 1543 mt7530_rmw(priv, MT7530_VAWD2, 1544 ETAG_CTRL_P_MASK(entry->port), 1545 ETAG_CTRL_P(entry->port, val)); 1546 1547 /* CPU port is always taken as a tagged port for serving more than one 1548 * VLANs across and also being applied with egress type stack mode for 1549 * that VLAN tags would be appended after hardware special tag used as 1550 * DSA tag. 1551 */ 1552 mt7530_rmw(priv, MT7530_VAWD2, 1553 ETAG_CTRL_P_MASK(MT7530_CPU_PORT), 1554 ETAG_CTRL_P(MT7530_CPU_PORT, 1555 MT7530_VLAN_EGRESS_STACK)); 1556 } 1557 1558 static void 1559 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1560 struct mt7530_hw_vlan_entry *entry) 1561 { 1562 u8 new_members; 1563 u32 val; 1564 1565 new_members = entry->old_members & ~BIT(entry->port); 1566 1567 val = mt7530_read(priv, MT7530_VAWD1); 1568 if (!(val & VLAN_VALID)) { 1569 dev_err(priv->dev, 1570 "Cannot be deleted due to invalid entry\n"); 1571 return; 1572 } 1573 1574 /* If certain member apart from CPU port is still alive in the VLAN, 1575 * the entry would be kept valid. Otherwise, the entry is got to be 1576 * disabled. 1577 */ 1578 if (new_members && new_members != BIT(MT7530_CPU_PORT)) { 1579 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1580 VLAN_VALID; 1581 mt7530_write(priv, MT7530_VAWD1, val); 1582 } else { 1583 mt7530_write(priv, MT7530_VAWD1, 0); 1584 mt7530_write(priv, MT7530_VAWD2, 0); 1585 } 1586 } 1587 1588 static void 1589 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1590 struct mt7530_hw_vlan_entry *entry, 1591 mt7530_vlan_op vlan_op) 1592 { 1593 u32 val; 1594 1595 /* Fetch entry */ 1596 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1597 1598 val = mt7530_read(priv, MT7530_VAWD1); 1599 1600 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1601 1602 /* Manipulate entry */ 1603 vlan_op(priv, entry); 1604 1605 /* Flush result to hardware */ 1606 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1607 } 1608 1609 static int 1610 mt7530_setup_vlan0(struct mt7530_priv *priv) 1611 { 1612 u32 val; 1613 1614 /* Validate the entry with independent learning, keep the original 1615 * ingress tag attribute. 1616 */ 1617 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1618 VLAN_VALID; 1619 mt7530_write(priv, MT7530_VAWD1, val); 1620 1621 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1622 } 1623 1624 static int 1625 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1626 const struct switchdev_obj_port_vlan *vlan, 1627 struct netlink_ext_ack *extack) 1628 { 1629 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1630 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1631 struct mt7530_hw_vlan_entry new_entry; 1632 struct mt7530_priv *priv = ds->priv; 1633 1634 mutex_lock(&priv->reg_mutex); 1635 1636 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1637 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1638 1639 if (pvid) { 1640 priv->ports[port].pvid = vlan->vid; 1641 1642 /* Accept all frames if PVID is set */ 1643 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1644 MT7530_VLAN_ACC_ALL); 1645 1646 /* Only configure PVID if VLAN filtering is enabled */ 1647 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1648 mt7530_rmw(priv, MT7530_PPBV1_P(port), 1649 G0_PORT_VID_MASK, 1650 G0_PORT_VID(vlan->vid)); 1651 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 1652 /* This VLAN is overwritten without PVID, so unset it */ 1653 priv->ports[port].pvid = G0_PORT_VID_DEF; 1654 1655 /* Only accept tagged frames if the port is VLAN-aware */ 1656 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1657 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1658 MT7530_VLAN_ACC_TAGGED); 1659 1660 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1661 G0_PORT_VID_DEF); 1662 } 1663 1664 mutex_unlock(&priv->reg_mutex); 1665 1666 return 0; 1667 } 1668 1669 static int 1670 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1671 const struct switchdev_obj_port_vlan *vlan) 1672 { 1673 struct mt7530_hw_vlan_entry target_entry; 1674 struct mt7530_priv *priv = ds->priv; 1675 1676 mutex_lock(&priv->reg_mutex); 1677 1678 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1679 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1680 mt7530_hw_vlan_del); 1681 1682 /* PVID is being restored to the default whenever the PVID port 1683 * is being removed from the VLAN. 1684 */ 1685 if (priv->ports[port].pvid == vlan->vid) { 1686 priv->ports[port].pvid = G0_PORT_VID_DEF; 1687 1688 /* Only accept tagged frames if the port is VLAN-aware */ 1689 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1690 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1691 MT7530_VLAN_ACC_TAGGED); 1692 1693 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1694 G0_PORT_VID_DEF); 1695 } 1696 1697 1698 mutex_unlock(&priv->reg_mutex); 1699 1700 return 0; 1701 } 1702 1703 static int mt753x_mirror_port_get(unsigned int id, u32 val) 1704 { 1705 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : 1706 MIRROR_PORT(val); 1707 } 1708 1709 static int mt753x_mirror_port_set(unsigned int id, u32 val) 1710 { 1711 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : 1712 MIRROR_PORT(val); 1713 } 1714 1715 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1716 struct dsa_mall_mirror_tc_entry *mirror, 1717 bool ingress, struct netlink_ext_ack *extack) 1718 { 1719 struct mt7530_priv *priv = ds->priv; 1720 int monitor_port; 1721 u32 val; 1722 1723 /* Check for existent entry */ 1724 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1725 return -EEXIST; 1726 1727 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1728 1729 /* MT7530 only supports one monitor port */ 1730 monitor_port = mt753x_mirror_port_get(priv->id, val); 1731 if (val & MT753X_MIRROR_EN(priv->id) && 1732 monitor_port != mirror->to_local_port) 1733 return -EEXIST; 1734 1735 val |= MT753X_MIRROR_EN(priv->id); 1736 val &= ~MT753X_MIRROR_MASK(priv->id); 1737 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); 1738 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1739 1740 val = mt7530_read(priv, MT7530_PCR_P(port)); 1741 if (ingress) { 1742 val |= PORT_RX_MIR; 1743 priv->mirror_rx |= BIT(port); 1744 } else { 1745 val |= PORT_TX_MIR; 1746 priv->mirror_tx |= BIT(port); 1747 } 1748 mt7530_write(priv, MT7530_PCR_P(port), val); 1749 1750 return 0; 1751 } 1752 1753 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1754 struct dsa_mall_mirror_tc_entry *mirror) 1755 { 1756 struct mt7530_priv *priv = ds->priv; 1757 u32 val; 1758 1759 val = mt7530_read(priv, MT7530_PCR_P(port)); 1760 if (mirror->ingress) { 1761 val &= ~PORT_RX_MIR; 1762 priv->mirror_rx &= ~BIT(port); 1763 } else { 1764 val &= ~PORT_TX_MIR; 1765 priv->mirror_tx &= ~BIT(port); 1766 } 1767 mt7530_write(priv, MT7530_PCR_P(port), val); 1768 1769 if (!priv->mirror_rx && !priv->mirror_tx) { 1770 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1771 val &= ~MT753X_MIRROR_EN(priv->id); 1772 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1773 } 1774 } 1775 1776 static enum dsa_tag_protocol 1777 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1778 enum dsa_tag_protocol mp) 1779 { 1780 return DSA_TAG_PROTO_MTK; 1781 } 1782 1783 #ifdef CONFIG_GPIOLIB 1784 static inline u32 1785 mt7530_gpio_to_bit(unsigned int offset) 1786 { 1787 /* Map GPIO offset to register bit 1788 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1789 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1790 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1791 * [14:12] port 3 LED 0..2 as GPIO 9..11 1792 * [18:16] port 4 LED 0..2 as GPIO 12..14 1793 */ 1794 return BIT(offset + offset / 3); 1795 } 1796 1797 static int 1798 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1799 { 1800 struct mt7530_priv *priv = gpiochip_get_data(gc); 1801 u32 bit = mt7530_gpio_to_bit(offset); 1802 1803 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1804 } 1805 1806 static void 1807 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1808 { 1809 struct mt7530_priv *priv = gpiochip_get_data(gc); 1810 u32 bit = mt7530_gpio_to_bit(offset); 1811 1812 if (value) 1813 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1814 else 1815 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1816 } 1817 1818 static int 1819 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1820 { 1821 struct mt7530_priv *priv = gpiochip_get_data(gc); 1822 u32 bit = mt7530_gpio_to_bit(offset); 1823 1824 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1825 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1826 } 1827 1828 static int 1829 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1830 { 1831 struct mt7530_priv *priv = gpiochip_get_data(gc); 1832 u32 bit = mt7530_gpio_to_bit(offset); 1833 1834 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 1835 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 1836 1837 return 0; 1838 } 1839 1840 static int 1841 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 1842 { 1843 struct mt7530_priv *priv = gpiochip_get_data(gc); 1844 u32 bit = mt7530_gpio_to_bit(offset); 1845 1846 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 1847 1848 if (value) 1849 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1850 else 1851 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1852 1853 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 1854 1855 return 0; 1856 } 1857 1858 static int 1859 mt7530_setup_gpio(struct mt7530_priv *priv) 1860 { 1861 struct device *dev = priv->dev; 1862 struct gpio_chip *gc; 1863 1864 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1865 if (!gc) 1866 return -ENOMEM; 1867 1868 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 1869 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 1870 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 1871 1872 gc->label = "mt7530"; 1873 gc->parent = dev; 1874 gc->owner = THIS_MODULE; 1875 gc->get_direction = mt7530_gpio_get_direction; 1876 gc->direction_input = mt7530_gpio_direction_input; 1877 gc->direction_output = mt7530_gpio_direction_output; 1878 gc->get = mt7530_gpio_get; 1879 gc->set = mt7530_gpio_set; 1880 gc->base = -1; 1881 gc->ngpio = 15; 1882 gc->can_sleep = true; 1883 1884 return devm_gpiochip_add_data(dev, gc, priv); 1885 } 1886 #endif /* CONFIG_GPIOLIB */ 1887 1888 static irqreturn_t 1889 mt7530_irq_thread_fn(int irq, void *dev_id) 1890 { 1891 struct mt7530_priv *priv = dev_id; 1892 bool handled = false; 1893 u32 val; 1894 int p; 1895 1896 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 1897 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); 1898 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); 1899 mutex_unlock(&priv->bus->mdio_lock); 1900 1901 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1902 if (BIT(p) & val) { 1903 unsigned int irq; 1904 1905 irq = irq_find_mapping(priv->irq_domain, p); 1906 handle_nested_irq(irq); 1907 handled = true; 1908 } 1909 } 1910 1911 return IRQ_RETVAL(handled); 1912 } 1913 1914 static void 1915 mt7530_irq_mask(struct irq_data *d) 1916 { 1917 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1918 1919 priv->irq_enable &= ~BIT(d->hwirq); 1920 } 1921 1922 static void 1923 mt7530_irq_unmask(struct irq_data *d) 1924 { 1925 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1926 1927 priv->irq_enable |= BIT(d->hwirq); 1928 } 1929 1930 static void 1931 mt7530_irq_bus_lock(struct irq_data *d) 1932 { 1933 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1934 1935 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 1936 } 1937 1938 static void 1939 mt7530_irq_bus_sync_unlock(struct irq_data *d) 1940 { 1941 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1942 1943 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 1944 mutex_unlock(&priv->bus->mdio_lock); 1945 } 1946 1947 static struct irq_chip mt7530_irq_chip = { 1948 .name = KBUILD_MODNAME, 1949 .irq_mask = mt7530_irq_mask, 1950 .irq_unmask = mt7530_irq_unmask, 1951 .irq_bus_lock = mt7530_irq_bus_lock, 1952 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, 1953 }; 1954 1955 static int 1956 mt7530_irq_map(struct irq_domain *domain, unsigned int irq, 1957 irq_hw_number_t hwirq) 1958 { 1959 irq_set_chip_data(irq, domain->host_data); 1960 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); 1961 irq_set_nested_thread(irq, true); 1962 irq_set_noprobe(irq); 1963 1964 return 0; 1965 } 1966 1967 static const struct irq_domain_ops mt7530_irq_domain_ops = { 1968 .map = mt7530_irq_map, 1969 .xlate = irq_domain_xlate_onecell, 1970 }; 1971 1972 static void 1973 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 1974 { 1975 struct dsa_switch *ds = priv->ds; 1976 int p; 1977 1978 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1979 if (BIT(p) & ds->phys_mii_mask) { 1980 unsigned int irq; 1981 1982 irq = irq_create_mapping(priv->irq_domain, p); 1983 ds->slave_mii_bus->irq[p] = irq; 1984 } 1985 } 1986 } 1987 1988 static int 1989 mt7530_setup_irq(struct mt7530_priv *priv) 1990 { 1991 struct device *dev = priv->dev; 1992 struct device_node *np = dev->of_node; 1993 int ret; 1994 1995 if (!of_property_read_bool(np, "interrupt-controller")) { 1996 dev_info(dev, "no interrupt support\n"); 1997 return 0; 1998 } 1999 2000 priv->irq = of_irq_get(np, 0); 2001 if (priv->irq <= 0) { 2002 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); 2003 return priv->irq ? : -EINVAL; 2004 } 2005 2006 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2007 &mt7530_irq_domain_ops, priv); 2008 if (!priv->irq_domain) { 2009 dev_err(dev, "failed to create IRQ domain\n"); 2010 return -ENOMEM; 2011 } 2012 2013 /* This register must be set for MT7530 to properly fire interrupts */ 2014 if (priv->id != ID_MT7531) 2015 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 2016 2017 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, 2018 IRQF_ONESHOT, KBUILD_MODNAME, priv); 2019 if (ret) { 2020 irq_domain_remove(priv->irq_domain); 2021 dev_err(dev, "failed to request IRQ: %d\n", ret); 2022 return ret; 2023 } 2024 2025 return 0; 2026 } 2027 2028 static void 2029 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2030 { 2031 int p; 2032 2033 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2034 if (BIT(p) & priv->ds->phys_mii_mask) { 2035 unsigned int irq; 2036 2037 irq = irq_find_mapping(priv->irq_domain, p); 2038 irq_dispose_mapping(irq); 2039 } 2040 } 2041 } 2042 2043 static void 2044 mt7530_free_irq_common(struct mt7530_priv *priv) 2045 { 2046 free_irq(priv->irq, priv); 2047 irq_domain_remove(priv->irq_domain); 2048 } 2049 2050 static void 2051 mt7530_free_irq(struct mt7530_priv *priv) 2052 { 2053 mt7530_free_mdio_irq(priv); 2054 mt7530_free_irq_common(priv); 2055 } 2056 2057 static int 2058 mt7530_setup_mdio(struct mt7530_priv *priv) 2059 { 2060 struct dsa_switch *ds = priv->ds; 2061 struct device *dev = priv->dev; 2062 struct mii_bus *bus; 2063 static int idx; 2064 int ret; 2065 2066 bus = devm_mdiobus_alloc(dev); 2067 if (!bus) 2068 return -ENOMEM; 2069 2070 ds->slave_mii_bus = bus; 2071 bus->priv = priv; 2072 bus->name = KBUILD_MODNAME "-mii"; 2073 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2074 bus->read = mt753x_phy_read; 2075 bus->write = mt753x_phy_write; 2076 bus->parent = dev; 2077 bus->phy_mask = ~ds->phys_mii_mask; 2078 2079 if (priv->irq) 2080 mt7530_setup_mdio_irq(priv); 2081 2082 ret = devm_mdiobus_register(dev, bus); 2083 if (ret) { 2084 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2085 if (priv->irq) 2086 mt7530_free_mdio_irq(priv); 2087 } 2088 2089 return ret; 2090 } 2091 2092 static int 2093 mt7530_setup(struct dsa_switch *ds) 2094 { 2095 struct mt7530_priv *priv = ds->priv; 2096 struct device_node *phy_node; 2097 struct device_node *mac_np; 2098 struct mt7530_dummy_poll p; 2099 phy_interface_t interface; 2100 struct device_node *dn; 2101 u32 id, val; 2102 int ret, i; 2103 2104 /* The parent node of master netdev which holds the common system 2105 * controller also is the container for two GMACs nodes representing 2106 * as two netdev instances. 2107 */ 2108 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent; 2109 ds->assisted_learning_on_cpu_port = true; 2110 ds->mtu_enforcement_ingress = true; 2111 2112 if (priv->id == ID_MT7530) { 2113 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2114 ret = regulator_enable(priv->core_pwr); 2115 if (ret < 0) { 2116 dev_err(priv->dev, 2117 "Failed to enable core power: %d\n", ret); 2118 return ret; 2119 } 2120 2121 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2122 ret = regulator_enable(priv->io_pwr); 2123 if (ret < 0) { 2124 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2125 ret); 2126 return ret; 2127 } 2128 } 2129 2130 /* Reset whole chip through gpio pin or memory-mapped registers for 2131 * different type of hardware 2132 */ 2133 if (priv->mcm) { 2134 reset_control_assert(priv->rstc); 2135 usleep_range(1000, 1100); 2136 reset_control_deassert(priv->rstc); 2137 } else { 2138 gpiod_set_value_cansleep(priv->reset, 0); 2139 usleep_range(1000, 1100); 2140 gpiod_set_value_cansleep(priv->reset, 1); 2141 } 2142 2143 /* Waiting for MT7530 got to stable */ 2144 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2145 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2146 20, 1000000); 2147 if (ret < 0) { 2148 dev_err(priv->dev, "reset timeout\n"); 2149 return ret; 2150 } 2151 2152 id = mt7530_read(priv, MT7530_CREV); 2153 id >>= CHIP_NAME_SHIFT; 2154 if (id != MT7530_ID) { 2155 dev_err(priv->dev, "chip %x can't be supported\n", id); 2156 return -ENODEV; 2157 } 2158 2159 /* Reset the switch through internal reset */ 2160 mt7530_write(priv, MT7530_SYS_CTRL, 2161 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2162 SYS_CTRL_REG_RST); 2163 2164 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */ 2165 val = mt7530_read(priv, MT7530_MHWTRAP); 2166 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 2167 val |= MHWTRAP_MANUAL; 2168 mt7530_write(priv, MT7530_MHWTRAP, val); 2169 2170 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2171 2172 /* Enable and reset MIB counters */ 2173 mt7530_mib_reset(ds); 2174 2175 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2176 /* Disable forwarding by default on all ports */ 2177 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2178 PCR_MATRIX_CLR); 2179 2180 /* Disable learning by default on all ports */ 2181 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2182 2183 if (dsa_is_cpu_port(ds, i)) { 2184 ret = mt753x_cpu_port_enable(ds, i); 2185 if (ret) 2186 return ret; 2187 } else { 2188 mt7530_port_disable(ds, i); 2189 2190 /* Set default PVID to 0 on all user ports */ 2191 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2192 G0_PORT_VID_DEF); 2193 } 2194 /* Enable consistent egress tag */ 2195 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2196 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2197 } 2198 2199 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2200 ret = mt7530_setup_vlan0(priv); 2201 if (ret) 2202 return ret; 2203 2204 /* Setup port 5 */ 2205 priv->p5_intf_sel = P5_DISABLED; 2206 interface = PHY_INTERFACE_MODE_NA; 2207 2208 if (!dsa_is_unused_port(ds, 5)) { 2209 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2210 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); 2211 if (ret && ret != -ENODEV) 2212 return ret; 2213 } else { 2214 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ 2215 for_each_child_of_node(dn, mac_np) { 2216 if (!of_device_is_compatible(mac_np, 2217 "mediatek,eth-mac")) 2218 continue; 2219 2220 ret = of_property_read_u32(mac_np, "reg", &id); 2221 if (ret < 0 || id != 1) 2222 continue; 2223 2224 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2225 if (!phy_node) 2226 continue; 2227 2228 if (phy_node->parent == priv->dev->of_node->parent) { 2229 ret = of_get_phy_mode(mac_np, &interface); 2230 if (ret && ret != -ENODEV) { 2231 of_node_put(mac_np); 2232 return ret; 2233 } 2234 id = of_mdio_parse_addr(ds->dev, phy_node); 2235 if (id == 0) 2236 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 2237 if (id == 4) 2238 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 2239 } 2240 of_node_put(mac_np); 2241 of_node_put(phy_node); 2242 break; 2243 } 2244 } 2245 2246 #ifdef CONFIG_GPIOLIB 2247 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2248 ret = mt7530_setup_gpio(priv); 2249 if (ret) 2250 return ret; 2251 } 2252 #endif /* CONFIG_GPIOLIB */ 2253 2254 mt7530_setup_port5(ds, interface); 2255 2256 /* Flush the FDB table */ 2257 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2258 if (ret < 0) 2259 return ret; 2260 2261 return 0; 2262 } 2263 2264 static int 2265 mt7531_setup(struct dsa_switch *ds) 2266 { 2267 struct mt7530_priv *priv = ds->priv; 2268 struct mt7530_dummy_poll p; 2269 u32 val, id; 2270 int ret, i; 2271 2272 /* Reset whole chip through gpio pin or memory-mapped registers for 2273 * different type of hardware 2274 */ 2275 if (priv->mcm) { 2276 reset_control_assert(priv->rstc); 2277 usleep_range(1000, 1100); 2278 reset_control_deassert(priv->rstc); 2279 } else { 2280 gpiod_set_value_cansleep(priv->reset, 0); 2281 usleep_range(1000, 1100); 2282 gpiod_set_value_cansleep(priv->reset, 1); 2283 } 2284 2285 /* Waiting for MT7530 got to stable */ 2286 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2287 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2288 20, 1000000); 2289 if (ret < 0) { 2290 dev_err(priv->dev, "reset timeout\n"); 2291 return ret; 2292 } 2293 2294 id = mt7530_read(priv, MT7531_CREV); 2295 id >>= CHIP_NAME_SHIFT; 2296 2297 if (id != MT7531_ID) { 2298 dev_err(priv->dev, "chip %x can't be supported\n", id); 2299 return -ENODEV; 2300 } 2301 2302 /* Reset the switch through internal reset */ 2303 mt7530_write(priv, MT7530_SYS_CTRL, 2304 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2305 SYS_CTRL_REG_RST); 2306 2307 if (mt7531_dual_sgmii_supported(priv)) { 2308 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; 2309 2310 /* Let ds->slave_mii_bus be able to access external phy. */ 2311 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2312 MT7531_EXT_P_MDC_11); 2313 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2314 MT7531_EXT_P_MDIO_12); 2315 } else { 2316 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2317 } 2318 dev_dbg(ds->dev, "P5 support %s interface\n", 2319 p5_intf_modes(priv->p5_intf_sel)); 2320 2321 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2322 MT7531_GPIO0_INTERRUPT); 2323 2324 /* Let phylink decide the interface later. */ 2325 priv->p5_interface = PHY_INTERFACE_MODE_NA; 2326 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2327 2328 /* Enable PHY core PLL, since phy_device has not yet been created 2329 * provided for phy_[read,write]_mmd_indirect is called, we provide 2330 * our own mt7531_ind_mmd_phy_[read,write] to complete this 2331 * function. 2332 */ 2333 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, 2334 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2335 val |= MT7531_PHY_PLL_BYPASS_MODE; 2336 val &= ~MT7531_PHY_PLL_OFF; 2337 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, 2338 CORE_PLL_GROUP4, val); 2339 2340 /* BPDU to CPU port */ 2341 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, 2342 BIT(MT7530_CPU_PORT)); 2343 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, 2344 MT753X_BPDU_CPU_ONLY); 2345 2346 /* Enable and reset MIB counters */ 2347 mt7530_mib_reset(ds); 2348 2349 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2350 /* Disable forwarding by default on all ports */ 2351 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2352 PCR_MATRIX_CLR); 2353 2354 /* Disable learning by default on all ports */ 2355 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2356 2357 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2358 2359 if (dsa_is_cpu_port(ds, i)) { 2360 ret = mt753x_cpu_port_enable(ds, i); 2361 if (ret) 2362 return ret; 2363 } else { 2364 mt7530_port_disable(ds, i); 2365 2366 /* Set default PVID to 0 on all user ports */ 2367 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2368 G0_PORT_VID_DEF); 2369 } 2370 2371 /* Enable consistent egress tag */ 2372 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2373 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2374 } 2375 2376 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2377 ret = mt7530_setup_vlan0(priv); 2378 if (ret) 2379 return ret; 2380 2381 ds->assisted_learning_on_cpu_port = true; 2382 ds->mtu_enforcement_ingress = true; 2383 2384 /* Flush the FDB table */ 2385 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2386 if (ret < 0) 2387 return ret; 2388 2389 return 0; 2390 } 2391 2392 static bool 2393 mt7530_phy_mode_supported(struct dsa_switch *ds, int port, 2394 const struct phylink_link_state *state) 2395 { 2396 struct mt7530_priv *priv = ds->priv; 2397 2398 switch (port) { 2399 case 0 ... 4: /* Internal phy */ 2400 if (state->interface != PHY_INTERFACE_MODE_GMII) 2401 return false; 2402 break; 2403 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2404 if (!phy_interface_mode_is_rgmii(state->interface) && 2405 state->interface != PHY_INTERFACE_MODE_MII && 2406 state->interface != PHY_INTERFACE_MODE_GMII) 2407 return false; 2408 break; 2409 case 6: /* 1st cpu port */ 2410 if (state->interface != PHY_INTERFACE_MODE_RGMII && 2411 state->interface != PHY_INTERFACE_MODE_TRGMII) 2412 return false; 2413 break; 2414 default: 2415 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, 2416 port); 2417 return false; 2418 } 2419 2420 return true; 2421 } 2422 2423 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) 2424 { 2425 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); 2426 } 2427 2428 static bool 2429 mt7531_phy_mode_supported(struct dsa_switch *ds, int port, 2430 const struct phylink_link_state *state) 2431 { 2432 struct mt7530_priv *priv = ds->priv; 2433 2434 switch (port) { 2435 case 0 ... 4: /* Internal phy */ 2436 if (state->interface != PHY_INTERFACE_MODE_GMII) 2437 return false; 2438 break; 2439 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ 2440 if (mt7531_is_rgmii_port(priv, port)) 2441 return phy_interface_mode_is_rgmii(state->interface); 2442 fallthrough; 2443 case 6: /* 1st cpu port supports sgmii/8023z only */ 2444 if (state->interface != PHY_INTERFACE_MODE_SGMII && 2445 !phy_interface_mode_is_8023z(state->interface)) 2446 return false; 2447 break; 2448 default: 2449 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, 2450 port); 2451 return false; 2452 } 2453 2454 return true; 2455 } 2456 2457 static bool 2458 mt753x_phy_mode_supported(struct dsa_switch *ds, int port, 2459 const struct phylink_link_state *state) 2460 { 2461 struct mt7530_priv *priv = ds->priv; 2462 2463 return priv->info->phy_mode_supported(ds, port, state); 2464 } 2465 2466 static int 2467 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) 2468 { 2469 struct mt7530_priv *priv = ds->priv; 2470 2471 return priv->info->pad_setup(ds, state->interface); 2472 } 2473 2474 static int 2475 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2476 phy_interface_t interface) 2477 { 2478 struct mt7530_priv *priv = ds->priv; 2479 2480 /* Only need to setup port5. */ 2481 if (port != 5) 2482 return 0; 2483 2484 mt7530_setup_port5(priv->ds, interface); 2485 2486 return 0; 2487 } 2488 2489 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 2490 phy_interface_t interface, 2491 struct phy_device *phydev) 2492 { 2493 u32 val; 2494 2495 if (!mt7531_is_rgmii_port(priv, port)) { 2496 dev_err(priv->dev, "RGMII mode is not available for port %d\n", 2497 port); 2498 return -EINVAL; 2499 } 2500 2501 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2502 val |= GP_CLK_EN; 2503 val &= ~GP_MODE_MASK; 2504 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2505 val &= ~CLK_SKEW_IN_MASK; 2506 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2507 val &= ~CLK_SKEW_OUT_MASK; 2508 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2509 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2510 2511 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2512 if (!phydev || phy_driver_is_genphy(phydev)) { 2513 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2514 switch (interface) { 2515 case PHY_INTERFACE_MODE_RGMII: 2516 val |= TXCLK_NO_REVERSE; 2517 val |= RXCLK_NO_DELAY; 2518 break; 2519 case PHY_INTERFACE_MODE_RGMII_RXID: 2520 val |= TXCLK_NO_REVERSE; 2521 break; 2522 case PHY_INTERFACE_MODE_RGMII_TXID: 2523 val |= RXCLK_NO_DELAY; 2524 break; 2525 case PHY_INTERFACE_MODE_RGMII_ID: 2526 break; 2527 default: 2528 return -EINVAL; 2529 } 2530 } 2531 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2532 2533 return 0; 2534 } 2535 2536 static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port, 2537 unsigned long *supported) 2538 { 2539 /* Port5 supports ethier RGMII or SGMII. 2540 * Port6 supports SGMII only. 2541 */ 2542 switch (port) { 2543 case 5: 2544 if (mt7531_is_rgmii_port(priv, port)) 2545 break; 2546 fallthrough; 2547 case 6: 2548 phylink_set(supported, 1000baseX_Full); 2549 phylink_set(supported, 2500baseX_Full); 2550 phylink_set(supported, 2500baseT_Full); 2551 } 2552 } 2553 2554 static void 2555 mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port, 2556 unsigned int mode, phy_interface_t interface, 2557 int speed, int duplex) 2558 { 2559 struct mt7530_priv *priv = ds->priv; 2560 unsigned int val; 2561 2562 /* For adjusting speed and duplex of SGMII force mode. */ 2563 if (interface != PHY_INTERFACE_MODE_SGMII || 2564 phylink_autoneg_inband(mode)) 2565 return; 2566 2567 /* SGMII force mode setting */ 2568 val = mt7530_read(priv, MT7531_SGMII_MODE(port)); 2569 val &= ~MT7531_SGMII_IF_MODE_MASK; 2570 2571 switch (speed) { 2572 case SPEED_10: 2573 val |= MT7531_SGMII_FORCE_SPEED_10; 2574 break; 2575 case SPEED_100: 2576 val |= MT7531_SGMII_FORCE_SPEED_100; 2577 break; 2578 case SPEED_1000: 2579 val |= MT7531_SGMII_FORCE_SPEED_1000; 2580 break; 2581 } 2582 2583 /* MT7531 SGMII 1G force mode can only work in full duplex mode, 2584 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2585 */ 2586 if ((speed == SPEED_10 || speed == SPEED_100) && 2587 duplex != DUPLEX_FULL) 2588 val |= MT7531_SGMII_FORCE_HALF_DUPLEX; 2589 2590 mt7530_write(priv, MT7531_SGMII_MODE(port), val); 2591 } 2592 2593 static bool mt753x_is_mac_port(u32 port) 2594 { 2595 return (port == 5 || port == 6); 2596 } 2597 2598 static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port, 2599 phy_interface_t interface) 2600 { 2601 u32 val; 2602 2603 if (!mt753x_is_mac_port(port)) 2604 return -EINVAL; 2605 2606 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2607 MT7531_SGMII_PHYA_PWD); 2608 2609 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port)); 2610 val &= ~MT7531_RG_TPHY_SPEED_MASK; 2611 /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B 2612 * encoding. 2613 */ 2614 val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ? 2615 MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G; 2616 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val); 2617 2618 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2619 2620 /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex 2621 * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2622 */ 2623 mt7530_rmw(priv, MT7531_SGMII_MODE(port), 2624 MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS, 2625 MT7531_SGMII_FORCE_SPEED_1000); 2626 2627 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2628 2629 return 0; 2630 } 2631 2632 static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port, 2633 phy_interface_t interface) 2634 { 2635 if (!mt753x_is_mac_port(port)) 2636 return -EINVAL; 2637 2638 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2639 MT7531_SGMII_PHYA_PWD); 2640 2641 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), 2642 MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G); 2643 2644 mt7530_set(priv, MT7531_SGMII_MODE(port), 2645 MT7531_SGMII_REMOTE_FAULT_DIS | 2646 MT7531_SGMII_SPEED_DUPLEX_AN); 2647 2648 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port), 2649 MT7531_SGMII_TX_CONFIG_MASK, 1); 2650 2651 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2652 2653 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART); 2654 2655 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2656 2657 return 0; 2658 } 2659 2660 static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port) 2661 { 2662 struct mt7530_priv *priv = ds->priv; 2663 u32 val; 2664 2665 /* Only restart AN when AN is enabled */ 2666 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2667 if (val & MT7531_SGMII_AN_ENABLE) { 2668 val |= MT7531_SGMII_AN_RESTART; 2669 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val); 2670 } 2671 } 2672 2673 static int 2674 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2675 phy_interface_t interface) 2676 { 2677 struct mt7530_priv *priv = ds->priv; 2678 struct phy_device *phydev; 2679 struct dsa_port *dp; 2680 2681 if (!mt753x_is_mac_port(port)) { 2682 dev_err(priv->dev, "port %d is not a MAC port\n", port); 2683 return -EINVAL; 2684 } 2685 2686 switch (interface) { 2687 case PHY_INTERFACE_MODE_RGMII: 2688 case PHY_INTERFACE_MODE_RGMII_ID: 2689 case PHY_INTERFACE_MODE_RGMII_RXID: 2690 case PHY_INTERFACE_MODE_RGMII_TXID: 2691 dp = dsa_to_port(ds, port); 2692 phydev = dp->slave->phydev; 2693 return mt7531_rgmii_setup(priv, port, interface, phydev); 2694 case PHY_INTERFACE_MODE_SGMII: 2695 return mt7531_sgmii_setup_mode_an(priv, port, interface); 2696 case PHY_INTERFACE_MODE_NA: 2697 case PHY_INTERFACE_MODE_1000BASEX: 2698 case PHY_INTERFACE_MODE_2500BASEX: 2699 if (phylink_autoneg_inband(mode)) 2700 return -EINVAL; 2701 2702 return mt7531_sgmii_setup_mode_force(priv, port, interface); 2703 default: 2704 return -EINVAL; 2705 } 2706 2707 return -EINVAL; 2708 } 2709 2710 static int 2711 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2712 const struct phylink_link_state *state) 2713 { 2714 struct mt7530_priv *priv = ds->priv; 2715 2716 return priv->info->mac_port_config(ds, port, mode, state->interface); 2717 } 2718 2719 static void 2720 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2721 const struct phylink_link_state *state) 2722 { 2723 struct mt7530_priv *priv = ds->priv; 2724 u32 mcr_cur, mcr_new; 2725 2726 if (!mt753x_phy_mode_supported(ds, port, state)) 2727 goto unsupported; 2728 2729 switch (port) { 2730 case 0 ... 4: /* Internal phy */ 2731 if (state->interface != PHY_INTERFACE_MODE_GMII) 2732 goto unsupported; 2733 break; 2734 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2735 if (priv->p5_interface == state->interface) 2736 break; 2737 2738 if (mt753x_mac_config(ds, port, mode, state) < 0) 2739 goto unsupported; 2740 2741 if (priv->p5_intf_sel != P5_DISABLED) 2742 priv->p5_interface = state->interface; 2743 break; 2744 case 6: /* 1st cpu port */ 2745 if (priv->p6_interface == state->interface) 2746 break; 2747 2748 mt753x_pad_setup(ds, state); 2749 2750 if (mt753x_mac_config(ds, port, mode, state) < 0) 2751 goto unsupported; 2752 2753 priv->p6_interface = state->interface; 2754 break; 2755 default: 2756 unsupported: 2757 dev_err(ds->dev, "%s: unsupported %s port: %i\n", 2758 __func__, phy_modes(state->interface), port); 2759 return; 2760 } 2761 2762 if (phylink_autoneg_inband(mode) && 2763 state->interface != PHY_INTERFACE_MODE_SGMII) { 2764 dev_err(ds->dev, "%s: in-band negotiation unsupported\n", 2765 __func__); 2766 return; 2767 } 2768 2769 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); 2770 mcr_new = mcr_cur; 2771 mcr_new &= ~PMCR_LINK_SETTINGS_MASK; 2772 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | 2773 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); 2774 2775 /* Are we connected to external phy */ 2776 if (port == 5 && dsa_is_user_port(ds, 5)) 2777 mcr_new |= PMCR_EXT_PHY; 2778 2779 if (mcr_new != mcr_cur) 2780 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); 2781 } 2782 2783 static void 2784 mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port) 2785 { 2786 struct mt7530_priv *priv = ds->priv; 2787 2788 if (!priv->info->mac_pcs_an_restart) 2789 return; 2790 2791 priv->info->mac_pcs_an_restart(ds, port); 2792 } 2793 2794 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, 2795 unsigned int mode, 2796 phy_interface_t interface) 2797 { 2798 struct mt7530_priv *priv = ds->priv; 2799 2800 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 2801 } 2802 2803 static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port, 2804 unsigned int mode, phy_interface_t interface, 2805 int speed, int duplex) 2806 { 2807 struct mt7530_priv *priv = ds->priv; 2808 2809 if (!priv->info->mac_pcs_link_up) 2810 return; 2811 2812 priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex); 2813 } 2814 2815 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, 2816 unsigned int mode, 2817 phy_interface_t interface, 2818 struct phy_device *phydev, 2819 int speed, int duplex, 2820 bool tx_pause, bool rx_pause) 2821 { 2822 struct mt7530_priv *priv = ds->priv; 2823 u32 mcr; 2824 2825 mt753x_mac_pcs_link_up(ds, port, mode, interface, speed, duplex); 2826 2827 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; 2828 2829 /* MT753x MAC works in 1G full duplex mode for all up-clocked 2830 * variants. 2831 */ 2832 if (interface == PHY_INTERFACE_MODE_TRGMII || 2833 (phy_interface_mode_is_8023z(interface))) { 2834 speed = SPEED_1000; 2835 duplex = DUPLEX_FULL; 2836 } 2837 2838 switch (speed) { 2839 case SPEED_1000: 2840 mcr |= PMCR_FORCE_SPEED_1000; 2841 break; 2842 case SPEED_100: 2843 mcr |= PMCR_FORCE_SPEED_100; 2844 break; 2845 } 2846 if (duplex == DUPLEX_FULL) { 2847 mcr |= PMCR_FORCE_FDX; 2848 if (tx_pause) 2849 mcr |= PMCR_TX_FC_EN; 2850 if (rx_pause) 2851 mcr |= PMCR_RX_FC_EN; 2852 } 2853 2854 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) { 2855 switch (speed) { 2856 case SPEED_1000: 2857 mcr |= PMCR_FORCE_EEE1G; 2858 break; 2859 case SPEED_100: 2860 mcr |= PMCR_FORCE_EEE100; 2861 break; 2862 } 2863 } 2864 2865 mt7530_set(priv, MT7530_PMCR_P(port), mcr); 2866 } 2867 2868 static int 2869 mt7531_cpu_port_config(struct dsa_switch *ds, int port) 2870 { 2871 struct mt7530_priv *priv = ds->priv; 2872 phy_interface_t interface; 2873 int speed; 2874 int ret; 2875 2876 switch (port) { 2877 case 5: 2878 if (mt7531_is_rgmii_port(priv, port)) 2879 interface = PHY_INTERFACE_MODE_RGMII; 2880 else 2881 interface = PHY_INTERFACE_MODE_2500BASEX; 2882 2883 priv->p5_interface = interface; 2884 break; 2885 case 6: 2886 interface = PHY_INTERFACE_MODE_2500BASEX; 2887 2888 mt7531_pad_setup(ds, interface); 2889 2890 priv->p6_interface = interface; 2891 break; 2892 default: 2893 return -EINVAL; 2894 } 2895 2896 if (interface == PHY_INTERFACE_MODE_2500BASEX) 2897 speed = SPEED_2500; 2898 else 2899 speed = SPEED_1000; 2900 2901 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); 2902 if (ret) 2903 return ret; 2904 mt7530_write(priv, MT7530_PMCR_P(port), 2905 PMCR_CPU_PORT_SETTING(priv->id)); 2906 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, 2907 speed, DUPLEX_FULL, true, true); 2908 2909 return 0; 2910 } 2911 2912 static void 2913 mt7530_mac_port_validate(struct dsa_switch *ds, int port, 2914 unsigned long *supported) 2915 { 2916 if (port == 5) 2917 phylink_set(supported, 1000baseX_Full); 2918 } 2919 2920 static void mt7531_mac_port_validate(struct dsa_switch *ds, int port, 2921 unsigned long *supported) 2922 { 2923 struct mt7530_priv *priv = ds->priv; 2924 2925 mt7531_sgmii_validate(priv, port, supported); 2926 } 2927 2928 static void 2929 mt753x_phylink_validate(struct dsa_switch *ds, int port, 2930 unsigned long *supported, 2931 struct phylink_link_state *state) 2932 { 2933 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 2934 struct mt7530_priv *priv = ds->priv; 2935 2936 if (state->interface != PHY_INTERFACE_MODE_NA && 2937 !mt753x_phy_mode_supported(ds, port, state)) { 2938 linkmode_zero(supported); 2939 return; 2940 } 2941 2942 phylink_set_port_modes(mask); 2943 2944 if (state->interface != PHY_INTERFACE_MODE_TRGMII && 2945 !phy_interface_mode_is_8023z(state->interface)) { 2946 phylink_set(mask, 10baseT_Half); 2947 phylink_set(mask, 10baseT_Full); 2948 phylink_set(mask, 100baseT_Half); 2949 phylink_set(mask, 100baseT_Full); 2950 phylink_set(mask, Autoneg); 2951 } 2952 2953 /* This switch only supports 1G full-duplex. */ 2954 if (state->interface != PHY_INTERFACE_MODE_MII) 2955 phylink_set(mask, 1000baseT_Full); 2956 2957 priv->info->mac_port_validate(ds, port, mask); 2958 2959 phylink_set(mask, Pause); 2960 phylink_set(mask, Asym_Pause); 2961 2962 linkmode_and(supported, supported, mask); 2963 linkmode_and(state->advertising, state->advertising, mask); 2964 2965 /* We can only operate at 2500BaseX or 1000BaseX. If requested 2966 * to advertise both, only report advertising at 2500BaseX. 2967 */ 2968 phylink_helper_basex_speed(state); 2969 } 2970 2971 static int 2972 mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port, 2973 struct phylink_link_state *state) 2974 { 2975 struct mt7530_priv *priv = ds->priv; 2976 u32 pmsr; 2977 2978 if (port < 0 || port >= MT7530_NUM_PORTS) 2979 return -EINVAL; 2980 2981 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2982 2983 state->link = (pmsr & PMSR_LINK); 2984 state->an_complete = state->link; 2985 state->duplex = !!(pmsr & PMSR_DPX); 2986 2987 switch (pmsr & PMSR_SPEED_MASK) { 2988 case PMSR_SPEED_10: 2989 state->speed = SPEED_10; 2990 break; 2991 case PMSR_SPEED_100: 2992 state->speed = SPEED_100; 2993 break; 2994 case PMSR_SPEED_1000: 2995 state->speed = SPEED_1000; 2996 break; 2997 default: 2998 state->speed = SPEED_UNKNOWN; 2999 break; 3000 } 3001 3002 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 3003 if (pmsr & PMSR_RX_FC) 3004 state->pause |= MLO_PAUSE_RX; 3005 if (pmsr & PMSR_TX_FC) 3006 state->pause |= MLO_PAUSE_TX; 3007 3008 return 1; 3009 } 3010 3011 static int 3012 mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port, 3013 struct phylink_link_state *state) 3014 { 3015 u32 status, val; 3016 u16 config_reg; 3017 3018 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 3019 state->link = !!(status & MT7531_SGMII_LINK_STATUS); 3020 if (state->interface == PHY_INTERFACE_MODE_SGMII && 3021 (status & MT7531_SGMII_AN_ENABLE)) { 3022 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port)); 3023 config_reg = val >> 16; 3024 3025 switch (config_reg & LPA_SGMII_SPD_MASK) { 3026 case LPA_SGMII_1000: 3027 state->speed = SPEED_1000; 3028 break; 3029 case LPA_SGMII_100: 3030 state->speed = SPEED_100; 3031 break; 3032 case LPA_SGMII_10: 3033 state->speed = SPEED_10; 3034 break; 3035 default: 3036 dev_err(priv->dev, "invalid sgmii PHY speed\n"); 3037 state->link = false; 3038 return -EINVAL; 3039 } 3040 3041 if (config_reg & LPA_SGMII_FULL_DUPLEX) 3042 state->duplex = DUPLEX_FULL; 3043 else 3044 state->duplex = DUPLEX_HALF; 3045 } 3046 3047 return 0; 3048 } 3049 3050 static int 3051 mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port, 3052 struct phylink_link_state *state) 3053 { 3054 struct mt7530_priv *priv = ds->priv; 3055 3056 if (state->interface == PHY_INTERFACE_MODE_SGMII) 3057 return mt7531_sgmii_pcs_get_state_an(priv, port, state); 3058 3059 return -EOPNOTSUPP; 3060 } 3061 3062 static int 3063 mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port, 3064 struct phylink_link_state *state) 3065 { 3066 struct mt7530_priv *priv = ds->priv; 3067 3068 return priv->info->mac_port_get_state(ds, port, state); 3069 } 3070 3071 static int 3072 mt753x_setup(struct dsa_switch *ds) 3073 { 3074 struct mt7530_priv *priv = ds->priv; 3075 int ret = priv->info->sw_setup(ds); 3076 3077 if (ret) 3078 return ret; 3079 3080 ret = mt7530_setup_irq(priv); 3081 if (ret) 3082 return ret; 3083 3084 ret = mt7530_setup_mdio(priv); 3085 if (ret && priv->irq) 3086 mt7530_free_irq_common(priv); 3087 3088 return ret; 3089 } 3090 3091 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, 3092 struct ethtool_eee *e) 3093 { 3094 struct mt7530_priv *priv = ds->priv; 3095 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); 3096 3097 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); 3098 e->tx_lpi_timer = GET_LPI_THRESH(eeecr); 3099 3100 return 0; 3101 } 3102 3103 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3104 struct ethtool_eee *e) 3105 { 3106 struct mt7530_priv *priv = ds->priv; 3107 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN; 3108 3109 if (e->tx_lpi_timer > 0xFFF) 3110 return -EINVAL; 3111 3112 set = SET_LPI_THRESH(e->tx_lpi_timer); 3113 if (!e->tx_lpi_enabled) 3114 /* Force LPI Mode without a delay */ 3115 set |= LPI_MODE_EN; 3116 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); 3117 3118 return 0; 3119 } 3120 3121 static const struct dsa_switch_ops mt7530_switch_ops = { 3122 .get_tag_protocol = mtk_get_tag_protocol, 3123 .setup = mt753x_setup, 3124 .get_strings = mt7530_get_strings, 3125 .get_ethtool_stats = mt7530_get_ethtool_stats, 3126 .get_sset_count = mt7530_get_sset_count, 3127 .set_ageing_time = mt7530_set_ageing_time, 3128 .port_enable = mt7530_port_enable, 3129 .port_disable = mt7530_port_disable, 3130 .port_change_mtu = mt7530_port_change_mtu, 3131 .port_max_mtu = mt7530_port_max_mtu, 3132 .port_stp_state_set = mt7530_stp_state_set, 3133 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3134 .port_bridge_flags = mt7530_port_bridge_flags, 3135 .port_bridge_join = mt7530_port_bridge_join, 3136 .port_bridge_leave = mt7530_port_bridge_leave, 3137 .port_fdb_add = mt7530_port_fdb_add, 3138 .port_fdb_del = mt7530_port_fdb_del, 3139 .port_fdb_dump = mt7530_port_fdb_dump, 3140 .port_mdb_add = mt7530_port_mdb_add, 3141 .port_mdb_del = mt7530_port_mdb_del, 3142 .port_vlan_filtering = mt7530_port_vlan_filtering, 3143 .port_vlan_add = mt7530_port_vlan_add, 3144 .port_vlan_del = mt7530_port_vlan_del, 3145 .port_mirror_add = mt753x_port_mirror_add, 3146 .port_mirror_del = mt753x_port_mirror_del, 3147 .phylink_validate = mt753x_phylink_validate, 3148 .phylink_mac_link_state = mt753x_phylink_mac_link_state, 3149 .phylink_mac_config = mt753x_phylink_mac_config, 3150 .phylink_mac_an_restart = mt753x_phylink_mac_an_restart, 3151 .phylink_mac_link_down = mt753x_phylink_mac_link_down, 3152 .phylink_mac_link_up = mt753x_phylink_mac_link_up, 3153 .get_mac_eee = mt753x_get_mac_eee, 3154 .set_mac_eee = mt753x_set_mac_eee, 3155 }; 3156 3157 static const struct mt753x_info mt753x_table[] = { 3158 [ID_MT7621] = { 3159 .id = ID_MT7621, 3160 .sw_setup = mt7530_setup, 3161 .phy_read = mt7530_phy_read, 3162 .phy_write = mt7530_phy_write, 3163 .pad_setup = mt7530_pad_clk_setup, 3164 .phy_mode_supported = mt7530_phy_mode_supported, 3165 .mac_port_validate = mt7530_mac_port_validate, 3166 .mac_port_get_state = mt7530_phylink_mac_link_state, 3167 .mac_port_config = mt7530_mac_config, 3168 }, 3169 [ID_MT7530] = { 3170 .id = ID_MT7530, 3171 .sw_setup = mt7530_setup, 3172 .phy_read = mt7530_phy_read, 3173 .phy_write = mt7530_phy_write, 3174 .pad_setup = mt7530_pad_clk_setup, 3175 .phy_mode_supported = mt7530_phy_mode_supported, 3176 .mac_port_validate = mt7530_mac_port_validate, 3177 .mac_port_get_state = mt7530_phylink_mac_link_state, 3178 .mac_port_config = mt7530_mac_config, 3179 }, 3180 [ID_MT7531] = { 3181 .id = ID_MT7531, 3182 .sw_setup = mt7531_setup, 3183 .phy_read = mt7531_ind_phy_read, 3184 .phy_write = mt7531_ind_phy_write, 3185 .pad_setup = mt7531_pad_setup, 3186 .cpu_port_config = mt7531_cpu_port_config, 3187 .phy_mode_supported = mt7531_phy_mode_supported, 3188 .mac_port_validate = mt7531_mac_port_validate, 3189 .mac_port_get_state = mt7531_phylink_mac_link_state, 3190 .mac_port_config = mt7531_mac_config, 3191 .mac_pcs_an_restart = mt7531_sgmii_restart_an, 3192 .mac_pcs_link_up = mt7531_sgmii_link_up_force, 3193 }, 3194 }; 3195 3196 static const struct of_device_id mt7530_of_match[] = { 3197 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], }, 3198 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], }, 3199 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], }, 3200 { /* sentinel */ }, 3201 }; 3202 MODULE_DEVICE_TABLE(of, mt7530_of_match); 3203 3204 static int 3205 mt7530_probe(struct mdio_device *mdiodev) 3206 { 3207 struct mt7530_priv *priv; 3208 struct device_node *dn; 3209 3210 dn = mdiodev->dev.of_node; 3211 3212 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 3213 if (!priv) 3214 return -ENOMEM; 3215 3216 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); 3217 if (!priv->ds) 3218 return -ENOMEM; 3219 3220 priv->ds->dev = &mdiodev->dev; 3221 priv->ds->num_ports = MT7530_NUM_PORTS; 3222 3223 /* Use medatek,mcm property to distinguish hardware type that would 3224 * casues a little bit differences on power-on sequence. 3225 */ 3226 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); 3227 if (priv->mcm) { 3228 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); 3229 3230 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); 3231 if (IS_ERR(priv->rstc)) { 3232 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 3233 return PTR_ERR(priv->rstc); 3234 } 3235 } 3236 3237 /* Get the hardware identifier from the devicetree node. 3238 * We will need it for some of the clock and regulator setup. 3239 */ 3240 priv->info = of_device_get_match_data(&mdiodev->dev); 3241 if (!priv->info) 3242 return -EINVAL; 3243 3244 /* Sanity check if these required device operations are filled 3245 * properly. 3246 */ 3247 if (!priv->info->sw_setup || !priv->info->pad_setup || 3248 !priv->info->phy_read || !priv->info->phy_write || 3249 !priv->info->phy_mode_supported || 3250 !priv->info->mac_port_validate || 3251 !priv->info->mac_port_get_state || !priv->info->mac_port_config) 3252 return -EINVAL; 3253 3254 priv->id = priv->info->id; 3255 3256 if (priv->id == ID_MT7530) { 3257 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); 3258 if (IS_ERR(priv->core_pwr)) 3259 return PTR_ERR(priv->core_pwr); 3260 3261 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); 3262 if (IS_ERR(priv->io_pwr)) 3263 return PTR_ERR(priv->io_pwr); 3264 } 3265 3266 /* Not MCM that indicates switch works as the remote standalone 3267 * integrated circuit so the GPIO pin would be used to complete 3268 * the reset, otherwise memory-mapped register accessing used 3269 * through syscon provides in the case of MCM. 3270 */ 3271 if (!priv->mcm) { 3272 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", 3273 GPIOD_OUT_LOW); 3274 if (IS_ERR(priv->reset)) { 3275 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 3276 return PTR_ERR(priv->reset); 3277 } 3278 } 3279 3280 priv->bus = mdiodev->bus; 3281 priv->dev = &mdiodev->dev; 3282 priv->ds->priv = priv; 3283 priv->ds->ops = &mt7530_switch_ops; 3284 mutex_init(&priv->reg_mutex); 3285 dev_set_drvdata(&mdiodev->dev, priv); 3286 3287 return dsa_register_switch(priv->ds); 3288 } 3289 3290 static void 3291 mt7530_remove(struct mdio_device *mdiodev) 3292 { 3293 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 3294 int ret = 0; 3295 3296 if (!priv) 3297 return; 3298 3299 ret = regulator_disable(priv->core_pwr); 3300 if (ret < 0) 3301 dev_err(priv->dev, 3302 "Failed to disable core power: %d\n", ret); 3303 3304 ret = regulator_disable(priv->io_pwr); 3305 if (ret < 0) 3306 dev_err(priv->dev, "Failed to disable io pwr: %d\n", 3307 ret); 3308 3309 if (priv->irq) 3310 mt7530_free_irq(priv); 3311 3312 dsa_unregister_switch(priv->ds); 3313 mutex_destroy(&priv->reg_mutex); 3314 3315 dev_set_drvdata(&mdiodev->dev, NULL); 3316 } 3317 3318 static void mt7530_shutdown(struct mdio_device *mdiodev) 3319 { 3320 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 3321 3322 if (!priv) 3323 return; 3324 3325 dsa_switch_shutdown(priv->ds); 3326 3327 dev_set_drvdata(&mdiodev->dev, NULL); 3328 } 3329 3330 static struct mdio_driver mt7530_mdio_driver = { 3331 .probe = mt7530_probe, 3332 .remove = mt7530_remove, 3333 .shutdown = mt7530_shutdown, 3334 .mdiodrv.driver = { 3335 .name = "mt7530", 3336 .of_match_table = mt7530_of_match, 3337 }, 3338 }; 3339 3340 mdio_module_driver(mt7530_mdio_driver); 3341 3342 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3343 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3344 MODULE_LICENSE("GPL"); 3345