1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 25 #include "mt7530.h" 26 27 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) 28 { 29 return container_of(pcs, struct mt753x_pcs, pcs); 30 } 31 32 /* String, offset, and register size in bytes if different from 4 bytes */ 33 static const struct mt7530_mib_desc mt7530_mib[] = { 34 MIB_DESC(1, 0x00, "TxDrop"), 35 MIB_DESC(1, 0x04, "TxCrcErr"), 36 MIB_DESC(1, 0x08, "TxUnicast"), 37 MIB_DESC(1, 0x0c, "TxMulticast"), 38 MIB_DESC(1, 0x10, "TxBroadcast"), 39 MIB_DESC(1, 0x14, "TxCollision"), 40 MIB_DESC(1, 0x18, "TxSingleCollision"), 41 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 42 MIB_DESC(1, 0x20, "TxDeferred"), 43 MIB_DESC(1, 0x24, "TxLateCollision"), 44 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 45 MIB_DESC(1, 0x2c, "TxPause"), 46 MIB_DESC(1, 0x30, "TxPktSz64"), 47 MIB_DESC(1, 0x34, "TxPktSz65To127"), 48 MIB_DESC(1, 0x38, "TxPktSz128To255"), 49 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 50 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 51 MIB_DESC(1, 0x44, "Tx1024ToMax"), 52 MIB_DESC(2, 0x48, "TxBytes"), 53 MIB_DESC(1, 0x60, "RxDrop"), 54 MIB_DESC(1, 0x64, "RxFiltering"), 55 MIB_DESC(1, 0x68, "RxUnicast"), 56 MIB_DESC(1, 0x6c, "RxMulticast"), 57 MIB_DESC(1, 0x70, "RxBroadcast"), 58 MIB_DESC(1, 0x74, "RxAlignErr"), 59 MIB_DESC(1, 0x78, "RxCrcErr"), 60 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 61 MIB_DESC(1, 0x80, "RxFragErr"), 62 MIB_DESC(1, 0x84, "RxOverSzErr"), 63 MIB_DESC(1, 0x88, "RxJabberErr"), 64 MIB_DESC(1, 0x8c, "RxPause"), 65 MIB_DESC(1, 0x90, "RxPktSz64"), 66 MIB_DESC(1, 0x94, "RxPktSz65To127"), 67 MIB_DESC(1, 0x98, "RxPktSz128To255"), 68 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 69 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 70 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 71 MIB_DESC(2, 0xa8, "RxBytes"), 72 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 73 MIB_DESC(1, 0xb4, "RxIngressDrop"), 74 MIB_DESC(1, 0xb8, "RxArlDrop"), 75 }; 76 77 /* Since phy_device has not yet been created and 78 * phy_{read,write}_mmd_indirect is not available, we provide our own 79 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers 80 * to complete this function. 81 */ 82 static int 83 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 84 { 85 struct mii_bus *bus = priv->bus; 86 int value, ret; 87 88 /* Write the desired MMD Devad */ 89 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 90 if (ret < 0) 91 goto err; 92 93 /* Write the desired MMD register address */ 94 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 95 if (ret < 0) 96 goto err; 97 98 /* Select the Function : DATA with no post increment */ 99 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 100 if (ret < 0) 101 goto err; 102 103 /* Read the content of the MMD's selected register */ 104 value = bus->read(bus, 0, MII_MMD_DATA); 105 106 return value; 107 err: 108 dev_err(&bus->dev, "failed to read mmd register\n"); 109 110 return ret; 111 } 112 113 static int 114 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 115 int devad, u32 data) 116 { 117 struct mii_bus *bus = priv->bus; 118 int ret; 119 120 /* Write the desired MMD Devad */ 121 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 122 if (ret < 0) 123 goto err; 124 125 /* Write the desired MMD register address */ 126 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 127 if (ret < 0) 128 goto err; 129 130 /* Select the Function : DATA with no post increment */ 131 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 132 if (ret < 0) 133 goto err; 134 135 /* Write the data into MMD's selected register */ 136 ret = bus->write(bus, 0, MII_MMD_DATA, data); 137 err: 138 if (ret < 0) 139 dev_err(&bus->dev, 140 "failed to write mmd register\n"); 141 return ret; 142 } 143 144 static void 145 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 146 { 147 struct mii_bus *bus = priv->bus; 148 149 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 150 151 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 152 153 mutex_unlock(&bus->mdio_lock); 154 } 155 156 static void 157 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 158 { 159 struct mii_bus *bus = priv->bus; 160 u32 val; 161 162 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 163 164 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 165 val &= ~mask; 166 val |= set; 167 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 168 169 mutex_unlock(&bus->mdio_lock); 170 } 171 172 static void 173 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 174 { 175 core_rmw(priv, reg, 0, val); 176 } 177 178 static void 179 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 180 { 181 core_rmw(priv, reg, val, 0); 182 } 183 184 static int 185 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 186 { 187 struct mii_bus *bus = priv->bus; 188 u16 page, r, lo, hi; 189 int ret; 190 191 page = (reg >> 6) & 0x3ff; 192 r = (reg >> 2) & 0xf; 193 lo = val & 0xffff; 194 hi = val >> 16; 195 196 /* MT7530 uses 31 as the pseudo port */ 197 ret = bus->write(bus, 0x1f, 0x1f, page); 198 if (ret < 0) 199 goto err; 200 201 ret = bus->write(bus, 0x1f, r, lo); 202 if (ret < 0) 203 goto err; 204 205 ret = bus->write(bus, 0x1f, 0x10, hi); 206 err: 207 if (ret < 0) 208 dev_err(&bus->dev, 209 "failed to write mt7530 register\n"); 210 return ret; 211 } 212 213 static u32 214 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 215 { 216 struct mii_bus *bus = priv->bus; 217 u16 page, r, lo, hi; 218 int ret; 219 220 page = (reg >> 6) & 0x3ff; 221 r = (reg >> 2) & 0xf; 222 223 /* MT7530 uses 31 as the pseudo port */ 224 ret = bus->write(bus, 0x1f, 0x1f, page); 225 if (ret < 0) { 226 dev_err(&bus->dev, 227 "failed to read mt7530 register\n"); 228 return ret; 229 } 230 231 lo = bus->read(bus, 0x1f, r); 232 hi = bus->read(bus, 0x1f, 0x10); 233 234 return (hi << 16) | (lo & 0xffff); 235 } 236 237 static void 238 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 239 { 240 struct mii_bus *bus = priv->bus; 241 242 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 243 244 mt7530_mii_write(priv, reg, val); 245 246 mutex_unlock(&bus->mdio_lock); 247 } 248 249 static u32 250 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 251 { 252 return mt7530_mii_read(p->priv, p->reg); 253 } 254 255 static u32 256 _mt7530_read(struct mt7530_dummy_poll *p) 257 { 258 struct mii_bus *bus = p->priv->bus; 259 u32 val; 260 261 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 262 263 val = mt7530_mii_read(p->priv, p->reg); 264 265 mutex_unlock(&bus->mdio_lock); 266 267 return val; 268 } 269 270 static u32 271 mt7530_read(struct mt7530_priv *priv, u32 reg) 272 { 273 struct mt7530_dummy_poll p; 274 275 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 276 return _mt7530_read(&p); 277 } 278 279 static void 280 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 281 u32 mask, u32 set) 282 { 283 struct mii_bus *bus = priv->bus; 284 u32 val; 285 286 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 287 288 val = mt7530_mii_read(priv, reg); 289 val &= ~mask; 290 val |= set; 291 mt7530_mii_write(priv, reg, val); 292 293 mutex_unlock(&bus->mdio_lock); 294 } 295 296 static void 297 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 298 { 299 mt7530_rmw(priv, reg, 0, val); 300 } 301 302 static void 303 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 304 { 305 mt7530_rmw(priv, reg, val, 0); 306 } 307 308 static int 309 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 310 { 311 u32 val; 312 int ret; 313 struct mt7530_dummy_poll p; 314 315 /* Set the command operating upon the MAC address entries */ 316 val = ATC_BUSY | ATC_MAT(0) | cmd; 317 mt7530_write(priv, MT7530_ATC, val); 318 319 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 320 ret = readx_poll_timeout(_mt7530_read, &p, val, 321 !(val & ATC_BUSY), 20, 20000); 322 if (ret < 0) { 323 dev_err(priv->dev, "reset timeout\n"); 324 return ret; 325 } 326 327 /* Additional sanity for read command if the specified 328 * entry is invalid 329 */ 330 val = mt7530_read(priv, MT7530_ATC); 331 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 332 return -EINVAL; 333 334 if (rsp) 335 *rsp = val; 336 337 return 0; 338 } 339 340 static void 341 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 342 { 343 u32 reg[3]; 344 int i; 345 346 /* Read from ARL table into an array */ 347 for (i = 0; i < 3; i++) { 348 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 349 350 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 351 __func__, __LINE__, i, reg[i]); 352 } 353 354 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 355 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 356 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 357 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 358 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 359 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 360 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 361 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 362 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 363 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 364 } 365 366 static void 367 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 368 u8 port_mask, const u8 *mac, 369 u8 aging, u8 type) 370 { 371 u32 reg[3] = { 0 }; 372 int i; 373 374 reg[1] |= vid & CVID_MASK; 375 reg[1] |= ATA2_IVL; 376 reg[1] |= ATA2_FID(FID_BRIDGED); 377 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 378 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 379 /* STATIC_ENT indicate that entry is static wouldn't 380 * be aged out and STATIC_EMP specified as erasing an 381 * entry 382 */ 383 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 384 reg[1] |= mac[5] << MAC_BYTE_5; 385 reg[1] |= mac[4] << MAC_BYTE_4; 386 reg[0] |= mac[3] << MAC_BYTE_3; 387 reg[0] |= mac[2] << MAC_BYTE_2; 388 reg[0] |= mac[1] << MAC_BYTE_1; 389 reg[0] |= mac[0] << MAC_BYTE_0; 390 391 /* Write array into the ARL table */ 392 for (i = 0; i < 3; i++) 393 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 394 } 395 396 /* Set up switch core clock for MT7530 */ 397 static void mt7530_pll_setup(struct mt7530_priv *priv) 398 { 399 /* Disable core clock */ 400 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 401 402 /* Disable PLL */ 403 core_write(priv, CORE_GSWPLL_GRP1, 0); 404 405 /* Set core clock into 500Mhz */ 406 core_write(priv, CORE_GSWPLL_GRP2, 407 RG_GSWPLL_POSDIV_500M(1) | 408 RG_GSWPLL_FBKDIV_500M(25)); 409 410 /* Enable PLL */ 411 core_write(priv, CORE_GSWPLL_GRP1, 412 RG_GSWPLL_EN_PRE | 413 RG_GSWPLL_POSDIV_200M(2) | 414 RG_GSWPLL_FBKDIV_200M(32)); 415 416 udelay(20); 417 418 /* Enable core clock */ 419 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 420 } 421 422 /* Setup port 6 interface mode and TRGMII TX circuit */ 423 static int 424 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 425 { 426 struct mt7530_priv *priv = ds->priv; 427 u32 ncpo1, ssc_delta, trgint, xtal; 428 429 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 430 431 if (xtal == HWTRAP_XTAL_20MHZ) { 432 dev_err(priv->dev, 433 "%s: MT7530 with a 20MHz XTAL is not supported!\n", 434 __func__); 435 return -EINVAL; 436 } 437 438 switch (interface) { 439 case PHY_INTERFACE_MODE_RGMII: 440 trgint = 0; 441 break; 442 case PHY_INTERFACE_MODE_TRGMII: 443 trgint = 1; 444 if (xtal == HWTRAP_XTAL_25MHZ) 445 ssc_delta = 0x57; 446 else 447 ssc_delta = 0x87; 448 if (priv->id == ID_MT7621) { 449 /* PLL frequency: 150MHz: 1.2GBit */ 450 if (xtal == HWTRAP_XTAL_40MHZ) 451 ncpo1 = 0x0780; 452 if (xtal == HWTRAP_XTAL_25MHZ) 453 ncpo1 = 0x0a00; 454 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 455 if (xtal == HWTRAP_XTAL_40MHZ) 456 ncpo1 = 0x0c80; 457 if (xtal == HWTRAP_XTAL_25MHZ) 458 ncpo1 = 0x1400; 459 } 460 break; 461 default: 462 dev_err(priv->dev, "xMII interface %d not supported\n", 463 interface); 464 return -EINVAL; 465 } 466 467 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 468 P6_INTF_MODE(trgint)); 469 470 if (trgint) { 471 /* Disable the MT7530 TRGMII clocks */ 472 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 473 474 /* Setup the MT7530 TRGMII Tx Clock */ 475 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 476 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 477 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 478 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 479 core_write(priv, CORE_PLL_GROUP4, 480 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 481 RG_SYSPLL_BIAS_LPF_EN); 482 core_write(priv, CORE_PLL_GROUP2, 483 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 484 RG_SYSPLL_POSDIV(1)); 485 core_write(priv, CORE_PLL_GROUP7, 486 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 487 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 488 489 /* Enable the MT7530 TRGMII clocks */ 490 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 491 } 492 493 return 0; 494 } 495 496 static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) 497 { 498 u32 val; 499 500 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 501 502 return (val & PAD_DUAL_SGMII_EN) != 0; 503 } 504 505 static int 506 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 507 { 508 return 0; 509 } 510 511 static void 512 mt7531_pll_setup(struct mt7530_priv *priv) 513 { 514 u32 top_sig; 515 u32 hwstrap; 516 u32 xtal; 517 u32 val; 518 519 if (mt7531_dual_sgmii_supported(priv)) 520 return; 521 522 val = mt7530_read(priv, MT7531_CREV); 523 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 524 hwstrap = mt7530_read(priv, MT7531_HWTRAP); 525 if ((val & CHIP_REV_M) > 0) 526 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : 527 HWTRAP_XTAL_FSEL_25MHZ; 528 else 529 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; 530 531 /* Step 1 : Disable MT7531 COREPLL */ 532 val = mt7530_read(priv, MT7531_PLLGP_EN); 533 val &= ~EN_COREPLL; 534 mt7530_write(priv, MT7531_PLLGP_EN, val); 535 536 /* Step 2: switch to XTAL output */ 537 val = mt7530_read(priv, MT7531_PLLGP_EN); 538 val |= SW_CLKSW; 539 mt7530_write(priv, MT7531_PLLGP_EN, val); 540 541 val = mt7530_read(priv, MT7531_PLLGP_CR0); 542 val &= ~RG_COREPLL_EN; 543 mt7530_write(priv, MT7531_PLLGP_CR0, val); 544 545 /* Step 3: disable PLLGP and enable program PLLGP */ 546 val = mt7530_read(priv, MT7531_PLLGP_EN); 547 val |= SW_PLLGP; 548 mt7530_write(priv, MT7531_PLLGP_EN, val); 549 550 /* Step 4: program COREPLL output frequency to 500MHz */ 551 val = mt7530_read(priv, MT7531_PLLGP_CR0); 552 val &= ~RG_COREPLL_POSDIV_M; 553 val |= 2 << RG_COREPLL_POSDIV_S; 554 mt7530_write(priv, MT7531_PLLGP_CR0, val); 555 usleep_range(25, 35); 556 557 switch (xtal) { 558 case HWTRAP_XTAL_FSEL_25MHZ: 559 val = mt7530_read(priv, MT7531_PLLGP_CR0); 560 val &= ~RG_COREPLL_SDM_PCW_M; 561 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 562 mt7530_write(priv, MT7531_PLLGP_CR0, val); 563 break; 564 case HWTRAP_XTAL_FSEL_40MHZ: 565 val = mt7530_read(priv, MT7531_PLLGP_CR0); 566 val &= ~RG_COREPLL_SDM_PCW_M; 567 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 568 mt7530_write(priv, MT7531_PLLGP_CR0, val); 569 break; 570 } 571 572 /* Set feedback divide ratio update signal to high */ 573 val = mt7530_read(priv, MT7531_PLLGP_CR0); 574 val |= RG_COREPLL_SDM_PCW_CHG; 575 mt7530_write(priv, MT7531_PLLGP_CR0, val); 576 /* Wait for at least 16 XTAL clocks */ 577 usleep_range(10, 20); 578 579 /* Step 5: set feedback divide ratio update signal to low */ 580 val = mt7530_read(priv, MT7531_PLLGP_CR0); 581 val &= ~RG_COREPLL_SDM_PCW_CHG; 582 mt7530_write(priv, MT7531_PLLGP_CR0, val); 583 584 /* Enable 325M clock for SGMII */ 585 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 586 587 /* Enable 250SSC clock for RGMII */ 588 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 589 590 /* Step 6: Enable MT7531 PLL */ 591 val = mt7530_read(priv, MT7531_PLLGP_CR0); 592 val |= RG_COREPLL_EN; 593 mt7530_write(priv, MT7531_PLLGP_CR0, val); 594 595 val = mt7530_read(priv, MT7531_PLLGP_EN); 596 val |= EN_COREPLL; 597 mt7530_write(priv, MT7531_PLLGP_EN, val); 598 usleep_range(25, 35); 599 } 600 601 static void 602 mt7530_mib_reset(struct dsa_switch *ds) 603 { 604 struct mt7530_priv *priv = ds->priv; 605 606 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 607 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 608 } 609 610 static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum) 611 { 612 return mdiobus_read_nested(priv->bus, port, regnum); 613 } 614 615 static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum, 616 u16 val) 617 { 618 return mdiobus_write_nested(priv->bus, port, regnum, val); 619 } 620 621 static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, 622 int devad, int regnum) 623 { 624 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); 625 } 626 627 static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad, 628 int regnum, u16 val) 629 { 630 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); 631 } 632 633 static int 634 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 635 int regnum) 636 { 637 struct mii_bus *bus = priv->bus; 638 struct mt7530_dummy_poll p; 639 u32 reg, val; 640 int ret; 641 642 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 643 644 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 645 646 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 647 !(val & MT7531_PHY_ACS_ST), 20, 100000); 648 if (ret < 0) { 649 dev_err(priv->dev, "poll timeout\n"); 650 goto out; 651 } 652 653 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 654 MT7531_MDIO_DEV_ADDR(devad) | regnum; 655 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 656 657 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 658 !(val & MT7531_PHY_ACS_ST), 20, 100000); 659 if (ret < 0) { 660 dev_err(priv->dev, "poll timeout\n"); 661 goto out; 662 } 663 664 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 665 MT7531_MDIO_DEV_ADDR(devad); 666 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 667 668 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 669 !(val & MT7531_PHY_ACS_ST), 20, 100000); 670 if (ret < 0) { 671 dev_err(priv->dev, "poll timeout\n"); 672 goto out; 673 } 674 675 ret = val & MT7531_MDIO_RW_DATA_MASK; 676 out: 677 mutex_unlock(&bus->mdio_lock); 678 679 return ret; 680 } 681 682 static int 683 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 684 int regnum, u16 data) 685 { 686 struct mii_bus *bus = priv->bus; 687 struct mt7530_dummy_poll p; 688 u32 val, reg; 689 int ret; 690 691 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 692 693 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 694 695 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 696 !(val & MT7531_PHY_ACS_ST), 20, 100000); 697 if (ret < 0) { 698 dev_err(priv->dev, "poll timeout\n"); 699 goto out; 700 } 701 702 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 703 MT7531_MDIO_DEV_ADDR(devad) | regnum; 704 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 705 706 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 707 !(val & MT7531_PHY_ACS_ST), 20, 100000); 708 if (ret < 0) { 709 dev_err(priv->dev, "poll timeout\n"); 710 goto out; 711 } 712 713 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 714 MT7531_MDIO_DEV_ADDR(devad) | data; 715 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 716 717 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 718 !(val & MT7531_PHY_ACS_ST), 20, 100000); 719 if (ret < 0) { 720 dev_err(priv->dev, "poll timeout\n"); 721 goto out; 722 } 723 724 out: 725 mutex_unlock(&bus->mdio_lock); 726 727 return ret; 728 } 729 730 static int 731 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 732 { 733 struct mii_bus *bus = priv->bus; 734 struct mt7530_dummy_poll p; 735 int ret; 736 u32 val; 737 738 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 739 740 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 741 742 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 743 !(val & MT7531_PHY_ACS_ST), 20, 100000); 744 if (ret < 0) { 745 dev_err(priv->dev, "poll timeout\n"); 746 goto out; 747 } 748 749 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 750 MT7531_MDIO_REG_ADDR(regnum); 751 752 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 753 754 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 755 !(val & MT7531_PHY_ACS_ST), 20, 100000); 756 if (ret < 0) { 757 dev_err(priv->dev, "poll timeout\n"); 758 goto out; 759 } 760 761 ret = val & MT7531_MDIO_RW_DATA_MASK; 762 out: 763 mutex_unlock(&bus->mdio_lock); 764 765 return ret; 766 } 767 768 static int 769 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 770 u16 data) 771 { 772 struct mii_bus *bus = priv->bus; 773 struct mt7530_dummy_poll p; 774 int ret; 775 u32 reg; 776 777 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 778 779 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 780 781 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 782 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 783 if (ret < 0) { 784 dev_err(priv->dev, "poll timeout\n"); 785 goto out; 786 } 787 788 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 789 MT7531_MDIO_REG_ADDR(regnum) | data; 790 791 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 792 793 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 794 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 795 if (ret < 0) { 796 dev_err(priv->dev, "poll timeout\n"); 797 goto out; 798 } 799 800 out: 801 mutex_unlock(&bus->mdio_lock); 802 803 return ret; 804 } 805 806 static int 807 mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) 808 { 809 struct mt7530_priv *priv = bus->priv; 810 811 return priv->info->phy_read_c22(priv, port, regnum); 812 } 813 814 static int 815 mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) 816 { 817 struct mt7530_priv *priv = bus->priv; 818 819 return priv->info->phy_read_c45(priv, port, devad, regnum); 820 } 821 822 static int 823 mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) 824 { 825 struct mt7530_priv *priv = bus->priv; 826 827 return priv->info->phy_write_c22(priv, port, regnum, val); 828 } 829 830 static int 831 mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, 832 u16 val) 833 { 834 struct mt7530_priv *priv = bus->priv; 835 836 return priv->info->phy_write_c45(priv, port, devad, regnum, val); 837 } 838 839 static void 840 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 841 uint8_t *data) 842 { 843 int i; 844 845 if (stringset != ETH_SS_STATS) 846 return; 847 848 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 849 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 850 ETH_GSTRING_LEN); 851 } 852 853 static void 854 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 855 uint64_t *data) 856 { 857 struct mt7530_priv *priv = ds->priv; 858 const struct mt7530_mib_desc *mib; 859 u32 reg, i; 860 u64 hi; 861 862 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 863 mib = &mt7530_mib[i]; 864 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 865 866 data[i] = mt7530_read(priv, reg); 867 if (mib->size == 2) { 868 hi = mt7530_read(priv, reg + 4); 869 data[i] |= hi << 32; 870 } 871 } 872 } 873 874 static int 875 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 876 { 877 if (sset != ETH_SS_STATS) 878 return 0; 879 880 return ARRAY_SIZE(mt7530_mib); 881 } 882 883 static int 884 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 885 { 886 struct mt7530_priv *priv = ds->priv; 887 unsigned int secs = msecs / 1000; 888 unsigned int tmp_age_count; 889 unsigned int error = -1; 890 unsigned int age_count; 891 unsigned int age_unit; 892 893 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 894 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 895 return -ERANGE; 896 897 /* iterate through all possible age_count to find the closest pair */ 898 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 899 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 900 901 if (tmp_age_unit <= AGE_UNIT_MAX) { 902 unsigned int tmp_error = secs - 903 (tmp_age_count + 1) * (tmp_age_unit + 1); 904 905 /* found a closer pair */ 906 if (error > tmp_error) { 907 error = tmp_error; 908 age_count = tmp_age_count; 909 age_unit = tmp_age_unit; 910 } 911 912 /* found the exact match, so break the loop */ 913 if (!error) 914 break; 915 } 916 } 917 918 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 919 920 return 0; 921 } 922 923 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 924 { 925 struct mt7530_priv *priv = ds->priv; 926 u8 tx_delay = 0; 927 int val; 928 929 mutex_lock(&priv->reg_mutex); 930 931 val = mt7530_read(priv, MT7530_MHWTRAP); 932 933 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 934 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 935 936 switch (priv->p5_intf_sel) { 937 case P5_INTF_SEL_PHY_P0: 938 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 939 val |= MHWTRAP_PHY0_SEL; 940 fallthrough; 941 case P5_INTF_SEL_PHY_P4: 942 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 943 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 944 945 /* Setup the MAC by default for the cpu port */ 946 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 947 break; 948 case P5_INTF_SEL_GMAC5: 949 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 950 val &= ~MHWTRAP_P5_DIS; 951 break; 952 case P5_DISABLED: 953 interface = PHY_INTERFACE_MODE_NA; 954 break; 955 default: 956 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", 957 priv->p5_intf_sel); 958 goto unlock_exit; 959 } 960 961 /* Setup RGMII settings */ 962 if (phy_interface_mode_is_rgmii(interface)) { 963 val |= MHWTRAP_P5_RGMII_MODE; 964 965 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 966 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 967 968 /* Don't set delay in DSA mode */ 969 if (!dsa_is_dsa_port(priv->ds, 5) && 970 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 971 interface == PHY_INTERFACE_MODE_RGMII_ID)) 972 tx_delay = 4; /* n * 0.5 ns */ 973 974 /* P5 RGMII TX Clock Control: delay x */ 975 mt7530_write(priv, MT7530_P5RGMIITXCR, 976 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 977 978 /* reduce P5 RGMII Tx driving, 8mA */ 979 mt7530_write(priv, MT7530_IO_DRV_CR, 980 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 981 } 982 983 mt7530_write(priv, MT7530_MHWTRAP, val); 984 985 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 986 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 987 988 priv->p5_interface = interface; 989 990 unlock_exit: 991 mutex_unlock(&priv->reg_mutex); 992 } 993 994 static int 995 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 996 { 997 struct mt7530_priv *priv = ds->priv; 998 int ret; 999 1000 /* Setup max capability of CPU port at first */ 1001 if (priv->info->cpu_port_config) { 1002 ret = priv->info->cpu_port_config(ds, port); 1003 if (ret) 1004 return ret; 1005 } 1006 1007 /* Enable Mediatek header mode on the cpu port */ 1008 mt7530_write(priv, MT7530_PVC_P(port), 1009 PORT_SPEC_TAG); 1010 1011 /* Disable flooding by default */ 1012 mt7530_rmw(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK, 1013 BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port))); 1014 1015 /* Set CPU port number */ 1016 if (priv->id == ID_MT7621) 1017 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 1018 1019 /* CPU port gets connected to all user ports of 1020 * the switch. 1021 */ 1022 mt7530_write(priv, MT7530_PCR_P(port), 1023 PCR_MATRIX(dsa_user_ports(priv->ds))); 1024 1025 /* Set to fallback mode for independent VLAN learning */ 1026 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1027 MT7530_PORT_FALLBACK_MODE); 1028 1029 return 0; 1030 } 1031 1032 static int 1033 mt7530_port_enable(struct dsa_switch *ds, int port, 1034 struct phy_device *phy) 1035 { 1036 struct dsa_port *dp = dsa_to_port(ds, port); 1037 struct mt7530_priv *priv = ds->priv; 1038 1039 mutex_lock(&priv->reg_mutex); 1040 1041 /* Allow the user port gets connected to the cpu port and also 1042 * restore the port matrix if the port is the member of a certain 1043 * bridge. 1044 */ 1045 if (dsa_port_is_user(dp)) { 1046 struct dsa_port *cpu_dp = dp->cpu_dp; 1047 1048 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); 1049 } 1050 priv->ports[port].enable = true; 1051 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1052 priv->ports[port].pm); 1053 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1054 1055 mutex_unlock(&priv->reg_mutex); 1056 1057 return 0; 1058 } 1059 1060 static void 1061 mt7530_port_disable(struct dsa_switch *ds, int port) 1062 { 1063 struct mt7530_priv *priv = ds->priv; 1064 1065 mutex_lock(&priv->reg_mutex); 1066 1067 /* Clear up all port matrix which could be restored in the next 1068 * enablement for the port. 1069 */ 1070 priv->ports[port].enable = false; 1071 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1072 PCR_MATRIX_CLR); 1073 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1074 1075 mutex_unlock(&priv->reg_mutex); 1076 } 1077 1078 static int 1079 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1080 { 1081 struct mt7530_priv *priv = ds->priv; 1082 struct mii_bus *bus = priv->bus; 1083 int length; 1084 u32 val; 1085 1086 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1087 * largest MTU of the slave ports. Because the switch only has a global 1088 * RX length register, only allowing CPU port here is enough. 1089 */ 1090 if (!dsa_is_cpu_port(ds, port)) 1091 return 0; 1092 1093 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 1094 1095 val = mt7530_mii_read(priv, MT7530_GMACCR); 1096 val &= ~MAX_RX_PKT_LEN_MASK; 1097 1098 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1099 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1100 if (length <= 1522) { 1101 val |= MAX_RX_PKT_LEN_1522; 1102 } else if (length <= 1536) { 1103 val |= MAX_RX_PKT_LEN_1536; 1104 } else if (length <= 1552) { 1105 val |= MAX_RX_PKT_LEN_1552; 1106 } else { 1107 val &= ~MAX_RX_JUMBO_MASK; 1108 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1109 val |= MAX_RX_PKT_LEN_JUMBO; 1110 } 1111 1112 mt7530_mii_write(priv, MT7530_GMACCR, val); 1113 1114 mutex_unlock(&bus->mdio_lock); 1115 1116 return 0; 1117 } 1118 1119 static int 1120 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1121 { 1122 return MT7530_MAX_MTU; 1123 } 1124 1125 static void 1126 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1127 { 1128 struct mt7530_priv *priv = ds->priv; 1129 u32 stp_state; 1130 1131 switch (state) { 1132 case BR_STATE_DISABLED: 1133 stp_state = MT7530_STP_DISABLED; 1134 break; 1135 case BR_STATE_BLOCKING: 1136 stp_state = MT7530_STP_BLOCKING; 1137 break; 1138 case BR_STATE_LISTENING: 1139 stp_state = MT7530_STP_LISTENING; 1140 break; 1141 case BR_STATE_LEARNING: 1142 stp_state = MT7530_STP_LEARNING; 1143 break; 1144 case BR_STATE_FORWARDING: 1145 default: 1146 stp_state = MT7530_STP_FORWARDING; 1147 break; 1148 } 1149 1150 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1151 FID_PST(FID_BRIDGED, stp_state)); 1152 } 1153 1154 static int 1155 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1156 struct switchdev_brport_flags flags, 1157 struct netlink_ext_ack *extack) 1158 { 1159 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1160 BR_BCAST_FLOOD)) 1161 return -EINVAL; 1162 1163 return 0; 1164 } 1165 1166 static int 1167 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1168 struct switchdev_brport_flags flags, 1169 struct netlink_ext_ack *extack) 1170 { 1171 struct mt7530_priv *priv = ds->priv; 1172 1173 if (flags.mask & BR_LEARNING) 1174 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1175 flags.val & BR_LEARNING ? 0 : SA_DIS); 1176 1177 if (flags.mask & BR_FLOOD) 1178 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), 1179 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1180 1181 if (flags.mask & BR_MCAST_FLOOD) 1182 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1183 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1184 1185 if (flags.mask & BR_BCAST_FLOOD) 1186 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), 1187 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1188 1189 return 0; 1190 } 1191 1192 static int 1193 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1194 struct dsa_bridge bridge, bool *tx_fwd_offload, 1195 struct netlink_ext_ack *extack) 1196 { 1197 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1198 struct dsa_port *cpu_dp = dp->cpu_dp; 1199 u32 port_bitmap = BIT(cpu_dp->index); 1200 struct mt7530_priv *priv = ds->priv; 1201 1202 mutex_lock(&priv->reg_mutex); 1203 1204 dsa_switch_for_each_user_port(other_dp, ds) { 1205 int other_port = other_dp->index; 1206 1207 if (dp == other_dp) 1208 continue; 1209 1210 /* Add this port to the port matrix of the other ports in the 1211 * same bridge. If the port is disabled, port matrix is kept 1212 * and not being setup until the port becomes enabled. 1213 */ 1214 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1215 continue; 1216 1217 if (priv->ports[other_port].enable) 1218 mt7530_set(priv, MT7530_PCR_P(other_port), 1219 PCR_MATRIX(BIT(port))); 1220 priv->ports[other_port].pm |= PCR_MATRIX(BIT(port)); 1221 1222 port_bitmap |= BIT(other_port); 1223 } 1224 1225 /* Add the all other ports to this port matrix. */ 1226 if (priv->ports[port].enable) 1227 mt7530_rmw(priv, MT7530_PCR_P(port), 1228 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1229 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1230 1231 /* Set to fallback mode for independent VLAN learning */ 1232 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1233 MT7530_PORT_FALLBACK_MODE); 1234 1235 mutex_unlock(&priv->reg_mutex); 1236 1237 return 0; 1238 } 1239 1240 static void 1241 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1242 { 1243 struct mt7530_priv *priv = ds->priv; 1244 bool all_user_ports_removed = true; 1245 int i; 1246 1247 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1248 * bridge. Don't set standalone ports to fallback mode. 1249 */ 1250 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) 1251 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1252 MT7530_PORT_FALLBACK_MODE); 1253 1254 mt7530_rmw(priv, MT7530_PVC_P(port), 1255 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1256 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1257 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1258 MT7530_VLAN_ACC_ALL); 1259 1260 /* Set PVID to 0 */ 1261 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1262 G0_PORT_VID_DEF); 1263 1264 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1265 if (dsa_is_user_port(ds, i) && 1266 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1267 all_user_ports_removed = false; 1268 break; 1269 } 1270 } 1271 1272 /* CPU port also does the same thing until all user ports belonging to 1273 * the CPU port get out of VLAN filtering mode. 1274 */ 1275 if (all_user_ports_removed) { 1276 struct dsa_port *dp = dsa_to_port(ds, port); 1277 struct dsa_port *cpu_dp = dp->cpu_dp; 1278 1279 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), 1280 PCR_MATRIX(dsa_user_ports(priv->ds))); 1281 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG 1282 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1283 } 1284 } 1285 1286 static void 1287 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1288 { 1289 struct mt7530_priv *priv = ds->priv; 1290 1291 /* Trapped into security mode allows packet forwarding through VLAN 1292 * table lookup. 1293 */ 1294 if (dsa_is_user_port(ds, port)) { 1295 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1296 MT7530_PORT_SECURITY_MODE); 1297 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1298 G0_PORT_VID(priv->ports[port].pvid)); 1299 1300 /* Only accept tagged frames if PVID is not set */ 1301 if (!priv->ports[port].pvid) 1302 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1303 MT7530_VLAN_ACC_TAGGED); 1304 1305 /* Set the port as a user port which is to be able to recognize 1306 * VID from incoming packets before fetching entry within the 1307 * VLAN table. 1308 */ 1309 mt7530_rmw(priv, MT7530_PVC_P(port), 1310 VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1311 VLAN_ATTR(MT7530_VLAN_USER) | 1312 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1313 } else { 1314 /* Also set CPU ports to the "user" VLAN port attribute, to 1315 * allow VLAN classification, but keep the EG_TAG attribute as 1316 * "consistent" (i.o.w. don't change its value) for packets 1317 * received by the switch from the CPU, so that tagged packets 1318 * are forwarded to user ports as tagged, and untagged as 1319 * untagged. 1320 */ 1321 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 1322 VLAN_ATTR(MT7530_VLAN_USER)); 1323 } 1324 } 1325 1326 static void 1327 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1328 struct dsa_bridge bridge) 1329 { 1330 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1331 struct dsa_port *cpu_dp = dp->cpu_dp; 1332 struct mt7530_priv *priv = ds->priv; 1333 1334 mutex_lock(&priv->reg_mutex); 1335 1336 dsa_switch_for_each_user_port(other_dp, ds) { 1337 int other_port = other_dp->index; 1338 1339 if (dp == other_dp) 1340 continue; 1341 1342 /* Remove this port from the port matrix of the other ports 1343 * in the same bridge. If the port is disabled, port matrix 1344 * is kept and not being setup until the port becomes enabled. 1345 */ 1346 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1347 continue; 1348 1349 if (priv->ports[other_port].enable) 1350 mt7530_clear(priv, MT7530_PCR_P(other_port), 1351 PCR_MATRIX(BIT(port))); 1352 priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port)); 1353 } 1354 1355 /* Set the cpu port to be the only one in the port matrix of 1356 * this port. 1357 */ 1358 if (priv->ports[port].enable) 1359 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1360 PCR_MATRIX(BIT(cpu_dp->index))); 1361 priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index)); 1362 1363 /* When a port is removed from the bridge, the port would be set up 1364 * back to the default as is at initial boot which is a VLAN-unaware 1365 * port. 1366 */ 1367 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1368 MT7530_PORT_MATRIX_MODE); 1369 1370 mutex_unlock(&priv->reg_mutex); 1371 } 1372 1373 static int 1374 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1375 const unsigned char *addr, u16 vid, 1376 struct dsa_db db) 1377 { 1378 struct mt7530_priv *priv = ds->priv; 1379 int ret; 1380 u8 port_mask = BIT(port); 1381 1382 mutex_lock(&priv->reg_mutex); 1383 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1384 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1385 mutex_unlock(&priv->reg_mutex); 1386 1387 return ret; 1388 } 1389 1390 static int 1391 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1392 const unsigned char *addr, u16 vid, 1393 struct dsa_db db) 1394 { 1395 struct mt7530_priv *priv = ds->priv; 1396 int ret; 1397 u8 port_mask = BIT(port); 1398 1399 mutex_lock(&priv->reg_mutex); 1400 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1401 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1402 mutex_unlock(&priv->reg_mutex); 1403 1404 return ret; 1405 } 1406 1407 static int 1408 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1409 dsa_fdb_dump_cb_t *cb, void *data) 1410 { 1411 struct mt7530_priv *priv = ds->priv; 1412 struct mt7530_fdb _fdb = { 0 }; 1413 int cnt = MT7530_NUM_FDB_RECORDS; 1414 int ret = 0; 1415 u32 rsp = 0; 1416 1417 mutex_lock(&priv->reg_mutex); 1418 1419 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1420 if (ret < 0) 1421 goto err; 1422 1423 do { 1424 if (rsp & ATC_SRCH_HIT) { 1425 mt7530_fdb_read(priv, &_fdb); 1426 if (_fdb.port_mask & BIT(port)) { 1427 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1428 data); 1429 if (ret < 0) 1430 break; 1431 } 1432 } 1433 } while (--cnt && 1434 !(rsp & ATC_SRCH_END) && 1435 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1436 err: 1437 mutex_unlock(&priv->reg_mutex); 1438 1439 return 0; 1440 } 1441 1442 static int 1443 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1444 const struct switchdev_obj_port_mdb *mdb, 1445 struct dsa_db db) 1446 { 1447 struct mt7530_priv *priv = ds->priv; 1448 const u8 *addr = mdb->addr; 1449 u16 vid = mdb->vid; 1450 u8 port_mask = 0; 1451 int ret; 1452 1453 mutex_lock(&priv->reg_mutex); 1454 1455 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1456 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1457 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1458 & PORT_MAP_MASK; 1459 1460 port_mask |= BIT(port); 1461 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1462 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1463 1464 mutex_unlock(&priv->reg_mutex); 1465 1466 return ret; 1467 } 1468 1469 static int 1470 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1471 const struct switchdev_obj_port_mdb *mdb, 1472 struct dsa_db db) 1473 { 1474 struct mt7530_priv *priv = ds->priv; 1475 const u8 *addr = mdb->addr; 1476 u16 vid = mdb->vid; 1477 u8 port_mask = 0; 1478 int ret; 1479 1480 mutex_lock(&priv->reg_mutex); 1481 1482 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1483 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1484 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1485 & PORT_MAP_MASK; 1486 1487 port_mask &= ~BIT(port); 1488 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1489 port_mask ? STATIC_ENT : STATIC_EMP); 1490 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1491 1492 mutex_unlock(&priv->reg_mutex); 1493 1494 return ret; 1495 } 1496 1497 static int 1498 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1499 { 1500 struct mt7530_dummy_poll p; 1501 u32 val; 1502 int ret; 1503 1504 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1505 mt7530_write(priv, MT7530_VTCR, val); 1506 1507 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1508 ret = readx_poll_timeout(_mt7530_read, &p, val, 1509 !(val & VTCR_BUSY), 20, 20000); 1510 if (ret < 0) { 1511 dev_err(priv->dev, "poll timeout\n"); 1512 return ret; 1513 } 1514 1515 val = mt7530_read(priv, MT7530_VTCR); 1516 if (val & VTCR_INVALID) { 1517 dev_err(priv->dev, "read VTCR invalid\n"); 1518 return -EINVAL; 1519 } 1520 1521 return 0; 1522 } 1523 1524 static int 1525 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1526 struct netlink_ext_ack *extack) 1527 { 1528 struct dsa_port *dp = dsa_to_port(ds, port); 1529 struct dsa_port *cpu_dp = dp->cpu_dp; 1530 1531 if (vlan_filtering) { 1532 /* The port is being kept as VLAN-unaware port when bridge is 1533 * set up with vlan_filtering not being set, Otherwise, the 1534 * port and the corresponding CPU port is required the setup 1535 * for becoming a VLAN-aware port. 1536 */ 1537 mt7530_port_set_vlan_aware(ds, port); 1538 mt7530_port_set_vlan_aware(ds, cpu_dp->index); 1539 } else { 1540 mt7530_port_set_vlan_unaware(ds, port); 1541 } 1542 1543 return 0; 1544 } 1545 1546 static void 1547 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1548 struct mt7530_hw_vlan_entry *entry) 1549 { 1550 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); 1551 u8 new_members; 1552 u32 val; 1553 1554 new_members = entry->old_members | BIT(entry->port); 1555 1556 /* Validate the entry with independent learning, create egress tag per 1557 * VLAN and joining the port as one of the port members. 1558 */ 1559 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1560 VLAN_VALID; 1561 mt7530_write(priv, MT7530_VAWD1, val); 1562 1563 /* Decide whether adding tag or not for those outgoing packets from the 1564 * port inside the VLAN. 1565 * CPU port is always taken as a tagged port for serving more than one 1566 * VLANs across and also being applied with egress type stack mode for 1567 * that VLAN tags would be appended after hardware special tag used as 1568 * DSA tag. 1569 */ 1570 if (dsa_port_is_cpu(dp)) 1571 val = MT7530_VLAN_EGRESS_STACK; 1572 else if (entry->untagged) 1573 val = MT7530_VLAN_EGRESS_UNTAG; 1574 else 1575 val = MT7530_VLAN_EGRESS_TAG; 1576 mt7530_rmw(priv, MT7530_VAWD2, 1577 ETAG_CTRL_P_MASK(entry->port), 1578 ETAG_CTRL_P(entry->port, val)); 1579 } 1580 1581 static void 1582 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1583 struct mt7530_hw_vlan_entry *entry) 1584 { 1585 u8 new_members; 1586 u32 val; 1587 1588 new_members = entry->old_members & ~BIT(entry->port); 1589 1590 val = mt7530_read(priv, MT7530_VAWD1); 1591 if (!(val & VLAN_VALID)) { 1592 dev_err(priv->dev, 1593 "Cannot be deleted due to invalid entry\n"); 1594 return; 1595 } 1596 1597 if (new_members) { 1598 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1599 VLAN_VALID; 1600 mt7530_write(priv, MT7530_VAWD1, val); 1601 } else { 1602 mt7530_write(priv, MT7530_VAWD1, 0); 1603 mt7530_write(priv, MT7530_VAWD2, 0); 1604 } 1605 } 1606 1607 static void 1608 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1609 struct mt7530_hw_vlan_entry *entry, 1610 mt7530_vlan_op vlan_op) 1611 { 1612 u32 val; 1613 1614 /* Fetch entry */ 1615 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1616 1617 val = mt7530_read(priv, MT7530_VAWD1); 1618 1619 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1620 1621 /* Manipulate entry */ 1622 vlan_op(priv, entry); 1623 1624 /* Flush result to hardware */ 1625 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1626 } 1627 1628 static int 1629 mt7530_setup_vlan0(struct mt7530_priv *priv) 1630 { 1631 u32 val; 1632 1633 /* Validate the entry with independent learning, keep the original 1634 * ingress tag attribute. 1635 */ 1636 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1637 VLAN_VALID; 1638 mt7530_write(priv, MT7530_VAWD1, val); 1639 1640 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1641 } 1642 1643 static int 1644 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1645 const struct switchdev_obj_port_vlan *vlan, 1646 struct netlink_ext_ack *extack) 1647 { 1648 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1649 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1650 struct mt7530_hw_vlan_entry new_entry; 1651 struct mt7530_priv *priv = ds->priv; 1652 1653 mutex_lock(&priv->reg_mutex); 1654 1655 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1656 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1657 1658 if (pvid) { 1659 priv->ports[port].pvid = vlan->vid; 1660 1661 /* Accept all frames if PVID is set */ 1662 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1663 MT7530_VLAN_ACC_ALL); 1664 1665 /* Only configure PVID if VLAN filtering is enabled */ 1666 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1667 mt7530_rmw(priv, MT7530_PPBV1_P(port), 1668 G0_PORT_VID_MASK, 1669 G0_PORT_VID(vlan->vid)); 1670 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 1671 /* This VLAN is overwritten without PVID, so unset it */ 1672 priv->ports[port].pvid = G0_PORT_VID_DEF; 1673 1674 /* Only accept tagged frames if the port is VLAN-aware */ 1675 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1676 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1677 MT7530_VLAN_ACC_TAGGED); 1678 1679 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1680 G0_PORT_VID_DEF); 1681 } 1682 1683 mutex_unlock(&priv->reg_mutex); 1684 1685 return 0; 1686 } 1687 1688 static int 1689 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1690 const struct switchdev_obj_port_vlan *vlan) 1691 { 1692 struct mt7530_hw_vlan_entry target_entry; 1693 struct mt7530_priv *priv = ds->priv; 1694 1695 mutex_lock(&priv->reg_mutex); 1696 1697 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1698 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1699 mt7530_hw_vlan_del); 1700 1701 /* PVID is being restored to the default whenever the PVID port 1702 * is being removed from the VLAN. 1703 */ 1704 if (priv->ports[port].pvid == vlan->vid) { 1705 priv->ports[port].pvid = G0_PORT_VID_DEF; 1706 1707 /* Only accept tagged frames if the port is VLAN-aware */ 1708 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1709 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1710 MT7530_VLAN_ACC_TAGGED); 1711 1712 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1713 G0_PORT_VID_DEF); 1714 } 1715 1716 1717 mutex_unlock(&priv->reg_mutex); 1718 1719 return 0; 1720 } 1721 1722 static int mt753x_mirror_port_get(unsigned int id, u32 val) 1723 { 1724 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : 1725 MIRROR_PORT(val); 1726 } 1727 1728 static int mt753x_mirror_port_set(unsigned int id, u32 val) 1729 { 1730 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : 1731 MIRROR_PORT(val); 1732 } 1733 1734 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1735 struct dsa_mall_mirror_tc_entry *mirror, 1736 bool ingress, struct netlink_ext_ack *extack) 1737 { 1738 struct mt7530_priv *priv = ds->priv; 1739 int monitor_port; 1740 u32 val; 1741 1742 /* Check for existent entry */ 1743 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1744 return -EEXIST; 1745 1746 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1747 1748 /* MT7530 only supports one monitor port */ 1749 monitor_port = mt753x_mirror_port_get(priv->id, val); 1750 if (val & MT753X_MIRROR_EN(priv->id) && 1751 monitor_port != mirror->to_local_port) 1752 return -EEXIST; 1753 1754 val |= MT753X_MIRROR_EN(priv->id); 1755 val &= ~MT753X_MIRROR_MASK(priv->id); 1756 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); 1757 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1758 1759 val = mt7530_read(priv, MT7530_PCR_P(port)); 1760 if (ingress) { 1761 val |= PORT_RX_MIR; 1762 priv->mirror_rx |= BIT(port); 1763 } else { 1764 val |= PORT_TX_MIR; 1765 priv->mirror_tx |= BIT(port); 1766 } 1767 mt7530_write(priv, MT7530_PCR_P(port), val); 1768 1769 return 0; 1770 } 1771 1772 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1773 struct dsa_mall_mirror_tc_entry *mirror) 1774 { 1775 struct mt7530_priv *priv = ds->priv; 1776 u32 val; 1777 1778 val = mt7530_read(priv, MT7530_PCR_P(port)); 1779 if (mirror->ingress) { 1780 val &= ~PORT_RX_MIR; 1781 priv->mirror_rx &= ~BIT(port); 1782 } else { 1783 val &= ~PORT_TX_MIR; 1784 priv->mirror_tx &= ~BIT(port); 1785 } 1786 mt7530_write(priv, MT7530_PCR_P(port), val); 1787 1788 if (!priv->mirror_rx && !priv->mirror_tx) { 1789 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1790 val &= ~MT753X_MIRROR_EN(priv->id); 1791 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1792 } 1793 } 1794 1795 static enum dsa_tag_protocol 1796 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1797 enum dsa_tag_protocol mp) 1798 { 1799 return DSA_TAG_PROTO_MTK; 1800 } 1801 1802 #ifdef CONFIG_GPIOLIB 1803 static inline u32 1804 mt7530_gpio_to_bit(unsigned int offset) 1805 { 1806 /* Map GPIO offset to register bit 1807 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1808 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1809 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1810 * [14:12] port 3 LED 0..2 as GPIO 9..11 1811 * [18:16] port 4 LED 0..2 as GPIO 12..14 1812 */ 1813 return BIT(offset + offset / 3); 1814 } 1815 1816 static int 1817 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1818 { 1819 struct mt7530_priv *priv = gpiochip_get_data(gc); 1820 u32 bit = mt7530_gpio_to_bit(offset); 1821 1822 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1823 } 1824 1825 static void 1826 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1827 { 1828 struct mt7530_priv *priv = gpiochip_get_data(gc); 1829 u32 bit = mt7530_gpio_to_bit(offset); 1830 1831 if (value) 1832 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1833 else 1834 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1835 } 1836 1837 static int 1838 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1839 { 1840 struct mt7530_priv *priv = gpiochip_get_data(gc); 1841 u32 bit = mt7530_gpio_to_bit(offset); 1842 1843 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1844 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1845 } 1846 1847 static int 1848 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1849 { 1850 struct mt7530_priv *priv = gpiochip_get_data(gc); 1851 u32 bit = mt7530_gpio_to_bit(offset); 1852 1853 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 1854 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 1855 1856 return 0; 1857 } 1858 1859 static int 1860 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 1861 { 1862 struct mt7530_priv *priv = gpiochip_get_data(gc); 1863 u32 bit = mt7530_gpio_to_bit(offset); 1864 1865 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 1866 1867 if (value) 1868 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1869 else 1870 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1871 1872 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 1873 1874 return 0; 1875 } 1876 1877 static int 1878 mt7530_setup_gpio(struct mt7530_priv *priv) 1879 { 1880 struct device *dev = priv->dev; 1881 struct gpio_chip *gc; 1882 1883 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1884 if (!gc) 1885 return -ENOMEM; 1886 1887 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 1888 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 1889 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 1890 1891 gc->label = "mt7530"; 1892 gc->parent = dev; 1893 gc->owner = THIS_MODULE; 1894 gc->get_direction = mt7530_gpio_get_direction; 1895 gc->direction_input = mt7530_gpio_direction_input; 1896 gc->direction_output = mt7530_gpio_direction_output; 1897 gc->get = mt7530_gpio_get; 1898 gc->set = mt7530_gpio_set; 1899 gc->base = -1; 1900 gc->ngpio = 15; 1901 gc->can_sleep = true; 1902 1903 return devm_gpiochip_add_data(dev, gc, priv); 1904 } 1905 #endif /* CONFIG_GPIOLIB */ 1906 1907 static irqreturn_t 1908 mt7530_irq_thread_fn(int irq, void *dev_id) 1909 { 1910 struct mt7530_priv *priv = dev_id; 1911 bool handled = false; 1912 u32 val; 1913 int p; 1914 1915 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 1916 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); 1917 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); 1918 mutex_unlock(&priv->bus->mdio_lock); 1919 1920 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1921 if (BIT(p) & val) { 1922 unsigned int irq; 1923 1924 irq = irq_find_mapping(priv->irq_domain, p); 1925 handle_nested_irq(irq); 1926 handled = true; 1927 } 1928 } 1929 1930 return IRQ_RETVAL(handled); 1931 } 1932 1933 static void 1934 mt7530_irq_mask(struct irq_data *d) 1935 { 1936 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1937 1938 priv->irq_enable &= ~BIT(d->hwirq); 1939 } 1940 1941 static void 1942 mt7530_irq_unmask(struct irq_data *d) 1943 { 1944 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1945 1946 priv->irq_enable |= BIT(d->hwirq); 1947 } 1948 1949 static void 1950 mt7530_irq_bus_lock(struct irq_data *d) 1951 { 1952 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1953 1954 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 1955 } 1956 1957 static void 1958 mt7530_irq_bus_sync_unlock(struct irq_data *d) 1959 { 1960 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1961 1962 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 1963 mutex_unlock(&priv->bus->mdio_lock); 1964 } 1965 1966 static struct irq_chip mt7530_irq_chip = { 1967 .name = KBUILD_MODNAME, 1968 .irq_mask = mt7530_irq_mask, 1969 .irq_unmask = mt7530_irq_unmask, 1970 .irq_bus_lock = mt7530_irq_bus_lock, 1971 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, 1972 }; 1973 1974 static int 1975 mt7530_irq_map(struct irq_domain *domain, unsigned int irq, 1976 irq_hw_number_t hwirq) 1977 { 1978 irq_set_chip_data(irq, domain->host_data); 1979 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); 1980 irq_set_nested_thread(irq, true); 1981 irq_set_noprobe(irq); 1982 1983 return 0; 1984 } 1985 1986 static const struct irq_domain_ops mt7530_irq_domain_ops = { 1987 .map = mt7530_irq_map, 1988 .xlate = irq_domain_xlate_onecell, 1989 }; 1990 1991 static void 1992 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 1993 { 1994 struct dsa_switch *ds = priv->ds; 1995 int p; 1996 1997 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1998 if (BIT(p) & ds->phys_mii_mask) { 1999 unsigned int irq; 2000 2001 irq = irq_create_mapping(priv->irq_domain, p); 2002 ds->slave_mii_bus->irq[p] = irq; 2003 } 2004 } 2005 } 2006 2007 static int 2008 mt7530_setup_irq(struct mt7530_priv *priv) 2009 { 2010 struct device *dev = priv->dev; 2011 struct device_node *np = dev->of_node; 2012 int ret; 2013 2014 if (!of_property_read_bool(np, "interrupt-controller")) { 2015 dev_info(dev, "no interrupt support\n"); 2016 return 0; 2017 } 2018 2019 priv->irq = of_irq_get(np, 0); 2020 if (priv->irq <= 0) { 2021 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); 2022 return priv->irq ? : -EINVAL; 2023 } 2024 2025 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2026 &mt7530_irq_domain_ops, priv); 2027 if (!priv->irq_domain) { 2028 dev_err(dev, "failed to create IRQ domain\n"); 2029 return -ENOMEM; 2030 } 2031 2032 /* This register must be set for MT7530 to properly fire interrupts */ 2033 if (priv->id != ID_MT7531) 2034 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 2035 2036 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, 2037 IRQF_ONESHOT, KBUILD_MODNAME, priv); 2038 if (ret) { 2039 irq_domain_remove(priv->irq_domain); 2040 dev_err(dev, "failed to request IRQ: %d\n", ret); 2041 return ret; 2042 } 2043 2044 return 0; 2045 } 2046 2047 static void 2048 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2049 { 2050 int p; 2051 2052 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2053 if (BIT(p) & priv->ds->phys_mii_mask) { 2054 unsigned int irq; 2055 2056 irq = irq_find_mapping(priv->irq_domain, p); 2057 irq_dispose_mapping(irq); 2058 } 2059 } 2060 } 2061 2062 static void 2063 mt7530_free_irq_common(struct mt7530_priv *priv) 2064 { 2065 free_irq(priv->irq, priv); 2066 irq_domain_remove(priv->irq_domain); 2067 } 2068 2069 static void 2070 mt7530_free_irq(struct mt7530_priv *priv) 2071 { 2072 mt7530_free_mdio_irq(priv); 2073 mt7530_free_irq_common(priv); 2074 } 2075 2076 static int 2077 mt7530_setup_mdio(struct mt7530_priv *priv) 2078 { 2079 struct dsa_switch *ds = priv->ds; 2080 struct device *dev = priv->dev; 2081 struct mii_bus *bus; 2082 static int idx; 2083 int ret; 2084 2085 bus = devm_mdiobus_alloc(dev); 2086 if (!bus) 2087 return -ENOMEM; 2088 2089 ds->slave_mii_bus = bus; 2090 bus->priv = priv; 2091 bus->name = KBUILD_MODNAME "-mii"; 2092 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2093 bus->read = mt753x_phy_read_c22; 2094 bus->write = mt753x_phy_write_c22; 2095 bus->read_c45 = mt753x_phy_read_c45; 2096 bus->write_c45 = mt753x_phy_write_c45; 2097 bus->parent = dev; 2098 bus->phy_mask = ~ds->phys_mii_mask; 2099 2100 if (priv->irq) 2101 mt7530_setup_mdio_irq(priv); 2102 2103 ret = devm_mdiobus_register(dev, bus); 2104 if (ret) { 2105 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2106 if (priv->irq) 2107 mt7530_free_mdio_irq(priv); 2108 } 2109 2110 return ret; 2111 } 2112 2113 static int 2114 mt7530_setup(struct dsa_switch *ds) 2115 { 2116 struct mt7530_priv *priv = ds->priv; 2117 struct device_node *dn = NULL; 2118 struct device_node *phy_node; 2119 struct device_node *mac_np; 2120 struct mt7530_dummy_poll p; 2121 phy_interface_t interface; 2122 struct dsa_port *cpu_dp; 2123 u32 id, val; 2124 int ret, i; 2125 2126 /* The parent node of master netdev which holds the common system 2127 * controller also is the container for two GMACs nodes representing 2128 * as two netdev instances. 2129 */ 2130 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2131 dn = cpu_dp->master->dev.of_node->parent; 2132 /* It doesn't matter which CPU port is found first, 2133 * their masters should share the same parent OF node 2134 */ 2135 break; 2136 } 2137 2138 if (!dn) { 2139 dev_err(ds->dev, "parent OF node of DSA master not found"); 2140 return -EINVAL; 2141 } 2142 2143 ds->assisted_learning_on_cpu_port = true; 2144 ds->mtu_enforcement_ingress = true; 2145 2146 if (priv->id == ID_MT7530) { 2147 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2148 ret = regulator_enable(priv->core_pwr); 2149 if (ret < 0) { 2150 dev_err(priv->dev, 2151 "Failed to enable core power: %d\n", ret); 2152 return ret; 2153 } 2154 2155 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2156 ret = regulator_enable(priv->io_pwr); 2157 if (ret < 0) { 2158 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2159 ret); 2160 return ret; 2161 } 2162 } 2163 2164 /* Reset whole chip through gpio pin or memory-mapped registers for 2165 * different type of hardware 2166 */ 2167 if (priv->mcm) { 2168 reset_control_assert(priv->rstc); 2169 usleep_range(1000, 1100); 2170 reset_control_deassert(priv->rstc); 2171 } else { 2172 gpiod_set_value_cansleep(priv->reset, 0); 2173 usleep_range(1000, 1100); 2174 gpiod_set_value_cansleep(priv->reset, 1); 2175 } 2176 2177 /* Waiting for MT7530 got to stable */ 2178 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2179 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2180 20, 1000000); 2181 if (ret < 0) { 2182 dev_err(priv->dev, "reset timeout\n"); 2183 return ret; 2184 } 2185 2186 id = mt7530_read(priv, MT7530_CREV); 2187 id >>= CHIP_NAME_SHIFT; 2188 if (id != MT7530_ID) { 2189 dev_err(priv->dev, "chip %x can't be supported\n", id); 2190 return -ENODEV; 2191 } 2192 2193 /* Reset the switch through internal reset */ 2194 mt7530_write(priv, MT7530_SYS_CTRL, 2195 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2196 SYS_CTRL_REG_RST); 2197 2198 mt7530_pll_setup(priv); 2199 2200 /* Lower Tx driving for TRGMII path */ 2201 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2202 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 2203 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 2204 2205 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2206 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 2207 RD_TAP_MASK, RD_TAP(16)); 2208 2209 /* Enable port 6 */ 2210 val = mt7530_read(priv, MT7530_MHWTRAP); 2211 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 2212 val |= MHWTRAP_MANUAL; 2213 mt7530_write(priv, MT7530_MHWTRAP, val); 2214 2215 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2216 2217 /* Enable and reset MIB counters */ 2218 mt7530_mib_reset(ds); 2219 2220 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2221 /* Disable forwarding by default on all ports */ 2222 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2223 PCR_MATRIX_CLR); 2224 2225 /* Disable learning by default on all ports */ 2226 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2227 2228 if (dsa_is_cpu_port(ds, i)) { 2229 ret = mt753x_cpu_port_enable(ds, i); 2230 if (ret) 2231 return ret; 2232 } else { 2233 mt7530_port_disable(ds, i); 2234 2235 /* Set default PVID to 0 on all user ports */ 2236 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2237 G0_PORT_VID_DEF); 2238 } 2239 /* Enable consistent egress tag */ 2240 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2241 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2242 } 2243 2244 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2245 ret = mt7530_setup_vlan0(priv); 2246 if (ret) 2247 return ret; 2248 2249 /* Setup port 5 */ 2250 priv->p5_intf_sel = P5_DISABLED; 2251 interface = PHY_INTERFACE_MODE_NA; 2252 2253 if (!dsa_is_unused_port(ds, 5)) { 2254 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2255 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); 2256 if (ret && ret != -ENODEV) 2257 return ret; 2258 } else { 2259 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ 2260 for_each_child_of_node(dn, mac_np) { 2261 if (!of_device_is_compatible(mac_np, 2262 "mediatek,eth-mac")) 2263 continue; 2264 2265 ret = of_property_read_u32(mac_np, "reg", &id); 2266 if (ret < 0 || id != 1) 2267 continue; 2268 2269 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2270 if (!phy_node) 2271 continue; 2272 2273 if (phy_node->parent == priv->dev->of_node->parent) { 2274 ret = of_get_phy_mode(mac_np, &interface); 2275 if (ret && ret != -ENODEV) { 2276 of_node_put(mac_np); 2277 of_node_put(phy_node); 2278 return ret; 2279 } 2280 id = of_mdio_parse_addr(ds->dev, phy_node); 2281 if (id == 0) 2282 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 2283 if (id == 4) 2284 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 2285 } 2286 of_node_put(mac_np); 2287 of_node_put(phy_node); 2288 break; 2289 } 2290 } 2291 2292 #ifdef CONFIG_GPIOLIB 2293 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2294 ret = mt7530_setup_gpio(priv); 2295 if (ret) 2296 return ret; 2297 } 2298 #endif /* CONFIG_GPIOLIB */ 2299 2300 mt7530_setup_port5(ds, interface); 2301 2302 /* Flush the FDB table */ 2303 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2304 if (ret < 0) 2305 return ret; 2306 2307 return 0; 2308 } 2309 2310 static int 2311 mt7531_setup(struct dsa_switch *ds) 2312 { 2313 struct mt7530_priv *priv = ds->priv; 2314 struct mt7530_dummy_poll p; 2315 struct dsa_port *cpu_dp; 2316 u32 val, id; 2317 int ret, i; 2318 2319 /* Reset whole chip through gpio pin or memory-mapped registers for 2320 * different type of hardware 2321 */ 2322 if (priv->mcm) { 2323 reset_control_assert(priv->rstc); 2324 usleep_range(1000, 1100); 2325 reset_control_deassert(priv->rstc); 2326 } else { 2327 gpiod_set_value_cansleep(priv->reset, 0); 2328 usleep_range(1000, 1100); 2329 gpiod_set_value_cansleep(priv->reset, 1); 2330 } 2331 2332 /* Waiting for MT7530 got to stable */ 2333 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2334 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2335 20, 1000000); 2336 if (ret < 0) { 2337 dev_err(priv->dev, "reset timeout\n"); 2338 return ret; 2339 } 2340 2341 id = mt7530_read(priv, MT7531_CREV); 2342 id >>= CHIP_NAME_SHIFT; 2343 2344 if (id != MT7531_ID) { 2345 dev_err(priv->dev, "chip %x can't be supported\n", id); 2346 return -ENODEV; 2347 } 2348 2349 /* all MACs must be forced link-down before sw reset */ 2350 for (i = 0; i < MT7530_NUM_PORTS; i++) 2351 mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); 2352 2353 /* Reset the switch through internal reset */ 2354 mt7530_write(priv, MT7530_SYS_CTRL, 2355 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2356 SYS_CTRL_REG_RST); 2357 2358 mt7531_pll_setup(priv); 2359 2360 if (mt7531_dual_sgmii_supported(priv)) { 2361 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; 2362 2363 /* Let ds->slave_mii_bus be able to access external phy. */ 2364 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2365 MT7531_EXT_P_MDC_11); 2366 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2367 MT7531_EXT_P_MDIO_12); 2368 } else { 2369 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2370 } 2371 dev_dbg(ds->dev, "P5 support %s interface\n", 2372 p5_intf_modes(priv->p5_intf_sel)); 2373 2374 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2375 MT7531_GPIO0_INTERRUPT); 2376 2377 /* Let phylink decide the interface later. */ 2378 priv->p5_interface = PHY_INTERFACE_MODE_NA; 2379 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2380 2381 /* Enable PHY core PLL, since phy_device has not yet been created 2382 * provided for phy_[read,write]_mmd_indirect is called, we provide 2383 * our own mt7531_ind_mmd_phy_[read,write] to complete this 2384 * function. 2385 */ 2386 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, 2387 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2388 val |= MT7531_PHY_PLL_BYPASS_MODE; 2389 val &= ~MT7531_PHY_PLL_OFF; 2390 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, 2391 CORE_PLL_GROUP4, val); 2392 2393 /* BPDU to CPU port */ 2394 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2395 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, 2396 BIT(cpu_dp->index)); 2397 break; 2398 } 2399 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, 2400 MT753X_BPDU_CPU_ONLY); 2401 2402 /* Enable and reset MIB counters */ 2403 mt7530_mib_reset(ds); 2404 2405 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2406 /* Disable forwarding by default on all ports */ 2407 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2408 PCR_MATRIX_CLR); 2409 2410 /* Disable learning by default on all ports */ 2411 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2412 2413 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2414 2415 if (dsa_is_cpu_port(ds, i)) { 2416 ret = mt753x_cpu_port_enable(ds, i); 2417 if (ret) 2418 return ret; 2419 } else { 2420 mt7530_port_disable(ds, i); 2421 2422 /* Set default PVID to 0 on all user ports */ 2423 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2424 G0_PORT_VID_DEF); 2425 } 2426 2427 /* Enable consistent egress tag */ 2428 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2429 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2430 } 2431 2432 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2433 ret = mt7530_setup_vlan0(priv); 2434 if (ret) 2435 return ret; 2436 2437 ds->assisted_learning_on_cpu_port = true; 2438 ds->mtu_enforcement_ingress = true; 2439 2440 /* Flush the FDB table */ 2441 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2442 if (ret < 0) 2443 return ret; 2444 2445 return 0; 2446 } 2447 2448 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 2449 struct phylink_config *config) 2450 { 2451 switch (port) { 2452 case 0 ... 4: /* Internal phy */ 2453 __set_bit(PHY_INTERFACE_MODE_GMII, 2454 config->supported_interfaces); 2455 break; 2456 2457 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2458 phy_interface_set_rgmii(config->supported_interfaces); 2459 __set_bit(PHY_INTERFACE_MODE_MII, 2460 config->supported_interfaces); 2461 __set_bit(PHY_INTERFACE_MODE_GMII, 2462 config->supported_interfaces); 2463 break; 2464 2465 case 6: /* 1st cpu port */ 2466 __set_bit(PHY_INTERFACE_MODE_RGMII, 2467 config->supported_interfaces); 2468 __set_bit(PHY_INTERFACE_MODE_TRGMII, 2469 config->supported_interfaces); 2470 break; 2471 } 2472 } 2473 2474 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) 2475 { 2476 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); 2477 } 2478 2479 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, 2480 struct phylink_config *config) 2481 { 2482 struct mt7530_priv *priv = ds->priv; 2483 2484 switch (port) { 2485 case 0 ... 4: /* Internal phy */ 2486 __set_bit(PHY_INTERFACE_MODE_GMII, 2487 config->supported_interfaces); 2488 break; 2489 2490 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ 2491 if (mt7531_is_rgmii_port(priv, port)) { 2492 phy_interface_set_rgmii(config->supported_interfaces); 2493 break; 2494 } 2495 fallthrough; 2496 2497 case 6: /* 1st cpu port supports sgmii/8023z only */ 2498 __set_bit(PHY_INTERFACE_MODE_SGMII, 2499 config->supported_interfaces); 2500 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2501 config->supported_interfaces); 2502 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2503 config->supported_interfaces); 2504 2505 config->mac_capabilities |= MAC_2500FD; 2506 break; 2507 } 2508 } 2509 2510 static int 2511 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) 2512 { 2513 struct mt7530_priv *priv = ds->priv; 2514 2515 return priv->info->pad_setup(ds, state->interface); 2516 } 2517 2518 static int 2519 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2520 phy_interface_t interface) 2521 { 2522 struct mt7530_priv *priv = ds->priv; 2523 2524 /* Only need to setup port5. */ 2525 if (port != 5) 2526 return 0; 2527 2528 mt7530_setup_port5(priv->ds, interface); 2529 2530 return 0; 2531 } 2532 2533 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 2534 phy_interface_t interface, 2535 struct phy_device *phydev) 2536 { 2537 u32 val; 2538 2539 if (!mt7531_is_rgmii_port(priv, port)) { 2540 dev_err(priv->dev, "RGMII mode is not available for port %d\n", 2541 port); 2542 return -EINVAL; 2543 } 2544 2545 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2546 val |= GP_CLK_EN; 2547 val &= ~GP_MODE_MASK; 2548 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2549 val &= ~CLK_SKEW_IN_MASK; 2550 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2551 val &= ~CLK_SKEW_OUT_MASK; 2552 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2553 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2554 2555 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2556 if (!phydev || phy_driver_is_genphy(phydev)) { 2557 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2558 switch (interface) { 2559 case PHY_INTERFACE_MODE_RGMII: 2560 val |= TXCLK_NO_REVERSE; 2561 val |= RXCLK_NO_DELAY; 2562 break; 2563 case PHY_INTERFACE_MODE_RGMII_RXID: 2564 val |= TXCLK_NO_REVERSE; 2565 break; 2566 case PHY_INTERFACE_MODE_RGMII_TXID: 2567 val |= RXCLK_NO_DELAY; 2568 break; 2569 case PHY_INTERFACE_MODE_RGMII_ID: 2570 break; 2571 default: 2572 return -EINVAL; 2573 } 2574 } 2575 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2576 2577 return 0; 2578 } 2579 2580 static void mt7531_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode, 2581 phy_interface_t interface, int speed, int duplex) 2582 { 2583 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2584 int port = pcs_to_mt753x_pcs(pcs)->port; 2585 unsigned int val; 2586 2587 /* For adjusting speed and duplex of SGMII force mode. */ 2588 if (interface != PHY_INTERFACE_MODE_SGMII || 2589 phylink_autoneg_inband(mode)) 2590 return; 2591 2592 /* SGMII force mode setting */ 2593 val = mt7530_read(priv, MT7531_SGMII_MODE(port)); 2594 val &= ~MT7531_SGMII_IF_MODE_MASK; 2595 2596 switch (speed) { 2597 case SPEED_10: 2598 val |= MT7531_SGMII_FORCE_SPEED_10; 2599 break; 2600 case SPEED_100: 2601 val |= MT7531_SGMII_FORCE_SPEED_100; 2602 break; 2603 case SPEED_1000: 2604 val |= MT7531_SGMII_FORCE_SPEED_1000; 2605 break; 2606 } 2607 2608 /* MT7531 SGMII 1G force mode can only work in full duplex mode, 2609 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2610 * 2611 * The speed check is unnecessary as the MAC capabilities apply 2612 * this restriction. --rmk 2613 */ 2614 if ((speed == SPEED_10 || speed == SPEED_100) && 2615 duplex != DUPLEX_FULL) 2616 val |= MT7531_SGMII_FORCE_HALF_DUPLEX; 2617 2618 mt7530_write(priv, MT7531_SGMII_MODE(port), val); 2619 } 2620 2621 static bool mt753x_is_mac_port(u32 port) 2622 { 2623 return (port == 5 || port == 6); 2624 } 2625 2626 static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port, 2627 phy_interface_t interface) 2628 { 2629 u32 val; 2630 2631 if (!mt753x_is_mac_port(port)) 2632 return -EINVAL; 2633 2634 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2635 MT7531_SGMII_PHYA_PWD); 2636 2637 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port)); 2638 val &= ~MT7531_RG_TPHY_SPEED_MASK; 2639 /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B 2640 * encoding. 2641 */ 2642 val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ? 2643 MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G; 2644 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val); 2645 2646 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2647 2648 /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex 2649 * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2650 */ 2651 mt7530_rmw(priv, MT7531_SGMII_MODE(port), 2652 MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS, 2653 MT7531_SGMII_FORCE_SPEED_1000); 2654 2655 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2656 2657 return 0; 2658 } 2659 2660 static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port, 2661 phy_interface_t interface) 2662 { 2663 if (!mt753x_is_mac_port(port)) 2664 return -EINVAL; 2665 2666 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2667 MT7531_SGMII_PHYA_PWD); 2668 2669 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), 2670 MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G); 2671 2672 mt7530_set(priv, MT7531_SGMII_MODE(port), 2673 MT7531_SGMII_REMOTE_FAULT_DIS | 2674 MT7531_SGMII_SPEED_DUPLEX_AN); 2675 2676 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port), 2677 MT7531_SGMII_TX_CONFIG_MASK, 1); 2678 2679 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2680 2681 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART); 2682 2683 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2684 2685 return 0; 2686 } 2687 2688 static void mt7531_pcs_an_restart(struct phylink_pcs *pcs) 2689 { 2690 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2691 int port = pcs_to_mt753x_pcs(pcs)->port; 2692 u32 val; 2693 2694 /* Only restart AN when AN is enabled */ 2695 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2696 if (val & MT7531_SGMII_AN_ENABLE) { 2697 val |= MT7531_SGMII_AN_RESTART; 2698 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val); 2699 } 2700 } 2701 2702 static int 2703 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2704 phy_interface_t interface) 2705 { 2706 struct mt7530_priv *priv = ds->priv; 2707 struct phy_device *phydev; 2708 struct dsa_port *dp; 2709 2710 if (!mt753x_is_mac_port(port)) { 2711 dev_err(priv->dev, "port %d is not a MAC port\n", port); 2712 return -EINVAL; 2713 } 2714 2715 switch (interface) { 2716 case PHY_INTERFACE_MODE_RGMII: 2717 case PHY_INTERFACE_MODE_RGMII_ID: 2718 case PHY_INTERFACE_MODE_RGMII_RXID: 2719 case PHY_INTERFACE_MODE_RGMII_TXID: 2720 dp = dsa_to_port(ds, port); 2721 phydev = dp->slave->phydev; 2722 return mt7531_rgmii_setup(priv, port, interface, phydev); 2723 case PHY_INTERFACE_MODE_SGMII: 2724 return mt7531_sgmii_setup_mode_an(priv, port, interface); 2725 case PHY_INTERFACE_MODE_NA: 2726 case PHY_INTERFACE_MODE_1000BASEX: 2727 case PHY_INTERFACE_MODE_2500BASEX: 2728 return mt7531_sgmii_setup_mode_force(priv, port, interface); 2729 default: 2730 return -EINVAL; 2731 } 2732 2733 return -EINVAL; 2734 } 2735 2736 static int 2737 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2738 const struct phylink_link_state *state) 2739 { 2740 struct mt7530_priv *priv = ds->priv; 2741 2742 return priv->info->mac_port_config(ds, port, mode, state->interface); 2743 } 2744 2745 static struct phylink_pcs * 2746 mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port, 2747 phy_interface_t interface) 2748 { 2749 struct mt7530_priv *priv = ds->priv; 2750 2751 switch (interface) { 2752 case PHY_INTERFACE_MODE_TRGMII: 2753 case PHY_INTERFACE_MODE_SGMII: 2754 case PHY_INTERFACE_MODE_1000BASEX: 2755 case PHY_INTERFACE_MODE_2500BASEX: 2756 return &priv->pcs[port].pcs; 2757 2758 default: 2759 return NULL; 2760 } 2761 } 2762 2763 static void 2764 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2765 const struct phylink_link_state *state) 2766 { 2767 struct mt7530_priv *priv = ds->priv; 2768 u32 mcr_cur, mcr_new; 2769 2770 switch (port) { 2771 case 0 ... 4: /* Internal phy */ 2772 if (state->interface != PHY_INTERFACE_MODE_GMII) 2773 goto unsupported; 2774 break; 2775 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2776 if (priv->p5_interface == state->interface) 2777 break; 2778 2779 if (mt753x_mac_config(ds, port, mode, state) < 0) 2780 goto unsupported; 2781 2782 if (priv->p5_intf_sel != P5_DISABLED) 2783 priv->p5_interface = state->interface; 2784 break; 2785 case 6: /* 1st cpu port */ 2786 if (priv->p6_interface == state->interface) 2787 break; 2788 2789 mt753x_pad_setup(ds, state); 2790 2791 if (mt753x_mac_config(ds, port, mode, state) < 0) 2792 goto unsupported; 2793 2794 priv->p6_interface = state->interface; 2795 break; 2796 default: 2797 unsupported: 2798 dev_err(ds->dev, "%s: unsupported %s port: %i\n", 2799 __func__, phy_modes(state->interface), port); 2800 return; 2801 } 2802 2803 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); 2804 mcr_new = mcr_cur; 2805 mcr_new &= ~PMCR_LINK_SETTINGS_MASK; 2806 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | 2807 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); 2808 2809 /* Are we connected to external phy */ 2810 if (port == 5 && dsa_is_user_port(ds, 5)) 2811 mcr_new |= PMCR_EXT_PHY; 2812 2813 if (mcr_new != mcr_cur) 2814 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); 2815 } 2816 2817 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, 2818 unsigned int mode, 2819 phy_interface_t interface) 2820 { 2821 struct mt7530_priv *priv = ds->priv; 2822 2823 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 2824 } 2825 2826 static void mt753x_phylink_pcs_link_up(struct phylink_pcs *pcs, 2827 unsigned int mode, 2828 phy_interface_t interface, 2829 int speed, int duplex) 2830 { 2831 if (pcs->ops->pcs_link_up) 2832 pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex); 2833 } 2834 2835 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, 2836 unsigned int mode, 2837 phy_interface_t interface, 2838 struct phy_device *phydev, 2839 int speed, int duplex, 2840 bool tx_pause, bool rx_pause) 2841 { 2842 struct mt7530_priv *priv = ds->priv; 2843 u32 mcr; 2844 2845 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; 2846 2847 /* MT753x MAC works in 1G full duplex mode for all up-clocked 2848 * variants. 2849 */ 2850 if (interface == PHY_INTERFACE_MODE_TRGMII || 2851 (phy_interface_mode_is_8023z(interface))) { 2852 speed = SPEED_1000; 2853 duplex = DUPLEX_FULL; 2854 } 2855 2856 switch (speed) { 2857 case SPEED_1000: 2858 mcr |= PMCR_FORCE_SPEED_1000; 2859 break; 2860 case SPEED_100: 2861 mcr |= PMCR_FORCE_SPEED_100; 2862 break; 2863 } 2864 if (duplex == DUPLEX_FULL) { 2865 mcr |= PMCR_FORCE_FDX; 2866 if (tx_pause) 2867 mcr |= PMCR_TX_FC_EN; 2868 if (rx_pause) 2869 mcr |= PMCR_RX_FC_EN; 2870 } 2871 2872 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) { 2873 switch (speed) { 2874 case SPEED_1000: 2875 mcr |= PMCR_FORCE_EEE1G; 2876 break; 2877 case SPEED_100: 2878 mcr |= PMCR_FORCE_EEE100; 2879 break; 2880 } 2881 } 2882 2883 mt7530_set(priv, MT7530_PMCR_P(port), mcr); 2884 } 2885 2886 static int 2887 mt7531_cpu_port_config(struct dsa_switch *ds, int port) 2888 { 2889 struct mt7530_priv *priv = ds->priv; 2890 phy_interface_t interface; 2891 int speed; 2892 int ret; 2893 2894 switch (port) { 2895 case 5: 2896 if (mt7531_is_rgmii_port(priv, port)) 2897 interface = PHY_INTERFACE_MODE_RGMII; 2898 else 2899 interface = PHY_INTERFACE_MODE_2500BASEX; 2900 2901 priv->p5_interface = interface; 2902 break; 2903 case 6: 2904 interface = PHY_INTERFACE_MODE_2500BASEX; 2905 2906 priv->p6_interface = interface; 2907 break; 2908 default: 2909 return -EINVAL; 2910 } 2911 2912 if (interface == PHY_INTERFACE_MODE_2500BASEX) 2913 speed = SPEED_2500; 2914 else 2915 speed = SPEED_1000; 2916 2917 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); 2918 if (ret) 2919 return ret; 2920 mt7530_write(priv, MT7530_PMCR_P(port), 2921 PMCR_CPU_PORT_SETTING(priv->id)); 2922 mt753x_phylink_pcs_link_up(&priv->pcs[port].pcs, MLO_AN_FIXED, 2923 interface, speed, DUPLEX_FULL); 2924 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, 2925 speed, DUPLEX_FULL, true, true); 2926 2927 return 0; 2928 } 2929 2930 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, 2931 struct phylink_config *config) 2932 { 2933 struct mt7530_priv *priv = ds->priv; 2934 2935 /* This switch only supports full-duplex at 1Gbps */ 2936 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2937 MAC_10 | MAC_100 | MAC_1000FD; 2938 2939 /* This driver does not make use of the speed, duplex, pause or the 2940 * advertisement in its mac_config, so it is safe to mark this driver 2941 * as non-legacy. 2942 */ 2943 config->legacy_pre_march2020 = false; 2944 2945 priv->info->mac_port_get_caps(ds, port, config); 2946 } 2947 2948 static int mt753x_pcs_validate(struct phylink_pcs *pcs, 2949 unsigned long *supported, 2950 const struct phylink_link_state *state) 2951 { 2952 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */ 2953 if (state->interface == PHY_INTERFACE_MODE_TRGMII || 2954 phy_interface_mode_is_8023z(state->interface)) 2955 phylink_clear(supported, Autoneg); 2956 2957 return 0; 2958 } 2959 2960 static void mt7530_pcs_get_state(struct phylink_pcs *pcs, 2961 struct phylink_link_state *state) 2962 { 2963 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2964 int port = pcs_to_mt753x_pcs(pcs)->port; 2965 u32 pmsr; 2966 2967 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2968 2969 state->link = (pmsr & PMSR_LINK); 2970 state->an_complete = state->link; 2971 state->duplex = !!(pmsr & PMSR_DPX); 2972 2973 switch (pmsr & PMSR_SPEED_MASK) { 2974 case PMSR_SPEED_10: 2975 state->speed = SPEED_10; 2976 break; 2977 case PMSR_SPEED_100: 2978 state->speed = SPEED_100; 2979 break; 2980 case PMSR_SPEED_1000: 2981 state->speed = SPEED_1000; 2982 break; 2983 default: 2984 state->speed = SPEED_UNKNOWN; 2985 break; 2986 } 2987 2988 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 2989 if (pmsr & PMSR_RX_FC) 2990 state->pause |= MLO_PAUSE_RX; 2991 if (pmsr & PMSR_TX_FC) 2992 state->pause |= MLO_PAUSE_TX; 2993 } 2994 2995 static int 2996 mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port, 2997 struct phylink_link_state *state) 2998 { 2999 u32 status, val; 3000 u16 config_reg; 3001 3002 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 3003 state->link = !!(status & MT7531_SGMII_LINK_STATUS); 3004 state->an_complete = !!(status & MT7531_SGMII_AN_COMPLETE); 3005 if (state->interface == PHY_INTERFACE_MODE_SGMII && 3006 (status & MT7531_SGMII_AN_ENABLE)) { 3007 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port)); 3008 config_reg = val >> 16; 3009 3010 switch (config_reg & LPA_SGMII_SPD_MASK) { 3011 case LPA_SGMII_1000: 3012 state->speed = SPEED_1000; 3013 break; 3014 case LPA_SGMII_100: 3015 state->speed = SPEED_100; 3016 break; 3017 case LPA_SGMII_10: 3018 state->speed = SPEED_10; 3019 break; 3020 default: 3021 dev_err(priv->dev, "invalid sgmii PHY speed\n"); 3022 state->link = false; 3023 return -EINVAL; 3024 } 3025 3026 if (config_reg & LPA_SGMII_FULL_DUPLEX) 3027 state->duplex = DUPLEX_FULL; 3028 else 3029 state->duplex = DUPLEX_HALF; 3030 } 3031 3032 return 0; 3033 } 3034 3035 static void 3036 mt7531_sgmii_pcs_get_state_inband(struct mt7530_priv *priv, int port, 3037 struct phylink_link_state *state) 3038 { 3039 unsigned int val; 3040 3041 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 3042 state->link = !!(val & MT7531_SGMII_LINK_STATUS); 3043 if (!state->link) 3044 return; 3045 3046 state->an_complete = state->link; 3047 3048 if (state->interface == PHY_INTERFACE_MODE_2500BASEX) 3049 state->speed = SPEED_2500; 3050 else 3051 state->speed = SPEED_1000; 3052 3053 state->duplex = DUPLEX_FULL; 3054 state->pause = MLO_PAUSE_NONE; 3055 } 3056 3057 static void mt7531_pcs_get_state(struct phylink_pcs *pcs, 3058 struct phylink_link_state *state) 3059 { 3060 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 3061 int port = pcs_to_mt753x_pcs(pcs)->port; 3062 3063 if (state->interface == PHY_INTERFACE_MODE_SGMII) { 3064 mt7531_sgmii_pcs_get_state_an(priv, port, state); 3065 return; 3066 } else if ((state->interface == PHY_INTERFACE_MODE_1000BASEX) || 3067 (state->interface == PHY_INTERFACE_MODE_2500BASEX)) { 3068 mt7531_sgmii_pcs_get_state_inband(priv, port, state); 3069 return; 3070 } 3071 3072 state->link = false; 3073 } 3074 3075 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode, 3076 phy_interface_t interface, 3077 const unsigned long *advertising, 3078 bool permit_pause_to_mac) 3079 { 3080 return 0; 3081 } 3082 3083 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) 3084 { 3085 } 3086 3087 static const struct phylink_pcs_ops mt7530_pcs_ops = { 3088 .pcs_validate = mt753x_pcs_validate, 3089 .pcs_get_state = mt7530_pcs_get_state, 3090 .pcs_config = mt753x_pcs_config, 3091 .pcs_an_restart = mt7530_pcs_an_restart, 3092 }; 3093 3094 static const struct phylink_pcs_ops mt7531_pcs_ops = { 3095 .pcs_validate = mt753x_pcs_validate, 3096 .pcs_get_state = mt7531_pcs_get_state, 3097 .pcs_config = mt753x_pcs_config, 3098 .pcs_an_restart = mt7531_pcs_an_restart, 3099 .pcs_link_up = mt7531_pcs_link_up, 3100 }; 3101 3102 static int 3103 mt753x_setup(struct dsa_switch *ds) 3104 { 3105 struct mt7530_priv *priv = ds->priv; 3106 int i, ret; 3107 3108 /* Initialise the PCS devices */ 3109 for (i = 0; i < priv->ds->num_ports; i++) { 3110 priv->pcs[i].pcs.ops = priv->info->pcs_ops; 3111 priv->pcs[i].priv = priv; 3112 priv->pcs[i].port = i; 3113 if (mt753x_is_mac_port(i)) 3114 priv->pcs[i].pcs.poll = 1; 3115 } 3116 3117 ret = priv->info->sw_setup(ds); 3118 if (ret) 3119 return ret; 3120 3121 ret = mt7530_setup_irq(priv); 3122 if (ret) 3123 return ret; 3124 3125 ret = mt7530_setup_mdio(priv); 3126 if (ret && priv->irq) 3127 mt7530_free_irq_common(priv); 3128 3129 return ret; 3130 } 3131 3132 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, 3133 struct ethtool_eee *e) 3134 { 3135 struct mt7530_priv *priv = ds->priv; 3136 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); 3137 3138 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); 3139 e->tx_lpi_timer = GET_LPI_THRESH(eeecr); 3140 3141 return 0; 3142 } 3143 3144 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3145 struct ethtool_eee *e) 3146 { 3147 struct mt7530_priv *priv = ds->priv; 3148 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN; 3149 3150 if (e->tx_lpi_timer > 0xFFF) 3151 return -EINVAL; 3152 3153 set = SET_LPI_THRESH(e->tx_lpi_timer); 3154 if (!e->tx_lpi_enabled) 3155 /* Force LPI Mode without a delay */ 3156 set |= LPI_MODE_EN; 3157 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); 3158 3159 return 0; 3160 } 3161 3162 static const struct dsa_switch_ops mt7530_switch_ops = { 3163 .get_tag_protocol = mtk_get_tag_protocol, 3164 .setup = mt753x_setup, 3165 .get_strings = mt7530_get_strings, 3166 .get_ethtool_stats = mt7530_get_ethtool_stats, 3167 .get_sset_count = mt7530_get_sset_count, 3168 .set_ageing_time = mt7530_set_ageing_time, 3169 .port_enable = mt7530_port_enable, 3170 .port_disable = mt7530_port_disable, 3171 .port_change_mtu = mt7530_port_change_mtu, 3172 .port_max_mtu = mt7530_port_max_mtu, 3173 .port_stp_state_set = mt7530_stp_state_set, 3174 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3175 .port_bridge_flags = mt7530_port_bridge_flags, 3176 .port_bridge_join = mt7530_port_bridge_join, 3177 .port_bridge_leave = mt7530_port_bridge_leave, 3178 .port_fdb_add = mt7530_port_fdb_add, 3179 .port_fdb_del = mt7530_port_fdb_del, 3180 .port_fdb_dump = mt7530_port_fdb_dump, 3181 .port_mdb_add = mt7530_port_mdb_add, 3182 .port_mdb_del = mt7530_port_mdb_del, 3183 .port_vlan_filtering = mt7530_port_vlan_filtering, 3184 .port_vlan_add = mt7530_port_vlan_add, 3185 .port_vlan_del = mt7530_port_vlan_del, 3186 .port_mirror_add = mt753x_port_mirror_add, 3187 .port_mirror_del = mt753x_port_mirror_del, 3188 .phylink_get_caps = mt753x_phylink_get_caps, 3189 .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs, 3190 .phylink_mac_config = mt753x_phylink_mac_config, 3191 .phylink_mac_link_down = mt753x_phylink_mac_link_down, 3192 .phylink_mac_link_up = mt753x_phylink_mac_link_up, 3193 .get_mac_eee = mt753x_get_mac_eee, 3194 .set_mac_eee = mt753x_set_mac_eee, 3195 }; 3196 3197 static const struct mt753x_info mt753x_table[] = { 3198 [ID_MT7621] = { 3199 .id = ID_MT7621, 3200 .pcs_ops = &mt7530_pcs_ops, 3201 .sw_setup = mt7530_setup, 3202 .phy_read_c22 = mt7530_phy_read_c22, 3203 .phy_write_c22 = mt7530_phy_write_c22, 3204 .phy_read_c45 = mt7530_phy_read_c45, 3205 .phy_write_c45 = mt7530_phy_write_c45, 3206 .pad_setup = mt7530_pad_clk_setup, 3207 .mac_port_get_caps = mt7530_mac_port_get_caps, 3208 .mac_port_config = mt7530_mac_config, 3209 }, 3210 [ID_MT7530] = { 3211 .id = ID_MT7530, 3212 .pcs_ops = &mt7530_pcs_ops, 3213 .sw_setup = mt7530_setup, 3214 .phy_read_c22 = mt7530_phy_read_c22, 3215 .phy_write_c22 = mt7530_phy_write_c22, 3216 .phy_read_c45 = mt7530_phy_read_c45, 3217 .phy_write_c45 = mt7530_phy_write_c45, 3218 .pad_setup = mt7530_pad_clk_setup, 3219 .mac_port_get_caps = mt7530_mac_port_get_caps, 3220 .mac_port_config = mt7530_mac_config, 3221 }, 3222 [ID_MT7531] = { 3223 .id = ID_MT7531, 3224 .pcs_ops = &mt7531_pcs_ops, 3225 .sw_setup = mt7531_setup, 3226 .phy_read_c22 = mt7531_ind_c22_phy_read, 3227 .phy_write_c22 = mt7531_ind_c22_phy_write, 3228 .phy_read_c45 = mt7531_ind_c45_phy_read, 3229 .phy_write_c45 = mt7531_ind_c45_phy_write, 3230 .pad_setup = mt7531_pad_setup, 3231 .cpu_port_config = mt7531_cpu_port_config, 3232 .mac_port_get_caps = mt7531_mac_port_get_caps, 3233 .mac_port_config = mt7531_mac_config, 3234 }, 3235 }; 3236 3237 static const struct of_device_id mt7530_of_match[] = { 3238 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], }, 3239 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], }, 3240 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], }, 3241 { /* sentinel */ }, 3242 }; 3243 MODULE_DEVICE_TABLE(of, mt7530_of_match); 3244 3245 static int 3246 mt7530_probe(struct mdio_device *mdiodev) 3247 { 3248 struct mt7530_priv *priv; 3249 struct device_node *dn; 3250 3251 dn = mdiodev->dev.of_node; 3252 3253 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 3254 if (!priv) 3255 return -ENOMEM; 3256 3257 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); 3258 if (!priv->ds) 3259 return -ENOMEM; 3260 3261 priv->ds->dev = &mdiodev->dev; 3262 priv->ds->num_ports = MT7530_NUM_PORTS; 3263 3264 /* Use medatek,mcm property to distinguish hardware type that would 3265 * casues a little bit differences on power-on sequence. 3266 */ 3267 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); 3268 if (priv->mcm) { 3269 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); 3270 3271 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); 3272 if (IS_ERR(priv->rstc)) { 3273 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 3274 return PTR_ERR(priv->rstc); 3275 } 3276 } 3277 3278 /* Get the hardware identifier from the devicetree node. 3279 * We will need it for some of the clock and regulator setup. 3280 */ 3281 priv->info = of_device_get_match_data(&mdiodev->dev); 3282 if (!priv->info) 3283 return -EINVAL; 3284 3285 /* Sanity check if these required device operations are filled 3286 * properly. 3287 */ 3288 if (!priv->info->sw_setup || !priv->info->pad_setup || 3289 !priv->info->phy_read_c22 || !priv->info->phy_write_c22 || 3290 !priv->info->mac_port_get_caps || 3291 !priv->info->mac_port_config) 3292 return -EINVAL; 3293 3294 priv->id = priv->info->id; 3295 3296 if (priv->id == ID_MT7530) { 3297 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); 3298 if (IS_ERR(priv->core_pwr)) 3299 return PTR_ERR(priv->core_pwr); 3300 3301 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); 3302 if (IS_ERR(priv->io_pwr)) 3303 return PTR_ERR(priv->io_pwr); 3304 } 3305 3306 /* Not MCM that indicates switch works as the remote standalone 3307 * integrated circuit so the GPIO pin would be used to complete 3308 * the reset, otherwise memory-mapped register accessing used 3309 * through syscon provides in the case of MCM. 3310 */ 3311 if (!priv->mcm) { 3312 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", 3313 GPIOD_OUT_LOW); 3314 if (IS_ERR(priv->reset)) { 3315 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 3316 return PTR_ERR(priv->reset); 3317 } 3318 } 3319 3320 priv->bus = mdiodev->bus; 3321 priv->dev = &mdiodev->dev; 3322 priv->ds->priv = priv; 3323 priv->ds->ops = &mt7530_switch_ops; 3324 mutex_init(&priv->reg_mutex); 3325 dev_set_drvdata(&mdiodev->dev, priv); 3326 3327 return dsa_register_switch(priv->ds); 3328 } 3329 3330 static void 3331 mt7530_remove(struct mdio_device *mdiodev) 3332 { 3333 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 3334 int ret = 0; 3335 3336 if (!priv) 3337 return; 3338 3339 ret = regulator_disable(priv->core_pwr); 3340 if (ret < 0) 3341 dev_err(priv->dev, 3342 "Failed to disable core power: %d\n", ret); 3343 3344 ret = regulator_disable(priv->io_pwr); 3345 if (ret < 0) 3346 dev_err(priv->dev, "Failed to disable io pwr: %d\n", 3347 ret); 3348 3349 if (priv->irq) 3350 mt7530_free_irq(priv); 3351 3352 dsa_unregister_switch(priv->ds); 3353 mutex_destroy(&priv->reg_mutex); 3354 } 3355 3356 static void mt7530_shutdown(struct mdio_device *mdiodev) 3357 { 3358 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 3359 3360 if (!priv) 3361 return; 3362 3363 dsa_switch_shutdown(priv->ds); 3364 3365 dev_set_drvdata(&mdiodev->dev, NULL); 3366 } 3367 3368 static struct mdio_driver mt7530_mdio_driver = { 3369 .probe = mt7530_probe, 3370 .remove = mt7530_remove, 3371 .shutdown = mt7530_shutdown, 3372 .mdiodrv.driver = { 3373 .name = "mt7530", 3374 .of_match_table = mt7530_of_match, 3375 }, 3376 }; 3377 3378 mdio_module_driver(mt7530_mdio_driver); 3379 3380 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3381 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3382 MODULE_LICENSE("GPL"); 3383