1 /* 2 * Mediatek MT7530 DSA Switch driver 3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 #include <linux/etherdevice.h> 15 #include <linux/if_bridge.h> 16 #include <linux/iopoll.h> 17 #include <linux/mdio.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/module.h> 20 #include <linux/netdevice.h> 21 #include <linux/of_gpio.h> 22 #include <linux/of_mdio.h> 23 #include <linux/of_net.h> 24 #include <linux/of_platform.h> 25 #include <linux/phy.h> 26 #include <linux/regmap.h> 27 #include <linux/regulator/consumer.h> 28 #include <linux/reset.h> 29 #include <linux/gpio/consumer.h> 30 #include <net/dsa.h> 31 32 #include "mt7530.h" 33 34 /* String, offset, and register size in bytes if different from 4 bytes */ 35 static const struct mt7530_mib_desc mt7530_mib[] = { 36 MIB_DESC(1, 0x00, "TxDrop"), 37 MIB_DESC(1, 0x04, "TxCrcErr"), 38 MIB_DESC(1, 0x08, "TxUnicast"), 39 MIB_DESC(1, 0x0c, "TxMulticast"), 40 MIB_DESC(1, 0x10, "TxBroadcast"), 41 MIB_DESC(1, 0x14, "TxCollision"), 42 MIB_DESC(1, 0x18, "TxSingleCollision"), 43 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 44 MIB_DESC(1, 0x20, "TxDeferred"), 45 MIB_DESC(1, 0x24, "TxLateCollision"), 46 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 47 MIB_DESC(1, 0x2c, "TxPause"), 48 MIB_DESC(1, 0x30, "TxPktSz64"), 49 MIB_DESC(1, 0x34, "TxPktSz65To127"), 50 MIB_DESC(1, 0x38, "TxPktSz128To255"), 51 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 52 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 53 MIB_DESC(1, 0x44, "Tx1024ToMax"), 54 MIB_DESC(2, 0x48, "TxBytes"), 55 MIB_DESC(1, 0x60, "RxDrop"), 56 MIB_DESC(1, 0x64, "RxFiltering"), 57 MIB_DESC(1, 0x6c, "RxMulticast"), 58 MIB_DESC(1, 0x70, "RxBroadcast"), 59 MIB_DESC(1, 0x74, "RxAlignErr"), 60 MIB_DESC(1, 0x78, "RxCrcErr"), 61 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 62 MIB_DESC(1, 0x80, "RxFragErr"), 63 MIB_DESC(1, 0x84, "RxOverSzErr"), 64 MIB_DESC(1, 0x88, "RxJabberErr"), 65 MIB_DESC(1, 0x8c, "RxPause"), 66 MIB_DESC(1, 0x90, "RxPktSz64"), 67 MIB_DESC(1, 0x94, "RxPktSz65To127"), 68 MIB_DESC(1, 0x98, "RxPktSz128To255"), 69 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 70 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 71 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 72 MIB_DESC(2, 0xa8, "RxBytes"), 73 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 74 MIB_DESC(1, 0xb4, "RxIngressDrop"), 75 MIB_DESC(1, 0xb8, "RxArlDrop"), 76 }; 77 78 static int 79 mt7623_trgmii_write(struct mt7530_priv *priv, u32 reg, u32 val) 80 { 81 int ret; 82 83 ret = regmap_write(priv->ethernet, TRGMII_BASE(reg), val); 84 if (ret < 0) 85 dev_err(priv->dev, 86 "failed to priv write register\n"); 87 return ret; 88 } 89 90 static u32 91 mt7623_trgmii_read(struct mt7530_priv *priv, u32 reg) 92 { 93 int ret; 94 u32 val; 95 96 ret = regmap_read(priv->ethernet, TRGMII_BASE(reg), &val); 97 if (ret < 0) { 98 dev_err(priv->dev, 99 "failed to priv read register\n"); 100 return ret; 101 } 102 103 return val; 104 } 105 106 static void 107 mt7623_trgmii_rmw(struct mt7530_priv *priv, u32 reg, 108 u32 mask, u32 set) 109 { 110 u32 val; 111 112 val = mt7623_trgmii_read(priv, reg); 113 val &= ~mask; 114 val |= set; 115 mt7623_trgmii_write(priv, reg, val); 116 } 117 118 static void 119 mt7623_trgmii_set(struct mt7530_priv *priv, u32 reg, u32 val) 120 { 121 mt7623_trgmii_rmw(priv, reg, 0, val); 122 } 123 124 static void 125 mt7623_trgmii_clear(struct mt7530_priv *priv, u32 reg, u32 val) 126 { 127 mt7623_trgmii_rmw(priv, reg, val, 0); 128 } 129 130 static int 131 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 132 { 133 struct mii_bus *bus = priv->bus; 134 int value, ret; 135 136 /* Write the desired MMD Devad */ 137 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 138 if (ret < 0) 139 goto err; 140 141 /* Write the desired MMD register address */ 142 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 143 if (ret < 0) 144 goto err; 145 146 /* Select the Function : DATA with no post increment */ 147 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 148 if (ret < 0) 149 goto err; 150 151 /* Read the content of the MMD's selected register */ 152 value = bus->read(bus, 0, MII_MMD_DATA); 153 154 return value; 155 err: 156 dev_err(&bus->dev, "failed to read mmd register\n"); 157 158 return ret; 159 } 160 161 static int 162 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 163 int devad, u32 data) 164 { 165 struct mii_bus *bus = priv->bus; 166 int ret; 167 168 /* Write the desired MMD Devad */ 169 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 170 if (ret < 0) 171 goto err; 172 173 /* Write the desired MMD register address */ 174 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 175 if (ret < 0) 176 goto err; 177 178 /* Select the Function : DATA with no post increment */ 179 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 180 if (ret < 0) 181 goto err; 182 183 /* Write the data into MMD's selected register */ 184 ret = bus->write(bus, 0, MII_MMD_DATA, data); 185 err: 186 if (ret < 0) 187 dev_err(&bus->dev, 188 "failed to write mmd register\n"); 189 return ret; 190 } 191 192 static void 193 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 194 { 195 struct mii_bus *bus = priv->bus; 196 197 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 198 199 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 200 201 mutex_unlock(&bus->mdio_lock); 202 } 203 204 static void 205 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 206 { 207 struct mii_bus *bus = priv->bus; 208 u32 val; 209 210 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 211 212 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 213 val &= ~mask; 214 val |= set; 215 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 216 217 mutex_unlock(&bus->mdio_lock); 218 } 219 220 static void 221 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 222 { 223 core_rmw(priv, reg, 0, val); 224 } 225 226 static void 227 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 228 { 229 core_rmw(priv, reg, val, 0); 230 } 231 232 static int 233 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 234 { 235 struct mii_bus *bus = priv->bus; 236 u16 page, r, lo, hi; 237 int ret; 238 239 page = (reg >> 6) & 0x3ff; 240 r = (reg >> 2) & 0xf; 241 lo = val & 0xffff; 242 hi = val >> 16; 243 244 /* MT7530 uses 31 as the pseudo port */ 245 ret = bus->write(bus, 0x1f, 0x1f, page); 246 if (ret < 0) 247 goto err; 248 249 ret = bus->write(bus, 0x1f, r, lo); 250 if (ret < 0) 251 goto err; 252 253 ret = bus->write(bus, 0x1f, 0x10, hi); 254 err: 255 if (ret < 0) 256 dev_err(&bus->dev, 257 "failed to write mt7530 register\n"); 258 return ret; 259 } 260 261 static u32 262 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 263 { 264 struct mii_bus *bus = priv->bus; 265 u16 page, r, lo, hi; 266 int ret; 267 268 page = (reg >> 6) & 0x3ff; 269 r = (reg >> 2) & 0xf; 270 271 /* MT7530 uses 31 as the pseudo port */ 272 ret = bus->write(bus, 0x1f, 0x1f, page); 273 if (ret < 0) { 274 dev_err(&bus->dev, 275 "failed to read mt7530 register\n"); 276 return ret; 277 } 278 279 lo = bus->read(bus, 0x1f, r); 280 hi = bus->read(bus, 0x1f, 0x10); 281 282 return (hi << 16) | (lo & 0xffff); 283 } 284 285 static void 286 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 287 { 288 struct mii_bus *bus = priv->bus; 289 290 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 291 292 mt7530_mii_write(priv, reg, val); 293 294 mutex_unlock(&bus->mdio_lock); 295 } 296 297 static u32 298 _mt7530_read(struct mt7530_dummy_poll *p) 299 { 300 struct mii_bus *bus = p->priv->bus; 301 u32 val; 302 303 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 304 305 val = mt7530_mii_read(p->priv, p->reg); 306 307 mutex_unlock(&bus->mdio_lock); 308 309 return val; 310 } 311 312 static u32 313 mt7530_read(struct mt7530_priv *priv, u32 reg) 314 { 315 struct mt7530_dummy_poll p; 316 317 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 318 return _mt7530_read(&p); 319 } 320 321 static void 322 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 323 u32 mask, u32 set) 324 { 325 struct mii_bus *bus = priv->bus; 326 u32 val; 327 328 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 329 330 val = mt7530_mii_read(priv, reg); 331 val &= ~mask; 332 val |= set; 333 mt7530_mii_write(priv, reg, val); 334 335 mutex_unlock(&bus->mdio_lock); 336 } 337 338 static void 339 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 340 { 341 mt7530_rmw(priv, reg, 0, val); 342 } 343 344 static void 345 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 346 { 347 mt7530_rmw(priv, reg, val, 0); 348 } 349 350 static int 351 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 352 { 353 u32 val; 354 int ret; 355 struct mt7530_dummy_poll p; 356 357 /* Set the command operating upon the MAC address entries */ 358 val = ATC_BUSY | ATC_MAT(0) | cmd; 359 mt7530_write(priv, MT7530_ATC, val); 360 361 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 362 ret = readx_poll_timeout(_mt7530_read, &p, val, 363 !(val & ATC_BUSY), 20, 20000); 364 if (ret < 0) { 365 dev_err(priv->dev, "reset timeout\n"); 366 return ret; 367 } 368 369 /* Additional sanity for read command if the specified 370 * entry is invalid 371 */ 372 val = mt7530_read(priv, MT7530_ATC); 373 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 374 return -EINVAL; 375 376 if (rsp) 377 *rsp = val; 378 379 return 0; 380 } 381 382 static void 383 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 384 { 385 u32 reg[3]; 386 int i; 387 388 /* Read from ARL table into an array */ 389 for (i = 0; i < 3; i++) { 390 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 391 392 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 393 __func__, __LINE__, i, reg[i]); 394 } 395 396 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 397 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 398 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 399 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 400 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 401 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 402 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 403 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 404 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 405 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 406 } 407 408 static void 409 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 410 u8 port_mask, const u8 *mac, 411 u8 aging, u8 type) 412 { 413 u32 reg[3] = { 0 }; 414 int i; 415 416 reg[1] |= vid & CVID_MASK; 417 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 418 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 419 /* STATIC_ENT indicate that entry is static wouldn't 420 * be aged out and STATIC_EMP specified as erasing an 421 * entry 422 */ 423 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 424 reg[1] |= mac[5] << MAC_BYTE_5; 425 reg[1] |= mac[4] << MAC_BYTE_4; 426 reg[0] |= mac[3] << MAC_BYTE_3; 427 reg[0] |= mac[2] << MAC_BYTE_2; 428 reg[0] |= mac[1] << MAC_BYTE_1; 429 reg[0] |= mac[0] << MAC_BYTE_0; 430 431 /* Write array into the ARL table */ 432 for (i = 0; i < 3; i++) 433 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 434 } 435 436 static int 437 mt7530_pad_clk_setup(struct dsa_switch *ds, int mode) 438 { 439 struct mt7530_priv *priv = ds->priv; 440 u32 ncpo1, ssc_delta, trgint, i; 441 442 switch (mode) { 443 case PHY_INTERFACE_MODE_RGMII: 444 trgint = 0; 445 ncpo1 = 0x0c80; 446 ssc_delta = 0x87; 447 break; 448 case PHY_INTERFACE_MODE_TRGMII: 449 trgint = 1; 450 ncpo1 = 0x1400; 451 ssc_delta = 0x57; 452 break; 453 default: 454 dev_err(priv->dev, "xMII mode %d not supported\n", mode); 455 return -EINVAL; 456 } 457 458 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 459 P6_INTF_MODE(trgint)); 460 461 /* Lower Tx Driving for TRGMII path */ 462 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) 463 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 464 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 465 466 /* Setup core clock for MT7530 */ 467 if (!trgint) { 468 /* Disable MT7530 core clock */ 469 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 470 471 /* Disable PLL, since phy_device has not yet been created 472 * provided for phy_[read,write]_mmd_indirect is called, we 473 * provide our own core_write_mmd_indirect to complete this 474 * function. 475 */ 476 core_write_mmd_indirect(priv, 477 CORE_GSWPLL_GRP1, 478 MDIO_MMD_VEND2, 479 0); 480 481 /* Set core clock into 500Mhz */ 482 core_write(priv, CORE_GSWPLL_GRP2, 483 RG_GSWPLL_POSDIV_500M(1) | 484 RG_GSWPLL_FBKDIV_500M(25)); 485 486 /* Enable PLL */ 487 core_write(priv, CORE_GSWPLL_GRP1, 488 RG_GSWPLL_EN_PRE | 489 RG_GSWPLL_POSDIV_200M(2) | 490 RG_GSWPLL_FBKDIV_200M(32)); 491 492 /* Enable MT7530 core clock */ 493 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 494 } 495 496 /* Setup the MT7530 TRGMII Tx Clock */ 497 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 498 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 499 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 500 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 501 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 502 core_write(priv, CORE_PLL_GROUP4, 503 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 504 RG_SYSPLL_BIAS_LPF_EN); 505 core_write(priv, CORE_PLL_GROUP2, 506 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 507 RG_SYSPLL_POSDIV(1)); 508 core_write(priv, CORE_PLL_GROUP7, 509 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 510 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 511 core_set(priv, CORE_TRGMII_GSW_CLK_CG, 512 REG_GSWCK_EN | REG_TRGMIICK_EN); 513 514 if (!trgint) 515 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 516 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 517 RD_TAP_MASK, RD_TAP(16)); 518 else 519 mt7623_trgmii_set(priv, GSW_INTF_MODE, INTF_MODE_TRGMII); 520 521 return 0; 522 } 523 524 static int 525 mt7623_pad_clk_setup(struct dsa_switch *ds) 526 { 527 struct mt7530_priv *priv = ds->priv; 528 int i; 529 530 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 531 mt7623_trgmii_write(priv, GSW_TRGMII_TD_ODT(i), 532 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 533 534 mt7623_trgmii_set(priv, GSW_TRGMII_RCK_CTRL, RX_RST | RXC_DQSISEL); 535 mt7623_trgmii_clear(priv, GSW_TRGMII_RCK_CTRL, RX_RST); 536 537 return 0; 538 } 539 540 static void 541 mt7530_mib_reset(struct dsa_switch *ds) 542 { 543 struct mt7530_priv *priv = ds->priv; 544 545 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 546 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 547 } 548 549 static void 550 mt7530_port_set_status(struct mt7530_priv *priv, int port, int enable) 551 { 552 u32 mask = PMCR_TX_EN | PMCR_RX_EN; 553 554 if (enable) 555 mt7530_set(priv, MT7530_PMCR_P(port), mask); 556 else 557 mt7530_clear(priv, MT7530_PMCR_P(port), mask); 558 } 559 560 static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum) 561 { 562 struct mt7530_priv *priv = ds->priv; 563 564 return mdiobus_read_nested(priv->bus, port, regnum); 565 } 566 567 static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum, 568 u16 val) 569 { 570 struct mt7530_priv *priv = ds->priv; 571 572 return mdiobus_write_nested(priv->bus, port, regnum, val); 573 } 574 575 static void 576 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 577 uint8_t *data) 578 { 579 int i; 580 581 if (stringset != ETH_SS_STATS) 582 return; 583 584 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 585 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 586 ETH_GSTRING_LEN); 587 } 588 589 static void 590 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 591 uint64_t *data) 592 { 593 struct mt7530_priv *priv = ds->priv; 594 const struct mt7530_mib_desc *mib; 595 u32 reg, i; 596 u64 hi; 597 598 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 599 mib = &mt7530_mib[i]; 600 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 601 602 data[i] = mt7530_read(priv, reg); 603 if (mib->size == 2) { 604 hi = mt7530_read(priv, reg + 4); 605 data[i] |= hi << 32; 606 } 607 } 608 } 609 610 static int 611 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 612 { 613 if (sset != ETH_SS_STATS) 614 return 0; 615 616 return ARRAY_SIZE(mt7530_mib); 617 } 618 619 static void mt7530_adjust_link(struct dsa_switch *ds, int port, 620 struct phy_device *phydev) 621 { 622 struct mt7530_priv *priv = ds->priv; 623 624 if (phy_is_pseudo_fixed_link(phydev)) { 625 dev_dbg(priv->dev, "phy-mode for master device = %x\n", 626 phydev->interface); 627 628 /* Setup TX circuit incluing relevant PAD and driving */ 629 mt7530_pad_clk_setup(ds, phydev->interface); 630 631 /* Setup RX circuit, relevant PAD and driving on the host 632 * which must be placed after the setup on the device side is 633 * all finished. 634 */ 635 mt7623_pad_clk_setup(ds); 636 } else { 637 u16 lcl_adv = 0, rmt_adv = 0; 638 u8 flowctrl; 639 u32 mcr = PMCR_USERP_LINK | PMCR_FORCE_MODE; 640 641 switch (phydev->speed) { 642 case SPEED_1000: 643 mcr |= PMCR_FORCE_SPEED_1000; 644 break; 645 case SPEED_100: 646 mcr |= PMCR_FORCE_SPEED_100; 647 break; 648 }; 649 650 if (phydev->link) 651 mcr |= PMCR_FORCE_LNK; 652 653 if (phydev->duplex) { 654 mcr |= PMCR_FORCE_FDX; 655 656 if (phydev->pause) 657 rmt_adv = LPA_PAUSE_CAP; 658 if (phydev->asym_pause) 659 rmt_adv |= LPA_PAUSE_ASYM; 660 661 lcl_adv = ethtool_adv_to_lcl_adv_t(phydev->advertising); 662 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 663 664 if (flowctrl & FLOW_CTRL_TX) 665 mcr |= PMCR_TX_FC_EN; 666 if (flowctrl & FLOW_CTRL_RX) 667 mcr |= PMCR_RX_FC_EN; 668 } 669 mt7530_write(priv, MT7530_PMCR_P(port), mcr); 670 } 671 } 672 673 static int 674 mt7530_cpu_port_enable(struct mt7530_priv *priv, 675 int port) 676 { 677 /* Enable Mediatek header mode on the cpu port */ 678 mt7530_write(priv, MT7530_PVC_P(port), 679 PORT_SPEC_TAG); 680 681 /* Setup the MAC by default for the cpu port */ 682 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_CPUP_LINK); 683 684 /* Disable auto learning on the cpu port */ 685 mt7530_set(priv, MT7530_PSC_P(port), SA_DIS); 686 687 /* Unknown unicast frame fordwarding to the cpu port */ 688 mt7530_set(priv, MT7530_MFC, UNU_FFP(BIT(port))); 689 690 /* CPU port gets connected to all user ports of 691 * the switch 692 */ 693 mt7530_write(priv, MT7530_PCR_P(port), 694 PCR_MATRIX(dsa_user_ports(priv->ds))); 695 696 return 0; 697 } 698 699 static int 700 mt7530_port_enable(struct dsa_switch *ds, int port, 701 struct phy_device *phy) 702 { 703 struct mt7530_priv *priv = ds->priv; 704 705 mutex_lock(&priv->reg_mutex); 706 707 /* Setup the MAC for the user port */ 708 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_USERP_LINK); 709 710 /* Allow the user port gets connected to the cpu port and also 711 * restore the port matrix if the port is the member of a certain 712 * bridge. 713 */ 714 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); 715 priv->ports[port].enable = true; 716 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 717 priv->ports[port].pm); 718 mt7530_port_set_status(priv, port, 1); 719 720 mutex_unlock(&priv->reg_mutex); 721 722 return 0; 723 } 724 725 static void 726 mt7530_port_disable(struct dsa_switch *ds, int port, 727 struct phy_device *phy) 728 { 729 struct mt7530_priv *priv = ds->priv; 730 731 mutex_lock(&priv->reg_mutex); 732 733 /* Clear up all port matrix which could be restored in the next 734 * enablement for the port. 735 */ 736 priv->ports[port].enable = false; 737 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 738 PCR_MATRIX_CLR); 739 mt7530_port_set_status(priv, port, 0); 740 741 mutex_unlock(&priv->reg_mutex); 742 } 743 744 static void 745 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 746 { 747 struct mt7530_priv *priv = ds->priv; 748 u32 stp_state; 749 750 switch (state) { 751 case BR_STATE_DISABLED: 752 stp_state = MT7530_STP_DISABLED; 753 break; 754 case BR_STATE_BLOCKING: 755 stp_state = MT7530_STP_BLOCKING; 756 break; 757 case BR_STATE_LISTENING: 758 stp_state = MT7530_STP_LISTENING; 759 break; 760 case BR_STATE_LEARNING: 761 stp_state = MT7530_STP_LEARNING; 762 break; 763 case BR_STATE_FORWARDING: 764 default: 765 stp_state = MT7530_STP_FORWARDING; 766 break; 767 } 768 769 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state); 770 } 771 772 static int 773 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 774 struct net_device *bridge) 775 { 776 struct mt7530_priv *priv = ds->priv; 777 u32 port_bitmap = BIT(MT7530_CPU_PORT); 778 int i; 779 780 mutex_lock(&priv->reg_mutex); 781 782 for (i = 0; i < MT7530_NUM_PORTS; i++) { 783 /* Add this port to the port matrix of the other ports in the 784 * same bridge. If the port is disabled, port matrix is kept 785 * and not being setup until the port becomes enabled. 786 */ 787 if (dsa_is_user_port(ds, i) && i != port) { 788 if (dsa_to_port(ds, i)->bridge_dev != bridge) 789 continue; 790 if (priv->ports[i].enable) 791 mt7530_set(priv, MT7530_PCR_P(i), 792 PCR_MATRIX(BIT(port))); 793 priv->ports[i].pm |= PCR_MATRIX(BIT(port)); 794 795 port_bitmap |= BIT(i); 796 } 797 } 798 799 /* Add the all other ports to this port matrix. */ 800 if (priv->ports[port].enable) 801 mt7530_rmw(priv, MT7530_PCR_P(port), 802 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 803 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 804 805 mutex_unlock(&priv->reg_mutex); 806 807 return 0; 808 } 809 810 static void 811 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 812 { 813 struct mt7530_priv *priv = ds->priv; 814 bool all_user_ports_removed = true; 815 int i; 816 817 /* When a port is removed from the bridge, the port would be set up 818 * back to the default as is at initial boot which is a VLAN-unaware 819 * port. 820 */ 821 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 822 MT7530_PORT_MATRIX_MODE); 823 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 824 VLAN_ATTR(MT7530_VLAN_TRANSPARENT)); 825 826 priv->ports[port].vlan_filtering = false; 827 828 for (i = 0; i < MT7530_NUM_PORTS; i++) { 829 if (dsa_is_user_port(ds, i) && 830 priv->ports[i].vlan_filtering) { 831 all_user_ports_removed = false; 832 break; 833 } 834 } 835 836 /* CPU port also does the same thing until all user ports belonging to 837 * the CPU port get out of VLAN filtering mode. 838 */ 839 if (all_user_ports_removed) { 840 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT), 841 PCR_MATRIX(dsa_user_ports(priv->ds))); 842 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), 843 PORT_SPEC_TAG); 844 } 845 } 846 847 static void 848 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 849 { 850 struct mt7530_priv *priv = ds->priv; 851 852 /* The real fabric path would be decided on the membership in the 853 * entry of VLAN table. PCR_MATRIX set up here with ALL_MEMBERS 854 * means potential VLAN can be consisting of certain subset of all 855 * ports. 856 */ 857 mt7530_rmw(priv, MT7530_PCR_P(port), 858 PCR_MATRIX_MASK, PCR_MATRIX(MT7530_ALL_MEMBERS)); 859 860 /* Trapped into security mode allows packet forwarding through VLAN 861 * table lookup. 862 */ 863 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 864 MT7530_PORT_SECURITY_MODE); 865 866 /* Set the port as a user port which is to be able to recognize VID 867 * from incoming packets before fetching entry within the VLAN table. 868 */ 869 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 870 VLAN_ATTR(MT7530_VLAN_USER)); 871 } 872 873 static void 874 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 875 struct net_device *bridge) 876 { 877 struct mt7530_priv *priv = ds->priv; 878 int i; 879 880 mutex_lock(&priv->reg_mutex); 881 882 for (i = 0; i < MT7530_NUM_PORTS; i++) { 883 /* Remove this port from the port matrix of the other ports 884 * in the same bridge. If the port is disabled, port matrix 885 * is kept and not being setup until the port becomes enabled. 886 * And the other port's port matrix cannot be broken when the 887 * other port is still a VLAN-aware port. 888 */ 889 if (!priv->ports[i].vlan_filtering && 890 dsa_is_user_port(ds, i) && i != port) { 891 if (dsa_to_port(ds, i)->bridge_dev != bridge) 892 continue; 893 if (priv->ports[i].enable) 894 mt7530_clear(priv, MT7530_PCR_P(i), 895 PCR_MATRIX(BIT(port))); 896 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port)); 897 } 898 } 899 900 /* Set the cpu port to be the only one in the port matrix of 901 * this port. 902 */ 903 if (priv->ports[port].enable) 904 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 905 PCR_MATRIX(BIT(MT7530_CPU_PORT))); 906 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); 907 908 mt7530_port_set_vlan_unaware(ds, port); 909 910 mutex_unlock(&priv->reg_mutex); 911 } 912 913 static int 914 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 915 const unsigned char *addr, u16 vid) 916 { 917 struct mt7530_priv *priv = ds->priv; 918 int ret; 919 u8 port_mask = BIT(port); 920 921 mutex_lock(&priv->reg_mutex); 922 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 923 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 924 mutex_unlock(&priv->reg_mutex); 925 926 return ret; 927 } 928 929 static int 930 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 931 const unsigned char *addr, u16 vid) 932 { 933 struct mt7530_priv *priv = ds->priv; 934 int ret; 935 u8 port_mask = BIT(port); 936 937 mutex_lock(&priv->reg_mutex); 938 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 939 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 940 mutex_unlock(&priv->reg_mutex); 941 942 return ret; 943 } 944 945 static int 946 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 947 dsa_fdb_dump_cb_t *cb, void *data) 948 { 949 struct mt7530_priv *priv = ds->priv; 950 struct mt7530_fdb _fdb = { 0 }; 951 int cnt = MT7530_NUM_FDB_RECORDS; 952 int ret = 0; 953 u32 rsp = 0; 954 955 mutex_lock(&priv->reg_mutex); 956 957 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 958 if (ret < 0) 959 goto err; 960 961 do { 962 if (rsp & ATC_SRCH_HIT) { 963 mt7530_fdb_read(priv, &_fdb); 964 if (_fdb.port_mask & BIT(port)) { 965 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 966 data); 967 if (ret < 0) 968 break; 969 } 970 } 971 } while (--cnt && 972 !(rsp & ATC_SRCH_END) && 973 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 974 err: 975 mutex_unlock(&priv->reg_mutex); 976 977 return 0; 978 } 979 980 static int 981 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 982 { 983 struct mt7530_dummy_poll p; 984 u32 val; 985 int ret; 986 987 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 988 mt7530_write(priv, MT7530_VTCR, val); 989 990 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 991 ret = readx_poll_timeout(_mt7530_read, &p, val, 992 !(val & VTCR_BUSY), 20, 20000); 993 if (ret < 0) { 994 dev_err(priv->dev, "poll timeout\n"); 995 return ret; 996 } 997 998 val = mt7530_read(priv, MT7530_VTCR); 999 if (val & VTCR_INVALID) { 1000 dev_err(priv->dev, "read VTCR invalid\n"); 1001 return -EINVAL; 1002 } 1003 1004 return 0; 1005 } 1006 1007 static int 1008 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, 1009 bool vlan_filtering) 1010 { 1011 struct mt7530_priv *priv = ds->priv; 1012 1013 priv->ports[port].vlan_filtering = vlan_filtering; 1014 1015 if (vlan_filtering) { 1016 /* The port is being kept as VLAN-unaware port when bridge is 1017 * set up with vlan_filtering not being set, Otherwise, the 1018 * port and the corresponding CPU port is required the setup 1019 * for becoming a VLAN-aware port. 1020 */ 1021 mt7530_port_set_vlan_aware(ds, port); 1022 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT); 1023 } 1024 1025 return 0; 1026 } 1027 1028 static int 1029 mt7530_port_vlan_prepare(struct dsa_switch *ds, int port, 1030 const struct switchdev_obj_port_vlan *vlan) 1031 { 1032 /* nothing needed */ 1033 1034 return 0; 1035 } 1036 1037 static void 1038 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1039 struct mt7530_hw_vlan_entry *entry) 1040 { 1041 u8 new_members; 1042 u32 val; 1043 1044 new_members = entry->old_members | BIT(entry->port) | 1045 BIT(MT7530_CPU_PORT); 1046 1047 /* Validate the entry with independent learning, create egress tag per 1048 * VLAN and joining the port as one of the port members. 1049 */ 1050 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID; 1051 mt7530_write(priv, MT7530_VAWD1, val); 1052 1053 /* Decide whether adding tag or not for those outgoing packets from the 1054 * port inside the VLAN. 1055 */ 1056 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG : 1057 MT7530_VLAN_EGRESS_TAG; 1058 mt7530_rmw(priv, MT7530_VAWD2, 1059 ETAG_CTRL_P_MASK(entry->port), 1060 ETAG_CTRL_P(entry->port, val)); 1061 1062 /* CPU port is always taken as a tagged port for serving more than one 1063 * VLANs across and also being applied with egress type stack mode for 1064 * that VLAN tags would be appended after hardware special tag used as 1065 * DSA tag. 1066 */ 1067 mt7530_rmw(priv, MT7530_VAWD2, 1068 ETAG_CTRL_P_MASK(MT7530_CPU_PORT), 1069 ETAG_CTRL_P(MT7530_CPU_PORT, 1070 MT7530_VLAN_EGRESS_STACK)); 1071 } 1072 1073 static void 1074 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1075 struct mt7530_hw_vlan_entry *entry) 1076 { 1077 u8 new_members; 1078 u32 val; 1079 1080 new_members = entry->old_members & ~BIT(entry->port); 1081 1082 val = mt7530_read(priv, MT7530_VAWD1); 1083 if (!(val & VLAN_VALID)) { 1084 dev_err(priv->dev, 1085 "Cannot be deleted due to invalid entry\n"); 1086 return; 1087 } 1088 1089 /* If certain member apart from CPU port is still alive in the VLAN, 1090 * the entry would be kept valid. Otherwise, the entry is got to be 1091 * disabled. 1092 */ 1093 if (new_members && new_members != BIT(MT7530_CPU_PORT)) { 1094 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1095 VLAN_VALID; 1096 mt7530_write(priv, MT7530_VAWD1, val); 1097 } else { 1098 mt7530_write(priv, MT7530_VAWD1, 0); 1099 mt7530_write(priv, MT7530_VAWD2, 0); 1100 } 1101 } 1102 1103 static void 1104 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1105 struct mt7530_hw_vlan_entry *entry, 1106 mt7530_vlan_op vlan_op) 1107 { 1108 u32 val; 1109 1110 /* Fetch entry */ 1111 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1112 1113 val = mt7530_read(priv, MT7530_VAWD1); 1114 1115 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1116 1117 /* Manipulate entry */ 1118 vlan_op(priv, entry); 1119 1120 /* Flush result to hardware */ 1121 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1122 } 1123 1124 static void 1125 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1126 const struct switchdev_obj_port_vlan *vlan) 1127 { 1128 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1129 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1130 struct mt7530_hw_vlan_entry new_entry; 1131 struct mt7530_priv *priv = ds->priv; 1132 u16 vid; 1133 1134 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not 1135 * being set. 1136 */ 1137 if (!priv->ports[port].vlan_filtering) 1138 return; 1139 1140 mutex_lock(&priv->reg_mutex); 1141 1142 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1143 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1144 mt7530_hw_vlan_update(priv, vid, &new_entry, 1145 mt7530_hw_vlan_add); 1146 } 1147 1148 if (pvid) { 1149 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1150 G0_PORT_VID(vlan->vid_end)); 1151 priv->ports[port].pvid = vlan->vid_end; 1152 } 1153 1154 mutex_unlock(&priv->reg_mutex); 1155 } 1156 1157 static int 1158 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1159 const struct switchdev_obj_port_vlan *vlan) 1160 { 1161 struct mt7530_hw_vlan_entry target_entry; 1162 struct mt7530_priv *priv = ds->priv; 1163 u16 vid, pvid; 1164 1165 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not 1166 * being set. 1167 */ 1168 if (!priv->ports[port].vlan_filtering) 1169 return 0; 1170 1171 mutex_lock(&priv->reg_mutex); 1172 1173 pvid = priv->ports[port].pvid; 1174 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1175 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1176 mt7530_hw_vlan_update(priv, vid, &target_entry, 1177 mt7530_hw_vlan_del); 1178 1179 /* PVID is being restored to the default whenever the PVID port 1180 * is being removed from the VLAN. 1181 */ 1182 if (pvid == vid) 1183 pvid = G0_PORT_VID_DEF; 1184 } 1185 1186 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid); 1187 priv->ports[port].pvid = pvid; 1188 1189 mutex_unlock(&priv->reg_mutex); 1190 1191 return 0; 1192 } 1193 1194 static enum dsa_tag_protocol 1195 mtk_get_tag_protocol(struct dsa_switch *ds, int port) 1196 { 1197 struct mt7530_priv *priv = ds->priv; 1198 1199 if (port != MT7530_CPU_PORT) { 1200 dev_warn(priv->dev, 1201 "port not matched with tagging CPU port\n"); 1202 return DSA_TAG_PROTO_NONE; 1203 } else { 1204 return DSA_TAG_PROTO_MTK; 1205 } 1206 } 1207 1208 static int 1209 mt7530_setup(struct dsa_switch *ds) 1210 { 1211 struct mt7530_priv *priv = ds->priv; 1212 int ret, i; 1213 u32 id, val; 1214 struct device_node *dn; 1215 struct mt7530_dummy_poll p; 1216 1217 /* The parent node of master netdev which holds the common system 1218 * controller also is the container for two GMACs nodes representing 1219 * as two netdev instances. 1220 */ 1221 dn = ds->ports[MT7530_CPU_PORT].master->dev.of_node->parent; 1222 priv->ethernet = syscon_node_to_regmap(dn); 1223 if (IS_ERR(priv->ethernet)) 1224 return PTR_ERR(priv->ethernet); 1225 1226 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 1227 ret = regulator_enable(priv->core_pwr); 1228 if (ret < 0) { 1229 dev_err(priv->dev, 1230 "Failed to enable core power: %d\n", ret); 1231 return ret; 1232 } 1233 1234 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 1235 ret = regulator_enable(priv->io_pwr); 1236 if (ret < 0) { 1237 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 1238 ret); 1239 return ret; 1240 } 1241 1242 /* Reset whole chip through gpio pin or memory-mapped registers for 1243 * different type of hardware 1244 */ 1245 if (priv->mcm) { 1246 reset_control_assert(priv->rstc); 1247 usleep_range(1000, 1100); 1248 reset_control_deassert(priv->rstc); 1249 } else { 1250 gpiod_set_value_cansleep(priv->reset, 0); 1251 usleep_range(1000, 1100); 1252 gpiod_set_value_cansleep(priv->reset, 1); 1253 } 1254 1255 /* Waiting for MT7530 got to stable */ 1256 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 1257 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 1258 20, 1000000); 1259 if (ret < 0) { 1260 dev_err(priv->dev, "reset timeout\n"); 1261 return ret; 1262 } 1263 1264 id = mt7530_read(priv, MT7530_CREV); 1265 id >>= CHIP_NAME_SHIFT; 1266 if (id != MT7530_ID) { 1267 dev_err(priv->dev, "chip %x can't be supported\n", id); 1268 return -ENODEV; 1269 } 1270 1271 /* Reset the switch through internal reset */ 1272 mt7530_write(priv, MT7530_SYS_CTRL, 1273 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 1274 SYS_CTRL_REG_RST); 1275 1276 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */ 1277 val = mt7530_read(priv, MT7530_MHWTRAP); 1278 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 1279 val |= MHWTRAP_MANUAL; 1280 mt7530_write(priv, MT7530_MHWTRAP, val); 1281 1282 /* Enable and reset MIB counters */ 1283 mt7530_mib_reset(ds); 1284 1285 mt7530_clear(priv, MT7530_MFC, UNU_FFP_MASK); 1286 1287 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1288 /* Disable forwarding by default on all ports */ 1289 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 1290 PCR_MATRIX_CLR); 1291 1292 if (dsa_is_cpu_port(ds, i)) 1293 mt7530_cpu_port_enable(priv, i); 1294 else 1295 mt7530_port_disable(ds, i, NULL); 1296 } 1297 1298 /* Flush the FDB table */ 1299 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 1300 if (ret < 0) 1301 return ret; 1302 1303 return 0; 1304 } 1305 1306 static const struct dsa_switch_ops mt7530_switch_ops = { 1307 .get_tag_protocol = mtk_get_tag_protocol, 1308 .setup = mt7530_setup, 1309 .get_strings = mt7530_get_strings, 1310 .phy_read = mt7530_phy_read, 1311 .phy_write = mt7530_phy_write, 1312 .get_ethtool_stats = mt7530_get_ethtool_stats, 1313 .get_sset_count = mt7530_get_sset_count, 1314 .adjust_link = mt7530_adjust_link, 1315 .port_enable = mt7530_port_enable, 1316 .port_disable = mt7530_port_disable, 1317 .port_stp_state_set = mt7530_stp_state_set, 1318 .port_bridge_join = mt7530_port_bridge_join, 1319 .port_bridge_leave = mt7530_port_bridge_leave, 1320 .port_fdb_add = mt7530_port_fdb_add, 1321 .port_fdb_del = mt7530_port_fdb_del, 1322 .port_fdb_dump = mt7530_port_fdb_dump, 1323 .port_vlan_filtering = mt7530_port_vlan_filtering, 1324 .port_vlan_prepare = mt7530_port_vlan_prepare, 1325 .port_vlan_add = mt7530_port_vlan_add, 1326 .port_vlan_del = mt7530_port_vlan_del, 1327 }; 1328 1329 static int 1330 mt7530_probe(struct mdio_device *mdiodev) 1331 { 1332 struct mt7530_priv *priv; 1333 struct device_node *dn; 1334 1335 dn = mdiodev->dev.of_node; 1336 1337 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 1338 if (!priv) 1339 return -ENOMEM; 1340 1341 priv->ds = dsa_switch_alloc(&mdiodev->dev, DSA_MAX_PORTS); 1342 if (!priv->ds) 1343 return -ENOMEM; 1344 1345 /* Use medatek,mcm property to distinguish hardware type that would 1346 * casues a little bit differences on power-on sequence. 1347 */ 1348 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); 1349 if (priv->mcm) { 1350 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); 1351 1352 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); 1353 if (IS_ERR(priv->rstc)) { 1354 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 1355 return PTR_ERR(priv->rstc); 1356 } 1357 } 1358 1359 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); 1360 if (IS_ERR(priv->core_pwr)) 1361 return PTR_ERR(priv->core_pwr); 1362 1363 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); 1364 if (IS_ERR(priv->io_pwr)) 1365 return PTR_ERR(priv->io_pwr); 1366 1367 /* Not MCM that indicates switch works as the remote standalone 1368 * integrated circuit so the GPIO pin would be used to complete 1369 * the reset, otherwise memory-mapped register accessing used 1370 * through syscon provides in the case of MCM. 1371 */ 1372 if (!priv->mcm) { 1373 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", 1374 GPIOD_OUT_LOW); 1375 if (IS_ERR(priv->reset)) { 1376 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 1377 return PTR_ERR(priv->reset); 1378 } 1379 } 1380 1381 priv->bus = mdiodev->bus; 1382 priv->dev = &mdiodev->dev; 1383 priv->ds->priv = priv; 1384 priv->ds->ops = &mt7530_switch_ops; 1385 mutex_init(&priv->reg_mutex); 1386 dev_set_drvdata(&mdiodev->dev, priv); 1387 1388 return dsa_register_switch(priv->ds); 1389 } 1390 1391 static void 1392 mt7530_remove(struct mdio_device *mdiodev) 1393 { 1394 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 1395 int ret = 0; 1396 1397 ret = regulator_disable(priv->core_pwr); 1398 if (ret < 0) 1399 dev_err(priv->dev, 1400 "Failed to disable core power: %d\n", ret); 1401 1402 ret = regulator_disable(priv->io_pwr); 1403 if (ret < 0) 1404 dev_err(priv->dev, "Failed to disable io pwr: %d\n", 1405 ret); 1406 1407 dsa_unregister_switch(priv->ds); 1408 mutex_destroy(&priv->reg_mutex); 1409 } 1410 1411 static const struct of_device_id mt7530_of_match[] = { 1412 { .compatible = "mediatek,mt7530" }, 1413 { /* sentinel */ }, 1414 }; 1415 MODULE_DEVICE_TABLE(of, mt7530_of_match); 1416 1417 static struct mdio_driver mt7530_mdio_driver = { 1418 .probe = mt7530_probe, 1419 .remove = mt7530_remove, 1420 .mdiodrv.driver = { 1421 .name = "mt7530", 1422 .of_match_table = mt7530_of_match, 1423 }, 1424 }; 1425 1426 mdio_module_driver(mt7530_mdio_driver); 1427 1428 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 1429 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 1430 MODULE_LICENSE("GPL"); 1431