1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 25 #include "mt7530.h" 26 27 /* String, offset, and register size in bytes if different from 4 bytes */ 28 static const struct mt7530_mib_desc mt7530_mib[] = { 29 MIB_DESC(1, 0x00, "TxDrop"), 30 MIB_DESC(1, 0x04, "TxCrcErr"), 31 MIB_DESC(1, 0x08, "TxUnicast"), 32 MIB_DESC(1, 0x0c, "TxMulticast"), 33 MIB_DESC(1, 0x10, "TxBroadcast"), 34 MIB_DESC(1, 0x14, "TxCollision"), 35 MIB_DESC(1, 0x18, "TxSingleCollision"), 36 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 37 MIB_DESC(1, 0x20, "TxDeferred"), 38 MIB_DESC(1, 0x24, "TxLateCollision"), 39 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 40 MIB_DESC(1, 0x2c, "TxPause"), 41 MIB_DESC(1, 0x30, "TxPktSz64"), 42 MIB_DESC(1, 0x34, "TxPktSz65To127"), 43 MIB_DESC(1, 0x38, "TxPktSz128To255"), 44 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 45 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 46 MIB_DESC(1, 0x44, "Tx1024ToMax"), 47 MIB_DESC(2, 0x48, "TxBytes"), 48 MIB_DESC(1, 0x60, "RxDrop"), 49 MIB_DESC(1, 0x64, "RxFiltering"), 50 MIB_DESC(1, 0x68, "RxUnicast"), 51 MIB_DESC(1, 0x6c, "RxMulticast"), 52 MIB_DESC(1, 0x70, "RxBroadcast"), 53 MIB_DESC(1, 0x74, "RxAlignErr"), 54 MIB_DESC(1, 0x78, "RxCrcErr"), 55 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 56 MIB_DESC(1, 0x80, "RxFragErr"), 57 MIB_DESC(1, 0x84, "RxOverSzErr"), 58 MIB_DESC(1, 0x88, "RxJabberErr"), 59 MIB_DESC(1, 0x8c, "RxPause"), 60 MIB_DESC(1, 0x90, "RxPktSz64"), 61 MIB_DESC(1, 0x94, "RxPktSz65To127"), 62 MIB_DESC(1, 0x98, "RxPktSz128To255"), 63 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 64 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 65 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 66 MIB_DESC(2, 0xa8, "RxBytes"), 67 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 68 MIB_DESC(1, 0xb4, "RxIngressDrop"), 69 MIB_DESC(1, 0xb8, "RxArlDrop"), 70 }; 71 72 /* Since phy_device has not yet been created and 73 * phy_{read,write}_mmd_indirect is not available, we provide our own 74 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers 75 * to complete this function. 76 */ 77 static int 78 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 79 { 80 struct mii_bus *bus = priv->bus; 81 int value, ret; 82 83 /* Write the desired MMD Devad */ 84 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 85 if (ret < 0) 86 goto err; 87 88 /* Write the desired MMD register address */ 89 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 90 if (ret < 0) 91 goto err; 92 93 /* Select the Function : DATA with no post increment */ 94 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 95 if (ret < 0) 96 goto err; 97 98 /* Read the content of the MMD's selected register */ 99 value = bus->read(bus, 0, MII_MMD_DATA); 100 101 return value; 102 err: 103 dev_err(&bus->dev, "failed to read mmd register\n"); 104 105 return ret; 106 } 107 108 static int 109 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 110 int devad, u32 data) 111 { 112 struct mii_bus *bus = priv->bus; 113 int ret; 114 115 /* Write the desired MMD Devad */ 116 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 117 if (ret < 0) 118 goto err; 119 120 /* Write the desired MMD register address */ 121 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 122 if (ret < 0) 123 goto err; 124 125 /* Select the Function : DATA with no post increment */ 126 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 127 if (ret < 0) 128 goto err; 129 130 /* Write the data into MMD's selected register */ 131 ret = bus->write(bus, 0, MII_MMD_DATA, data); 132 err: 133 if (ret < 0) 134 dev_err(&bus->dev, 135 "failed to write mmd register\n"); 136 return ret; 137 } 138 139 static void 140 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 141 { 142 struct mii_bus *bus = priv->bus; 143 144 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 145 146 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 147 148 mutex_unlock(&bus->mdio_lock); 149 } 150 151 static void 152 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 153 { 154 struct mii_bus *bus = priv->bus; 155 u32 val; 156 157 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 158 159 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 160 val &= ~mask; 161 val |= set; 162 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 163 164 mutex_unlock(&bus->mdio_lock); 165 } 166 167 static void 168 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 169 { 170 core_rmw(priv, reg, 0, val); 171 } 172 173 static void 174 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 175 { 176 core_rmw(priv, reg, val, 0); 177 } 178 179 static int 180 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 181 { 182 struct mii_bus *bus = priv->bus; 183 u16 page, r, lo, hi; 184 int ret; 185 186 page = (reg >> 6) & 0x3ff; 187 r = (reg >> 2) & 0xf; 188 lo = val & 0xffff; 189 hi = val >> 16; 190 191 /* MT7530 uses 31 as the pseudo port */ 192 ret = bus->write(bus, 0x1f, 0x1f, page); 193 if (ret < 0) 194 goto err; 195 196 ret = bus->write(bus, 0x1f, r, lo); 197 if (ret < 0) 198 goto err; 199 200 ret = bus->write(bus, 0x1f, 0x10, hi); 201 err: 202 if (ret < 0) 203 dev_err(&bus->dev, 204 "failed to write mt7530 register\n"); 205 return ret; 206 } 207 208 static u32 209 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 210 { 211 struct mii_bus *bus = priv->bus; 212 u16 page, r, lo, hi; 213 int ret; 214 215 page = (reg >> 6) & 0x3ff; 216 r = (reg >> 2) & 0xf; 217 218 /* MT7530 uses 31 as the pseudo port */ 219 ret = bus->write(bus, 0x1f, 0x1f, page); 220 if (ret < 0) { 221 dev_err(&bus->dev, 222 "failed to read mt7530 register\n"); 223 return ret; 224 } 225 226 lo = bus->read(bus, 0x1f, r); 227 hi = bus->read(bus, 0x1f, 0x10); 228 229 return (hi << 16) | (lo & 0xffff); 230 } 231 232 static void 233 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 234 { 235 struct mii_bus *bus = priv->bus; 236 237 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 238 239 mt7530_mii_write(priv, reg, val); 240 241 mutex_unlock(&bus->mdio_lock); 242 } 243 244 static u32 245 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 246 { 247 return mt7530_mii_read(p->priv, p->reg); 248 } 249 250 static u32 251 _mt7530_read(struct mt7530_dummy_poll *p) 252 { 253 struct mii_bus *bus = p->priv->bus; 254 u32 val; 255 256 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 257 258 val = mt7530_mii_read(p->priv, p->reg); 259 260 mutex_unlock(&bus->mdio_lock); 261 262 return val; 263 } 264 265 static u32 266 mt7530_read(struct mt7530_priv *priv, u32 reg) 267 { 268 struct mt7530_dummy_poll p; 269 270 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 271 return _mt7530_read(&p); 272 } 273 274 static void 275 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 276 u32 mask, u32 set) 277 { 278 struct mii_bus *bus = priv->bus; 279 u32 val; 280 281 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 282 283 val = mt7530_mii_read(priv, reg); 284 val &= ~mask; 285 val |= set; 286 mt7530_mii_write(priv, reg, val); 287 288 mutex_unlock(&bus->mdio_lock); 289 } 290 291 static void 292 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 293 { 294 mt7530_rmw(priv, reg, 0, val); 295 } 296 297 static void 298 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 299 { 300 mt7530_rmw(priv, reg, val, 0); 301 } 302 303 static int 304 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 305 { 306 u32 val; 307 int ret; 308 struct mt7530_dummy_poll p; 309 310 /* Set the command operating upon the MAC address entries */ 311 val = ATC_BUSY | ATC_MAT(0) | cmd; 312 mt7530_write(priv, MT7530_ATC, val); 313 314 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 315 ret = readx_poll_timeout(_mt7530_read, &p, val, 316 !(val & ATC_BUSY), 20, 20000); 317 if (ret < 0) { 318 dev_err(priv->dev, "reset timeout\n"); 319 return ret; 320 } 321 322 /* Additional sanity for read command if the specified 323 * entry is invalid 324 */ 325 val = mt7530_read(priv, MT7530_ATC); 326 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 327 return -EINVAL; 328 329 if (rsp) 330 *rsp = val; 331 332 return 0; 333 } 334 335 static void 336 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 337 { 338 u32 reg[3]; 339 int i; 340 341 /* Read from ARL table into an array */ 342 for (i = 0; i < 3; i++) { 343 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 344 345 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 346 __func__, __LINE__, i, reg[i]); 347 } 348 349 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 350 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 351 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 352 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 353 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 354 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 355 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 356 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 357 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 358 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 359 } 360 361 static void 362 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 363 u8 port_mask, const u8 *mac, 364 u8 aging, u8 type) 365 { 366 u32 reg[3] = { 0 }; 367 int i; 368 369 reg[1] |= vid & CVID_MASK; 370 reg[1] |= ATA2_IVL; 371 reg[1] |= ATA2_FID(FID_BRIDGED); 372 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 373 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 374 /* STATIC_ENT indicate that entry is static wouldn't 375 * be aged out and STATIC_EMP specified as erasing an 376 * entry 377 */ 378 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 379 reg[1] |= mac[5] << MAC_BYTE_5; 380 reg[1] |= mac[4] << MAC_BYTE_4; 381 reg[0] |= mac[3] << MAC_BYTE_3; 382 reg[0] |= mac[2] << MAC_BYTE_2; 383 reg[0] |= mac[1] << MAC_BYTE_1; 384 reg[0] |= mac[0] << MAC_BYTE_0; 385 386 /* Write array into the ARL table */ 387 for (i = 0; i < 3; i++) 388 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 389 } 390 391 /* Setup TX circuit including relevant PAD and driving */ 392 static int 393 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 394 { 395 struct mt7530_priv *priv = ds->priv; 396 u32 ncpo1, ssc_delta, trgint, i, xtal; 397 398 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 399 400 if (xtal == HWTRAP_XTAL_20MHZ) { 401 dev_err(priv->dev, 402 "%s: MT7530 with a 20MHz XTAL is not supported!\n", 403 __func__); 404 return -EINVAL; 405 } 406 407 switch (interface) { 408 case PHY_INTERFACE_MODE_RGMII: 409 trgint = 0; 410 /* PLL frequency: 125MHz */ 411 ncpo1 = 0x0c80; 412 break; 413 case PHY_INTERFACE_MODE_TRGMII: 414 trgint = 1; 415 if (priv->id == ID_MT7621) { 416 /* PLL frequency: 150MHz: 1.2GBit */ 417 if (xtal == HWTRAP_XTAL_40MHZ) 418 ncpo1 = 0x0780; 419 if (xtal == HWTRAP_XTAL_25MHZ) 420 ncpo1 = 0x0a00; 421 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 422 if (xtal == HWTRAP_XTAL_40MHZ) 423 ncpo1 = 0x0c80; 424 if (xtal == HWTRAP_XTAL_25MHZ) 425 ncpo1 = 0x1400; 426 } 427 break; 428 default: 429 dev_err(priv->dev, "xMII interface %d not supported\n", 430 interface); 431 return -EINVAL; 432 } 433 434 if (xtal == HWTRAP_XTAL_25MHZ) 435 ssc_delta = 0x57; 436 else 437 ssc_delta = 0x87; 438 439 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 440 P6_INTF_MODE(trgint)); 441 442 /* Lower Tx Driving for TRGMII path */ 443 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) 444 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 445 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 446 447 /* Disable MT7530 core and TRGMII Tx clocks */ 448 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, 449 REG_GSWCK_EN | REG_TRGMIICK_EN); 450 451 /* Setup core clock for MT7530 */ 452 /* Disable PLL */ 453 core_write(priv, CORE_GSWPLL_GRP1, 0); 454 455 /* Set core clock into 500Mhz */ 456 core_write(priv, CORE_GSWPLL_GRP2, 457 RG_GSWPLL_POSDIV_500M(1) | 458 RG_GSWPLL_FBKDIV_500M(25)); 459 460 /* Enable PLL */ 461 core_write(priv, CORE_GSWPLL_GRP1, 462 RG_GSWPLL_EN_PRE | 463 RG_GSWPLL_POSDIV_200M(2) | 464 RG_GSWPLL_FBKDIV_200M(32)); 465 466 /* Setup the MT7530 TRGMII Tx Clock */ 467 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 468 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 469 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 470 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 471 core_write(priv, CORE_PLL_GROUP4, 472 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 473 RG_SYSPLL_BIAS_LPF_EN); 474 core_write(priv, CORE_PLL_GROUP2, 475 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 476 RG_SYSPLL_POSDIV(1)); 477 core_write(priv, CORE_PLL_GROUP7, 478 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 479 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 480 481 /* Enable MT7530 core and TRGMII Tx clocks */ 482 core_set(priv, CORE_TRGMII_GSW_CLK_CG, 483 REG_GSWCK_EN | REG_TRGMIICK_EN); 484 485 if (!trgint) 486 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 487 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 488 RD_TAP_MASK, RD_TAP(16)); 489 return 0; 490 } 491 492 static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) 493 { 494 u32 val; 495 496 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 497 498 return (val & PAD_DUAL_SGMII_EN) != 0; 499 } 500 501 static int 502 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 503 { 504 struct mt7530_priv *priv = ds->priv; 505 u32 top_sig; 506 u32 hwstrap; 507 u32 xtal; 508 u32 val; 509 510 if (mt7531_dual_sgmii_supported(priv)) 511 return 0; 512 513 val = mt7530_read(priv, MT7531_CREV); 514 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 515 hwstrap = mt7530_read(priv, MT7531_HWTRAP); 516 if ((val & CHIP_REV_M) > 0) 517 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : 518 HWTRAP_XTAL_FSEL_25MHZ; 519 else 520 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; 521 522 /* Step 1 : Disable MT7531 COREPLL */ 523 val = mt7530_read(priv, MT7531_PLLGP_EN); 524 val &= ~EN_COREPLL; 525 mt7530_write(priv, MT7531_PLLGP_EN, val); 526 527 /* Step 2: switch to XTAL output */ 528 val = mt7530_read(priv, MT7531_PLLGP_EN); 529 val |= SW_CLKSW; 530 mt7530_write(priv, MT7531_PLLGP_EN, val); 531 532 val = mt7530_read(priv, MT7531_PLLGP_CR0); 533 val &= ~RG_COREPLL_EN; 534 mt7530_write(priv, MT7531_PLLGP_CR0, val); 535 536 /* Step 3: disable PLLGP and enable program PLLGP */ 537 val = mt7530_read(priv, MT7531_PLLGP_EN); 538 val |= SW_PLLGP; 539 mt7530_write(priv, MT7531_PLLGP_EN, val); 540 541 /* Step 4: program COREPLL output frequency to 500MHz */ 542 val = mt7530_read(priv, MT7531_PLLGP_CR0); 543 val &= ~RG_COREPLL_POSDIV_M; 544 val |= 2 << RG_COREPLL_POSDIV_S; 545 mt7530_write(priv, MT7531_PLLGP_CR0, val); 546 usleep_range(25, 35); 547 548 switch (xtal) { 549 case HWTRAP_XTAL_FSEL_25MHZ: 550 val = mt7530_read(priv, MT7531_PLLGP_CR0); 551 val &= ~RG_COREPLL_SDM_PCW_M; 552 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 553 mt7530_write(priv, MT7531_PLLGP_CR0, val); 554 break; 555 case HWTRAP_XTAL_FSEL_40MHZ: 556 val = mt7530_read(priv, MT7531_PLLGP_CR0); 557 val &= ~RG_COREPLL_SDM_PCW_M; 558 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 559 mt7530_write(priv, MT7531_PLLGP_CR0, val); 560 break; 561 } 562 563 /* Set feedback divide ratio update signal to high */ 564 val = mt7530_read(priv, MT7531_PLLGP_CR0); 565 val |= RG_COREPLL_SDM_PCW_CHG; 566 mt7530_write(priv, MT7531_PLLGP_CR0, val); 567 /* Wait for at least 16 XTAL clocks */ 568 usleep_range(10, 20); 569 570 /* Step 5: set feedback divide ratio update signal to low */ 571 val = mt7530_read(priv, MT7531_PLLGP_CR0); 572 val &= ~RG_COREPLL_SDM_PCW_CHG; 573 mt7530_write(priv, MT7531_PLLGP_CR0, val); 574 575 /* Enable 325M clock for SGMII */ 576 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 577 578 /* Enable 250SSC clock for RGMII */ 579 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 580 581 /* Step 6: Enable MT7531 PLL */ 582 val = mt7530_read(priv, MT7531_PLLGP_CR0); 583 val |= RG_COREPLL_EN; 584 mt7530_write(priv, MT7531_PLLGP_CR0, val); 585 586 val = mt7530_read(priv, MT7531_PLLGP_EN); 587 val |= EN_COREPLL; 588 mt7530_write(priv, MT7531_PLLGP_EN, val); 589 usleep_range(25, 35); 590 591 return 0; 592 } 593 594 static void 595 mt7530_mib_reset(struct dsa_switch *ds) 596 { 597 struct mt7530_priv *priv = ds->priv; 598 599 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 600 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 601 } 602 603 static int mt7530_phy_read(struct mt7530_priv *priv, int port, int regnum) 604 { 605 return mdiobus_read_nested(priv->bus, port, regnum); 606 } 607 608 static int mt7530_phy_write(struct mt7530_priv *priv, int port, int regnum, 609 u16 val) 610 { 611 return mdiobus_write_nested(priv->bus, port, regnum, val); 612 } 613 614 static int 615 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 616 int regnum) 617 { 618 struct mii_bus *bus = priv->bus; 619 struct mt7530_dummy_poll p; 620 u32 reg, val; 621 int ret; 622 623 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 624 625 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 626 627 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 628 !(val & MT7531_PHY_ACS_ST), 20, 100000); 629 if (ret < 0) { 630 dev_err(priv->dev, "poll timeout\n"); 631 goto out; 632 } 633 634 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 635 MT7531_MDIO_DEV_ADDR(devad) | regnum; 636 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 637 638 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 639 !(val & MT7531_PHY_ACS_ST), 20, 100000); 640 if (ret < 0) { 641 dev_err(priv->dev, "poll timeout\n"); 642 goto out; 643 } 644 645 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 646 MT7531_MDIO_DEV_ADDR(devad); 647 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 648 649 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 650 !(val & MT7531_PHY_ACS_ST), 20, 100000); 651 if (ret < 0) { 652 dev_err(priv->dev, "poll timeout\n"); 653 goto out; 654 } 655 656 ret = val & MT7531_MDIO_RW_DATA_MASK; 657 out: 658 mutex_unlock(&bus->mdio_lock); 659 660 return ret; 661 } 662 663 static int 664 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 665 int regnum, u32 data) 666 { 667 struct mii_bus *bus = priv->bus; 668 struct mt7530_dummy_poll p; 669 u32 val, reg; 670 int ret; 671 672 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 673 674 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 675 676 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 677 !(val & MT7531_PHY_ACS_ST), 20, 100000); 678 if (ret < 0) { 679 dev_err(priv->dev, "poll timeout\n"); 680 goto out; 681 } 682 683 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 684 MT7531_MDIO_DEV_ADDR(devad) | regnum; 685 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 686 687 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 688 !(val & MT7531_PHY_ACS_ST), 20, 100000); 689 if (ret < 0) { 690 dev_err(priv->dev, "poll timeout\n"); 691 goto out; 692 } 693 694 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 695 MT7531_MDIO_DEV_ADDR(devad) | data; 696 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 697 698 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 699 !(val & MT7531_PHY_ACS_ST), 20, 100000); 700 if (ret < 0) { 701 dev_err(priv->dev, "poll timeout\n"); 702 goto out; 703 } 704 705 out: 706 mutex_unlock(&bus->mdio_lock); 707 708 return ret; 709 } 710 711 static int 712 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 713 { 714 struct mii_bus *bus = priv->bus; 715 struct mt7530_dummy_poll p; 716 int ret; 717 u32 val; 718 719 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 720 721 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 722 723 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 724 !(val & MT7531_PHY_ACS_ST), 20, 100000); 725 if (ret < 0) { 726 dev_err(priv->dev, "poll timeout\n"); 727 goto out; 728 } 729 730 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 731 MT7531_MDIO_REG_ADDR(regnum); 732 733 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 734 735 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 736 !(val & MT7531_PHY_ACS_ST), 20, 100000); 737 if (ret < 0) { 738 dev_err(priv->dev, "poll timeout\n"); 739 goto out; 740 } 741 742 ret = val & MT7531_MDIO_RW_DATA_MASK; 743 out: 744 mutex_unlock(&bus->mdio_lock); 745 746 return ret; 747 } 748 749 static int 750 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 751 u16 data) 752 { 753 struct mii_bus *bus = priv->bus; 754 struct mt7530_dummy_poll p; 755 int ret; 756 u32 reg; 757 758 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 759 760 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 761 762 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 763 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 764 if (ret < 0) { 765 dev_err(priv->dev, "poll timeout\n"); 766 goto out; 767 } 768 769 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 770 MT7531_MDIO_REG_ADDR(regnum) | data; 771 772 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 773 774 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 775 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 776 if (ret < 0) { 777 dev_err(priv->dev, "poll timeout\n"); 778 goto out; 779 } 780 781 out: 782 mutex_unlock(&bus->mdio_lock); 783 784 return ret; 785 } 786 787 static int 788 mt7531_ind_phy_read(struct mt7530_priv *priv, int port, int regnum) 789 { 790 int devad; 791 int ret; 792 793 if (regnum & MII_ADDR_C45) { 794 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; 795 ret = mt7531_ind_c45_phy_read(priv, port, devad, 796 regnum & MII_REGADDR_C45_MASK); 797 } else { 798 ret = mt7531_ind_c22_phy_read(priv, port, regnum); 799 } 800 801 return ret; 802 } 803 804 static int 805 mt7531_ind_phy_write(struct mt7530_priv *priv, int port, int regnum, 806 u16 data) 807 { 808 int devad; 809 int ret; 810 811 if (regnum & MII_ADDR_C45) { 812 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; 813 ret = mt7531_ind_c45_phy_write(priv, port, devad, 814 regnum & MII_REGADDR_C45_MASK, 815 data); 816 } else { 817 ret = mt7531_ind_c22_phy_write(priv, port, regnum, data); 818 } 819 820 return ret; 821 } 822 823 static int 824 mt753x_phy_read(struct mii_bus *bus, int port, int regnum) 825 { 826 struct mt7530_priv *priv = bus->priv; 827 828 return priv->info->phy_read(priv, port, regnum); 829 } 830 831 static int 832 mt753x_phy_write(struct mii_bus *bus, int port, int regnum, u16 val) 833 { 834 struct mt7530_priv *priv = bus->priv; 835 836 return priv->info->phy_write(priv, port, regnum, val); 837 } 838 839 static void 840 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 841 uint8_t *data) 842 { 843 int i; 844 845 if (stringset != ETH_SS_STATS) 846 return; 847 848 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 849 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 850 ETH_GSTRING_LEN); 851 } 852 853 static void 854 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 855 uint64_t *data) 856 { 857 struct mt7530_priv *priv = ds->priv; 858 const struct mt7530_mib_desc *mib; 859 u32 reg, i; 860 u64 hi; 861 862 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 863 mib = &mt7530_mib[i]; 864 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 865 866 data[i] = mt7530_read(priv, reg); 867 if (mib->size == 2) { 868 hi = mt7530_read(priv, reg + 4); 869 data[i] |= hi << 32; 870 } 871 } 872 } 873 874 static int 875 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 876 { 877 if (sset != ETH_SS_STATS) 878 return 0; 879 880 return ARRAY_SIZE(mt7530_mib); 881 } 882 883 static int 884 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 885 { 886 struct mt7530_priv *priv = ds->priv; 887 unsigned int secs = msecs / 1000; 888 unsigned int tmp_age_count; 889 unsigned int error = -1; 890 unsigned int age_count; 891 unsigned int age_unit; 892 893 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 894 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 895 return -ERANGE; 896 897 /* iterate through all possible age_count to find the closest pair */ 898 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 899 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 900 901 if (tmp_age_unit <= AGE_UNIT_MAX) { 902 unsigned int tmp_error = secs - 903 (tmp_age_count + 1) * (tmp_age_unit + 1); 904 905 /* found a closer pair */ 906 if (error > tmp_error) { 907 error = tmp_error; 908 age_count = tmp_age_count; 909 age_unit = tmp_age_unit; 910 } 911 912 /* found the exact match, so break the loop */ 913 if (!error) 914 break; 915 } 916 } 917 918 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 919 920 return 0; 921 } 922 923 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 924 { 925 struct mt7530_priv *priv = ds->priv; 926 u8 tx_delay = 0; 927 int val; 928 929 mutex_lock(&priv->reg_mutex); 930 931 val = mt7530_read(priv, MT7530_MHWTRAP); 932 933 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 934 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 935 936 switch (priv->p5_intf_sel) { 937 case P5_INTF_SEL_PHY_P0: 938 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 939 val |= MHWTRAP_PHY0_SEL; 940 fallthrough; 941 case P5_INTF_SEL_PHY_P4: 942 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 943 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 944 945 /* Setup the MAC by default for the cpu port */ 946 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 947 break; 948 case P5_INTF_SEL_GMAC5: 949 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 950 val &= ~MHWTRAP_P5_DIS; 951 break; 952 case P5_DISABLED: 953 interface = PHY_INTERFACE_MODE_NA; 954 break; 955 default: 956 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", 957 priv->p5_intf_sel); 958 goto unlock_exit; 959 } 960 961 /* Setup RGMII settings */ 962 if (phy_interface_mode_is_rgmii(interface)) { 963 val |= MHWTRAP_P5_RGMII_MODE; 964 965 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 966 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 967 968 /* Don't set delay in DSA mode */ 969 if (!dsa_is_dsa_port(priv->ds, 5) && 970 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 971 interface == PHY_INTERFACE_MODE_RGMII_ID)) 972 tx_delay = 4; /* n * 0.5 ns */ 973 974 /* P5 RGMII TX Clock Control: delay x */ 975 mt7530_write(priv, MT7530_P5RGMIITXCR, 976 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 977 978 /* reduce P5 RGMII Tx driving, 8mA */ 979 mt7530_write(priv, MT7530_IO_DRV_CR, 980 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 981 } 982 983 mt7530_write(priv, MT7530_MHWTRAP, val); 984 985 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 986 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 987 988 priv->p5_interface = interface; 989 990 unlock_exit: 991 mutex_unlock(&priv->reg_mutex); 992 } 993 994 static int 995 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 996 { 997 struct mt7530_priv *priv = ds->priv; 998 int ret; 999 1000 /* Setup max capability of CPU port at first */ 1001 if (priv->info->cpu_port_config) { 1002 ret = priv->info->cpu_port_config(ds, port); 1003 if (ret) 1004 return ret; 1005 } 1006 1007 /* Enable Mediatek header mode on the cpu port */ 1008 mt7530_write(priv, MT7530_PVC_P(port), 1009 PORT_SPEC_TAG); 1010 1011 /* Disable flooding by default */ 1012 mt7530_rmw(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK, 1013 BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port))); 1014 1015 /* Set CPU port number */ 1016 if (priv->id == ID_MT7621) 1017 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 1018 1019 /* CPU port gets connected to all user ports of 1020 * the switch. 1021 */ 1022 mt7530_write(priv, MT7530_PCR_P(port), 1023 PCR_MATRIX(dsa_user_ports(priv->ds))); 1024 1025 /* Set to fallback mode for independent VLAN learning */ 1026 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1027 MT7530_PORT_FALLBACK_MODE); 1028 1029 return 0; 1030 } 1031 1032 static int 1033 mt7530_port_enable(struct dsa_switch *ds, int port, 1034 struct phy_device *phy) 1035 { 1036 struct mt7530_priv *priv = ds->priv; 1037 1038 mutex_lock(&priv->reg_mutex); 1039 1040 /* Allow the user port gets connected to the cpu port and also 1041 * restore the port matrix if the port is the member of a certain 1042 * bridge. 1043 */ 1044 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); 1045 priv->ports[port].enable = true; 1046 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1047 priv->ports[port].pm); 1048 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1049 1050 mutex_unlock(&priv->reg_mutex); 1051 1052 return 0; 1053 } 1054 1055 static void 1056 mt7530_port_disable(struct dsa_switch *ds, int port) 1057 { 1058 struct mt7530_priv *priv = ds->priv; 1059 1060 mutex_lock(&priv->reg_mutex); 1061 1062 /* Clear up all port matrix which could be restored in the next 1063 * enablement for the port. 1064 */ 1065 priv->ports[port].enable = false; 1066 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1067 PCR_MATRIX_CLR); 1068 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1069 1070 mutex_unlock(&priv->reg_mutex); 1071 } 1072 1073 static int 1074 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1075 { 1076 struct mt7530_priv *priv = ds->priv; 1077 struct mii_bus *bus = priv->bus; 1078 int length; 1079 u32 val; 1080 1081 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1082 * largest MTU of the slave ports. Because the switch only has a global 1083 * RX length register, only allowing CPU port here is enough. 1084 */ 1085 if (!dsa_is_cpu_port(ds, port)) 1086 return 0; 1087 1088 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 1089 1090 val = mt7530_mii_read(priv, MT7530_GMACCR); 1091 val &= ~MAX_RX_PKT_LEN_MASK; 1092 1093 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1094 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1095 if (length <= 1522) { 1096 val |= MAX_RX_PKT_LEN_1522; 1097 } else if (length <= 1536) { 1098 val |= MAX_RX_PKT_LEN_1536; 1099 } else if (length <= 1552) { 1100 val |= MAX_RX_PKT_LEN_1552; 1101 } else { 1102 val &= ~MAX_RX_JUMBO_MASK; 1103 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1104 val |= MAX_RX_PKT_LEN_JUMBO; 1105 } 1106 1107 mt7530_mii_write(priv, MT7530_GMACCR, val); 1108 1109 mutex_unlock(&bus->mdio_lock); 1110 1111 return 0; 1112 } 1113 1114 static int 1115 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1116 { 1117 return MT7530_MAX_MTU; 1118 } 1119 1120 static void 1121 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1122 { 1123 struct mt7530_priv *priv = ds->priv; 1124 u32 stp_state; 1125 1126 switch (state) { 1127 case BR_STATE_DISABLED: 1128 stp_state = MT7530_STP_DISABLED; 1129 break; 1130 case BR_STATE_BLOCKING: 1131 stp_state = MT7530_STP_BLOCKING; 1132 break; 1133 case BR_STATE_LISTENING: 1134 stp_state = MT7530_STP_LISTENING; 1135 break; 1136 case BR_STATE_LEARNING: 1137 stp_state = MT7530_STP_LEARNING; 1138 break; 1139 case BR_STATE_FORWARDING: 1140 default: 1141 stp_state = MT7530_STP_FORWARDING; 1142 break; 1143 } 1144 1145 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1146 FID_PST(FID_BRIDGED, stp_state)); 1147 } 1148 1149 static int 1150 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1151 struct switchdev_brport_flags flags, 1152 struct netlink_ext_ack *extack) 1153 { 1154 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1155 BR_BCAST_FLOOD)) 1156 return -EINVAL; 1157 1158 return 0; 1159 } 1160 1161 static int 1162 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1163 struct switchdev_brport_flags flags, 1164 struct netlink_ext_ack *extack) 1165 { 1166 struct mt7530_priv *priv = ds->priv; 1167 1168 if (flags.mask & BR_LEARNING) 1169 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1170 flags.val & BR_LEARNING ? 0 : SA_DIS); 1171 1172 if (flags.mask & BR_FLOOD) 1173 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), 1174 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1175 1176 if (flags.mask & BR_MCAST_FLOOD) 1177 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1178 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1179 1180 if (flags.mask & BR_BCAST_FLOOD) 1181 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), 1182 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1183 1184 return 0; 1185 } 1186 1187 static int 1188 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1189 struct net_device *bridge) 1190 { 1191 struct mt7530_priv *priv = ds->priv; 1192 u32 port_bitmap = BIT(MT7530_CPU_PORT); 1193 int i; 1194 1195 mutex_lock(&priv->reg_mutex); 1196 1197 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1198 /* Add this port to the port matrix of the other ports in the 1199 * same bridge. If the port is disabled, port matrix is kept 1200 * and not being setup until the port becomes enabled. 1201 */ 1202 if (dsa_is_user_port(ds, i) && i != port) { 1203 if (dsa_to_port(ds, i)->bridge_dev != bridge) 1204 continue; 1205 if (priv->ports[i].enable) 1206 mt7530_set(priv, MT7530_PCR_P(i), 1207 PCR_MATRIX(BIT(port))); 1208 priv->ports[i].pm |= PCR_MATRIX(BIT(port)); 1209 1210 port_bitmap |= BIT(i); 1211 } 1212 } 1213 1214 /* Add the all other ports to this port matrix. */ 1215 if (priv->ports[port].enable) 1216 mt7530_rmw(priv, MT7530_PCR_P(port), 1217 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1218 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1219 1220 /* Set to fallback mode for independent VLAN learning */ 1221 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1222 MT7530_PORT_FALLBACK_MODE); 1223 1224 mutex_unlock(&priv->reg_mutex); 1225 1226 return 0; 1227 } 1228 1229 static void 1230 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1231 { 1232 struct mt7530_priv *priv = ds->priv; 1233 bool all_user_ports_removed = true; 1234 int i; 1235 1236 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1237 * bridge. Don't set standalone ports to fallback mode. 1238 */ 1239 if (dsa_to_port(ds, port)->bridge_dev) 1240 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1241 MT7530_PORT_FALLBACK_MODE); 1242 1243 mt7530_rmw(priv, MT7530_PVC_P(port), 1244 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1245 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1246 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1247 MT7530_VLAN_ACC_ALL); 1248 1249 /* Set PVID to 0 */ 1250 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1251 G0_PORT_VID_DEF); 1252 1253 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1254 if (dsa_is_user_port(ds, i) && 1255 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1256 all_user_ports_removed = false; 1257 break; 1258 } 1259 } 1260 1261 /* CPU port also does the same thing until all user ports belonging to 1262 * the CPU port get out of VLAN filtering mode. 1263 */ 1264 if (all_user_ports_removed) { 1265 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT), 1266 PCR_MATRIX(dsa_user_ports(priv->ds))); 1267 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG 1268 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1269 } 1270 } 1271 1272 static void 1273 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1274 { 1275 struct mt7530_priv *priv = ds->priv; 1276 1277 /* Trapped into security mode allows packet forwarding through VLAN 1278 * table lookup. 1279 */ 1280 if (dsa_is_user_port(ds, port)) { 1281 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1282 MT7530_PORT_SECURITY_MODE); 1283 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1284 G0_PORT_VID(priv->ports[port].pvid)); 1285 1286 /* Only accept tagged frames if PVID is not set */ 1287 if (!priv->ports[port].pvid) 1288 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1289 MT7530_VLAN_ACC_TAGGED); 1290 } 1291 1292 /* Set the port as a user port which is to be able to recognize VID 1293 * from incoming packets before fetching entry within the VLAN table. 1294 */ 1295 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1296 VLAN_ATTR(MT7530_VLAN_USER) | 1297 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1298 } 1299 1300 static void 1301 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1302 struct net_device *bridge) 1303 { 1304 struct mt7530_priv *priv = ds->priv; 1305 int i; 1306 1307 mutex_lock(&priv->reg_mutex); 1308 1309 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1310 /* Remove this port from the port matrix of the other ports 1311 * in the same bridge. If the port is disabled, port matrix 1312 * is kept and not being setup until the port becomes enabled. 1313 */ 1314 if (dsa_is_user_port(ds, i) && i != port) { 1315 if (dsa_to_port(ds, i)->bridge_dev != bridge) 1316 continue; 1317 if (priv->ports[i].enable) 1318 mt7530_clear(priv, MT7530_PCR_P(i), 1319 PCR_MATRIX(BIT(port))); 1320 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port)); 1321 } 1322 } 1323 1324 /* Set the cpu port to be the only one in the port matrix of 1325 * this port. 1326 */ 1327 if (priv->ports[port].enable) 1328 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1329 PCR_MATRIX(BIT(MT7530_CPU_PORT))); 1330 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); 1331 1332 /* When a port is removed from the bridge, the port would be set up 1333 * back to the default as is at initial boot which is a VLAN-unaware 1334 * port. 1335 */ 1336 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1337 MT7530_PORT_MATRIX_MODE); 1338 1339 mutex_unlock(&priv->reg_mutex); 1340 } 1341 1342 static int 1343 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1344 const unsigned char *addr, u16 vid) 1345 { 1346 struct mt7530_priv *priv = ds->priv; 1347 int ret; 1348 u8 port_mask = BIT(port); 1349 1350 mutex_lock(&priv->reg_mutex); 1351 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1352 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1353 mutex_unlock(&priv->reg_mutex); 1354 1355 return ret; 1356 } 1357 1358 static int 1359 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1360 const unsigned char *addr, u16 vid) 1361 { 1362 struct mt7530_priv *priv = ds->priv; 1363 int ret; 1364 u8 port_mask = BIT(port); 1365 1366 mutex_lock(&priv->reg_mutex); 1367 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1368 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1369 mutex_unlock(&priv->reg_mutex); 1370 1371 return ret; 1372 } 1373 1374 static int 1375 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1376 dsa_fdb_dump_cb_t *cb, void *data) 1377 { 1378 struct mt7530_priv *priv = ds->priv; 1379 struct mt7530_fdb _fdb = { 0 }; 1380 int cnt = MT7530_NUM_FDB_RECORDS; 1381 int ret = 0; 1382 u32 rsp = 0; 1383 1384 mutex_lock(&priv->reg_mutex); 1385 1386 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1387 if (ret < 0) 1388 goto err; 1389 1390 do { 1391 if (rsp & ATC_SRCH_HIT) { 1392 mt7530_fdb_read(priv, &_fdb); 1393 if (_fdb.port_mask & BIT(port)) { 1394 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1395 data); 1396 if (ret < 0) 1397 break; 1398 } 1399 } 1400 } while (--cnt && 1401 !(rsp & ATC_SRCH_END) && 1402 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1403 err: 1404 mutex_unlock(&priv->reg_mutex); 1405 1406 return 0; 1407 } 1408 1409 static int 1410 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1411 const struct switchdev_obj_port_mdb *mdb) 1412 { 1413 struct mt7530_priv *priv = ds->priv; 1414 const u8 *addr = mdb->addr; 1415 u16 vid = mdb->vid; 1416 u8 port_mask = 0; 1417 int ret; 1418 1419 mutex_lock(&priv->reg_mutex); 1420 1421 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1422 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1423 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1424 & PORT_MAP_MASK; 1425 1426 port_mask |= BIT(port); 1427 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1428 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1429 1430 mutex_unlock(&priv->reg_mutex); 1431 1432 return ret; 1433 } 1434 1435 static int 1436 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1437 const struct switchdev_obj_port_mdb *mdb) 1438 { 1439 struct mt7530_priv *priv = ds->priv; 1440 const u8 *addr = mdb->addr; 1441 u16 vid = mdb->vid; 1442 u8 port_mask = 0; 1443 int ret; 1444 1445 mutex_lock(&priv->reg_mutex); 1446 1447 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1448 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1449 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1450 & PORT_MAP_MASK; 1451 1452 port_mask &= ~BIT(port); 1453 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1454 port_mask ? STATIC_ENT : STATIC_EMP); 1455 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1456 1457 mutex_unlock(&priv->reg_mutex); 1458 1459 return ret; 1460 } 1461 1462 static int 1463 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1464 { 1465 struct mt7530_dummy_poll p; 1466 u32 val; 1467 int ret; 1468 1469 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1470 mt7530_write(priv, MT7530_VTCR, val); 1471 1472 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1473 ret = readx_poll_timeout(_mt7530_read, &p, val, 1474 !(val & VTCR_BUSY), 20, 20000); 1475 if (ret < 0) { 1476 dev_err(priv->dev, "poll timeout\n"); 1477 return ret; 1478 } 1479 1480 val = mt7530_read(priv, MT7530_VTCR); 1481 if (val & VTCR_INVALID) { 1482 dev_err(priv->dev, "read VTCR invalid\n"); 1483 return -EINVAL; 1484 } 1485 1486 return 0; 1487 } 1488 1489 static int 1490 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1491 struct netlink_ext_ack *extack) 1492 { 1493 if (vlan_filtering) { 1494 /* The port is being kept as VLAN-unaware port when bridge is 1495 * set up with vlan_filtering not being set, Otherwise, the 1496 * port and the corresponding CPU port is required the setup 1497 * for becoming a VLAN-aware port. 1498 */ 1499 mt7530_port_set_vlan_aware(ds, port); 1500 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT); 1501 } else { 1502 mt7530_port_set_vlan_unaware(ds, port); 1503 } 1504 1505 return 0; 1506 } 1507 1508 static void 1509 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1510 struct mt7530_hw_vlan_entry *entry) 1511 { 1512 u8 new_members; 1513 u32 val; 1514 1515 new_members = entry->old_members | BIT(entry->port) | 1516 BIT(MT7530_CPU_PORT); 1517 1518 /* Validate the entry with independent learning, create egress tag per 1519 * VLAN and joining the port as one of the port members. 1520 */ 1521 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1522 VLAN_VALID; 1523 mt7530_write(priv, MT7530_VAWD1, val); 1524 1525 /* Decide whether adding tag or not for those outgoing packets from the 1526 * port inside the VLAN. 1527 */ 1528 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG : 1529 MT7530_VLAN_EGRESS_TAG; 1530 mt7530_rmw(priv, MT7530_VAWD2, 1531 ETAG_CTRL_P_MASK(entry->port), 1532 ETAG_CTRL_P(entry->port, val)); 1533 1534 /* CPU port is always taken as a tagged port for serving more than one 1535 * VLANs across and also being applied with egress type stack mode for 1536 * that VLAN tags would be appended after hardware special tag used as 1537 * DSA tag. 1538 */ 1539 mt7530_rmw(priv, MT7530_VAWD2, 1540 ETAG_CTRL_P_MASK(MT7530_CPU_PORT), 1541 ETAG_CTRL_P(MT7530_CPU_PORT, 1542 MT7530_VLAN_EGRESS_STACK)); 1543 } 1544 1545 static void 1546 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1547 struct mt7530_hw_vlan_entry *entry) 1548 { 1549 u8 new_members; 1550 u32 val; 1551 1552 new_members = entry->old_members & ~BIT(entry->port); 1553 1554 val = mt7530_read(priv, MT7530_VAWD1); 1555 if (!(val & VLAN_VALID)) { 1556 dev_err(priv->dev, 1557 "Cannot be deleted due to invalid entry\n"); 1558 return; 1559 } 1560 1561 /* If certain member apart from CPU port is still alive in the VLAN, 1562 * the entry would be kept valid. Otherwise, the entry is got to be 1563 * disabled. 1564 */ 1565 if (new_members && new_members != BIT(MT7530_CPU_PORT)) { 1566 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1567 VLAN_VALID; 1568 mt7530_write(priv, MT7530_VAWD1, val); 1569 } else { 1570 mt7530_write(priv, MT7530_VAWD1, 0); 1571 mt7530_write(priv, MT7530_VAWD2, 0); 1572 } 1573 } 1574 1575 static void 1576 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1577 struct mt7530_hw_vlan_entry *entry, 1578 mt7530_vlan_op vlan_op) 1579 { 1580 u32 val; 1581 1582 /* Fetch entry */ 1583 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1584 1585 val = mt7530_read(priv, MT7530_VAWD1); 1586 1587 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1588 1589 /* Manipulate entry */ 1590 vlan_op(priv, entry); 1591 1592 /* Flush result to hardware */ 1593 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1594 } 1595 1596 static int 1597 mt7530_setup_vlan0(struct mt7530_priv *priv) 1598 { 1599 u32 val; 1600 1601 /* Validate the entry with independent learning, keep the original 1602 * ingress tag attribute. 1603 */ 1604 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1605 VLAN_VALID; 1606 mt7530_write(priv, MT7530_VAWD1, val); 1607 1608 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1609 } 1610 1611 static int 1612 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1613 const struct switchdev_obj_port_vlan *vlan, 1614 struct netlink_ext_ack *extack) 1615 { 1616 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1617 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1618 struct mt7530_hw_vlan_entry new_entry; 1619 struct mt7530_priv *priv = ds->priv; 1620 1621 mutex_lock(&priv->reg_mutex); 1622 1623 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1624 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1625 1626 if (pvid) { 1627 priv->ports[port].pvid = vlan->vid; 1628 1629 /* Accept all frames if PVID is set */ 1630 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1631 MT7530_VLAN_ACC_ALL); 1632 1633 /* Only configure PVID if VLAN filtering is enabled */ 1634 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1635 mt7530_rmw(priv, MT7530_PPBV1_P(port), 1636 G0_PORT_VID_MASK, 1637 G0_PORT_VID(vlan->vid)); 1638 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 1639 /* This VLAN is overwritten without PVID, so unset it */ 1640 priv->ports[port].pvid = G0_PORT_VID_DEF; 1641 1642 /* Only accept tagged frames if the port is VLAN-aware */ 1643 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1644 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1645 MT7530_VLAN_ACC_TAGGED); 1646 1647 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1648 G0_PORT_VID_DEF); 1649 } 1650 1651 mutex_unlock(&priv->reg_mutex); 1652 1653 return 0; 1654 } 1655 1656 static int 1657 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1658 const struct switchdev_obj_port_vlan *vlan) 1659 { 1660 struct mt7530_hw_vlan_entry target_entry; 1661 struct mt7530_priv *priv = ds->priv; 1662 1663 mutex_lock(&priv->reg_mutex); 1664 1665 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1666 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1667 mt7530_hw_vlan_del); 1668 1669 /* PVID is being restored to the default whenever the PVID port 1670 * is being removed from the VLAN. 1671 */ 1672 if (priv->ports[port].pvid == vlan->vid) { 1673 priv->ports[port].pvid = G0_PORT_VID_DEF; 1674 1675 /* Only accept tagged frames if the port is VLAN-aware */ 1676 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1677 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1678 MT7530_VLAN_ACC_TAGGED); 1679 1680 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1681 G0_PORT_VID_DEF); 1682 } 1683 1684 1685 mutex_unlock(&priv->reg_mutex); 1686 1687 return 0; 1688 } 1689 1690 static int mt753x_mirror_port_get(unsigned int id, u32 val) 1691 { 1692 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : 1693 MIRROR_PORT(val); 1694 } 1695 1696 static int mt753x_mirror_port_set(unsigned int id, u32 val) 1697 { 1698 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : 1699 MIRROR_PORT(val); 1700 } 1701 1702 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1703 struct dsa_mall_mirror_tc_entry *mirror, 1704 bool ingress) 1705 { 1706 struct mt7530_priv *priv = ds->priv; 1707 int monitor_port; 1708 u32 val; 1709 1710 /* Check for existent entry */ 1711 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1712 return -EEXIST; 1713 1714 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1715 1716 /* MT7530 only supports one monitor port */ 1717 monitor_port = mt753x_mirror_port_get(priv->id, val); 1718 if (val & MT753X_MIRROR_EN(priv->id) && 1719 monitor_port != mirror->to_local_port) 1720 return -EEXIST; 1721 1722 val |= MT753X_MIRROR_EN(priv->id); 1723 val &= ~MT753X_MIRROR_MASK(priv->id); 1724 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); 1725 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1726 1727 val = mt7530_read(priv, MT7530_PCR_P(port)); 1728 if (ingress) { 1729 val |= PORT_RX_MIR; 1730 priv->mirror_rx |= BIT(port); 1731 } else { 1732 val |= PORT_TX_MIR; 1733 priv->mirror_tx |= BIT(port); 1734 } 1735 mt7530_write(priv, MT7530_PCR_P(port), val); 1736 1737 return 0; 1738 } 1739 1740 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1741 struct dsa_mall_mirror_tc_entry *mirror) 1742 { 1743 struct mt7530_priv *priv = ds->priv; 1744 u32 val; 1745 1746 val = mt7530_read(priv, MT7530_PCR_P(port)); 1747 if (mirror->ingress) { 1748 val &= ~PORT_RX_MIR; 1749 priv->mirror_rx &= ~BIT(port); 1750 } else { 1751 val &= ~PORT_TX_MIR; 1752 priv->mirror_tx &= ~BIT(port); 1753 } 1754 mt7530_write(priv, MT7530_PCR_P(port), val); 1755 1756 if (!priv->mirror_rx && !priv->mirror_tx) { 1757 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1758 val &= ~MT753X_MIRROR_EN(priv->id); 1759 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1760 } 1761 } 1762 1763 static enum dsa_tag_protocol 1764 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1765 enum dsa_tag_protocol mp) 1766 { 1767 return DSA_TAG_PROTO_MTK; 1768 } 1769 1770 #ifdef CONFIG_GPIOLIB 1771 static inline u32 1772 mt7530_gpio_to_bit(unsigned int offset) 1773 { 1774 /* Map GPIO offset to register bit 1775 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1776 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1777 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1778 * [14:12] port 3 LED 0..2 as GPIO 9..11 1779 * [18:16] port 4 LED 0..2 as GPIO 12..14 1780 */ 1781 return BIT(offset + offset / 3); 1782 } 1783 1784 static int 1785 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1786 { 1787 struct mt7530_priv *priv = gpiochip_get_data(gc); 1788 u32 bit = mt7530_gpio_to_bit(offset); 1789 1790 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1791 } 1792 1793 static void 1794 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1795 { 1796 struct mt7530_priv *priv = gpiochip_get_data(gc); 1797 u32 bit = mt7530_gpio_to_bit(offset); 1798 1799 if (value) 1800 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1801 else 1802 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1803 } 1804 1805 static int 1806 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1807 { 1808 struct mt7530_priv *priv = gpiochip_get_data(gc); 1809 u32 bit = mt7530_gpio_to_bit(offset); 1810 1811 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1812 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1813 } 1814 1815 static int 1816 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1817 { 1818 struct mt7530_priv *priv = gpiochip_get_data(gc); 1819 u32 bit = mt7530_gpio_to_bit(offset); 1820 1821 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 1822 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 1823 1824 return 0; 1825 } 1826 1827 static int 1828 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 1829 { 1830 struct mt7530_priv *priv = gpiochip_get_data(gc); 1831 u32 bit = mt7530_gpio_to_bit(offset); 1832 1833 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 1834 1835 if (value) 1836 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1837 else 1838 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1839 1840 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 1841 1842 return 0; 1843 } 1844 1845 static int 1846 mt7530_setup_gpio(struct mt7530_priv *priv) 1847 { 1848 struct device *dev = priv->dev; 1849 struct gpio_chip *gc; 1850 1851 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1852 if (!gc) 1853 return -ENOMEM; 1854 1855 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 1856 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 1857 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 1858 1859 gc->label = "mt7530"; 1860 gc->parent = dev; 1861 gc->owner = THIS_MODULE; 1862 gc->get_direction = mt7530_gpio_get_direction; 1863 gc->direction_input = mt7530_gpio_direction_input; 1864 gc->direction_output = mt7530_gpio_direction_output; 1865 gc->get = mt7530_gpio_get; 1866 gc->set = mt7530_gpio_set; 1867 gc->base = -1; 1868 gc->ngpio = 15; 1869 gc->can_sleep = true; 1870 1871 return devm_gpiochip_add_data(dev, gc, priv); 1872 } 1873 #endif /* CONFIG_GPIOLIB */ 1874 1875 static irqreturn_t 1876 mt7530_irq_thread_fn(int irq, void *dev_id) 1877 { 1878 struct mt7530_priv *priv = dev_id; 1879 bool handled = false; 1880 u32 val; 1881 int p; 1882 1883 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 1884 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); 1885 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); 1886 mutex_unlock(&priv->bus->mdio_lock); 1887 1888 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1889 if (BIT(p) & val) { 1890 unsigned int irq; 1891 1892 irq = irq_find_mapping(priv->irq_domain, p); 1893 handle_nested_irq(irq); 1894 handled = true; 1895 } 1896 } 1897 1898 return IRQ_RETVAL(handled); 1899 } 1900 1901 static void 1902 mt7530_irq_mask(struct irq_data *d) 1903 { 1904 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1905 1906 priv->irq_enable &= ~BIT(d->hwirq); 1907 } 1908 1909 static void 1910 mt7530_irq_unmask(struct irq_data *d) 1911 { 1912 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1913 1914 priv->irq_enable |= BIT(d->hwirq); 1915 } 1916 1917 static void 1918 mt7530_irq_bus_lock(struct irq_data *d) 1919 { 1920 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1921 1922 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 1923 } 1924 1925 static void 1926 mt7530_irq_bus_sync_unlock(struct irq_data *d) 1927 { 1928 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1929 1930 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 1931 mutex_unlock(&priv->bus->mdio_lock); 1932 } 1933 1934 static struct irq_chip mt7530_irq_chip = { 1935 .name = KBUILD_MODNAME, 1936 .irq_mask = mt7530_irq_mask, 1937 .irq_unmask = mt7530_irq_unmask, 1938 .irq_bus_lock = mt7530_irq_bus_lock, 1939 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, 1940 }; 1941 1942 static int 1943 mt7530_irq_map(struct irq_domain *domain, unsigned int irq, 1944 irq_hw_number_t hwirq) 1945 { 1946 irq_set_chip_data(irq, domain->host_data); 1947 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); 1948 irq_set_nested_thread(irq, true); 1949 irq_set_noprobe(irq); 1950 1951 return 0; 1952 } 1953 1954 static const struct irq_domain_ops mt7530_irq_domain_ops = { 1955 .map = mt7530_irq_map, 1956 .xlate = irq_domain_xlate_onecell, 1957 }; 1958 1959 static void 1960 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 1961 { 1962 struct dsa_switch *ds = priv->ds; 1963 int p; 1964 1965 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1966 if (BIT(p) & ds->phys_mii_mask) { 1967 unsigned int irq; 1968 1969 irq = irq_create_mapping(priv->irq_domain, p); 1970 ds->slave_mii_bus->irq[p] = irq; 1971 } 1972 } 1973 } 1974 1975 static int 1976 mt7530_setup_irq(struct mt7530_priv *priv) 1977 { 1978 struct device *dev = priv->dev; 1979 struct device_node *np = dev->of_node; 1980 int ret; 1981 1982 if (!of_property_read_bool(np, "interrupt-controller")) { 1983 dev_info(dev, "no interrupt support\n"); 1984 return 0; 1985 } 1986 1987 priv->irq = of_irq_get(np, 0); 1988 if (priv->irq <= 0) { 1989 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); 1990 return priv->irq ? : -EINVAL; 1991 } 1992 1993 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 1994 &mt7530_irq_domain_ops, priv); 1995 if (!priv->irq_domain) { 1996 dev_err(dev, "failed to create IRQ domain\n"); 1997 return -ENOMEM; 1998 } 1999 2000 /* This register must be set for MT7530 to properly fire interrupts */ 2001 if (priv->id != ID_MT7531) 2002 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 2003 2004 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, 2005 IRQF_ONESHOT, KBUILD_MODNAME, priv); 2006 if (ret) { 2007 irq_domain_remove(priv->irq_domain); 2008 dev_err(dev, "failed to request IRQ: %d\n", ret); 2009 return ret; 2010 } 2011 2012 return 0; 2013 } 2014 2015 static void 2016 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2017 { 2018 int p; 2019 2020 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2021 if (BIT(p) & priv->ds->phys_mii_mask) { 2022 unsigned int irq; 2023 2024 irq = irq_find_mapping(priv->irq_domain, p); 2025 irq_dispose_mapping(irq); 2026 } 2027 } 2028 } 2029 2030 static void 2031 mt7530_free_irq_common(struct mt7530_priv *priv) 2032 { 2033 free_irq(priv->irq, priv); 2034 irq_domain_remove(priv->irq_domain); 2035 } 2036 2037 static void 2038 mt7530_free_irq(struct mt7530_priv *priv) 2039 { 2040 mt7530_free_mdio_irq(priv); 2041 mt7530_free_irq_common(priv); 2042 } 2043 2044 static int 2045 mt7530_setup_mdio(struct mt7530_priv *priv) 2046 { 2047 struct dsa_switch *ds = priv->ds; 2048 struct device *dev = priv->dev; 2049 struct mii_bus *bus; 2050 static int idx; 2051 int ret; 2052 2053 bus = devm_mdiobus_alloc(dev); 2054 if (!bus) 2055 return -ENOMEM; 2056 2057 ds->slave_mii_bus = bus; 2058 bus->priv = priv; 2059 bus->name = KBUILD_MODNAME "-mii"; 2060 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2061 bus->read = mt753x_phy_read; 2062 bus->write = mt753x_phy_write; 2063 bus->parent = dev; 2064 bus->phy_mask = ~ds->phys_mii_mask; 2065 2066 if (priv->irq) 2067 mt7530_setup_mdio_irq(priv); 2068 2069 ret = mdiobus_register(bus); 2070 if (ret) { 2071 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2072 if (priv->irq) 2073 mt7530_free_mdio_irq(priv); 2074 } 2075 2076 return ret; 2077 } 2078 2079 static int 2080 mt7530_setup(struct dsa_switch *ds) 2081 { 2082 struct mt7530_priv *priv = ds->priv; 2083 struct device_node *phy_node; 2084 struct device_node *mac_np; 2085 struct mt7530_dummy_poll p; 2086 phy_interface_t interface; 2087 struct device_node *dn; 2088 u32 id, val; 2089 int ret, i; 2090 2091 /* The parent node of master netdev which holds the common system 2092 * controller also is the container for two GMACs nodes representing 2093 * as two netdev instances. 2094 */ 2095 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent; 2096 ds->assisted_learning_on_cpu_port = true; 2097 ds->mtu_enforcement_ingress = true; 2098 2099 if (priv->id == ID_MT7530) { 2100 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2101 ret = regulator_enable(priv->core_pwr); 2102 if (ret < 0) { 2103 dev_err(priv->dev, 2104 "Failed to enable core power: %d\n", ret); 2105 return ret; 2106 } 2107 2108 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2109 ret = regulator_enable(priv->io_pwr); 2110 if (ret < 0) { 2111 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2112 ret); 2113 return ret; 2114 } 2115 } 2116 2117 /* Reset whole chip through gpio pin or memory-mapped registers for 2118 * different type of hardware 2119 */ 2120 if (priv->mcm) { 2121 reset_control_assert(priv->rstc); 2122 usleep_range(1000, 1100); 2123 reset_control_deassert(priv->rstc); 2124 } else { 2125 gpiod_set_value_cansleep(priv->reset, 0); 2126 usleep_range(1000, 1100); 2127 gpiod_set_value_cansleep(priv->reset, 1); 2128 } 2129 2130 /* Waiting for MT7530 got to stable */ 2131 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2132 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2133 20, 1000000); 2134 if (ret < 0) { 2135 dev_err(priv->dev, "reset timeout\n"); 2136 return ret; 2137 } 2138 2139 id = mt7530_read(priv, MT7530_CREV); 2140 id >>= CHIP_NAME_SHIFT; 2141 if (id != MT7530_ID) { 2142 dev_err(priv->dev, "chip %x can't be supported\n", id); 2143 return -ENODEV; 2144 } 2145 2146 /* Reset the switch through internal reset */ 2147 mt7530_write(priv, MT7530_SYS_CTRL, 2148 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2149 SYS_CTRL_REG_RST); 2150 2151 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */ 2152 val = mt7530_read(priv, MT7530_MHWTRAP); 2153 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 2154 val |= MHWTRAP_MANUAL; 2155 mt7530_write(priv, MT7530_MHWTRAP, val); 2156 2157 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2158 2159 /* Enable and reset MIB counters */ 2160 mt7530_mib_reset(ds); 2161 2162 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2163 /* Disable forwarding by default on all ports */ 2164 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2165 PCR_MATRIX_CLR); 2166 2167 /* Disable learning by default on all ports */ 2168 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2169 2170 if (dsa_is_cpu_port(ds, i)) { 2171 ret = mt753x_cpu_port_enable(ds, i); 2172 if (ret) 2173 return ret; 2174 } else { 2175 mt7530_port_disable(ds, i); 2176 2177 /* Set default PVID to 0 on all user ports */ 2178 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2179 G0_PORT_VID_DEF); 2180 } 2181 /* Enable consistent egress tag */ 2182 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2183 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2184 } 2185 2186 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2187 ret = mt7530_setup_vlan0(priv); 2188 if (ret) 2189 return ret; 2190 2191 /* Setup port 5 */ 2192 priv->p5_intf_sel = P5_DISABLED; 2193 interface = PHY_INTERFACE_MODE_NA; 2194 2195 if (!dsa_is_unused_port(ds, 5)) { 2196 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2197 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); 2198 if (ret && ret != -ENODEV) 2199 return ret; 2200 } else { 2201 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ 2202 for_each_child_of_node(dn, mac_np) { 2203 if (!of_device_is_compatible(mac_np, 2204 "mediatek,eth-mac")) 2205 continue; 2206 2207 ret = of_property_read_u32(mac_np, "reg", &id); 2208 if (ret < 0 || id != 1) 2209 continue; 2210 2211 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2212 if (!phy_node) 2213 continue; 2214 2215 if (phy_node->parent == priv->dev->of_node->parent) { 2216 ret = of_get_phy_mode(mac_np, &interface); 2217 if (ret && ret != -ENODEV) { 2218 of_node_put(mac_np); 2219 return ret; 2220 } 2221 id = of_mdio_parse_addr(ds->dev, phy_node); 2222 if (id == 0) 2223 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 2224 if (id == 4) 2225 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 2226 } 2227 of_node_put(mac_np); 2228 of_node_put(phy_node); 2229 break; 2230 } 2231 } 2232 2233 #ifdef CONFIG_GPIOLIB 2234 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2235 ret = mt7530_setup_gpio(priv); 2236 if (ret) 2237 return ret; 2238 } 2239 #endif /* CONFIG_GPIOLIB */ 2240 2241 mt7530_setup_port5(ds, interface); 2242 2243 /* Flush the FDB table */ 2244 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2245 if (ret < 0) 2246 return ret; 2247 2248 return 0; 2249 } 2250 2251 static int 2252 mt7531_setup(struct dsa_switch *ds) 2253 { 2254 struct mt7530_priv *priv = ds->priv; 2255 struct mt7530_dummy_poll p; 2256 u32 val, id; 2257 int ret, i; 2258 2259 /* Reset whole chip through gpio pin or memory-mapped registers for 2260 * different type of hardware 2261 */ 2262 if (priv->mcm) { 2263 reset_control_assert(priv->rstc); 2264 usleep_range(1000, 1100); 2265 reset_control_deassert(priv->rstc); 2266 } else { 2267 gpiod_set_value_cansleep(priv->reset, 0); 2268 usleep_range(1000, 1100); 2269 gpiod_set_value_cansleep(priv->reset, 1); 2270 } 2271 2272 /* Waiting for MT7530 got to stable */ 2273 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2274 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2275 20, 1000000); 2276 if (ret < 0) { 2277 dev_err(priv->dev, "reset timeout\n"); 2278 return ret; 2279 } 2280 2281 id = mt7530_read(priv, MT7531_CREV); 2282 id >>= CHIP_NAME_SHIFT; 2283 2284 if (id != MT7531_ID) { 2285 dev_err(priv->dev, "chip %x can't be supported\n", id); 2286 return -ENODEV; 2287 } 2288 2289 /* Reset the switch through internal reset */ 2290 mt7530_write(priv, MT7530_SYS_CTRL, 2291 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2292 SYS_CTRL_REG_RST); 2293 2294 if (mt7531_dual_sgmii_supported(priv)) { 2295 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; 2296 2297 /* Let ds->slave_mii_bus be able to access external phy. */ 2298 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2299 MT7531_EXT_P_MDC_11); 2300 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2301 MT7531_EXT_P_MDIO_12); 2302 } else { 2303 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2304 } 2305 dev_dbg(ds->dev, "P5 support %s interface\n", 2306 p5_intf_modes(priv->p5_intf_sel)); 2307 2308 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2309 MT7531_GPIO0_INTERRUPT); 2310 2311 /* Let phylink decide the interface later. */ 2312 priv->p5_interface = PHY_INTERFACE_MODE_NA; 2313 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2314 2315 /* Enable PHY core PLL, since phy_device has not yet been created 2316 * provided for phy_[read,write]_mmd_indirect is called, we provide 2317 * our own mt7531_ind_mmd_phy_[read,write] to complete this 2318 * function. 2319 */ 2320 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, 2321 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2322 val |= MT7531_PHY_PLL_BYPASS_MODE; 2323 val &= ~MT7531_PHY_PLL_OFF; 2324 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, 2325 CORE_PLL_GROUP4, val); 2326 2327 /* BPDU to CPU port */ 2328 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, 2329 BIT(MT7530_CPU_PORT)); 2330 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, 2331 MT753X_BPDU_CPU_ONLY); 2332 2333 /* Enable and reset MIB counters */ 2334 mt7530_mib_reset(ds); 2335 2336 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2337 /* Disable forwarding by default on all ports */ 2338 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2339 PCR_MATRIX_CLR); 2340 2341 /* Disable learning by default on all ports */ 2342 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2343 2344 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2345 2346 if (dsa_is_cpu_port(ds, i)) { 2347 ret = mt753x_cpu_port_enable(ds, i); 2348 if (ret) 2349 return ret; 2350 } else { 2351 mt7530_port_disable(ds, i); 2352 2353 /* Set default PVID to 0 on all user ports */ 2354 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2355 G0_PORT_VID_DEF); 2356 } 2357 2358 /* Enable consistent egress tag */ 2359 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2360 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2361 } 2362 2363 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2364 ret = mt7530_setup_vlan0(priv); 2365 if (ret) 2366 return ret; 2367 2368 ds->assisted_learning_on_cpu_port = true; 2369 ds->mtu_enforcement_ingress = true; 2370 2371 /* Flush the FDB table */ 2372 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2373 if (ret < 0) 2374 return ret; 2375 2376 return 0; 2377 } 2378 2379 static bool 2380 mt7530_phy_mode_supported(struct dsa_switch *ds, int port, 2381 const struct phylink_link_state *state) 2382 { 2383 struct mt7530_priv *priv = ds->priv; 2384 2385 switch (port) { 2386 case 0 ... 4: /* Internal phy */ 2387 if (state->interface != PHY_INTERFACE_MODE_GMII) 2388 return false; 2389 break; 2390 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2391 if (!phy_interface_mode_is_rgmii(state->interface) && 2392 state->interface != PHY_INTERFACE_MODE_MII && 2393 state->interface != PHY_INTERFACE_MODE_GMII) 2394 return false; 2395 break; 2396 case 6: /* 1st cpu port */ 2397 if (state->interface != PHY_INTERFACE_MODE_RGMII && 2398 state->interface != PHY_INTERFACE_MODE_TRGMII) 2399 return false; 2400 break; 2401 default: 2402 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, 2403 port); 2404 return false; 2405 } 2406 2407 return true; 2408 } 2409 2410 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) 2411 { 2412 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); 2413 } 2414 2415 static bool 2416 mt7531_phy_mode_supported(struct dsa_switch *ds, int port, 2417 const struct phylink_link_state *state) 2418 { 2419 struct mt7530_priv *priv = ds->priv; 2420 2421 switch (port) { 2422 case 0 ... 4: /* Internal phy */ 2423 if (state->interface != PHY_INTERFACE_MODE_GMII) 2424 return false; 2425 break; 2426 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ 2427 if (mt7531_is_rgmii_port(priv, port)) 2428 return phy_interface_mode_is_rgmii(state->interface); 2429 fallthrough; 2430 case 6: /* 1st cpu port supports sgmii/8023z only */ 2431 if (state->interface != PHY_INTERFACE_MODE_SGMII && 2432 !phy_interface_mode_is_8023z(state->interface)) 2433 return false; 2434 break; 2435 default: 2436 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, 2437 port); 2438 return false; 2439 } 2440 2441 return true; 2442 } 2443 2444 static bool 2445 mt753x_phy_mode_supported(struct dsa_switch *ds, int port, 2446 const struct phylink_link_state *state) 2447 { 2448 struct mt7530_priv *priv = ds->priv; 2449 2450 return priv->info->phy_mode_supported(ds, port, state); 2451 } 2452 2453 static int 2454 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) 2455 { 2456 struct mt7530_priv *priv = ds->priv; 2457 2458 return priv->info->pad_setup(ds, state->interface); 2459 } 2460 2461 static int 2462 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2463 phy_interface_t interface) 2464 { 2465 struct mt7530_priv *priv = ds->priv; 2466 2467 /* Only need to setup port5. */ 2468 if (port != 5) 2469 return 0; 2470 2471 mt7530_setup_port5(priv->ds, interface); 2472 2473 return 0; 2474 } 2475 2476 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 2477 phy_interface_t interface, 2478 struct phy_device *phydev) 2479 { 2480 u32 val; 2481 2482 if (!mt7531_is_rgmii_port(priv, port)) { 2483 dev_err(priv->dev, "RGMII mode is not available for port %d\n", 2484 port); 2485 return -EINVAL; 2486 } 2487 2488 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2489 val |= GP_CLK_EN; 2490 val &= ~GP_MODE_MASK; 2491 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2492 val &= ~CLK_SKEW_IN_MASK; 2493 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2494 val &= ~CLK_SKEW_OUT_MASK; 2495 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2496 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2497 2498 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2499 if (!phydev || phy_driver_is_genphy(phydev)) { 2500 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2501 switch (interface) { 2502 case PHY_INTERFACE_MODE_RGMII: 2503 val |= TXCLK_NO_REVERSE; 2504 val |= RXCLK_NO_DELAY; 2505 break; 2506 case PHY_INTERFACE_MODE_RGMII_RXID: 2507 val |= TXCLK_NO_REVERSE; 2508 break; 2509 case PHY_INTERFACE_MODE_RGMII_TXID: 2510 val |= RXCLK_NO_DELAY; 2511 break; 2512 case PHY_INTERFACE_MODE_RGMII_ID: 2513 break; 2514 default: 2515 return -EINVAL; 2516 } 2517 } 2518 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2519 2520 return 0; 2521 } 2522 2523 static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port, 2524 unsigned long *supported) 2525 { 2526 /* Port5 supports ethier RGMII or SGMII. 2527 * Port6 supports SGMII only. 2528 */ 2529 switch (port) { 2530 case 5: 2531 if (mt7531_is_rgmii_port(priv, port)) 2532 break; 2533 fallthrough; 2534 case 6: 2535 phylink_set(supported, 1000baseX_Full); 2536 phylink_set(supported, 2500baseX_Full); 2537 phylink_set(supported, 2500baseT_Full); 2538 } 2539 } 2540 2541 static void 2542 mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port, 2543 unsigned int mode, phy_interface_t interface, 2544 int speed, int duplex) 2545 { 2546 struct mt7530_priv *priv = ds->priv; 2547 unsigned int val; 2548 2549 /* For adjusting speed and duplex of SGMII force mode. */ 2550 if (interface != PHY_INTERFACE_MODE_SGMII || 2551 phylink_autoneg_inband(mode)) 2552 return; 2553 2554 /* SGMII force mode setting */ 2555 val = mt7530_read(priv, MT7531_SGMII_MODE(port)); 2556 val &= ~MT7531_SGMII_IF_MODE_MASK; 2557 2558 switch (speed) { 2559 case SPEED_10: 2560 val |= MT7531_SGMII_FORCE_SPEED_10; 2561 break; 2562 case SPEED_100: 2563 val |= MT7531_SGMII_FORCE_SPEED_100; 2564 break; 2565 case SPEED_1000: 2566 val |= MT7531_SGMII_FORCE_SPEED_1000; 2567 break; 2568 } 2569 2570 /* MT7531 SGMII 1G force mode can only work in full duplex mode, 2571 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2572 */ 2573 if ((speed == SPEED_10 || speed == SPEED_100) && 2574 duplex != DUPLEX_FULL) 2575 val |= MT7531_SGMII_FORCE_HALF_DUPLEX; 2576 2577 mt7530_write(priv, MT7531_SGMII_MODE(port), val); 2578 } 2579 2580 static bool mt753x_is_mac_port(u32 port) 2581 { 2582 return (port == 5 || port == 6); 2583 } 2584 2585 static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port, 2586 phy_interface_t interface) 2587 { 2588 u32 val; 2589 2590 if (!mt753x_is_mac_port(port)) 2591 return -EINVAL; 2592 2593 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2594 MT7531_SGMII_PHYA_PWD); 2595 2596 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port)); 2597 val &= ~MT7531_RG_TPHY_SPEED_MASK; 2598 /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B 2599 * encoding. 2600 */ 2601 val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ? 2602 MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G; 2603 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val); 2604 2605 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2606 2607 /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex 2608 * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2609 */ 2610 mt7530_rmw(priv, MT7531_SGMII_MODE(port), 2611 MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS, 2612 MT7531_SGMII_FORCE_SPEED_1000); 2613 2614 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2615 2616 return 0; 2617 } 2618 2619 static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port, 2620 phy_interface_t interface) 2621 { 2622 if (!mt753x_is_mac_port(port)) 2623 return -EINVAL; 2624 2625 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2626 MT7531_SGMII_PHYA_PWD); 2627 2628 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), 2629 MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G); 2630 2631 mt7530_set(priv, MT7531_SGMII_MODE(port), 2632 MT7531_SGMII_REMOTE_FAULT_DIS | 2633 MT7531_SGMII_SPEED_DUPLEX_AN); 2634 2635 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port), 2636 MT7531_SGMII_TX_CONFIG_MASK, 1); 2637 2638 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2639 2640 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART); 2641 2642 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2643 2644 return 0; 2645 } 2646 2647 static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port) 2648 { 2649 struct mt7530_priv *priv = ds->priv; 2650 u32 val; 2651 2652 /* Only restart AN when AN is enabled */ 2653 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2654 if (val & MT7531_SGMII_AN_ENABLE) { 2655 val |= MT7531_SGMII_AN_RESTART; 2656 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val); 2657 } 2658 } 2659 2660 static int 2661 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2662 phy_interface_t interface) 2663 { 2664 struct mt7530_priv *priv = ds->priv; 2665 struct phy_device *phydev; 2666 struct dsa_port *dp; 2667 2668 if (!mt753x_is_mac_port(port)) { 2669 dev_err(priv->dev, "port %d is not a MAC port\n", port); 2670 return -EINVAL; 2671 } 2672 2673 switch (interface) { 2674 case PHY_INTERFACE_MODE_RGMII: 2675 case PHY_INTERFACE_MODE_RGMII_ID: 2676 case PHY_INTERFACE_MODE_RGMII_RXID: 2677 case PHY_INTERFACE_MODE_RGMII_TXID: 2678 dp = dsa_to_port(ds, port); 2679 phydev = dp->slave->phydev; 2680 return mt7531_rgmii_setup(priv, port, interface, phydev); 2681 case PHY_INTERFACE_MODE_SGMII: 2682 return mt7531_sgmii_setup_mode_an(priv, port, interface); 2683 case PHY_INTERFACE_MODE_NA: 2684 case PHY_INTERFACE_MODE_1000BASEX: 2685 case PHY_INTERFACE_MODE_2500BASEX: 2686 if (phylink_autoneg_inband(mode)) 2687 return -EINVAL; 2688 2689 return mt7531_sgmii_setup_mode_force(priv, port, interface); 2690 default: 2691 return -EINVAL; 2692 } 2693 2694 return -EINVAL; 2695 } 2696 2697 static int 2698 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2699 const struct phylink_link_state *state) 2700 { 2701 struct mt7530_priv *priv = ds->priv; 2702 2703 return priv->info->mac_port_config(ds, port, mode, state->interface); 2704 } 2705 2706 static void 2707 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2708 const struct phylink_link_state *state) 2709 { 2710 struct mt7530_priv *priv = ds->priv; 2711 u32 mcr_cur, mcr_new; 2712 2713 if (!mt753x_phy_mode_supported(ds, port, state)) 2714 goto unsupported; 2715 2716 switch (port) { 2717 case 0 ... 4: /* Internal phy */ 2718 if (state->interface != PHY_INTERFACE_MODE_GMII) 2719 goto unsupported; 2720 break; 2721 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2722 if (priv->p5_interface == state->interface) 2723 break; 2724 2725 if (mt753x_mac_config(ds, port, mode, state) < 0) 2726 goto unsupported; 2727 2728 if (priv->p5_intf_sel != P5_DISABLED) 2729 priv->p5_interface = state->interface; 2730 break; 2731 case 6: /* 1st cpu port */ 2732 if (priv->p6_interface == state->interface) 2733 break; 2734 2735 mt753x_pad_setup(ds, state); 2736 2737 if (mt753x_mac_config(ds, port, mode, state) < 0) 2738 goto unsupported; 2739 2740 priv->p6_interface = state->interface; 2741 break; 2742 default: 2743 unsupported: 2744 dev_err(ds->dev, "%s: unsupported %s port: %i\n", 2745 __func__, phy_modes(state->interface), port); 2746 return; 2747 } 2748 2749 if (phylink_autoneg_inband(mode) && 2750 state->interface != PHY_INTERFACE_MODE_SGMII) { 2751 dev_err(ds->dev, "%s: in-band negotiation unsupported\n", 2752 __func__); 2753 return; 2754 } 2755 2756 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); 2757 mcr_new = mcr_cur; 2758 mcr_new &= ~PMCR_LINK_SETTINGS_MASK; 2759 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | 2760 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); 2761 2762 /* Are we connected to external phy */ 2763 if (port == 5 && dsa_is_user_port(ds, 5)) 2764 mcr_new |= PMCR_EXT_PHY; 2765 2766 if (mcr_new != mcr_cur) 2767 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); 2768 } 2769 2770 static void 2771 mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port) 2772 { 2773 struct mt7530_priv *priv = ds->priv; 2774 2775 if (!priv->info->mac_pcs_an_restart) 2776 return; 2777 2778 priv->info->mac_pcs_an_restart(ds, port); 2779 } 2780 2781 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, 2782 unsigned int mode, 2783 phy_interface_t interface) 2784 { 2785 struct mt7530_priv *priv = ds->priv; 2786 2787 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 2788 } 2789 2790 static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port, 2791 unsigned int mode, phy_interface_t interface, 2792 int speed, int duplex) 2793 { 2794 struct mt7530_priv *priv = ds->priv; 2795 2796 if (!priv->info->mac_pcs_link_up) 2797 return; 2798 2799 priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex); 2800 } 2801 2802 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, 2803 unsigned int mode, 2804 phy_interface_t interface, 2805 struct phy_device *phydev, 2806 int speed, int duplex, 2807 bool tx_pause, bool rx_pause) 2808 { 2809 struct mt7530_priv *priv = ds->priv; 2810 u32 mcr; 2811 2812 mt753x_mac_pcs_link_up(ds, port, mode, interface, speed, duplex); 2813 2814 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; 2815 2816 /* MT753x MAC works in 1G full duplex mode for all up-clocked 2817 * variants. 2818 */ 2819 if (interface == PHY_INTERFACE_MODE_TRGMII || 2820 (phy_interface_mode_is_8023z(interface))) { 2821 speed = SPEED_1000; 2822 duplex = DUPLEX_FULL; 2823 } 2824 2825 switch (speed) { 2826 case SPEED_1000: 2827 mcr |= PMCR_FORCE_SPEED_1000; 2828 break; 2829 case SPEED_100: 2830 mcr |= PMCR_FORCE_SPEED_100; 2831 break; 2832 } 2833 if (duplex == DUPLEX_FULL) { 2834 mcr |= PMCR_FORCE_FDX; 2835 if (tx_pause) 2836 mcr |= PMCR_TX_FC_EN; 2837 if (rx_pause) 2838 mcr |= PMCR_RX_FC_EN; 2839 } 2840 2841 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, 0) >= 0) { 2842 switch (speed) { 2843 case SPEED_1000: 2844 mcr |= PMCR_FORCE_EEE1G; 2845 break; 2846 case SPEED_100: 2847 mcr |= PMCR_FORCE_EEE100; 2848 break; 2849 } 2850 } 2851 2852 mt7530_set(priv, MT7530_PMCR_P(port), mcr); 2853 } 2854 2855 static int 2856 mt7531_cpu_port_config(struct dsa_switch *ds, int port) 2857 { 2858 struct mt7530_priv *priv = ds->priv; 2859 phy_interface_t interface; 2860 int speed; 2861 int ret; 2862 2863 switch (port) { 2864 case 5: 2865 if (mt7531_is_rgmii_port(priv, port)) 2866 interface = PHY_INTERFACE_MODE_RGMII; 2867 else 2868 interface = PHY_INTERFACE_MODE_2500BASEX; 2869 2870 priv->p5_interface = interface; 2871 break; 2872 case 6: 2873 interface = PHY_INTERFACE_MODE_2500BASEX; 2874 2875 mt7531_pad_setup(ds, interface); 2876 2877 priv->p6_interface = interface; 2878 break; 2879 default: 2880 return -EINVAL; 2881 } 2882 2883 if (interface == PHY_INTERFACE_MODE_2500BASEX) 2884 speed = SPEED_2500; 2885 else 2886 speed = SPEED_1000; 2887 2888 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); 2889 if (ret) 2890 return ret; 2891 mt7530_write(priv, MT7530_PMCR_P(port), 2892 PMCR_CPU_PORT_SETTING(priv->id)); 2893 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, 2894 speed, DUPLEX_FULL, true, true); 2895 2896 return 0; 2897 } 2898 2899 static void 2900 mt7530_mac_port_validate(struct dsa_switch *ds, int port, 2901 unsigned long *supported) 2902 { 2903 if (port == 5) 2904 phylink_set(supported, 1000baseX_Full); 2905 } 2906 2907 static void mt7531_mac_port_validate(struct dsa_switch *ds, int port, 2908 unsigned long *supported) 2909 { 2910 struct mt7530_priv *priv = ds->priv; 2911 2912 mt7531_sgmii_validate(priv, port, supported); 2913 } 2914 2915 static void 2916 mt753x_phylink_validate(struct dsa_switch *ds, int port, 2917 unsigned long *supported, 2918 struct phylink_link_state *state) 2919 { 2920 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 2921 struct mt7530_priv *priv = ds->priv; 2922 2923 if (state->interface != PHY_INTERFACE_MODE_NA && 2924 !mt753x_phy_mode_supported(ds, port, state)) { 2925 linkmode_zero(supported); 2926 return; 2927 } 2928 2929 phylink_set_port_modes(mask); 2930 2931 if (state->interface != PHY_INTERFACE_MODE_TRGMII || 2932 !phy_interface_mode_is_8023z(state->interface)) { 2933 phylink_set(mask, 10baseT_Half); 2934 phylink_set(mask, 10baseT_Full); 2935 phylink_set(mask, 100baseT_Half); 2936 phylink_set(mask, 100baseT_Full); 2937 phylink_set(mask, Autoneg); 2938 } 2939 2940 /* This switch only supports 1G full-duplex. */ 2941 if (state->interface != PHY_INTERFACE_MODE_MII) 2942 phylink_set(mask, 1000baseT_Full); 2943 2944 priv->info->mac_port_validate(ds, port, mask); 2945 2946 phylink_set(mask, Pause); 2947 phylink_set(mask, Asym_Pause); 2948 2949 linkmode_and(supported, supported, mask); 2950 linkmode_and(state->advertising, state->advertising, mask); 2951 2952 /* We can only operate at 2500BaseX or 1000BaseX. If requested 2953 * to advertise both, only report advertising at 2500BaseX. 2954 */ 2955 phylink_helper_basex_speed(state); 2956 } 2957 2958 static int 2959 mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port, 2960 struct phylink_link_state *state) 2961 { 2962 struct mt7530_priv *priv = ds->priv; 2963 u32 pmsr; 2964 2965 if (port < 0 || port >= MT7530_NUM_PORTS) 2966 return -EINVAL; 2967 2968 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2969 2970 state->link = (pmsr & PMSR_LINK); 2971 state->an_complete = state->link; 2972 state->duplex = !!(pmsr & PMSR_DPX); 2973 2974 switch (pmsr & PMSR_SPEED_MASK) { 2975 case PMSR_SPEED_10: 2976 state->speed = SPEED_10; 2977 break; 2978 case PMSR_SPEED_100: 2979 state->speed = SPEED_100; 2980 break; 2981 case PMSR_SPEED_1000: 2982 state->speed = SPEED_1000; 2983 break; 2984 default: 2985 state->speed = SPEED_UNKNOWN; 2986 break; 2987 } 2988 2989 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 2990 if (pmsr & PMSR_RX_FC) 2991 state->pause |= MLO_PAUSE_RX; 2992 if (pmsr & PMSR_TX_FC) 2993 state->pause |= MLO_PAUSE_TX; 2994 2995 return 1; 2996 } 2997 2998 static int 2999 mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port, 3000 struct phylink_link_state *state) 3001 { 3002 u32 status, val; 3003 u16 config_reg; 3004 3005 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 3006 state->link = !!(status & MT7531_SGMII_LINK_STATUS); 3007 if (state->interface == PHY_INTERFACE_MODE_SGMII && 3008 (status & MT7531_SGMII_AN_ENABLE)) { 3009 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port)); 3010 config_reg = val >> 16; 3011 3012 switch (config_reg & LPA_SGMII_SPD_MASK) { 3013 case LPA_SGMII_1000: 3014 state->speed = SPEED_1000; 3015 break; 3016 case LPA_SGMII_100: 3017 state->speed = SPEED_100; 3018 break; 3019 case LPA_SGMII_10: 3020 state->speed = SPEED_10; 3021 break; 3022 default: 3023 dev_err(priv->dev, "invalid sgmii PHY speed\n"); 3024 state->link = false; 3025 return -EINVAL; 3026 } 3027 3028 if (config_reg & LPA_SGMII_FULL_DUPLEX) 3029 state->duplex = DUPLEX_FULL; 3030 else 3031 state->duplex = DUPLEX_HALF; 3032 } 3033 3034 return 0; 3035 } 3036 3037 static int 3038 mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port, 3039 struct phylink_link_state *state) 3040 { 3041 struct mt7530_priv *priv = ds->priv; 3042 3043 if (state->interface == PHY_INTERFACE_MODE_SGMII) 3044 return mt7531_sgmii_pcs_get_state_an(priv, port, state); 3045 3046 return -EOPNOTSUPP; 3047 } 3048 3049 static int 3050 mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port, 3051 struct phylink_link_state *state) 3052 { 3053 struct mt7530_priv *priv = ds->priv; 3054 3055 return priv->info->mac_port_get_state(ds, port, state); 3056 } 3057 3058 static int 3059 mt753x_setup(struct dsa_switch *ds) 3060 { 3061 struct mt7530_priv *priv = ds->priv; 3062 int ret = priv->info->sw_setup(ds); 3063 3064 if (ret) 3065 return ret; 3066 3067 ret = mt7530_setup_irq(priv); 3068 if (ret) 3069 return ret; 3070 3071 ret = mt7530_setup_mdio(priv); 3072 if (ret && priv->irq) 3073 mt7530_free_irq_common(priv); 3074 3075 return ret; 3076 } 3077 3078 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, 3079 struct ethtool_eee *e) 3080 { 3081 struct mt7530_priv *priv = ds->priv; 3082 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); 3083 3084 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); 3085 e->tx_lpi_timer = GET_LPI_THRESH(eeecr); 3086 3087 return 0; 3088 } 3089 3090 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3091 struct ethtool_eee *e) 3092 { 3093 struct mt7530_priv *priv = ds->priv; 3094 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN; 3095 3096 if (e->tx_lpi_timer > 0xFFF) 3097 return -EINVAL; 3098 3099 set = SET_LPI_THRESH(e->tx_lpi_timer); 3100 if (!e->tx_lpi_enabled) 3101 /* Force LPI Mode without a delay */ 3102 set |= LPI_MODE_EN; 3103 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); 3104 3105 return 0; 3106 } 3107 3108 static const struct dsa_switch_ops mt7530_switch_ops = { 3109 .get_tag_protocol = mtk_get_tag_protocol, 3110 .setup = mt753x_setup, 3111 .get_strings = mt7530_get_strings, 3112 .get_ethtool_stats = mt7530_get_ethtool_stats, 3113 .get_sset_count = mt7530_get_sset_count, 3114 .set_ageing_time = mt7530_set_ageing_time, 3115 .port_enable = mt7530_port_enable, 3116 .port_disable = mt7530_port_disable, 3117 .port_change_mtu = mt7530_port_change_mtu, 3118 .port_max_mtu = mt7530_port_max_mtu, 3119 .port_stp_state_set = mt7530_stp_state_set, 3120 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3121 .port_bridge_flags = mt7530_port_bridge_flags, 3122 .port_bridge_join = mt7530_port_bridge_join, 3123 .port_bridge_leave = mt7530_port_bridge_leave, 3124 .port_fdb_add = mt7530_port_fdb_add, 3125 .port_fdb_del = mt7530_port_fdb_del, 3126 .port_fdb_dump = mt7530_port_fdb_dump, 3127 .port_mdb_add = mt7530_port_mdb_add, 3128 .port_mdb_del = mt7530_port_mdb_del, 3129 .port_vlan_filtering = mt7530_port_vlan_filtering, 3130 .port_vlan_add = mt7530_port_vlan_add, 3131 .port_vlan_del = mt7530_port_vlan_del, 3132 .port_mirror_add = mt753x_port_mirror_add, 3133 .port_mirror_del = mt753x_port_mirror_del, 3134 .phylink_validate = mt753x_phylink_validate, 3135 .phylink_mac_link_state = mt753x_phylink_mac_link_state, 3136 .phylink_mac_config = mt753x_phylink_mac_config, 3137 .phylink_mac_an_restart = mt753x_phylink_mac_an_restart, 3138 .phylink_mac_link_down = mt753x_phylink_mac_link_down, 3139 .phylink_mac_link_up = mt753x_phylink_mac_link_up, 3140 .get_mac_eee = mt753x_get_mac_eee, 3141 .set_mac_eee = mt753x_set_mac_eee, 3142 }; 3143 3144 static const struct mt753x_info mt753x_table[] = { 3145 [ID_MT7621] = { 3146 .id = ID_MT7621, 3147 .sw_setup = mt7530_setup, 3148 .phy_read = mt7530_phy_read, 3149 .phy_write = mt7530_phy_write, 3150 .pad_setup = mt7530_pad_clk_setup, 3151 .phy_mode_supported = mt7530_phy_mode_supported, 3152 .mac_port_validate = mt7530_mac_port_validate, 3153 .mac_port_get_state = mt7530_phylink_mac_link_state, 3154 .mac_port_config = mt7530_mac_config, 3155 }, 3156 [ID_MT7530] = { 3157 .id = ID_MT7530, 3158 .sw_setup = mt7530_setup, 3159 .phy_read = mt7530_phy_read, 3160 .phy_write = mt7530_phy_write, 3161 .pad_setup = mt7530_pad_clk_setup, 3162 .phy_mode_supported = mt7530_phy_mode_supported, 3163 .mac_port_validate = mt7530_mac_port_validate, 3164 .mac_port_get_state = mt7530_phylink_mac_link_state, 3165 .mac_port_config = mt7530_mac_config, 3166 }, 3167 [ID_MT7531] = { 3168 .id = ID_MT7531, 3169 .sw_setup = mt7531_setup, 3170 .phy_read = mt7531_ind_phy_read, 3171 .phy_write = mt7531_ind_phy_write, 3172 .pad_setup = mt7531_pad_setup, 3173 .cpu_port_config = mt7531_cpu_port_config, 3174 .phy_mode_supported = mt7531_phy_mode_supported, 3175 .mac_port_validate = mt7531_mac_port_validate, 3176 .mac_port_get_state = mt7531_phylink_mac_link_state, 3177 .mac_port_config = mt7531_mac_config, 3178 .mac_pcs_an_restart = mt7531_sgmii_restart_an, 3179 .mac_pcs_link_up = mt7531_sgmii_link_up_force, 3180 }, 3181 }; 3182 3183 static const struct of_device_id mt7530_of_match[] = { 3184 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], }, 3185 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], }, 3186 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], }, 3187 { /* sentinel */ }, 3188 }; 3189 MODULE_DEVICE_TABLE(of, mt7530_of_match); 3190 3191 static int 3192 mt7530_probe(struct mdio_device *mdiodev) 3193 { 3194 struct mt7530_priv *priv; 3195 struct device_node *dn; 3196 3197 dn = mdiodev->dev.of_node; 3198 3199 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 3200 if (!priv) 3201 return -ENOMEM; 3202 3203 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); 3204 if (!priv->ds) 3205 return -ENOMEM; 3206 3207 priv->ds->dev = &mdiodev->dev; 3208 priv->ds->num_ports = MT7530_NUM_PORTS; 3209 3210 /* Use medatek,mcm property to distinguish hardware type that would 3211 * casues a little bit differences on power-on sequence. 3212 */ 3213 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); 3214 if (priv->mcm) { 3215 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); 3216 3217 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); 3218 if (IS_ERR(priv->rstc)) { 3219 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 3220 return PTR_ERR(priv->rstc); 3221 } 3222 } 3223 3224 /* Get the hardware identifier from the devicetree node. 3225 * We will need it for some of the clock and regulator setup. 3226 */ 3227 priv->info = of_device_get_match_data(&mdiodev->dev); 3228 if (!priv->info) 3229 return -EINVAL; 3230 3231 /* Sanity check if these required device operations are filled 3232 * properly. 3233 */ 3234 if (!priv->info->sw_setup || !priv->info->pad_setup || 3235 !priv->info->phy_read || !priv->info->phy_write || 3236 !priv->info->phy_mode_supported || 3237 !priv->info->mac_port_validate || 3238 !priv->info->mac_port_get_state || !priv->info->mac_port_config) 3239 return -EINVAL; 3240 3241 priv->id = priv->info->id; 3242 3243 if (priv->id == ID_MT7530) { 3244 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); 3245 if (IS_ERR(priv->core_pwr)) 3246 return PTR_ERR(priv->core_pwr); 3247 3248 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); 3249 if (IS_ERR(priv->io_pwr)) 3250 return PTR_ERR(priv->io_pwr); 3251 } 3252 3253 /* Not MCM that indicates switch works as the remote standalone 3254 * integrated circuit so the GPIO pin would be used to complete 3255 * the reset, otherwise memory-mapped register accessing used 3256 * through syscon provides in the case of MCM. 3257 */ 3258 if (!priv->mcm) { 3259 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", 3260 GPIOD_OUT_LOW); 3261 if (IS_ERR(priv->reset)) { 3262 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 3263 return PTR_ERR(priv->reset); 3264 } 3265 } 3266 3267 priv->bus = mdiodev->bus; 3268 priv->dev = &mdiodev->dev; 3269 priv->ds->priv = priv; 3270 priv->ds->ops = &mt7530_switch_ops; 3271 mutex_init(&priv->reg_mutex); 3272 dev_set_drvdata(&mdiodev->dev, priv); 3273 3274 return dsa_register_switch(priv->ds); 3275 } 3276 3277 static void 3278 mt7530_remove(struct mdio_device *mdiodev) 3279 { 3280 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 3281 int ret = 0; 3282 3283 if (!priv) 3284 return; 3285 3286 ret = regulator_disable(priv->core_pwr); 3287 if (ret < 0) 3288 dev_err(priv->dev, 3289 "Failed to disable core power: %d\n", ret); 3290 3291 ret = regulator_disable(priv->io_pwr); 3292 if (ret < 0) 3293 dev_err(priv->dev, "Failed to disable io pwr: %d\n", 3294 ret); 3295 3296 if (priv->irq) 3297 mt7530_free_irq(priv); 3298 3299 dsa_unregister_switch(priv->ds); 3300 mutex_destroy(&priv->reg_mutex); 3301 3302 dev_set_drvdata(&mdiodev->dev, NULL); 3303 } 3304 3305 static void mt7530_shutdown(struct mdio_device *mdiodev) 3306 { 3307 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 3308 3309 if (!priv) 3310 return; 3311 3312 dsa_switch_shutdown(priv->ds); 3313 3314 dev_set_drvdata(&mdiodev->dev, NULL); 3315 } 3316 3317 static struct mdio_driver mt7530_mdio_driver = { 3318 .probe = mt7530_probe, 3319 .remove = mt7530_remove, 3320 .shutdown = mt7530_shutdown, 3321 .mdiodrv.driver = { 3322 .name = "mt7530", 3323 .of_match_table = mt7530_of_match, 3324 }, 3325 }; 3326 3327 mdio_module_driver(mt7530_mdio_driver); 3328 3329 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3330 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3331 MODULE_LICENSE("GPL"); 3332