1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Microchip LAN937X switch register definitions
3  * Copyright (C) 2019-2021 Microchip Technology Inc.
4  */
5 #ifndef __LAN937X_REG_H
6 #define __LAN937X_REG_H
7 
8 #define PORT_CTRL_ADDR(port, addr)	((addr) | (((port) + 1)  << 12))
9 
10 /* 0 - Operation */
11 #define REG_GLOBAL_CTRL_0		0x0007
12 
13 #define SW_PHY_REG_BLOCK		BIT(7)
14 #define SW_FAST_MODE			BIT(3)
15 #define SW_FAST_MODE_OVERRIDE		BIT(2)
16 
17 #define REG_SW_INT_STATUS__4		0x0010
18 #define REG_SW_INT_MASK__4		0x0014
19 
20 #define LUE_INT				BIT(31)
21 #define TRIG_TS_INT			BIT(30)
22 #define APB_TIMEOUT_INT			BIT(29)
23 #define OVER_TEMP_INT			BIT(28)
24 #define HSR_INT				BIT(27)
25 #define PIO_INT				BIT(26)
26 #define POR_READY_INT			BIT(25)
27 
28 #define SWITCH_INT_MASK			\
29 	(LUE_INT | TRIG_TS_INT | APB_TIMEOUT_INT | OVER_TEMP_INT | HSR_INT | \
30 	 PIO_INT | POR_READY_INT)
31 
32 #define REG_SW_PORT_INT_STATUS__4	0x0018
33 #define REG_SW_PORT_INT_MASK__4		0x001C
34 
35 /* 1 - Global */
36 #define REG_SW_GLOBAL_OUTPUT_CTRL__1	0x0103
37 #define SW_CLK125_ENB			BIT(1)
38 #define SW_CLK25_ENB			BIT(0)
39 
40 /* 3 - Operation Control */
41 #define REG_SW_OPERATION		0x0300
42 
43 #define SW_DOUBLE_TAG			BIT(7)
44 #define SW_OVER_TEMP_ENABLE		BIT(2)
45 #define SW_RESET			BIT(1)
46 
47 #define REG_SW_LUE_CTRL_0		0x0310
48 
49 #define SW_VLAN_ENABLE			BIT(7)
50 #define SW_DROP_INVALID_VID		BIT(6)
51 #define SW_AGE_CNT_M			0x7
52 #define SW_AGE_CNT_S			3
53 #define SW_RESV_MCAST_ENABLE		BIT(2)
54 
55 #define REG_SW_LUE_CTRL_1		0x0311
56 
57 #define UNICAST_LEARN_DISABLE		BIT(7)
58 #define SW_FLUSH_STP_TABLE		BIT(5)
59 #define SW_FLUSH_MSTP_TABLE		BIT(4)
60 #define SW_SRC_ADDR_FILTER		BIT(3)
61 #define SW_AGING_ENABLE			BIT(2)
62 #define SW_FAST_AGING			BIT(1)
63 #define SW_LINK_AUTO_AGING		BIT(0)
64 
65 #define REG_SW_AGE_PERIOD__1		0x0313
66 #define SW_AGE_PERIOD_7_0_M		GENMASK(7, 0)
67 
68 #define REG_SW_AGE_PERIOD__2		0x0320
69 #define SW_AGE_PERIOD_19_8_M		GENMASK(19, 8)
70 
71 #define REG_SW_MAC_CTRL_0		0x0330
72 #define SW_NEW_BACKOFF			BIT(7)
73 #define SW_PAUSE_UNH_MODE		BIT(1)
74 #define SW_AGGR_BACKOFF			BIT(0)
75 
76 #define REG_SW_MAC_CTRL_1		0x0331
77 #define SW_SHORT_IFG			BIT(7)
78 #define MULTICAST_STORM_DISABLE		BIT(6)
79 #define SW_BACK_PRESSURE		BIT(5)
80 #define FAIR_FLOW_CTRL			BIT(4)
81 #define NO_EXC_COLLISION_DROP		BIT(3)
82 #define SW_LEGAL_PACKET_DISABLE		BIT(1)
83 #define SW_PASS_SHORT_FRAME		BIT(0)
84 
85 #define REG_SW_MAC_CTRL_6		0x0336
86 #define SW_MIB_COUNTER_FLUSH		BIT(7)
87 #define SW_MIB_COUNTER_FREEZE		BIT(6)
88 
89 /* 4 - LUE */
90 #define REG_SW_ALU_STAT_CTRL__4		0x041C
91 
92 #define REG_SW_ALU_VAL_B		0x0424
93 #define ALU_V_OVERRIDE			BIT(31)
94 #define ALU_V_USE_FID			BIT(30)
95 #define ALU_V_PORT_MAP			0xFF
96 
97 /* 7 - VPhy */
98 #define REG_VPHY_IND_ADDR__2		0x075C
99 #define REG_VPHY_IND_DATA__2		0x0760
100 
101 #define REG_VPHY_IND_CTRL__2		0x0768
102 
103 #define VPHY_IND_WRITE			BIT(1)
104 #define VPHY_IND_BUSY			BIT(0)
105 
106 #define REG_VPHY_SPECIAL_CTRL__2	0x077C
107 #define VPHY_SMI_INDIRECT_ENABLE	BIT(15)
108 #define VPHY_SW_LOOPBACK		BIT(14)
109 #define VPHY_MDIO_INTERNAL_ENABLE	BIT(13)
110 #define VPHY_SPI_INDIRECT_ENABLE	BIT(12)
111 #define VPHY_PORT_MODE_M		0x3
112 #define VPHY_PORT_MODE_S		8
113 #define VPHY_MODE_RGMII			0
114 #define VPHY_MODE_MII_PHY		1
115 #define VPHY_MODE_SGMII			2
116 #define VPHY_MODE_RMII_PHY		3
117 #define VPHY_SW_COLLISION_TEST		BIT(7)
118 #define VPHY_SPEED_DUPLEX_STAT_M	0x7
119 #define VPHY_SPEED_DUPLEX_STAT_S	2
120 #define VPHY_SPEED_1000			BIT(4)
121 #define VPHY_SPEED_100			BIT(3)
122 #define VPHY_FULL_DUPLEX		BIT(2)
123 
124 /* Port Registers */
125 
126 /* 0 - Operation */
127 #define REG_PORT_INT_STATUS		0x001B
128 #define REG_PORT_INT_MASK		0x001F
129 
130 #define PORT_TAS_INT			BIT(5)
131 #define PORT_QCI_INT			BIT(4)
132 #define PORT_SGMII_INT			BIT(3)
133 #define PORT_PTP_INT			BIT(2)
134 #define PORT_PHY_INT			BIT(1)
135 #define PORT_ACL_INT			BIT(0)
136 
137 #define PORT_SRC_PHY_INT		1
138 
139 #define REG_PORT_CTRL_0			0x0020
140 
141 #define PORT_MAC_LOOPBACK		BIT(7)
142 #define PORT_MAC_REMOTE_LOOPBACK	BIT(6)
143 #define PORT_K2L_INSERT_ENABLE		BIT(5)
144 #define PORT_K2L_DEBUG_ENABLE		BIT(4)
145 #define PORT_TAIL_TAG_ENABLE		BIT(2)
146 #define PORT_QUEUE_SPLIT_ENABLE		0x3
147 
148 /* 1 - Phy */
149 #define REG_PORT_T1_PHY_CTRL_BASE	0x0100
150 
151 /* 3 - xMII */
152 #define PORT_SGMII_SEL			BIT(7)
153 #define PORT_GRXC_ENABLE		BIT(0)
154 
155 #define PORT_MII_SEL_EDGE		BIT(5)
156 
157 #define REG_PORT_XMII_CTRL_4		0x0304
158 #define REG_PORT_XMII_CTRL_5		0x0306
159 
160 #define PORT_DLL_RESET			BIT(15)
161 #define PORT_TUNE_ADJ			GENMASK(13, 7)
162 
163 /* 4 - MAC */
164 #define REG_PORT_MAC_CTRL_0		0x0400
165 #define PORT_CHECK_LENGTH		BIT(2)
166 #define PORT_BROADCAST_STORM		BIT(1)
167 #define PORT_JUMBO_PACKET		BIT(0)
168 
169 #define REG_PORT_MAC_CTRL_1		0x0401
170 #define PORT_BACK_PRESSURE		BIT(3)
171 #define PORT_PASS_ALL			BIT(0)
172 
173 #define PORT_MAX_FR_SIZE		0x404
174 #define FR_MIN_SIZE		1522
175 
176 /* 8 - Classification and Policing */
177 #define REG_PORT_MRI_PRIO_CTRL		0x0801
178 #define PORT_HIGHEST_PRIO		BIT(7)
179 #define PORT_OR_PRIO			BIT(6)
180 #define PORT_MAC_PRIO_ENABLE		BIT(4)
181 #define PORT_VLAN_PRIO_ENABLE		BIT(3)
182 #define PORT_802_1P_PRIO_ENABLE		BIT(2)
183 #define PORT_DIFFSERV_PRIO_ENABLE	BIT(1)
184 #define PORT_ACL_PRIO_ENABLE		BIT(0)
185 
186 #define P_PRIO_CTRL			REG_PORT_MRI_PRIO_CTRL
187 
188 /* 9 - Shaping */
189 #define REG_PORT_MTI_CREDIT_INCREMENT	0x091C
190 
191 /* The port number as per the datasheet */
192 #define RGMII_2_PORT_NUM		5
193 #define RGMII_1_PORT_NUM		6
194 
195 #define LAN937X_RGMII_2_PORT		(RGMII_2_PORT_NUM - 1)
196 #define LAN937X_RGMII_1_PORT		(RGMII_1_PORT_NUM - 1)
197 
198 #define RGMII_1_TX_DELAY_2NS		2
199 #define RGMII_2_TX_DELAY_2NS		0
200 #define RGMII_1_RX_DELAY_2NS		0x1B
201 #define RGMII_2_RX_DELAY_2NS		0x14
202 
203 #define LAN937X_TAG_LEN			2
204 
205 #endif
206