1 // SPDX-License-Identifier: GPL-2.0 2 /* Microchip LAN937X switch driver main logic 3 * Copyright (C) 2019-2022 Microchip Technology Inc. 4 */ 5 #include <linux/kernel.h> 6 #include <linux/module.h> 7 #include <linux/iopoll.h> 8 #include <linux/phy.h> 9 #include <linux/of_net.h> 10 #include <linux/of_mdio.h> 11 #include <linux/if_bridge.h> 12 #include <linux/if_vlan.h> 13 #include <linux/math.h> 14 #include <net/dsa.h> 15 #include <net/switchdev.h> 16 17 #include "lan937x_reg.h" 18 #include "ksz_common.h" 19 #include "lan937x.h" 20 21 static int lan937x_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 22 { 23 return regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0); 24 } 25 26 static int lan937x_port_cfg(struct ksz_device *dev, int port, int offset, 27 u8 bits, bool set) 28 { 29 return regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset), 30 bits, set ? bits : 0); 31 } 32 33 static int lan937x_enable_spi_indirect_access(struct ksz_device *dev) 34 { 35 u16 data16; 36 int ret; 37 38 /* Enable Phy access through SPI */ 39 ret = lan937x_cfg(dev, REG_GLOBAL_CTRL_0, SW_PHY_REG_BLOCK, false); 40 if (ret < 0) 41 return ret; 42 43 ret = ksz_read16(dev, REG_VPHY_SPECIAL_CTRL__2, &data16); 44 if (ret < 0) 45 return ret; 46 47 /* Allow SPI access */ 48 data16 |= VPHY_SPI_INDIRECT_ENABLE; 49 50 return ksz_write16(dev, REG_VPHY_SPECIAL_CTRL__2, data16); 51 } 52 53 static int lan937x_vphy_ind_addr_wr(struct ksz_device *dev, int addr, int reg) 54 { 55 u16 addr_base = REG_PORT_T1_PHY_CTRL_BASE; 56 u16 temp; 57 58 /* get register address based on the logical port */ 59 temp = PORT_CTRL_ADDR(addr, (addr_base + (reg << 2))); 60 61 return ksz_write16(dev, REG_VPHY_IND_ADDR__2, temp); 62 } 63 64 static int lan937x_internal_phy_write(struct ksz_device *dev, int addr, int reg, 65 u16 val) 66 { 67 unsigned int value; 68 int ret; 69 70 /* Check for internal phy port */ 71 if (!dev->info->internal_phy[addr]) 72 return -EOPNOTSUPP; 73 74 ret = lan937x_vphy_ind_addr_wr(dev, addr, reg); 75 if (ret < 0) 76 return ret; 77 78 /* Write the data to be written to the VPHY reg */ 79 ret = ksz_write16(dev, REG_VPHY_IND_DATA__2, val); 80 if (ret < 0) 81 return ret; 82 83 /* Write the Write En and Busy bit */ 84 ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2, 85 (VPHY_IND_WRITE | VPHY_IND_BUSY)); 86 if (ret < 0) 87 return ret; 88 89 ret = regmap_read_poll_timeout(dev->regmap[1], REG_VPHY_IND_CTRL__2, 90 value, !(value & VPHY_IND_BUSY), 10, 91 1000); 92 if (ret < 0) { 93 dev_err(dev->dev, "Failed to write phy register\n"); 94 return ret; 95 } 96 97 return 0; 98 } 99 100 static int lan937x_internal_phy_read(struct ksz_device *dev, int addr, int reg, 101 u16 *val) 102 { 103 unsigned int value; 104 int ret; 105 106 /* Check for internal phy port, return 0xffff for non-existent phy */ 107 if (!dev->info->internal_phy[addr]) 108 return 0xffff; 109 110 ret = lan937x_vphy_ind_addr_wr(dev, addr, reg); 111 if (ret < 0) 112 return ret; 113 114 /* Write Read and Busy bit to start the transaction */ 115 ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2, VPHY_IND_BUSY); 116 if (ret < 0) 117 return ret; 118 119 ret = regmap_read_poll_timeout(dev->regmap[1], REG_VPHY_IND_CTRL__2, 120 value, !(value & VPHY_IND_BUSY), 10, 121 1000); 122 if (ret < 0) { 123 dev_err(dev->dev, "Failed to read phy register\n"); 124 return ret; 125 } 126 127 /* Read the VPHY register which has the PHY data */ 128 return ksz_read16(dev, REG_VPHY_IND_DATA__2, val); 129 } 130 131 void lan937x_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data) 132 { 133 lan937x_internal_phy_read(dev, addr, reg, data); 134 } 135 136 void lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val) 137 { 138 lan937x_internal_phy_write(dev, addr, reg, val); 139 } 140 141 static int lan937x_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 142 { 143 struct ksz_device *dev = bus->priv; 144 u16 val; 145 int ret; 146 147 if (regnum & MII_ADDR_C45) 148 return -EOPNOTSUPP; 149 150 ret = lan937x_internal_phy_read(dev, addr, regnum, &val); 151 if (ret < 0) 152 return ret; 153 154 return val; 155 } 156 157 static int lan937x_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 158 u16 val) 159 { 160 struct ksz_device *dev = bus->priv; 161 162 if (regnum & MII_ADDR_C45) 163 return -EOPNOTSUPP; 164 165 return lan937x_internal_phy_write(dev, addr, regnum, val); 166 } 167 168 static int lan937x_mdio_register(struct ksz_device *dev) 169 { 170 struct dsa_switch *ds = dev->ds; 171 struct device_node *mdio_np; 172 struct mii_bus *bus; 173 int ret; 174 175 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); 176 if (!mdio_np) { 177 dev_err(ds->dev, "no MDIO bus node\n"); 178 return -ENODEV; 179 } 180 181 bus = devm_mdiobus_alloc(ds->dev); 182 if (!bus) { 183 of_node_put(mdio_np); 184 return -ENOMEM; 185 } 186 187 bus->priv = dev; 188 bus->read = lan937x_sw_mdio_read; 189 bus->write = lan937x_sw_mdio_write; 190 bus->name = "lan937x slave smi"; 191 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); 192 bus->parent = ds->dev; 193 bus->phy_mask = ~ds->phys_mii_mask; 194 195 ds->slave_mii_bus = bus; 196 197 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); 198 if (ret) { 199 dev_err(ds->dev, "unable to register MDIO bus %s\n", 200 bus->id); 201 } 202 203 of_node_put(mdio_np); 204 205 return ret; 206 } 207 208 int lan937x_reset_switch(struct ksz_device *dev) 209 { 210 u32 data32; 211 int ret; 212 213 /* reset switch */ 214 ret = lan937x_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 215 if (ret < 0) 216 return ret; 217 218 /* Enable Auto Aging */ 219 ret = lan937x_cfg(dev, REG_SW_LUE_CTRL_1, SW_LINK_AUTO_AGING, true); 220 if (ret < 0) 221 return ret; 222 223 /* disable interrupts */ 224 ret = ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 225 if (ret < 0) 226 return ret; 227 228 ret = ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0xFF); 229 if (ret < 0) 230 return ret; 231 232 return ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 233 } 234 235 void lan937x_port_setup(struct ksz_device *dev, int port, bool cpu_port) 236 { 237 const u32 *masks = dev->info->masks; 238 const u16 *regs = dev->info->regs; 239 struct dsa_switch *ds = dev->ds; 240 u8 member; 241 242 /* enable tag tail for host port */ 243 if (cpu_port) 244 lan937x_port_cfg(dev, port, REG_PORT_CTRL_0, 245 PORT_TAIL_TAG_ENABLE, true); 246 247 /* disable frame check length field */ 248 lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0, PORT_CHECK_LENGTH, 249 false); 250 251 /* set back pressure for half duplex */ 252 lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, 253 true); 254 255 /* enable 802.1p priority */ 256 lan937x_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); 257 258 if (!dev->info->internal_phy[port]) 259 lan937x_port_cfg(dev, port, regs[P_XMII_CTRL_0], 260 masks[P_MII_TX_FLOW_CTRL] | 261 masks[P_MII_RX_FLOW_CTRL], 262 true); 263 264 if (cpu_port) 265 member = dsa_user_ports(ds); 266 else 267 member = BIT(dsa_upstream_port(ds, port)); 268 269 dev->dev_ops->cfg_port_member(dev, port, member); 270 } 271 272 void lan937x_config_cpu_port(struct dsa_switch *ds) 273 { 274 struct ksz_device *dev = ds->priv; 275 struct dsa_port *dp; 276 277 dsa_switch_for_each_cpu_port(dp, ds) { 278 if (dev->info->cpu_ports & (1 << dp->index)) { 279 dev->cpu_port = dp->index; 280 281 /* enable cpu port */ 282 lan937x_port_setup(dev, dp->index, true); 283 } 284 } 285 286 dsa_switch_for_each_user_port(dp, ds) { 287 ksz_port_stp_state_set(ds, dp->index, BR_STATE_DISABLED); 288 } 289 } 290 291 int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu) 292 { 293 struct dsa_switch *ds = dev->ds; 294 int ret; 295 296 new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN; 297 298 if (dsa_is_cpu_port(ds, port)) 299 new_mtu += LAN937X_TAG_LEN; 300 301 if (new_mtu >= FR_MIN_SIZE) 302 ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0, 303 PORT_JUMBO_PACKET, true); 304 else 305 ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0, 306 PORT_JUMBO_PACKET, false); 307 if (ret < 0) { 308 dev_err(ds->dev, "failed to enable jumbo\n"); 309 return ret; 310 } 311 312 /* Write the frame size in PORT_MAX_FR_SIZE register */ 313 ksz_pwrite16(dev, port, PORT_MAX_FR_SIZE, new_mtu); 314 315 return 0; 316 } 317 318 static void lan937x_set_tune_adj(struct ksz_device *dev, int port, 319 u16 reg, u8 val) 320 { 321 u16 data16; 322 323 ksz_pread16(dev, port, reg, &data16); 324 325 /* Update tune Adjust */ 326 data16 |= FIELD_PREP(PORT_TUNE_ADJ, val); 327 ksz_pwrite16(dev, port, reg, data16); 328 329 /* write DLL reset to take effect */ 330 data16 |= PORT_DLL_RESET; 331 ksz_pwrite16(dev, port, reg, data16); 332 } 333 334 static void lan937x_set_rgmii_tx_delay(struct ksz_device *dev, int port) 335 { 336 u8 val; 337 338 /* Apply different codes based on the ports as per characterization 339 * results 340 */ 341 val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_TX_DELAY_2NS : 342 RGMII_2_TX_DELAY_2NS; 343 344 lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_5, val); 345 } 346 347 static void lan937x_set_rgmii_rx_delay(struct ksz_device *dev, int port) 348 { 349 u8 val; 350 351 val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_RX_DELAY_2NS : 352 RGMII_2_RX_DELAY_2NS; 353 354 lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_4, val); 355 } 356 357 void lan937x_phylink_get_caps(struct ksz_device *dev, int port, 358 struct phylink_config *config) 359 { 360 config->mac_capabilities = MAC_100FD; 361 362 if (dev->info->supports_rgmii[port]) { 363 /* MII/RMII/RGMII ports */ 364 config->mac_capabilities |= MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 365 MAC_100HD | MAC_10 | MAC_1000FD; 366 } 367 } 368 369 void lan937x_setup_rgmii_delay(struct ksz_device *dev, int port) 370 { 371 struct ksz_port *p = &dev->ports[port]; 372 373 if (p->rgmii_tx_val) { 374 lan937x_set_rgmii_tx_delay(dev, port); 375 dev_info(dev->dev, "Applied rgmii tx delay for the port %d\n", 376 port); 377 } 378 379 if (p->rgmii_rx_val) { 380 lan937x_set_rgmii_rx_delay(dev, port); 381 dev_info(dev->dev, "Applied rgmii rx delay for the port %d\n", 382 port); 383 } 384 } 385 386 int lan937x_setup(struct dsa_switch *ds) 387 { 388 struct ksz_device *dev = ds->priv; 389 int ret; 390 391 /* enable Indirect Access from SPI to the VPHY registers */ 392 ret = lan937x_enable_spi_indirect_access(dev); 393 if (ret < 0) { 394 dev_err(dev->dev, "failed to enable spi indirect access"); 395 return ret; 396 } 397 398 ret = lan937x_mdio_register(dev); 399 if (ret < 0) { 400 dev_err(dev->dev, "failed to register the mdio"); 401 return ret; 402 } 403 404 /* The VLAN aware is a global setting. Mixed vlan 405 * filterings are not supported. 406 */ 407 ds->vlan_filtering_is_global = true; 408 409 /* Enable aggressive back off for half duplex & UNH mode */ 410 lan937x_cfg(dev, REG_SW_MAC_CTRL_0, 411 (SW_PAUSE_UNH_MODE | SW_NEW_BACKOFF | SW_AGGR_BACKOFF), 412 true); 413 414 /* If NO_EXC_COLLISION_DROP bit is set, the switch will not drop 415 * packets when 16 or more collisions occur 416 */ 417 lan937x_cfg(dev, REG_SW_MAC_CTRL_1, NO_EXC_COLLISION_DROP, true); 418 419 /* enable global MIB counter freeze function */ 420 lan937x_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); 421 422 /* disable CLK125 & CLK25, 1: disable, 0: enable */ 423 lan937x_cfg(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, 424 (SW_CLK125_ENB | SW_CLK25_ENB), true); 425 426 return 0; 427 } 428 429 int lan937x_switch_init(struct ksz_device *dev) 430 { 431 dev->port_mask = (1 << dev->info->port_cnt) - 1; 432 433 return 0; 434 } 435 436 void lan937x_switch_exit(struct ksz_device *dev) 437 { 438 lan937x_reset_switch(dev); 439 } 440 441 MODULE_AUTHOR("Arun Ramadoss <arun.ramadoss@microchip.com>"); 442 MODULE_DESCRIPTION("Microchip LAN937x Series Switch DSA Driver"); 443 MODULE_LICENSE("GPL"); 444