1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 #include <linux/irq.h> 17 18 #define KSZ_MAX_NUM_PORTS 8 19 20 struct ksz_device; 21 22 struct vlan_table { 23 u32 table[3]; 24 }; 25 26 struct ksz_port_mib { 27 struct mutex cnt_mutex; /* structure access */ 28 u8 cnt_ptr; 29 u64 *counters; 30 struct rtnl_link_stats64 stats64; 31 struct ethtool_pause_stats pause_stats; 32 struct spinlock stats64_lock; 33 }; 34 35 struct ksz_mib_names { 36 int index; 37 char string[ETH_GSTRING_LEN]; 38 }; 39 40 struct ksz_chip_data { 41 u32 chip_id; 42 const char *dev_name; 43 int num_vlans; 44 int num_alus; 45 int num_statics; 46 int cpu_ports; 47 int port_cnt; 48 u8 port_nirqs; 49 const struct ksz_dev_ops *ops; 50 bool phy_errata_9477; 51 bool ksz87xx_eee_link_erratum; 52 const struct ksz_mib_names *mib_names; 53 int mib_cnt; 54 u8 reg_mib_cnt; 55 const u16 *regs; 56 const u32 *masks; 57 const u8 *shifts; 58 const u8 *xmii_ctrl0; 59 const u8 *xmii_ctrl1; 60 int stp_ctrl_reg; 61 int broadcast_ctrl_reg; 62 int multicast_ctrl_reg; 63 int start_ctrl_reg; 64 bool supports_mii[KSZ_MAX_NUM_PORTS]; 65 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 66 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 67 bool internal_phy[KSZ_MAX_NUM_PORTS]; 68 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 69 const struct regmap_access_table *wr_table; 70 const struct regmap_access_table *rd_table; 71 }; 72 73 struct ksz_irq { 74 u16 masked; 75 struct irq_chip chip; 76 struct irq_domain *domain; 77 int nirqs; 78 char name[16]; 79 }; 80 81 struct ksz_port { 82 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 83 bool learning; 84 int stp_state; 85 struct phy_device phydev; 86 87 u32 on:1; /* port is not disabled by hardware */ 88 u32 fiber:1; /* port is fiber */ 89 u32 force:1; 90 u32 read:1; /* read MIB counters in background */ 91 u32 freeze:1; /* MIB counter freeze is enabled */ 92 93 struct ksz_port_mib mib; 94 phy_interface_t interface; 95 u16 max_frame; 96 u32 rgmii_tx_val; 97 u32 rgmii_rx_val; 98 struct ksz_device *ksz_dev; 99 struct ksz_irq pirq; 100 u8 num; 101 }; 102 103 struct ksz_device { 104 struct dsa_switch *ds; 105 struct ksz_platform_data *pdata; 106 const struct ksz_chip_data *info; 107 108 struct mutex dev_mutex; /* device access */ 109 struct mutex regmap_mutex; /* regmap access */ 110 struct mutex alu_mutex; /* ALU access */ 111 struct mutex vlan_mutex; /* vlan access */ 112 const struct ksz_dev_ops *dev_ops; 113 114 struct device *dev; 115 struct regmap *regmap[3]; 116 117 void *priv; 118 int irq; 119 120 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 121 122 /* chip specific data */ 123 u32 chip_id; 124 u8 chip_rev; 125 int cpu_port; /* port connected to CPU */ 126 int phy_port_cnt; 127 phy_interface_t compat_interface; 128 bool synclko_125; 129 bool synclko_disable; 130 131 struct vlan_table *vlan_cache; 132 133 struct ksz_port *ports; 134 struct delayed_work mib_read; 135 unsigned long mib_read_interval; 136 u16 mirror_rx; 137 u16 mirror_tx; 138 u16 port_mask; 139 struct mutex lock_irq; /* IRQ Access */ 140 struct ksz_irq girq; 141 }; 142 143 /* List of supported models */ 144 enum ksz_model { 145 KSZ8563, 146 KSZ8795, 147 KSZ8794, 148 KSZ8765, 149 KSZ8830, 150 KSZ9477, 151 KSZ9896, 152 KSZ9897, 153 KSZ9893, 154 KSZ9567, 155 LAN9370, 156 LAN9371, 157 LAN9372, 158 LAN9373, 159 LAN9374, 160 }; 161 162 enum ksz_chip_id { 163 KSZ8563_CHIP_ID = 0x8563, 164 KSZ8795_CHIP_ID = 0x8795, 165 KSZ8794_CHIP_ID = 0x8794, 166 KSZ8765_CHIP_ID = 0x8765, 167 KSZ8830_CHIP_ID = 0x8830, 168 KSZ9477_CHIP_ID = 0x00947700, 169 KSZ9896_CHIP_ID = 0x00989600, 170 KSZ9897_CHIP_ID = 0x00989700, 171 KSZ9893_CHIP_ID = 0x00989300, 172 KSZ9567_CHIP_ID = 0x00956700, 173 LAN9370_CHIP_ID = 0x00937000, 174 LAN9371_CHIP_ID = 0x00937100, 175 LAN9372_CHIP_ID = 0x00937200, 176 LAN9373_CHIP_ID = 0x00937300, 177 LAN9374_CHIP_ID = 0x00937400, 178 }; 179 180 enum ksz_regs { 181 REG_IND_CTRL_0, 182 REG_IND_DATA_8, 183 REG_IND_DATA_CHECK, 184 REG_IND_DATA_HI, 185 REG_IND_DATA_LO, 186 REG_IND_MIB_CHECK, 187 REG_IND_BYTE, 188 P_FORCE_CTRL, 189 P_LINK_STATUS, 190 P_LOCAL_CTRL, 191 P_NEG_RESTART_CTRL, 192 P_REMOTE_STATUS, 193 P_SPEED_STATUS, 194 S_TAIL_TAG_CTRL, 195 P_STP_CTRL, 196 S_START_CTRL, 197 S_BROADCAST_CTRL, 198 S_MULTICAST_CTRL, 199 P_XMII_CTRL_0, 200 P_XMII_CTRL_1, 201 }; 202 203 enum ksz_masks { 204 PORT_802_1P_REMAPPING, 205 SW_TAIL_TAG_ENABLE, 206 MIB_COUNTER_OVERFLOW, 207 MIB_COUNTER_VALID, 208 VLAN_TABLE_FID, 209 VLAN_TABLE_MEMBERSHIP, 210 VLAN_TABLE_VALID, 211 STATIC_MAC_TABLE_VALID, 212 STATIC_MAC_TABLE_USE_FID, 213 STATIC_MAC_TABLE_FID, 214 STATIC_MAC_TABLE_OVERRIDE, 215 STATIC_MAC_TABLE_FWD_PORTS, 216 DYNAMIC_MAC_TABLE_ENTRIES_H, 217 DYNAMIC_MAC_TABLE_MAC_EMPTY, 218 DYNAMIC_MAC_TABLE_NOT_READY, 219 DYNAMIC_MAC_TABLE_ENTRIES, 220 DYNAMIC_MAC_TABLE_FID, 221 DYNAMIC_MAC_TABLE_SRC_PORT, 222 DYNAMIC_MAC_TABLE_TIMESTAMP, 223 ALU_STAT_WRITE, 224 ALU_STAT_READ, 225 P_MII_TX_FLOW_CTRL, 226 P_MII_RX_FLOW_CTRL, 227 }; 228 229 enum ksz_shifts { 230 VLAN_TABLE_MEMBERSHIP_S, 231 VLAN_TABLE, 232 STATIC_MAC_FWD_PORTS, 233 STATIC_MAC_FID, 234 DYNAMIC_MAC_ENTRIES_H, 235 DYNAMIC_MAC_ENTRIES, 236 DYNAMIC_MAC_FID, 237 DYNAMIC_MAC_TIMESTAMP, 238 DYNAMIC_MAC_SRC_PORT, 239 ALU_STAT_INDEX, 240 }; 241 242 enum ksz_xmii_ctrl0 { 243 P_MII_100MBIT, 244 P_MII_10MBIT, 245 P_MII_FULL_DUPLEX, 246 P_MII_HALF_DUPLEX, 247 }; 248 249 enum ksz_xmii_ctrl1 { 250 P_RGMII_SEL, 251 P_RMII_SEL, 252 P_GMII_SEL, 253 P_MII_SEL, 254 P_GMII_1GBIT, 255 P_GMII_NOT_1GBIT, 256 }; 257 258 struct alu_struct { 259 /* entry 1 */ 260 u8 is_static:1; 261 u8 is_src_filter:1; 262 u8 is_dst_filter:1; 263 u8 prio_age:3; 264 u32 _reserv_0_1:23; 265 u8 mstp:3; 266 /* entry 2 */ 267 u8 is_override:1; 268 u8 is_use_fid:1; 269 u32 _reserv_1_1:23; 270 u8 port_forward:7; 271 /* entry 3 & 4*/ 272 u32 _reserv_2_1:9; 273 u8 fid:7; 274 u8 mac[ETH_ALEN]; 275 }; 276 277 struct ksz_dev_ops { 278 int (*setup)(struct dsa_switch *ds); 279 void (*teardown)(struct dsa_switch *ds); 280 u32 (*get_port_addr)(int port, int offset); 281 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 282 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 283 void (*port_cleanup)(struct ksz_device *dev, int port); 284 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 285 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); 286 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 287 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 288 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 289 u64 *cnt); 290 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 291 u64 *dropped, u64 *cnt); 292 void (*r_mib_stat64)(struct ksz_device *dev, int port); 293 int (*vlan_filtering)(struct ksz_device *dev, int port, 294 bool flag, struct netlink_ext_ack *extack); 295 int (*vlan_add)(struct ksz_device *dev, int port, 296 const struct switchdev_obj_port_vlan *vlan, 297 struct netlink_ext_ack *extack); 298 int (*vlan_del)(struct ksz_device *dev, int port, 299 const struct switchdev_obj_port_vlan *vlan); 300 int (*mirror_add)(struct ksz_device *dev, int port, 301 struct dsa_mall_mirror_tc_entry *mirror, 302 bool ingress, struct netlink_ext_ack *extack); 303 void (*mirror_del)(struct ksz_device *dev, int port, 304 struct dsa_mall_mirror_tc_entry *mirror); 305 int (*fdb_add)(struct ksz_device *dev, int port, 306 const unsigned char *addr, u16 vid, struct dsa_db db); 307 int (*fdb_del)(struct ksz_device *dev, int port, 308 const unsigned char *addr, u16 vid, struct dsa_db db); 309 int (*fdb_dump)(struct ksz_device *dev, int port, 310 dsa_fdb_dump_cb_t *cb, void *data); 311 int (*mdb_add)(struct ksz_device *dev, int port, 312 const struct switchdev_obj_port_mdb *mdb, 313 struct dsa_db db); 314 int (*mdb_del)(struct ksz_device *dev, int port, 315 const struct switchdev_obj_port_mdb *mdb, 316 struct dsa_db db); 317 void (*get_caps)(struct ksz_device *dev, int port, 318 struct phylink_config *config); 319 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 320 int (*max_mtu)(struct ksz_device *dev, int port); 321 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 322 void (*port_init_cnt)(struct ksz_device *dev, int port); 323 void (*phylink_mac_config)(struct ksz_device *dev, int port, 324 unsigned int mode, 325 const struct phylink_link_state *state); 326 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 327 unsigned int mode, 328 phy_interface_t interface, 329 struct phy_device *phydev, int speed, 330 int duplex, bool tx_pause, bool rx_pause); 331 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 332 void (*config_cpu_port)(struct dsa_switch *ds); 333 int (*enable_stp_addr)(struct ksz_device *dev); 334 int (*reset)(struct ksz_device *dev); 335 int (*init)(struct ksz_device *dev); 336 void (*exit)(struct ksz_device *dev); 337 }; 338 339 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 340 int ksz_switch_register(struct ksz_device *dev); 341 void ksz_switch_remove(struct ksz_device *dev); 342 343 void ksz_init_mib_timer(struct ksz_device *dev); 344 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 345 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 346 bool ksz_get_gbit(struct ksz_device *dev, int port); 347 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 348 extern const struct ksz_chip_data ksz_switch_chips[]; 349 350 /* Common register access functions */ 351 352 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 353 { 354 unsigned int value; 355 int ret = regmap_read(dev->regmap[0], reg, &value); 356 357 if (ret) 358 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 359 ERR_PTR(ret)); 360 361 *val = value; 362 return ret; 363 } 364 365 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 366 { 367 unsigned int value; 368 int ret = regmap_read(dev->regmap[1], reg, &value); 369 370 if (ret) 371 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 372 ERR_PTR(ret)); 373 374 *val = value; 375 return ret; 376 } 377 378 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 379 { 380 unsigned int value; 381 int ret = regmap_read(dev->regmap[2], reg, &value); 382 383 if (ret) 384 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 385 ERR_PTR(ret)); 386 387 *val = value; 388 return ret; 389 } 390 391 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 392 { 393 u32 value[2]; 394 int ret; 395 396 ret = regmap_bulk_read(dev->regmap[2], reg, value, 2); 397 if (ret) 398 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 399 ERR_PTR(ret)); 400 else 401 *val = (u64)value[0] << 32 | value[1]; 402 403 return ret; 404 } 405 406 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 407 { 408 int ret; 409 410 ret = regmap_write(dev->regmap[0], reg, value); 411 if (ret) 412 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 413 ERR_PTR(ret)); 414 415 return ret; 416 } 417 418 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 419 { 420 int ret; 421 422 ret = regmap_write(dev->regmap[1], reg, value); 423 if (ret) 424 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 425 ERR_PTR(ret)); 426 427 return ret; 428 } 429 430 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 431 { 432 int ret; 433 434 ret = regmap_write(dev->regmap[2], reg, value); 435 if (ret) 436 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 437 ERR_PTR(ret)); 438 439 return ret; 440 } 441 442 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 443 { 444 u32 val[2]; 445 446 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 447 value = swab64(value); 448 val[0] = swab32(value & 0xffffffffULL); 449 val[1] = swab32(value >> 32ULL); 450 451 return regmap_bulk_write(dev->regmap[2], reg, val, 2); 452 } 453 454 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 455 u8 *data) 456 { 457 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 458 } 459 460 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 461 u16 *data) 462 { 463 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 464 } 465 466 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 467 u32 *data) 468 { 469 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 470 } 471 472 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 473 u8 data) 474 { 475 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 476 } 477 478 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 479 u16 data) 480 { 481 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 482 data); 483 } 484 485 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 486 u32 data) 487 { 488 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 489 data); 490 } 491 492 static inline void ksz_prmw8(struct ksz_device *dev, int port, int offset, 493 u8 mask, u8 val) 494 { 495 regmap_update_bits(dev->regmap[0], 496 dev->dev_ops->get_port_addr(port, offset), 497 mask, val); 498 } 499 500 static inline void ksz_regmap_lock(void *__mtx) 501 { 502 struct mutex *mtx = __mtx; 503 mutex_lock(mtx); 504 } 505 506 static inline void ksz_regmap_unlock(void *__mtx) 507 { 508 struct mutex *mtx = __mtx; 509 mutex_unlock(mtx); 510 } 511 512 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 513 { 514 return dev->chip_id == KSZ8830_CHIP_ID; 515 } 516 517 static inline int is_lan937x(struct ksz_device *dev) 518 { 519 return dev->chip_id == LAN9370_CHIP_ID || 520 dev->chip_id == LAN9371_CHIP_ID || 521 dev->chip_id == LAN9372_CHIP_ID || 522 dev->chip_id == LAN9373_CHIP_ID || 523 dev->chip_id == LAN9374_CHIP_ID; 524 } 525 526 /* STP State Defines */ 527 #define PORT_TX_ENABLE BIT(2) 528 #define PORT_RX_ENABLE BIT(1) 529 #define PORT_LEARN_DISABLE BIT(0) 530 531 /* Switch ID Defines */ 532 #define REG_CHIP_ID0 0x00 533 534 #define SW_FAMILY_ID_M GENMASK(15, 8) 535 #define KSZ87_FAMILY_ID 0x87 536 #define KSZ88_FAMILY_ID 0x88 537 538 #define KSZ8_PORT_STATUS_0 0x08 539 #define KSZ8_PORT_FIBER_MODE BIT(7) 540 541 #define SW_CHIP_ID_M GENMASK(7, 4) 542 #define KSZ87_CHIP_ID_94 0x6 543 #define KSZ87_CHIP_ID_95 0x9 544 #define KSZ88_CHIP_ID_63 0x3 545 546 #define SW_REV_ID_M GENMASK(7, 4) 547 548 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 549 #define REG_CHIP_ID4 0x0f 550 #define SKU_ID_KSZ8563 0x3c 551 552 /* Driver set switch broadcast storm protection at 10% rate. */ 553 #define BROADCAST_STORM_PROT_RATE 10 554 555 /* 148,800 frames * 67 ms / 100 */ 556 #define BROADCAST_STORM_VALUE 9969 557 558 #define BROADCAST_STORM_RATE_HI 0x07 559 #define BROADCAST_STORM_RATE_LO 0xFF 560 #define BROADCAST_STORM_RATE 0x07FF 561 562 #define MULTICAST_STORM_DISABLE BIT(6) 563 564 #define SW_START 0x01 565 566 /* xMII configuration */ 567 #define P_MII_DUPLEX_M BIT(6) 568 #define P_MII_100MBIT_M BIT(4) 569 570 #define P_GMII_1GBIT_M BIT(6) 571 #define P_RGMII_ID_IG_ENABLE BIT(4) 572 #define P_RGMII_ID_EG_ENABLE BIT(3) 573 #define P_MII_MAC_MODE BIT(2) 574 #define P_MII_SEL_M 0x3 575 576 /* Interrupt */ 577 #define REG_SW_PORT_INT_STATUS__4 0x0018 578 #define REG_SW_PORT_INT_MASK__4 0x001C 579 580 #define REG_PORT_INT_STATUS 0x001B 581 #define REG_PORT_INT_MASK 0x001F 582 583 #define PORT_SRC_PHY_INT 1 584 585 /* Regmap tables generation */ 586 #define KSZ_SPI_OP_RD 3 587 #define KSZ_SPI_OP_WR 2 588 589 #define swabnot_used(x) 0 590 591 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 592 swab##swp((opcode) << ((regbits) + (regpad))) 593 594 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 595 { \ 596 .name = #width, \ 597 .val_bits = (width), \ 598 .reg_stride = 1, \ 599 .reg_bits = (regbits) + (regalign), \ 600 .pad_bits = (regpad), \ 601 .max_register = BIT(regbits) - 1, \ 602 .cache_type = REGCACHE_NONE, \ 603 .read_flag_mask = \ 604 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 605 regbits, regpad), \ 606 .write_flag_mask = \ 607 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 608 regbits, regpad), \ 609 .lock = ksz_regmap_lock, \ 610 .unlock = ksz_regmap_unlock, \ 611 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 612 .val_format_endian = REGMAP_ENDIAN_BIG \ 613 } 614 615 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 616 static const struct regmap_config ksz##_regmap_config[] = { \ 617 KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 618 KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 619 KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 620 } 621 622 #endif 623