1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Microchip switch driver common header
3  *
4  * Copyright (C) 2017-2019 Microchip Technology Inc.
5  */
6 
7 #ifndef __KSZ_COMMON_H
8 #define __KSZ_COMMON_H
9 
10 #include <linux/etherdevice.h>
11 #include <linux/kernel.h>
12 #include <linux/mutex.h>
13 #include <linux/phy.h>
14 #include <linux/regmap.h>
15 #include <net/dsa.h>
16 #include <linux/irq.h>
17 
18 #include "ksz_ptp.h"
19 
20 #define KSZ_MAX_NUM_PORTS 8
21 
22 struct ksz_device;
23 struct ksz_port;
24 
25 enum ksz_regmap_width {
26 	KSZ_REGMAP_8,
27 	KSZ_REGMAP_16,
28 	KSZ_REGMAP_32,
29 	__KSZ_NUM_REGMAPS,
30 };
31 
32 struct vlan_table {
33 	u32 table[3];
34 };
35 
36 struct ksz_port_mib {
37 	struct mutex cnt_mutex;		/* structure access */
38 	u8 cnt_ptr;
39 	u64 *counters;
40 	struct rtnl_link_stats64 stats64;
41 	struct ethtool_pause_stats pause_stats;
42 	struct spinlock stats64_lock;
43 };
44 
45 struct ksz_mib_names {
46 	int index;
47 	char string[ETH_GSTRING_LEN];
48 };
49 
50 struct ksz_chip_data {
51 	u32 chip_id;
52 	const char *dev_name;
53 	int num_vlans;
54 	int num_alus;
55 	int num_statics;
56 	int cpu_ports;
57 	int port_cnt;
58 	u8 port_nirqs;
59 	u8 num_tx_queues;
60 	bool tc_cbs_supported;
61 	bool tc_ets_supported;
62 	const struct ksz_dev_ops *ops;
63 	bool ksz87xx_eee_link_erratum;
64 	const struct ksz_mib_names *mib_names;
65 	int mib_cnt;
66 	u8 reg_mib_cnt;
67 	const u16 *regs;
68 	const u32 *masks;
69 	const u8 *shifts;
70 	const u8 *xmii_ctrl0;
71 	const u8 *xmii_ctrl1;
72 	int stp_ctrl_reg;
73 	int broadcast_ctrl_reg;
74 	int multicast_ctrl_reg;
75 	int start_ctrl_reg;
76 	bool supports_mii[KSZ_MAX_NUM_PORTS];
77 	bool supports_rmii[KSZ_MAX_NUM_PORTS];
78 	bool supports_rgmii[KSZ_MAX_NUM_PORTS];
79 	bool internal_phy[KSZ_MAX_NUM_PORTS];
80 	bool gbit_capable[KSZ_MAX_NUM_PORTS];
81 	const struct regmap_access_table *wr_table;
82 	const struct regmap_access_table *rd_table;
83 };
84 
85 struct ksz_irq {
86 	u16 masked;
87 	u16 reg_mask;
88 	u16 reg_status;
89 	struct irq_domain *domain;
90 	int nirqs;
91 	int irq_num;
92 	char name[16];
93 	struct ksz_device *dev;
94 };
95 
96 struct ksz_ptp_irq {
97 	struct ksz_port *port;
98 	u16 ts_reg;
99 	bool ts_en;
100 	char name[16];
101 	int num;
102 };
103 
104 struct ksz_port {
105 	bool remove_tag;		/* Remove Tag flag set, for ksz8795 only */
106 	bool learning;
107 	int stp_state;
108 	struct phy_device phydev;
109 
110 	u32 fiber:1;			/* port is fiber */
111 	u32 force:1;
112 	u32 read:1;			/* read MIB counters in background */
113 	u32 freeze:1;			/* MIB counter freeze is enabled */
114 
115 	struct ksz_port_mib mib;
116 	phy_interface_t interface;
117 	u32 rgmii_tx_val;
118 	u32 rgmii_rx_val;
119 	struct ksz_device *ksz_dev;
120 	struct ksz_irq pirq;
121 	u8 num;
122 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP)
123 	struct hwtstamp_config tstamp_config;
124 	bool hwts_tx_en;
125 	bool hwts_rx_en;
126 	struct ksz_irq ptpirq;
127 	struct ksz_ptp_irq ptpmsg_irq[3];
128 	ktime_t tstamp_msg;
129 	struct completion tstamp_msg_comp;
130 #endif
131 };
132 
133 struct ksz_device {
134 	struct dsa_switch *ds;
135 	struct ksz_platform_data *pdata;
136 	const struct ksz_chip_data *info;
137 
138 	struct mutex dev_mutex;		/* device access */
139 	struct mutex regmap_mutex;	/* regmap access */
140 	struct mutex alu_mutex;		/* ALU access */
141 	struct mutex vlan_mutex;	/* vlan access */
142 	const struct ksz_dev_ops *dev_ops;
143 
144 	struct device *dev;
145 	struct regmap *regmap[__KSZ_NUM_REGMAPS];
146 
147 	void *priv;
148 	int irq;
149 
150 	struct gpio_desc *reset_gpio;	/* Optional reset GPIO */
151 
152 	/* chip specific data */
153 	u32 chip_id;
154 	u8 chip_rev;
155 	int cpu_port;			/* port connected to CPU */
156 	int phy_port_cnt;
157 	phy_interface_t compat_interface;
158 	bool synclko_125;
159 	bool synclko_disable;
160 
161 	struct vlan_table *vlan_cache;
162 
163 	struct ksz_port *ports;
164 	struct delayed_work mib_read;
165 	unsigned long mib_read_interval;
166 	u16 mirror_rx;
167 	u16 mirror_tx;
168 	u16 port_mask;
169 	struct mutex lock_irq;		/* IRQ Access */
170 	struct ksz_irq girq;
171 	struct ksz_ptp_data ptp_data;
172 };
173 
174 /* List of supported models */
175 enum ksz_model {
176 	KSZ8563,
177 	KSZ8795,
178 	KSZ8794,
179 	KSZ8765,
180 	KSZ8830,
181 	KSZ9477,
182 	KSZ9896,
183 	KSZ9897,
184 	KSZ9893,
185 	KSZ9563,
186 	KSZ9567,
187 	LAN9370,
188 	LAN9371,
189 	LAN9372,
190 	LAN9373,
191 	LAN9374,
192 };
193 
194 enum ksz_chip_id {
195 	KSZ8563_CHIP_ID = 0x8563,
196 	KSZ8795_CHIP_ID = 0x8795,
197 	KSZ8794_CHIP_ID = 0x8794,
198 	KSZ8765_CHIP_ID = 0x8765,
199 	KSZ8830_CHIP_ID = 0x8830,
200 	KSZ9477_CHIP_ID = 0x00947700,
201 	KSZ9896_CHIP_ID = 0x00989600,
202 	KSZ9897_CHIP_ID = 0x00989700,
203 	KSZ9893_CHIP_ID = 0x00989300,
204 	KSZ9563_CHIP_ID = 0x00956300,
205 	KSZ9567_CHIP_ID = 0x00956700,
206 	LAN9370_CHIP_ID = 0x00937000,
207 	LAN9371_CHIP_ID = 0x00937100,
208 	LAN9372_CHIP_ID = 0x00937200,
209 	LAN9373_CHIP_ID = 0x00937300,
210 	LAN9374_CHIP_ID = 0x00937400,
211 };
212 
213 enum ksz_regs {
214 	REG_IND_CTRL_0,
215 	REG_IND_DATA_8,
216 	REG_IND_DATA_CHECK,
217 	REG_IND_DATA_HI,
218 	REG_IND_DATA_LO,
219 	REG_IND_MIB_CHECK,
220 	REG_IND_BYTE,
221 	P_FORCE_CTRL,
222 	P_LINK_STATUS,
223 	P_LOCAL_CTRL,
224 	P_NEG_RESTART_CTRL,
225 	P_REMOTE_STATUS,
226 	P_SPEED_STATUS,
227 	S_TAIL_TAG_CTRL,
228 	P_STP_CTRL,
229 	S_START_CTRL,
230 	S_BROADCAST_CTRL,
231 	S_MULTICAST_CTRL,
232 	P_XMII_CTRL_0,
233 	P_XMII_CTRL_1,
234 };
235 
236 enum ksz_masks {
237 	PORT_802_1P_REMAPPING,
238 	SW_TAIL_TAG_ENABLE,
239 	MIB_COUNTER_OVERFLOW,
240 	MIB_COUNTER_VALID,
241 	VLAN_TABLE_FID,
242 	VLAN_TABLE_MEMBERSHIP,
243 	VLAN_TABLE_VALID,
244 	STATIC_MAC_TABLE_VALID,
245 	STATIC_MAC_TABLE_USE_FID,
246 	STATIC_MAC_TABLE_FID,
247 	STATIC_MAC_TABLE_OVERRIDE,
248 	STATIC_MAC_TABLE_FWD_PORTS,
249 	DYNAMIC_MAC_TABLE_ENTRIES_H,
250 	DYNAMIC_MAC_TABLE_MAC_EMPTY,
251 	DYNAMIC_MAC_TABLE_NOT_READY,
252 	DYNAMIC_MAC_TABLE_ENTRIES,
253 	DYNAMIC_MAC_TABLE_FID,
254 	DYNAMIC_MAC_TABLE_SRC_PORT,
255 	DYNAMIC_MAC_TABLE_TIMESTAMP,
256 	ALU_STAT_WRITE,
257 	ALU_STAT_READ,
258 	P_MII_TX_FLOW_CTRL,
259 	P_MII_RX_FLOW_CTRL,
260 };
261 
262 enum ksz_shifts {
263 	VLAN_TABLE_MEMBERSHIP_S,
264 	VLAN_TABLE,
265 	STATIC_MAC_FWD_PORTS,
266 	STATIC_MAC_FID,
267 	DYNAMIC_MAC_ENTRIES_H,
268 	DYNAMIC_MAC_ENTRIES,
269 	DYNAMIC_MAC_FID,
270 	DYNAMIC_MAC_TIMESTAMP,
271 	DYNAMIC_MAC_SRC_PORT,
272 	ALU_STAT_INDEX,
273 };
274 
275 enum ksz_xmii_ctrl0 {
276 	P_MII_100MBIT,
277 	P_MII_10MBIT,
278 	P_MII_FULL_DUPLEX,
279 	P_MII_HALF_DUPLEX,
280 };
281 
282 enum ksz_xmii_ctrl1 {
283 	P_RGMII_SEL,
284 	P_RMII_SEL,
285 	P_GMII_SEL,
286 	P_MII_SEL,
287 	P_GMII_1GBIT,
288 	P_GMII_NOT_1GBIT,
289 };
290 
291 struct alu_struct {
292 	/* entry 1 */
293 	u8	is_static:1;
294 	u8	is_src_filter:1;
295 	u8	is_dst_filter:1;
296 	u8	prio_age:3;
297 	u32	_reserv_0_1:23;
298 	u8	mstp:3;
299 	/* entry 2 */
300 	u8	is_override:1;
301 	u8	is_use_fid:1;
302 	u32	_reserv_1_1:23;
303 	u8	port_forward:7;
304 	/* entry 3 & 4*/
305 	u32	_reserv_2_1:9;
306 	u8	fid:7;
307 	u8	mac[ETH_ALEN];
308 };
309 
310 struct ksz_dev_ops {
311 	int (*setup)(struct dsa_switch *ds);
312 	void (*teardown)(struct dsa_switch *ds);
313 	u32 (*get_port_addr)(int port, int offset);
314 	void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member);
315 	void (*flush_dyn_mac_table)(struct ksz_device *dev, int port);
316 	void (*port_cleanup)(struct ksz_device *dev, int port);
317 	void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port);
318 	int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs);
319 	int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val);
320 	int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val);
321 	void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr,
322 			  u64 *cnt);
323 	void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr,
324 			  u64 *dropped, u64 *cnt);
325 	void (*r_mib_stat64)(struct ksz_device *dev, int port);
326 	int  (*vlan_filtering)(struct ksz_device *dev, int port,
327 			       bool flag, struct netlink_ext_ack *extack);
328 	int  (*vlan_add)(struct ksz_device *dev, int port,
329 			 const struct switchdev_obj_port_vlan *vlan,
330 			 struct netlink_ext_ack *extack);
331 	int  (*vlan_del)(struct ksz_device *dev, int port,
332 			 const struct switchdev_obj_port_vlan *vlan);
333 	int (*mirror_add)(struct ksz_device *dev, int port,
334 			  struct dsa_mall_mirror_tc_entry *mirror,
335 			  bool ingress, struct netlink_ext_ack *extack);
336 	void (*mirror_del)(struct ksz_device *dev, int port,
337 			   struct dsa_mall_mirror_tc_entry *mirror);
338 	int (*fdb_add)(struct ksz_device *dev, int port,
339 		       const unsigned char *addr, u16 vid, struct dsa_db db);
340 	int (*fdb_del)(struct ksz_device *dev, int port,
341 		       const unsigned char *addr, u16 vid, struct dsa_db db);
342 	int (*fdb_dump)(struct ksz_device *dev, int port,
343 			dsa_fdb_dump_cb_t *cb, void *data);
344 	int (*mdb_add)(struct ksz_device *dev, int port,
345 		       const struct switchdev_obj_port_mdb *mdb,
346 		       struct dsa_db db);
347 	int (*mdb_del)(struct ksz_device *dev, int port,
348 		       const struct switchdev_obj_port_mdb *mdb,
349 		       struct dsa_db db);
350 	void (*get_caps)(struct ksz_device *dev, int port,
351 			 struct phylink_config *config);
352 	int (*change_mtu)(struct ksz_device *dev, int port, int mtu);
353 	void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze);
354 	void (*port_init_cnt)(struct ksz_device *dev, int port);
355 	void (*phylink_mac_config)(struct ksz_device *dev, int port,
356 				   unsigned int mode,
357 				   const struct phylink_link_state *state);
358 	void (*phylink_mac_link_up)(struct ksz_device *dev, int port,
359 				    unsigned int mode,
360 				    phy_interface_t interface,
361 				    struct phy_device *phydev, int speed,
362 				    int duplex, bool tx_pause, bool rx_pause);
363 	void (*setup_rgmii_delay)(struct ksz_device *dev, int port);
364 	int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val);
365 	void (*config_cpu_port)(struct dsa_switch *ds);
366 	int (*enable_stp_addr)(struct ksz_device *dev);
367 	int (*reset)(struct ksz_device *dev);
368 	int (*init)(struct ksz_device *dev);
369 	void (*exit)(struct ksz_device *dev);
370 };
371 
372 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv);
373 int ksz_switch_register(struct ksz_device *dev);
374 void ksz_switch_remove(struct ksz_device *dev);
375 
376 void ksz_init_mib_timer(struct ksz_device *dev);
377 void ksz_r_mib_stats64(struct ksz_device *dev, int port);
378 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port);
379 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
380 bool ksz_get_gbit(struct ksz_device *dev, int port);
381 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit);
382 extern const struct ksz_chip_data ksz_switch_chips[];
383 
384 /* Common register access functions */
385 static inline struct regmap *ksz_regmap_8(struct ksz_device *dev)
386 {
387 	return dev->regmap[KSZ_REGMAP_8];
388 }
389 
390 static inline struct regmap *ksz_regmap_16(struct ksz_device *dev)
391 {
392 	return dev->regmap[KSZ_REGMAP_16];
393 }
394 
395 static inline struct regmap *ksz_regmap_32(struct ksz_device *dev)
396 {
397 	return dev->regmap[KSZ_REGMAP_32];
398 }
399 
400 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val)
401 {
402 	unsigned int value;
403 	int ret = regmap_read(ksz_regmap_8(dev), reg, &value);
404 
405 	if (ret)
406 		dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg,
407 			ERR_PTR(ret));
408 
409 	*val = value;
410 	return ret;
411 }
412 
413 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val)
414 {
415 	unsigned int value;
416 	int ret = regmap_read(ksz_regmap_16(dev), reg, &value);
417 
418 	if (ret)
419 		dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg,
420 			ERR_PTR(ret));
421 
422 	*val = value;
423 	return ret;
424 }
425 
426 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val)
427 {
428 	unsigned int value;
429 	int ret = regmap_read(ksz_regmap_32(dev), reg, &value);
430 
431 	if (ret)
432 		dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg,
433 			ERR_PTR(ret));
434 
435 	*val = value;
436 	return ret;
437 }
438 
439 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val)
440 {
441 	u32 value[2];
442 	int ret;
443 
444 	ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2);
445 	if (ret)
446 		dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg,
447 			ERR_PTR(ret));
448 	else
449 		*val = (u64)value[0] << 32 | value[1];
450 
451 	return ret;
452 }
453 
454 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value)
455 {
456 	int ret;
457 
458 	ret = regmap_write(ksz_regmap_8(dev), reg, value);
459 	if (ret)
460 		dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg,
461 			ERR_PTR(ret));
462 
463 	return ret;
464 }
465 
466 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value)
467 {
468 	int ret;
469 
470 	ret = regmap_write(ksz_regmap_16(dev), reg, value);
471 	if (ret)
472 		dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg,
473 			ERR_PTR(ret));
474 
475 	return ret;
476 }
477 
478 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value)
479 {
480 	int ret;
481 
482 	ret = regmap_write(ksz_regmap_32(dev), reg, value);
483 	if (ret)
484 		dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg,
485 			ERR_PTR(ret));
486 
487 	return ret;
488 }
489 
490 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask,
491 			    u16 value)
492 {
493 	int ret;
494 
495 	ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value);
496 	if (ret)
497 		dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg,
498 			ERR_PTR(ret));
499 
500 	return ret;
501 }
502 
503 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask,
504 			    u32 value)
505 {
506 	int ret;
507 
508 	ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value);
509 	if (ret)
510 		dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg,
511 			ERR_PTR(ret));
512 
513 	return ret;
514 }
515 
516 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value)
517 {
518 	u32 val[2];
519 
520 	/* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */
521 	value = swab64(value);
522 	val[0] = swab32(value & 0xffffffffULL);
523 	val[1] = swab32(value >> 32ULL);
524 
525 	return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2);
526 }
527 
528 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val)
529 {
530 	int ret;
531 
532 	ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val);
533 	if (ret)
534 		dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset,
535 			ERR_PTR(ret));
536 
537 	return ret;
538 }
539 
540 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset,
541 			     u8 *data)
542 {
543 	return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data);
544 }
545 
546 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset,
547 			      u16 *data)
548 {
549 	return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data);
550 }
551 
552 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset,
553 			      u32 *data)
554 {
555 	return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data);
556 }
557 
558 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset,
559 			      u8 data)
560 {
561 	return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data);
562 }
563 
564 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset,
565 			       u16 data)
566 {
567 	return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset),
568 			   data);
569 }
570 
571 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset,
572 			       u32 data)
573 {
574 	return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset),
575 			   data);
576 }
577 
578 static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset,
579 			    u8 mask, u8 val)
580 {
581 	return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset),
582 			mask, val);
583 }
584 
585 static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset,
586 			     u32 mask, u32 val)
587 {
588 	return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset),
589 			 mask, val);
590 }
591 
592 static inline void ksz_regmap_lock(void *__mtx)
593 {
594 	struct mutex *mtx = __mtx;
595 	mutex_lock(mtx);
596 }
597 
598 static inline void ksz_regmap_unlock(void *__mtx)
599 {
600 	struct mutex *mtx = __mtx;
601 	mutex_unlock(mtx);
602 }
603 
604 static inline bool ksz_is_ksz88x3(struct ksz_device *dev)
605 {
606 	return dev->chip_id == KSZ8830_CHIP_ID;
607 }
608 
609 static inline int is_lan937x(struct ksz_device *dev)
610 {
611 	return dev->chip_id == LAN9370_CHIP_ID ||
612 		dev->chip_id == LAN9371_CHIP_ID ||
613 		dev->chip_id == LAN9372_CHIP_ID ||
614 		dev->chip_id == LAN9373_CHIP_ID ||
615 		dev->chip_id == LAN9374_CHIP_ID;
616 }
617 
618 /* STP State Defines */
619 #define PORT_TX_ENABLE			BIT(2)
620 #define PORT_RX_ENABLE			BIT(1)
621 #define PORT_LEARN_DISABLE		BIT(0)
622 
623 /* Switch ID Defines */
624 #define REG_CHIP_ID0			0x00
625 
626 #define SW_FAMILY_ID_M			GENMASK(15, 8)
627 #define KSZ87_FAMILY_ID			0x87
628 #define KSZ88_FAMILY_ID			0x88
629 
630 #define KSZ8_PORT_STATUS_0		0x08
631 #define KSZ8_PORT_FIBER_MODE		BIT(7)
632 
633 #define SW_CHIP_ID_M			GENMASK(7, 4)
634 #define KSZ87_CHIP_ID_94		0x6
635 #define KSZ87_CHIP_ID_95		0x9
636 #define KSZ88_CHIP_ID_63		0x3
637 
638 #define SW_REV_ID_M			GENMASK(7, 4)
639 
640 /* KSZ9893, KSZ9563, KSZ8563 specific register  */
641 #define REG_CHIP_ID4			0x0f
642 #define SKU_ID_KSZ8563			0x3c
643 #define SKU_ID_KSZ9563			0x1c
644 
645 /* Driver set switch broadcast storm protection at 10% rate. */
646 #define BROADCAST_STORM_PROT_RATE	10
647 
648 /* 148,800 frames * 67 ms / 100 */
649 #define BROADCAST_STORM_VALUE		9969
650 
651 #define BROADCAST_STORM_RATE_HI		0x07
652 #define BROADCAST_STORM_RATE_LO		0xFF
653 #define BROADCAST_STORM_RATE		0x07FF
654 
655 #define MULTICAST_STORM_DISABLE		BIT(6)
656 
657 #define SW_START			0x01
658 
659 /* xMII configuration */
660 #define P_MII_DUPLEX_M			BIT(6)
661 #define P_MII_100MBIT_M			BIT(4)
662 
663 #define P_GMII_1GBIT_M			BIT(6)
664 #define P_RGMII_ID_IG_ENABLE		BIT(4)
665 #define P_RGMII_ID_EG_ENABLE		BIT(3)
666 #define P_MII_MAC_MODE			BIT(2)
667 #define P_MII_SEL_M			0x3
668 
669 /* Interrupt */
670 #define REG_SW_PORT_INT_STATUS__1	0x001B
671 #define REG_SW_PORT_INT_MASK__1		0x001F
672 
673 #define REG_PORT_INT_STATUS		0x001B
674 #define REG_PORT_INT_MASK		0x001F
675 
676 #define PORT_SRC_PHY_INT		1
677 #define PORT_SRC_PTP_INT		2
678 
679 #define KSZ8795_HUGE_PACKET_SIZE	2000
680 #define KSZ8863_HUGE_PACKET_SIZE	1916
681 #define KSZ8863_NORMAL_PACKET_SIZE	1536
682 #define KSZ8_LEGAL_PACKET_SIZE		1518
683 #define KSZ9477_MAX_FRAME_SIZE		9000
684 
685 #define KSZ9477_REG_PORT_OUT_RATE_0	0x0420
686 #define KSZ9477_OUT_RATE_NO_LIMIT	0
687 
688 #define KSZ9477_PORT_MRI_TC_MAP__4	0x0808
689 
690 #define KSZ9477_PORT_TC_MAP_S		4
691 #define KSZ9477_MAX_TC_PRIO		7
692 
693 /* CBS related registers */
694 #define REG_PORT_MTI_QUEUE_INDEX__4	0x0900
695 
696 #define REG_PORT_MTI_QUEUE_CTRL_0	0x0914
697 
698 #define MTI_SCHEDULE_MODE_M		GENMASK(7, 6)
699 #define MTI_SCHEDULE_STRICT_PRIO	0
700 #define MTI_SCHEDULE_WRR		2
701 #define MTI_SHAPING_M			GENMASK(5, 4)
702 #define MTI_SHAPING_OFF			0
703 #define MTI_SHAPING_SRP			1
704 #define MTI_SHAPING_TIME_AWARE		2
705 
706 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1	0x0915
707 #define KSZ9477_DEFAULT_WRR_WEIGHT	1
708 
709 #define REG_PORT_MTI_HI_WATER_MARK	0x0916
710 #define REG_PORT_MTI_LO_WATER_MARK	0x0918
711 
712 /* Regmap tables generation */
713 #define KSZ_SPI_OP_RD		3
714 #define KSZ_SPI_OP_WR		2
715 
716 #define swabnot_used(x)		0
717 
718 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad)		\
719 	swab##swp((opcode) << ((regbits) + (regpad)))
720 
721 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign)		\
722 	{								\
723 		.name = #width,						\
724 		.val_bits = (width),					\
725 		.reg_stride = 1,					\
726 		.reg_bits = (regbits) + (regalign),			\
727 		.pad_bits = (regpad),					\
728 		.max_register = BIT(regbits) - 1,			\
729 		.cache_type = REGCACHE_NONE,				\
730 		.read_flag_mask =					\
731 			KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp,	\
732 					     regbits, regpad),		\
733 		.write_flag_mask =					\
734 			KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp,	\
735 					     regbits, regpad),		\
736 		.lock = ksz_regmap_lock,				\
737 		.unlock = ksz_regmap_unlock,				\
738 		.reg_format_endian = REGMAP_ENDIAN_BIG,			\
739 		.val_format_endian = REGMAP_ENDIAN_BIG			\
740 	}
741 
742 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign)		\
743 	static const struct regmap_config ksz##_regmap_config[] = {	\
744 		[KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \
745 		[KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \
746 		[KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \
747 	}
748 
749 #endif
750