1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 #include <linux/irq.h> 17 18 #include "ksz_ptp.h" 19 20 #define KSZ_MAX_NUM_PORTS 8 21 22 struct ksz_device; 23 struct ksz_port; 24 25 struct vlan_table { 26 u32 table[3]; 27 }; 28 29 struct ksz_port_mib { 30 struct mutex cnt_mutex; /* structure access */ 31 u8 cnt_ptr; 32 u64 *counters; 33 struct rtnl_link_stats64 stats64; 34 struct ethtool_pause_stats pause_stats; 35 struct spinlock stats64_lock; 36 }; 37 38 struct ksz_mib_names { 39 int index; 40 char string[ETH_GSTRING_LEN]; 41 }; 42 43 struct ksz_chip_data { 44 u32 chip_id; 45 const char *dev_name; 46 int num_vlans; 47 int num_alus; 48 int num_statics; 49 int cpu_ports; 50 int port_cnt; 51 u8 port_nirqs; 52 u8 num_tx_queues; 53 bool tc_cbs_supported; 54 bool tc_ets_supported; 55 const struct ksz_dev_ops *ops; 56 bool phy_errata_9477; 57 bool ksz87xx_eee_link_erratum; 58 const struct ksz_mib_names *mib_names; 59 int mib_cnt; 60 u8 reg_mib_cnt; 61 const u16 *regs; 62 const u32 *masks; 63 const u8 *shifts; 64 const u8 *xmii_ctrl0; 65 const u8 *xmii_ctrl1; 66 int stp_ctrl_reg; 67 int broadcast_ctrl_reg; 68 int multicast_ctrl_reg; 69 int start_ctrl_reg; 70 bool supports_mii[KSZ_MAX_NUM_PORTS]; 71 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 72 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 73 bool internal_phy[KSZ_MAX_NUM_PORTS]; 74 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 75 const struct regmap_access_table *wr_table; 76 const struct regmap_access_table *rd_table; 77 }; 78 79 struct ksz_irq { 80 u16 masked; 81 u16 reg_mask; 82 u16 reg_status; 83 struct irq_domain *domain; 84 int nirqs; 85 int irq_num; 86 char name[16]; 87 struct ksz_device *dev; 88 }; 89 90 struct ksz_ptp_irq { 91 struct ksz_port *port; 92 u16 ts_reg; 93 bool ts_en; 94 char name[16]; 95 int num; 96 }; 97 98 struct ksz_port { 99 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 100 bool learning; 101 int stp_state; 102 struct phy_device phydev; 103 104 u32 on:1; /* port is not disabled by hardware */ 105 u32 fiber:1; /* port is fiber */ 106 u32 force:1; 107 u32 read:1; /* read MIB counters in background */ 108 u32 freeze:1; /* MIB counter freeze is enabled */ 109 110 struct ksz_port_mib mib; 111 phy_interface_t interface; 112 u32 rgmii_tx_val; 113 u32 rgmii_rx_val; 114 struct ksz_device *ksz_dev; 115 struct ksz_irq pirq; 116 u8 num; 117 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) 118 struct hwtstamp_config tstamp_config; 119 bool hwts_tx_en; 120 bool hwts_rx_en; 121 struct ksz_irq ptpirq; 122 struct ksz_ptp_irq ptpmsg_irq[3]; 123 ktime_t tstamp_msg; 124 struct completion tstamp_msg_comp; 125 #endif 126 }; 127 128 struct ksz_device { 129 struct dsa_switch *ds; 130 struct ksz_platform_data *pdata; 131 const struct ksz_chip_data *info; 132 133 struct mutex dev_mutex; /* device access */ 134 struct mutex regmap_mutex; /* regmap access */ 135 struct mutex alu_mutex; /* ALU access */ 136 struct mutex vlan_mutex; /* vlan access */ 137 const struct ksz_dev_ops *dev_ops; 138 139 struct device *dev; 140 struct regmap *regmap[3]; 141 142 void *priv; 143 int irq; 144 145 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 146 147 /* chip specific data */ 148 u32 chip_id; 149 u8 chip_rev; 150 int cpu_port; /* port connected to CPU */ 151 int phy_port_cnt; 152 phy_interface_t compat_interface; 153 bool synclko_125; 154 bool synclko_disable; 155 156 struct vlan_table *vlan_cache; 157 158 struct ksz_port *ports; 159 struct delayed_work mib_read; 160 unsigned long mib_read_interval; 161 u16 mirror_rx; 162 u16 mirror_tx; 163 u16 port_mask; 164 struct mutex lock_irq; /* IRQ Access */ 165 struct ksz_irq girq; 166 struct ksz_ptp_data ptp_data; 167 }; 168 169 /* List of supported models */ 170 enum ksz_model { 171 KSZ8563, 172 KSZ8795, 173 KSZ8794, 174 KSZ8765, 175 KSZ8830, 176 KSZ9477, 177 KSZ9896, 178 KSZ9897, 179 KSZ9893, 180 KSZ9563, 181 KSZ9567, 182 LAN9370, 183 LAN9371, 184 LAN9372, 185 LAN9373, 186 LAN9374, 187 }; 188 189 enum ksz_chip_id { 190 KSZ8563_CHIP_ID = 0x8563, 191 KSZ8795_CHIP_ID = 0x8795, 192 KSZ8794_CHIP_ID = 0x8794, 193 KSZ8765_CHIP_ID = 0x8765, 194 KSZ8830_CHIP_ID = 0x8830, 195 KSZ9477_CHIP_ID = 0x00947700, 196 KSZ9896_CHIP_ID = 0x00989600, 197 KSZ9897_CHIP_ID = 0x00989700, 198 KSZ9893_CHIP_ID = 0x00989300, 199 KSZ9563_CHIP_ID = 0x00956300, 200 KSZ9567_CHIP_ID = 0x00956700, 201 LAN9370_CHIP_ID = 0x00937000, 202 LAN9371_CHIP_ID = 0x00937100, 203 LAN9372_CHIP_ID = 0x00937200, 204 LAN9373_CHIP_ID = 0x00937300, 205 LAN9374_CHIP_ID = 0x00937400, 206 }; 207 208 enum ksz_regs { 209 REG_IND_CTRL_0, 210 REG_IND_DATA_8, 211 REG_IND_DATA_CHECK, 212 REG_IND_DATA_HI, 213 REG_IND_DATA_LO, 214 REG_IND_MIB_CHECK, 215 REG_IND_BYTE, 216 P_FORCE_CTRL, 217 P_LINK_STATUS, 218 P_LOCAL_CTRL, 219 P_NEG_RESTART_CTRL, 220 P_REMOTE_STATUS, 221 P_SPEED_STATUS, 222 S_TAIL_TAG_CTRL, 223 P_STP_CTRL, 224 S_START_CTRL, 225 S_BROADCAST_CTRL, 226 S_MULTICAST_CTRL, 227 P_XMII_CTRL_0, 228 P_XMII_CTRL_1, 229 }; 230 231 enum ksz_masks { 232 PORT_802_1P_REMAPPING, 233 SW_TAIL_TAG_ENABLE, 234 MIB_COUNTER_OVERFLOW, 235 MIB_COUNTER_VALID, 236 VLAN_TABLE_FID, 237 VLAN_TABLE_MEMBERSHIP, 238 VLAN_TABLE_VALID, 239 STATIC_MAC_TABLE_VALID, 240 STATIC_MAC_TABLE_USE_FID, 241 STATIC_MAC_TABLE_FID, 242 STATIC_MAC_TABLE_OVERRIDE, 243 STATIC_MAC_TABLE_FWD_PORTS, 244 DYNAMIC_MAC_TABLE_ENTRIES_H, 245 DYNAMIC_MAC_TABLE_MAC_EMPTY, 246 DYNAMIC_MAC_TABLE_NOT_READY, 247 DYNAMIC_MAC_TABLE_ENTRIES, 248 DYNAMIC_MAC_TABLE_FID, 249 DYNAMIC_MAC_TABLE_SRC_PORT, 250 DYNAMIC_MAC_TABLE_TIMESTAMP, 251 ALU_STAT_WRITE, 252 ALU_STAT_READ, 253 P_MII_TX_FLOW_CTRL, 254 P_MII_RX_FLOW_CTRL, 255 }; 256 257 enum ksz_shifts { 258 VLAN_TABLE_MEMBERSHIP_S, 259 VLAN_TABLE, 260 STATIC_MAC_FWD_PORTS, 261 STATIC_MAC_FID, 262 DYNAMIC_MAC_ENTRIES_H, 263 DYNAMIC_MAC_ENTRIES, 264 DYNAMIC_MAC_FID, 265 DYNAMIC_MAC_TIMESTAMP, 266 DYNAMIC_MAC_SRC_PORT, 267 ALU_STAT_INDEX, 268 }; 269 270 enum ksz_xmii_ctrl0 { 271 P_MII_100MBIT, 272 P_MII_10MBIT, 273 P_MII_FULL_DUPLEX, 274 P_MII_HALF_DUPLEX, 275 }; 276 277 enum ksz_xmii_ctrl1 { 278 P_RGMII_SEL, 279 P_RMII_SEL, 280 P_GMII_SEL, 281 P_MII_SEL, 282 P_GMII_1GBIT, 283 P_GMII_NOT_1GBIT, 284 }; 285 286 struct alu_struct { 287 /* entry 1 */ 288 u8 is_static:1; 289 u8 is_src_filter:1; 290 u8 is_dst_filter:1; 291 u8 prio_age:3; 292 u32 _reserv_0_1:23; 293 u8 mstp:3; 294 /* entry 2 */ 295 u8 is_override:1; 296 u8 is_use_fid:1; 297 u32 _reserv_1_1:23; 298 u8 port_forward:7; 299 /* entry 3 & 4*/ 300 u32 _reserv_2_1:9; 301 u8 fid:7; 302 u8 mac[ETH_ALEN]; 303 }; 304 305 struct ksz_dev_ops { 306 int (*setup)(struct dsa_switch *ds); 307 void (*teardown)(struct dsa_switch *ds); 308 u32 (*get_port_addr)(int port, int offset); 309 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 310 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 311 void (*port_cleanup)(struct ksz_device *dev, int port); 312 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 313 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); 314 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 315 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 316 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 317 u64 *cnt); 318 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 319 u64 *dropped, u64 *cnt); 320 void (*r_mib_stat64)(struct ksz_device *dev, int port); 321 int (*vlan_filtering)(struct ksz_device *dev, int port, 322 bool flag, struct netlink_ext_ack *extack); 323 int (*vlan_add)(struct ksz_device *dev, int port, 324 const struct switchdev_obj_port_vlan *vlan, 325 struct netlink_ext_ack *extack); 326 int (*vlan_del)(struct ksz_device *dev, int port, 327 const struct switchdev_obj_port_vlan *vlan); 328 int (*mirror_add)(struct ksz_device *dev, int port, 329 struct dsa_mall_mirror_tc_entry *mirror, 330 bool ingress, struct netlink_ext_ack *extack); 331 void (*mirror_del)(struct ksz_device *dev, int port, 332 struct dsa_mall_mirror_tc_entry *mirror); 333 int (*fdb_add)(struct ksz_device *dev, int port, 334 const unsigned char *addr, u16 vid, struct dsa_db db); 335 int (*fdb_del)(struct ksz_device *dev, int port, 336 const unsigned char *addr, u16 vid, struct dsa_db db); 337 int (*fdb_dump)(struct ksz_device *dev, int port, 338 dsa_fdb_dump_cb_t *cb, void *data); 339 int (*mdb_add)(struct ksz_device *dev, int port, 340 const struct switchdev_obj_port_mdb *mdb, 341 struct dsa_db db); 342 int (*mdb_del)(struct ksz_device *dev, int port, 343 const struct switchdev_obj_port_mdb *mdb, 344 struct dsa_db db); 345 void (*get_caps)(struct ksz_device *dev, int port, 346 struct phylink_config *config); 347 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 348 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 349 void (*port_init_cnt)(struct ksz_device *dev, int port); 350 void (*phylink_mac_config)(struct ksz_device *dev, int port, 351 unsigned int mode, 352 const struct phylink_link_state *state); 353 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 354 unsigned int mode, 355 phy_interface_t interface, 356 struct phy_device *phydev, int speed, 357 int duplex, bool tx_pause, bool rx_pause); 358 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 359 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val); 360 void (*config_cpu_port)(struct dsa_switch *ds); 361 int (*enable_stp_addr)(struct ksz_device *dev); 362 int (*reset)(struct ksz_device *dev); 363 int (*init)(struct ksz_device *dev); 364 void (*exit)(struct ksz_device *dev); 365 }; 366 367 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 368 int ksz_switch_register(struct ksz_device *dev); 369 void ksz_switch_remove(struct ksz_device *dev); 370 371 void ksz_init_mib_timer(struct ksz_device *dev); 372 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 373 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port); 374 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 375 bool ksz_get_gbit(struct ksz_device *dev, int port); 376 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 377 extern const struct ksz_chip_data ksz_switch_chips[]; 378 379 /* Common register access functions */ 380 381 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 382 { 383 unsigned int value; 384 int ret = regmap_read(dev->regmap[0], reg, &value); 385 386 if (ret) 387 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 388 ERR_PTR(ret)); 389 390 *val = value; 391 return ret; 392 } 393 394 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 395 { 396 unsigned int value; 397 int ret = regmap_read(dev->regmap[1], reg, &value); 398 399 if (ret) 400 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 401 ERR_PTR(ret)); 402 403 *val = value; 404 return ret; 405 } 406 407 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 408 { 409 unsigned int value; 410 int ret = regmap_read(dev->regmap[2], reg, &value); 411 412 if (ret) 413 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 414 ERR_PTR(ret)); 415 416 *val = value; 417 return ret; 418 } 419 420 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 421 { 422 u32 value[2]; 423 int ret; 424 425 ret = regmap_bulk_read(dev->regmap[2], reg, value, 2); 426 if (ret) 427 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 428 ERR_PTR(ret)); 429 else 430 *val = (u64)value[0] << 32 | value[1]; 431 432 return ret; 433 } 434 435 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 436 { 437 int ret; 438 439 ret = regmap_write(dev->regmap[0], reg, value); 440 if (ret) 441 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 442 ERR_PTR(ret)); 443 444 return ret; 445 } 446 447 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 448 { 449 int ret; 450 451 ret = regmap_write(dev->regmap[1], reg, value); 452 if (ret) 453 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 454 ERR_PTR(ret)); 455 456 return ret; 457 } 458 459 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 460 { 461 int ret; 462 463 ret = regmap_write(dev->regmap[2], reg, value); 464 if (ret) 465 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 466 ERR_PTR(ret)); 467 468 return ret; 469 } 470 471 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, 472 u16 value) 473 { 474 int ret; 475 476 ret = regmap_update_bits(dev->regmap[1], reg, mask, value); 477 if (ret) 478 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg, 479 ERR_PTR(ret)); 480 481 return ret; 482 } 483 484 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask, 485 u32 value) 486 { 487 int ret; 488 489 ret = regmap_update_bits(dev->regmap[2], reg, mask, value); 490 if (ret) 491 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg, 492 ERR_PTR(ret)); 493 494 return ret; 495 } 496 497 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 498 { 499 u32 val[2]; 500 501 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 502 value = swab64(value); 503 val[0] = swab32(value & 0xffffffffULL); 504 val[1] = swab32(value >> 32ULL); 505 506 return regmap_bulk_write(dev->regmap[2], reg, val, 2); 507 } 508 509 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val) 510 { 511 return regmap_update_bits(dev->regmap[0], offset, mask, val); 512 } 513 514 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 515 u8 *data) 516 { 517 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 518 } 519 520 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 521 u16 *data) 522 { 523 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 524 } 525 526 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 527 u32 *data) 528 { 529 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 530 } 531 532 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 533 u8 data) 534 { 535 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 536 } 537 538 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 539 u16 data) 540 { 541 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 542 data); 543 } 544 545 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 546 u32 data) 547 { 548 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 549 data); 550 } 551 552 static inline void ksz_prmw8(struct ksz_device *dev, int port, int offset, 553 u8 mask, u8 val) 554 { 555 regmap_update_bits(dev->regmap[0], 556 dev->dev_ops->get_port_addr(port, offset), 557 mask, val); 558 } 559 560 static inline void ksz_regmap_lock(void *__mtx) 561 { 562 struct mutex *mtx = __mtx; 563 mutex_lock(mtx); 564 } 565 566 static inline void ksz_regmap_unlock(void *__mtx) 567 { 568 struct mutex *mtx = __mtx; 569 mutex_unlock(mtx); 570 } 571 572 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 573 { 574 return dev->chip_id == KSZ8830_CHIP_ID; 575 } 576 577 static inline int is_lan937x(struct ksz_device *dev) 578 { 579 return dev->chip_id == LAN9370_CHIP_ID || 580 dev->chip_id == LAN9371_CHIP_ID || 581 dev->chip_id == LAN9372_CHIP_ID || 582 dev->chip_id == LAN9373_CHIP_ID || 583 dev->chip_id == LAN9374_CHIP_ID; 584 } 585 586 /* STP State Defines */ 587 #define PORT_TX_ENABLE BIT(2) 588 #define PORT_RX_ENABLE BIT(1) 589 #define PORT_LEARN_DISABLE BIT(0) 590 591 /* Switch ID Defines */ 592 #define REG_CHIP_ID0 0x00 593 594 #define SW_FAMILY_ID_M GENMASK(15, 8) 595 #define KSZ87_FAMILY_ID 0x87 596 #define KSZ88_FAMILY_ID 0x88 597 598 #define KSZ8_PORT_STATUS_0 0x08 599 #define KSZ8_PORT_FIBER_MODE BIT(7) 600 601 #define SW_CHIP_ID_M GENMASK(7, 4) 602 #define KSZ87_CHIP_ID_94 0x6 603 #define KSZ87_CHIP_ID_95 0x9 604 #define KSZ88_CHIP_ID_63 0x3 605 606 #define SW_REV_ID_M GENMASK(7, 4) 607 608 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 609 #define REG_CHIP_ID4 0x0f 610 #define SKU_ID_KSZ8563 0x3c 611 #define SKU_ID_KSZ9563 0x1c 612 613 /* Driver set switch broadcast storm protection at 10% rate. */ 614 #define BROADCAST_STORM_PROT_RATE 10 615 616 /* 148,800 frames * 67 ms / 100 */ 617 #define BROADCAST_STORM_VALUE 9969 618 619 #define BROADCAST_STORM_RATE_HI 0x07 620 #define BROADCAST_STORM_RATE_LO 0xFF 621 #define BROADCAST_STORM_RATE 0x07FF 622 623 #define MULTICAST_STORM_DISABLE BIT(6) 624 625 #define SW_START 0x01 626 627 /* xMII configuration */ 628 #define P_MII_DUPLEX_M BIT(6) 629 #define P_MII_100MBIT_M BIT(4) 630 631 #define P_GMII_1GBIT_M BIT(6) 632 #define P_RGMII_ID_IG_ENABLE BIT(4) 633 #define P_RGMII_ID_EG_ENABLE BIT(3) 634 #define P_MII_MAC_MODE BIT(2) 635 #define P_MII_SEL_M 0x3 636 637 /* Interrupt */ 638 #define REG_SW_PORT_INT_STATUS__1 0x001B 639 #define REG_SW_PORT_INT_MASK__1 0x001F 640 641 #define REG_PORT_INT_STATUS 0x001B 642 #define REG_PORT_INT_MASK 0x001F 643 644 #define PORT_SRC_PHY_INT 1 645 #define PORT_SRC_PTP_INT 2 646 647 #define KSZ8795_HUGE_PACKET_SIZE 2000 648 #define KSZ8863_HUGE_PACKET_SIZE 1916 649 #define KSZ8863_NORMAL_PACKET_SIZE 1536 650 #define KSZ8_LEGAL_PACKET_SIZE 1518 651 #define KSZ9477_MAX_FRAME_SIZE 9000 652 653 #define KSZ9477_REG_PORT_OUT_RATE_0 0x0420 654 #define KSZ9477_OUT_RATE_NO_LIMIT 0 655 656 #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808 657 658 #define KSZ9477_PORT_TC_MAP_S 4 659 #define KSZ9477_MAX_TC_PRIO 7 660 661 /* CBS related registers */ 662 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900 663 664 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914 665 666 #define MTI_SCHEDULE_MODE_M GENMASK(7, 6) 667 #define MTI_SCHEDULE_STRICT_PRIO 0 668 #define MTI_SCHEDULE_WRR 2 669 #define MTI_SHAPING_M GENMASK(5, 4) 670 #define MTI_SHAPING_OFF 0 671 #define MTI_SHAPING_SRP 1 672 #define MTI_SHAPING_TIME_AWARE 2 673 674 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915 675 #define KSZ9477_DEFAULT_WRR_WEIGHT 1 676 677 #define REG_PORT_MTI_HI_WATER_MARK 0x0916 678 #define REG_PORT_MTI_LO_WATER_MARK 0x0918 679 680 /* Regmap tables generation */ 681 #define KSZ_SPI_OP_RD 3 682 #define KSZ_SPI_OP_WR 2 683 684 #define swabnot_used(x) 0 685 686 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 687 swab##swp((opcode) << ((regbits) + (regpad))) 688 689 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 690 { \ 691 .name = #width, \ 692 .val_bits = (width), \ 693 .reg_stride = 1, \ 694 .reg_bits = (regbits) + (regalign), \ 695 .pad_bits = (regpad), \ 696 .max_register = BIT(regbits) - 1, \ 697 .cache_type = REGCACHE_NONE, \ 698 .read_flag_mask = \ 699 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 700 regbits, regpad), \ 701 .write_flag_mask = \ 702 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 703 regbits, regpad), \ 704 .lock = ksz_regmap_lock, \ 705 .unlock = ksz_regmap_unlock, \ 706 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 707 .val_format_endian = REGMAP_ENDIAN_BIG \ 708 } 709 710 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 711 static const struct regmap_config ksz##_regmap_config[] = { \ 712 KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 713 KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 714 KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 715 } 716 717 #endif 718