1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 17 #define KSZ_MAX_NUM_PORTS 8 18 19 struct ksz_device; 20 21 struct vlan_table { 22 u32 table[3]; 23 }; 24 25 struct ksz_port_mib { 26 struct mutex cnt_mutex; /* structure access */ 27 u8 cnt_ptr; 28 u64 *counters; 29 struct rtnl_link_stats64 stats64; 30 struct ethtool_pause_stats pause_stats; 31 struct spinlock stats64_lock; 32 }; 33 34 struct ksz_mib_names { 35 int index; 36 char string[ETH_GSTRING_LEN]; 37 }; 38 39 struct ksz_chip_data { 40 u32 chip_id; 41 const char *dev_name; 42 int num_vlans; 43 int num_alus; 44 int num_statics; 45 int cpu_ports; 46 int port_cnt; 47 const struct ksz_dev_ops *ops; 48 bool phy_errata_9477; 49 bool ksz87xx_eee_link_erratum; 50 const struct ksz_mib_names *mib_names; 51 int mib_cnt; 52 u8 reg_mib_cnt; 53 const u16 *regs; 54 const u32 *masks; 55 const u8 *shifts; 56 const u8 *xmii_ctrl0; 57 const u8 *xmii_ctrl1; 58 int stp_ctrl_reg; 59 int broadcast_ctrl_reg; 60 int multicast_ctrl_reg; 61 int start_ctrl_reg; 62 bool supports_mii[KSZ_MAX_NUM_PORTS]; 63 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 64 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 65 bool internal_phy[KSZ_MAX_NUM_PORTS]; 66 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 67 const struct regmap_access_table *wr_table; 68 const struct regmap_access_table *rd_table; 69 }; 70 71 struct ksz_port { 72 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 73 bool learning; 74 int stp_state; 75 struct phy_device phydev; 76 77 u32 on:1; /* port is not disabled by hardware */ 78 u32 fiber:1; /* port is fiber */ 79 u32 force:1; 80 u32 read:1; /* read MIB counters in background */ 81 u32 freeze:1; /* MIB counter freeze is enabled */ 82 83 struct ksz_port_mib mib; 84 phy_interface_t interface; 85 u16 max_frame; 86 u32 rgmii_tx_val; 87 u32 rgmii_rx_val; 88 struct ksz_device *ksz_dev; 89 u8 num; 90 }; 91 92 struct ksz_device { 93 struct dsa_switch *ds; 94 struct ksz_platform_data *pdata; 95 const struct ksz_chip_data *info; 96 97 struct mutex dev_mutex; /* device access */ 98 struct mutex regmap_mutex; /* regmap access */ 99 struct mutex alu_mutex; /* ALU access */ 100 struct mutex vlan_mutex; /* vlan access */ 101 const struct ksz_dev_ops *dev_ops; 102 103 struct device *dev; 104 struct regmap *regmap[3]; 105 106 void *priv; 107 108 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 109 110 /* chip specific data */ 111 u32 chip_id; 112 u8 chip_rev; 113 int cpu_port; /* port connected to CPU */ 114 int phy_port_cnt; 115 phy_interface_t compat_interface; 116 bool synclko_125; 117 bool synclko_disable; 118 119 struct vlan_table *vlan_cache; 120 121 struct ksz_port *ports; 122 struct delayed_work mib_read; 123 unsigned long mib_read_interval; 124 u16 mirror_rx; 125 u16 mirror_tx; 126 u16 port_mask; 127 }; 128 129 /* List of supported models */ 130 enum ksz_model { 131 KSZ8563, 132 KSZ8795, 133 KSZ8794, 134 KSZ8765, 135 KSZ8830, 136 KSZ9477, 137 KSZ9897, 138 KSZ9893, 139 KSZ9567, 140 LAN9370, 141 LAN9371, 142 LAN9372, 143 LAN9373, 144 LAN9374, 145 }; 146 147 enum ksz_chip_id { 148 KSZ8563_CHIP_ID = 0x8563, 149 KSZ8795_CHIP_ID = 0x8795, 150 KSZ8794_CHIP_ID = 0x8794, 151 KSZ8765_CHIP_ID = 0x8765, 152 KSZ8830_CHIP_ID = 0x8830, 153 KSZ9477_CHIP_ID = 0x00947700, 154 KSZ9897_CHIP_ID = 0x00989700, 155 KSZ9893_CHIP_ID = 0x00989300, 156 KSZ9567_CHIP_ID = 0x00956700, 157 LAN9370_CHIP_ID = 0x00937000, 158 LAN9371_CHIP_ID = 0x00937100, 159 LAN9372_CHIP_ID = 0x00937200, 160 LAN9373_CHIP_ID = 0x00937300, 161 LAN9374_CHIP_ID = 0x00937400, 162 }; 163 164 enum ksz_regs { 165 REG_IND_CTRL_0, 166 REG_IND_DATA_8, 167 REG_IND_DATA_CHECK, 168 REG_IND_DATA_HI, 169 REG_IND_DATA_LO, 170 REG_IND_MIB_CHECK, 171 REG_IND_BYTE, 172 P_FORCE_CTRL, 173 P_LINK_STATUS, 174 P_LOCAL_CTRL, 175 P_NEG_RESTART_CTRL, 176 P_REMOTE_STATUS, 177 P_SPEED_STATUS, 178 S_TAIL_TAG_CTRL, 179 P_STP_CTRL, 180 S_START_CTRL, 181 S_BROADCAST_CTRL, 182 S_MULTICAST_CTRL, 183 P_XMII_CTRL_0, 184 P_XMII_CTRL_1, 185 }; 186 187 enum ksz_masks { 188 PORT_802_1P_REMAPPING, 189 SW_TAIL_TAG_ENABLE, 190 MIB_COUNTER_OVERFLOW, 191 MIB_COUNTER_VALID, 192 VLAN_TABLE_FID, 193 VLAN_TABLE_MEMBERSHIP, 194 VLAN_TABLE_VALID, 195 STATIC_MAC_TABLE_VALID, 196 STATIC_MAC_TABLE_USE_FID, 197 STATIC_MAC_TABLE_FID, 198 STATIC_MAC_TABLE_OVERRIDE, 199 STATIC_MAC_TABLE_FWD_PORTS, 200 DYNAMIC_MAC_TABLE_ENTRIES_H, 201 DYNAMIC_MAC_TABLE_MAC_EMPTY, 202 DYNAMIC_MAC_TABLE_NOT_READY, 203 DYNAMIC_MAC_TABLE_ENTRIES, 204 DYNAMIC_MAC_TABLE_FID, 205 DYNAMIC_MAC_TABLE_SRC_PORT, 206 DYNAMIC_MAC_TABLE_TIMESTAMP, 207 ALU_STAT_WRITE, 208 ALU_STAT_READ, 209 P_MII_TX_FLOW_CTRL, 210 P_MII_RX_FLOW_CTRL, 211 }; 212 213 enum ksz_shifts { 214 VLAN_TABLE_MEMBERSHIP_S, 215 VLAN_TABLE, 216 STATIC_MAC_FWD_PORTS, 217 STATIC_MAC_FID, 218 DYNAMIC_MAC_ENTRIES_H, 219 DYNAMIC_MAC_ENTRIES, 220 DYNAMIC_MAC_FID, 221 DYNAMIC_MAC_TIMESTAMP, 222 DYNAMIC_MAC_SRC_PORT, 223 ALU_STAT_INDEX, 224 }; 225 226 enum ksz_xmii_ctrl0 { 227 P_MII_100MBIT, 228 P_MII_10MBIT, 229 P_MII_FULL_DUPLEX, 230 P_MII_HALF_DUPLEX, 231 }; 232 233 enum ksz_xmii_ctrl1 { 234 P_RGMII_SEL, 235 P_RMII_SEL, 236 P_GMII_SEL, 237 P_MII_SEL, 238 P_GMII_1GBIT, 239 P_GMII_NOT_1GBIT, 240 }; 241 242 struct alu_struct { 243 /* entry 1 */ 244 u8 is_static:1; 245 u8 is_src_filter:1; 246 u8 is_dst_filter:1; 247 u8 prio_age:3; 248 u32 _reserv_0_1:23; 249 u8 mstp:3; 250 /* entry 2 */ 251 u8 is_override:1; 252 u8 is_use_fid:1; 253 u32 _reserv_1_1:23; 254 u8 port_forward:7; 255 /* entry 3 & 4*/ 256 u32 _reserv_2_1:9; 257 u8 fid:7; 258 u8 mac[ETH_ALEN]; 259 }; 260 261 struct ksz_dev_ops { 262 int (*setup)(struct dsa_switch *ds); 263 u32 (*get_port_addr)(int port, int offset); 264 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 265 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 266 void (*port_cleanup)(struct ksz_device *dev, int port); 267 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 268 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 269 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 270 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 271 u64 *cnt); 272 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 273 u64 *dropped, u64 *cnt); 274 void (*r_mib_stat64)(struct ksz_device *dev, int port); 275 int (*vlan_filtering)(struct ksz_device *dev, int port, 276 bool flag, struct netlink_ext_ack *extack); 277 int (*vlan_add)(struct ksz_device *dev, int port, 278 const struct switchdev_obj_port_vlan *vlan, 279 struct netlink_ext_ack *extack); 280 int (*vlan_del)(struct ksz_device *dev, int port, 281 const struct switchdev_obj_port_vlan *vlan); 282 int (*mirror_add)(struct ksz_device *dev, int port, 283 struct dsa_mall_mirror_tc_entry *mirror, 284 bool ingress, struct netlink_ext_ack *extack); 285 void (*mirror_del)(struct ksz_device *dev, int port, 286 struct dsa_mall_mirror_tc_entry *mirror); 287 int (*fdb_add)(struct ksz_device *dev, int port, 288 const unsigned char *addr, u16 vid, struct dsa_db db); 289 int (*fdb_del)(struct ksz_device *dev, int port, 290 const unsigned char *addr, u16 vid, struct dsa_db db); 291 int (*fdb_dump)(struct ksz_device *dev, int port, 292 dsa_fdb_dump_cb_t *cb, void *data); 293 int (*mdb_add)(struct ksz_device *dev, int port, 294 const struct switchdev_obj_port_mdb *mdb, 295 struct dsa_db db); 296 int (*mdb_del)(struct ksz_device *dev, int port, 297 const struct switchdev_obj_port_mdb *mdb, 298 struct dsa_db db); 299 void (*get_caps)(struct ksz_device *dev, int port, 300 struct phylink_config *config); 301 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 302 int (*max_mtu)(struct ksz_device *dev, int port); 303 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 304 void (*port_init_cnt)(struct ksz_device *dev, int port); 305 void (*phylink_mac_config)(struct ksz_device *dev, int port, 306 unsigned int mode, 307 const struct phylink_link_state *state); 308 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 309 unsigned int mode, 310 phy_interface_t interface, 311 struct phy_device *phydev, int speed, 312 int duplex, bool tx_pause, bool rx_pause); 313 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 314 void (*config_cpu_port)(struct dsa_switch *ds); 315 int (*enable_stp_addr)(struct ksz_device *dev); 316 int (*reset)(struct ksz_device *dev); 317 int (*init)(struct ksz_device *dev); 318 void (*exit)(struct ksz_device *dev); 319 }; 320 321 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 322 int ksz_switch_register(struct ksz_device *dev); 323 void ksz_switch_remove(struct ksz_device *dev); 324 325 void ksz_init_mib_timer(struct ksz_device *dev); 326 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 327 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 328 bool ksz_get_gbit(struct ksz_device *dev, int port); 329 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 330 extern const struct ksz_chip_data ksz_switch_chips[]; 331 332 /* Common register access functions */ 333 334 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 335 { 336 unsigned int value; 337 int ret = regmap_read(dev->regmap[0], reg, &value); 338 339 if (ret) 340 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 341 ERR_PTR(ret)); 342 343 *val = value; 344 return ret; 345 } 346 347 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 348 { 349 unsigned int value; 350 int ret = regmap_read(dev->regmap[1], reg, &value); 351 352 if (ret) 353 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 354 ERR_PTR(ret)); 355 356 *val = value; 357 return ret; 358 } 359 360 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 361 { 362 unsigned int value; 363 int ret = regmap_read(dev->regmap[2], reg, &value); 364 365 if (ret) 366 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 367 ERR_PTR(ret)); 368 369 *val = value; 370 return ret; 371 } 372 373 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 374 { 375 u32 value[2]; 376 int ret; 377 378 ret = regmap_bulk_read(dev->regmap[2], reg, value, 2); 379 if (ret) 380 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 381 ERR_PTR(ret)); 382 else 383 *val = (u64)value[0] << 32 | value[1]; 384 385 return ret; 386 } 387 388 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 389 { 390 int ret; 391 392 ret = regmap_write(dev->regmap[0], reg, value); 393 if (ret) 394 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 395 ERR_PTR(ret)); 396 397 return ret; 398 } 399 400 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 401 { 402 int ret; 403 404 ret = regmap_write(dev->regmap[1], reg, value); 405 if (ret) 406 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 407 ERR_PTR(ret)); 408 409 return ret; 410 } 411 412 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 413 { 414 int ret; 415 416 ret = regmap_write(dev->regmap[2], reg, value); 417 if (ret) 418 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 419 ERR_PTR(ret)); 420 421 return ret; 422 } 423 424 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 425 { 426 u32 val[2]; 427 428 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 429 value = swab64(value); 430 val[0] = swab32(value & 0xffffffffULL); 431 val[1] = swab32(value >> 32ULL); 432 433 return regmap_bulk_write(dev->regmap[2], reg, val, 2); 434 } 435 436 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 437 u8 *data) 438 { 439 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 440 } 441 442 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 443 u16 *data) 444 { 445 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 446 } 447 448 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 449 u32 *data) 450 { 451 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 452 } 453 454 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 455 u8 data) 456 { 457 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 458 } 459 460 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 461 u16 data) 462 { 463 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 464 data); 465 } 466 467 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 468 u32 data) 469 { 470 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 471 data); 472 } 473 474 static inline void ksz_prmw8(struct ksz_device *dev, int port, int offset, 475 u8 mask, u8 val) 476 { 477 regmap_update_bits(dev->regmap[0], 478 dev->dev_ops->get_port_addr(port, offset), 479 mask, val); 480 } 481 482 static inline void ksz_regmap_lock(void *__mtx) 483 { 484 struct mutex *mtx = __mtx; 485 mutex_lock(mtx); 486 } 487 488 static inline void ksz_regmap_unlock(void *__mtx) 489 { 490 struct mutex *mtx = __mtx; 491 mutex_unlock(mtx); 492 } 493 494 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 495 { 496 return dev->chip_id == KSZ8830_CHIP_ID; 497 } 498 499 static inline int is_lan937x(struct ksz_device *dev) 500 { 501 return dev->chip_id == LAN9370_CHIP_ID || 502 dev->chip_id == LAN9371_CHIP_ID || 503 dev->chip_id == LAN9372_CHIP_ID || 504 dev->chip_id == LAN9373_CHIP_ID || 505 dev->chip_id == LAN9374_CHIP_ID; 506 } 507 508 /* STP State Defines */ 509 #define PORT_TX_ENABLE BIT(2) 510 #define PORT_RX_ENABLE BIT(1) 511 #define PORT_LEARN_DISABLE BIT(0) 512 513 /* Switch ID Defines */ 514 #define REG_CHIP_ID0 0x00 515 516 #define SW_FAMILY_ID_M GENMASK(15, 8) 517 #define KSZ87_FAMILY_ID 0x87 518 #define KSZ88_FAMILY_ID 0x88 519 520 #define KSZ8_PORT_STATUS_0 0x08 521 #define KSZ8_PORT_FIBER_MODE BIT(7) 522 523 #define SW_CHIP_ID_M GENMASK(7, 4) 524 #define KSZ87_CHIP_ID_94 0x6 525 #define KSZ87_CHIP_ID_95 0x9 526 #define KSZ88_CHIP_ID_63 0x3 527 528 #define SW_REV_ID_M GENMASK(7, 4) 529 530 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 531 #define REG_CHIP_ID4 0x0f 532 #define SKU_ID_KSZ8563 0x3c 533 534 /* Driver set switch broadcast storm protection at 10% rate. */ 535 #define BROADCAST_STORM_PROT_RATE 10 536 537 /* 148,800 frames * 67 ms / 100 */ 538 #define BROADCAST_STORM_VALUE 9969 539 540 #define BROADCAST_STORM_RATE_HI 0x07 541 #define BROADCAST_STORM_RATE_LO 0xFF 542 #define BROADCAST_STORM_RATE 0x07FF 543 544 #define MULTICAST_STORM_DISABLE BIT(6) 545 546 #define SW_START 0x01 547 548 /* xMII configuration */ 549 #define P_MII_DUPLEX_M BIT(6) 550 #define P_MII_100MBIT_M BIT(4) 551 552 #define P_GMII_1GBIT_M BIT(6) 553 #define P_RGMII_ID_IG_ENABLE BIT(4) 554 #define P_RGMII_ID_EG_ENABLE BIT(3) 555 #define P_MII_MAC_MODE BIT(2) 556 #define P_MII_SEL_M 0x3 557 558 /* Regmap tables generation */ 559 #define KSZ_SPI_OP_RD 3 560 #define KSZ_SPI_OP_WR 2 561 562 #define swabnot_used(x) 0 563 564 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 565 swab##swp((opcode) << ((regbits) + (regpad))) 566 567 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 568 { \ 569 .name = #width, \ 570 .val_bits = (width), \ 571 .reg_stride = 1, \ 572 .reg_bits = (regbits) + (regalign), \ 573 .pad_bits = (regpad), \ 574 .max_register = BIT(regbits) - 1, \ 575 .cache_type = REGCACHE_NONE, \ 576 .read_flag_mask = \ 577 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 578 regbits, regpad), \ 579 .write_flag_mask = \ 580 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 581 regbits, regpad), \ 582 .lock = ksz_regmap_lock, \ 583 .unlock = ksz_regmap_unlock, \ 584 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 585 .val_format_endian = REGMAP_ENDIAN_BIG \ 586 } 587 588 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 589 static const struct regmap_config ksz##_regmap_config[] = { \ 590 KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 591 KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 592 KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 593 } 594 595 #endif 596