1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 #include <linux/irq.h> 17 18 #include "ksz_ptp.h" 19 20 #define KSZ_MAX_NUM_PORTS 8 21 22 struct ksz_device; 23 struct ksz_port; 24 25 struct vlan_table { 26 u32 table[3]; 27 }; 28 29 struct ksz_port_mib { 30 struct mutex cnt_mutex; /* structure access */ 31 u8 cnt_ptr; 32 u64 *counters; 33 struct rtnl_link_stats64 stats64; 34 struct ethtool_pause_stats pause_stats; 35 struct spinlock stats64_lock; 36 }; 37 38 struct ksz_mib_names { 39 int index; 40 char string[ETH_GSTRING_LEN]; 41 }; 42 43 struct ksz_chip_data { 44 u32 chip_id; 45 const char *dev_name; 46 int num_vlans; 47 int num_alus; 48 int num_statics; 49 int cpu_ports; 50 int port_cnt; 51 u8 port_nirqs; 52 u8 num_tx_queues; 53 const struct ksz_dev_ops *ops; 54 bool phy_errata_9477; 55 bool ksz87xx_eee_link_erratum; 56 const struct ksz_mib_names *mib_names; 57 int mib_cnt; 58 u8 reg_mib_cnt; 59 const u16 *regs; 60 const u32 *masks; 61 const u8 *shifts; 62 const u8 *xmii_ctrl0; 63 const u8 *xmii_ctrl1; 64 int stp_ctrl_reg; 65 int broadcast_ctrl_reg; 66 int multicast_ctrl_reg; 67 int start_ctrl_reg; 68 bool supports_mii[KSZ_MAX_NUM_PORTS]; 69 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 70 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 71 bool internal_phy[KSZ_MAX_NUM_PORTS]; 72 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 73 const struct regmap_access_table *wr_table; 74 const struct regmap_access_table *rd_table; 75 }; 76 77 struct ksz_irq { 78 u16 masked; 79 u16 reg_mask; 80 u16 reg_status; 81 struct irq_domain *domain; 82 int nirqs; 83 int irq_num; 84 char name[16]; 85 struct ksz_device *dev; 86 }; 87 88 struct ksz_ptp_irq { 89 struct ksz_port *port; 90 u16 ts_reg; 91 bool ts_en; 92 char name[16]; 93 int num; 94 }; 95 96 struct ksz_port { 97 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 98 bool learning; 99 int stp_state; 100 struct phy_device phydev; 101 102 u32 on:1; /* port is not disabled by hardware */ 103 u32 fiber:1; /* port is fiber */ 104 u32 force:1; 105 u32 read:1; /* read MIB counters in background */ 106 u32 freeze:1; /* MIB counter freeze is enabled */ 107 108 struct ksz_port_mib mib; 109 phy_interface_t interface; 110 u32 rgmii_tx_val; 111 u32 rgmii_rx_val; 112 struct ksz_device *ksz_dev; 113 struct ksz_irq pirq; 114 u8 num; 115 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) 116 struct hwtstamp_config tstamp_config; 117 bool hwts_tx_en; 118 bool hwts_rx_en; 119 struct ksz_irq ptpirq; 120 struct ksz_ptp_irq ptpmsg_irq[3]; 121 ktime_t tstamp_msg; 122 struct completion tstamp_msg_comp; 123 #endif 124 }; 125 126 struct ksz_device { 127 struct dsa_switch *ds; 128 struct ksz_platform_data *pdata; 129 const struct ksz_chip_data *info; 130 131 struct mutex dev_mutex; /* device access */ 132 struct mutex regmap_mutex; /* regmap access */ 133 struct mutex alu_mutex; /* ALU access */ 134 struct mutex vlan_mutex; /* vlan access */ 135 const struct ksz_dev_ops *dev_ops; 136 137 struct device *dev; 138 struct regmap *regmap[3]; 139 140 void *priv; 141 int irq; 142 143 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 144 145 /* chip specific data */ 146 u32 chip_id; 147 u8 chip_rev; 148 int cpu_port; /* port connected to CPU */ 149 int phy_port_cnt; 150 phy_interface_t compat_interface; 151 bool synclko_125; 152 bool synclko_disable; 153 154 struct vlan_table *vlan_cache; 155 156 struct ksz_port *ports; 157 struct delayed_work mib_read; 158 unsigned long mib_read_interval; 159 u16 mirror_rx; 160 u16 mirror_tx; 161 u16 port_mask; 162 struct mutex lock_irq; /* IRQ Access */ 163 struct ksz_irq girq; 164 struct ksz_ptp_data ptp_data; 165 }; 166 167 /* List of supported models */ 168 enum ksz_model { 169 KSZ8563, 170 KSZ8795, 171 KSZ8794, 172 KSZ8765, 173 KSZ8830, 174 KSZ9477, 175 KSZ9896, 176 KSZ9897, 177 KSZ9893, 178 KSZ9563, 179 KSZ9567, 180 LAN9370, 181 LAN9371, 182 LAN9372, 183 LAN9373, 184 LAN9374, 185 }; 186 187 enum ksz_chip_id { 188 KSZ8563_CHIP_ID = 0x8563, 189 KSZ8795_CHIP_ID = 0x8795, 190 KSZ8794_CHIP_ID = 0x8794, 191 KSZ8765_CHIP_ID = 0x8765, 192 KSZ8830_CHIP_ID = 0x8830, 193 KSZ9477_CHIP_ID = 0x00947700, 194 KSZ9896_CHIP_ID = 0x00989600, 195 KSZ9897_CHIP_ID = 0x00989700, 196 KSZ9893_CHIP_ID = 0x00989300, 197 KSZ9563_CHIP_ID = 0x00956300, 198 KSZ9567_CHIP_ID = 0x00956700, 199 LAN9370_CHIP_ID = 0x00937000, 200 LAN9371_CHIP_ID = 0x00937100, 201 LAN9372_CHIP_ID = 0x00937200, 202 LAN9373_CHIP_ID = 0x00937300, 203 LAN9374_CHIP_ID = 0x00937400, 204 }; 205 206 enum ksz_regs { 207 REG_IND_CTRL_0, 208 REG_IND_DATA_8, 209 REG_IND_DATA_CHECK, 210 REG_IND_DATA_HI, 211 REG_IND_DATA_LO, 212 REG_IND_MIB_CHECK, 213 REG_IND_BYTE, 214 P_FORCE_CTRL, 215 P_LINK_STATUS, 216 P_LOCAL_CTRL, 217 P_NEG_RESTART_CTRL, 218 P_REMOTE_STATUS, 219 P_SPEED_STATUS, 220 S_TAIL_TAG_CTRL, 221 P_STP_CTRL, 222 S_START_CTRL, 223 S_BROADCAST_CTRL, 224 S_MULTICAST_CTRL, 225 P_XMII_CTRL_0, 226 P_XMII_CTRL_1, 227 }; 228 229 enum ksz_masks { 230 PORT_802_1P_REMAPPING, 231 SW_TAIL_TAG_ENABLE, 232 MIB_COUNTER_OVERFLOW, 233 MIB_COUNTER_VALID, 234 VLAN_TABLE_FID, 235 VLAN_TABLE_MEMBERSHIP, 236 VLAN_TABLE_VALID, 237 STATIC_MAC_TABLE_VALID, 238 STATIC_MAC_TABLE_USE_FID, 239 STATIC_MAC_TABLE_FID, 240 STATIC_MAC_TABLE_OVERRIDE, 241 STATIC_MAC_TABLE_FWD_PORTS, 242 DYNAMIC_MAC_TABLE_ENTRIES_H, 243 DYNAMIC_MAC_TABLE_MAC_EMPTY, 244 DYNAMIC_MAC_TABLE_NOT_READY, 245 DYNAMIC_MAC_TABLE_ENTRIES, 246 DYNAMIC_MAC_TABLE_FID, 247 DYNAMIC_MAC_TABLE_SRC_PORT, 248 DYNAMIC_MAC_TABLE_TIMESTAMP, 249 ALU_STAT_WRITE, 250 ALU_STAT_READ, 251 P_MII_TX_FLOW_CTRL, 252 P_MII_RX_FLOW_CTRL, 253 }; 254 255 enum ksz_shifts { 256 VLAN_TABLE_MEMBERSHIP_S, 257 VLAN_TABLE, 258 STATIC_MAC_FWD_PORTS, 259 STATIC_MAC_FID, 260 DYNAMIC_MAC_ENTRIES_H, 261 DYNAMIC_MAC_ENTRIES, 262 DYNAMIC_MAC_FID, 263 DYNAMIC_MAC_TIMESTAMP, 264 DYNAMIC_MAC_SRC_PORT, 265 ALU_STAT_INDEX, 266 }; 267 268 enum ksz_xmii_ctrl0 { 269 P_MII_100MBIT, 270 P_MII_10MBIT, 271 P_MII_FULL_DUPLEX, 272 P_MII_HALF_DUPLEX, 273 }; 274 275 enum ksz_xmii_ctrl1 { 276 P_RGMII_SEL, 277 P_RMII_SEL, 278 P_GMII_SEL, 279 P_MII_SEL, 280 P_GMII_1GBIT, 281 P_GMII_NOT_1GBIT, 282 }; 283 284 struct alu_struct { 285 /* entry 1 */ 286 u8 is_static:1; 287 u8 is_src_filter:1; 288 u8 is_dst_filter:1; 289 u8 prio_age:3; 290 u32 _reserv_0_1:23; 291 u8 mstp:3; 292 /* entry 2 */ 293 u8 is_override:1; 294 u8 is_use_fid:1; 295 u32 _reserv_1_1:23; 296 u8 port_forward:7; 297 /* entry 3 & 4*/ 298 u32 _reserv_2_1:9; 299 u8 fid:7; 300 u8 mac[ETH_ALEN]; 301 }; 302 303 struct ksz_dev_ops { 304 int (*setup)(struct dsa_switch *ds); 305 void (*teardown)(struct dsa_switch *ds); 306 u32 (*get_port_addr)(int port, int offset); 307 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 308 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 309 void (*port_cleanup)(struct ksz_device *dev, int port); 310 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 311 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); 312 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 313 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 314 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 315 u64 *cnt); 316 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 317 u64 *dropped, u64 *cnt); 318 void (*r_mib_stat64)(struct ksz_device *dev, int port); 319 int (*vlan_filtering)(struct ksz_device *dev, int port, 320 bool flag, struct netlink_ext_ack *extack); 321 int (*vlan_add)(struct ksz_device *dev, int port, 322 const struct switchdev_obj_port_vlan *vlan, 323 struct netlink_ext_ack *extack); 324 int (*vlan_del)(struct ksz_device *dev, int port, 325 const struct switchdev_obj_port_vlan *vlan); 326 int (*mirror_add)(struct ksz_device *dev, int port, 327 struct dsa_mall_mirror_tc_entry *mirror, 328 bool ingress, struct netlink_ext_ack *extack); 329 void (*mirror_del)(struct ksz_device *dev, int port, 330 struct dsa_mall_mirror_tc_entry *mirror); 331 int (*fdb_add)(struct ksz_device *dev, int port, 332 const unsigned char *addr, u16 vid, struct dsa_db db); 333 int (*fdb_del)(struct ksz_device *dev, int port, 334 const unsigned char *addr, u16 vid, struct dsa_db db); 335 int (*fdb_dump)(struct ksz_device *dev, int port, 336 dsa_fdb_dump_cb_t *cb, void *data); 337 int (*mdb_add)(struct ksz_device *dev, int port, 338 const struct switchdev_obj_port_mdb *mdb, 339 struct dsa_db db); 340 int (*mdb_del)(struct ksz_device *dev, int port, 341 const struct switchdev_obj_port_mdb *mdb, 342 struct dsa_db db); 343 void (*get_caps)(struct ksz_device *dev, int port, 344 struct phylink_config *config); 345 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 346 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 347 void (*port_init_cnt)(struct ksz_device *dev, int port); 348 void (*phylink_mac_config)(struct ksz_device *dev, int port, 349 unsigned int mode, 350 const struct phylink_link_state *state); 351 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 352 unsigned int mode, 353 phy_interface_t interface, 354 struct phy_device *phydev, int speed, 355 int duplex, bool tx_pause, bool rx_pause); 356 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 357 void (*config_cpu_port)(struct dsa_switch *ds); 358 int (*enable_stp_addr)(struct ksz_device *dev); 359 int (*reset)(struct ksz_device *dev); 360 int (*init)(struct ksz_device *dev); 361 void (*exit)(struct ksz_device *dev); 362 }; 363 364 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 365 int ksz_switch_register(struct ksz_device *dev); 366 void ksz_switch_remove(struct ksz_device *dev); 367 368 void ksz_init_mib_timer(struct ksz_device *dev); 369 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 370 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port); 371 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 372 bool ksz_get_gbit(struct ksz_device *dev, int port); 373 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 374 extern const struct ksz_chip_data ksz_switch_chips[]; 375 376 /* Common register access functions */ 377 378 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 379 { 380 unsigned int value; 381 int ret = regmap_read(dev->regmap[0], reg, &value); 382 383 if (ret) 384 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 385 ERR_PTR(ret)); 386 387 *val = value; 388 return ret; 389 } 390 391 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 392 { 393 unsigned int value; 394 int ret = regmap_read(dev->regmap[1], reg, &value); 395 396 if (ret) 397 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 398 ERR_PTR(ret)); 399 400 *val = value; 401 return ret; 402 } 403 404 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 405 { 406 unsigned int value; 407 int ret = regmap_read(dev->regmap[2], reg, &value); 408 409 if (ret) 410 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 411 ERR_PTR(ret)); 412 413 *val = value; 414 return ret; 415 } 416 417 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 418 { 419 u32 value[2]; 420 int ret; 421 422 ret = regmap_bulk_read(dev->regmap[2], reg, value, 2); 423 if (ret) 424 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 425 ERR_PTR(ret)); 426 else 427 *val = (u64)value[0] << 32 | value[1]; 428 429 return ret; 430 } 431 432 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 433 { 434 int ret; 435 436 ret = regmap_write(dev->regmap[0], reg, value); 437 if (ret) 438 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 439 ERR_PTR(ret)); 440 441 return ret; 442 } 443 444 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 445 { 446 int ret; 447 448 ret = regmap_write(dev->regmap[1], reg, value); 449 if (ret) 450 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 451 ERR_PTR(ret)); 452 453 return ret; 454 } 455 456 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 457 { 458 int ret; 459 460 ret = regmap_write(dev->regmap[2], reg, value); 461 if (ret) 462 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 463 ERR_PTR(ret)); 464 465 return ret; 466 } 467 468 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, 469 u16 value) 470 { 471 int ret; 472 473 ret = regmap_update_bits(dev->regmap[1], reg, mask, value); 474 if (ret) 475 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg, 476 ERR_PTR(ret)); 477 478 return ret; 479 } 480 481 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask, 482 u32 value) 483 { 484 int ret; 485 486 ret = regmap_update_bits(dev->regmap[2], reg, mask, value); 487 if (ret) 488 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg, 489 ERR_PTR(ret)); 490 491 return ret; 492 } 493 494 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 495 { 496 u32 val[2]; 497 498 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 499 value = swab64(value); 500 val[0] = swab32(value & 0xffffffffULL); 501 val[1] = swab32(value >> 32ULL); 502 503 return regmap_bulk_write(dev->regmap[2], reg, val, 2); 504 } 505 506 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val) 507 { 508 return regmap_update_bits(dev->regmap[0], offset, mask, val); 509 } 510 511 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 512 u8 *data) 513 { 514 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 515 } 516 517 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 518 u16 *data) 519 { 520 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 521 } 522 523 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 524 u32 *data) 525 { 526 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 527 } 528 529 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 530 u8 data) 531 { 532 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 533 } 534 535 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 536 u16 data) 537 { 538 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 539 data); 540 } 541 542 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 543 u32 data) 544 { 545 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 546 data); 547 } 548 549 static inline void ksz_prmw8(struct ksz_device *dev, int port, int offset, 550 u8 mask, u8 val) 551 { 552 regmap_update_bits(dev->regmap[0], 553 dev->dev_ops->get_port_addr(port, offset), 554 mask, val); 555 } 556 557 static inline void ksz_regmap_lock(void *__mtx) 558 { 559 struct mutex *mtx = __mtx; 560 mutex_lock(mtx); 561 } 562 563 static inline void ksz_regmap_unlock(void *__mtx) 564 { 565 struct mutex *mtx = __mtx; 566 mutex_unlock(mtx); 567 } 568 569 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 570 { 571 return dev->chip_id == KSZ8830_CHIP_ID; 572 } 573 574 static inline int is_lan937x(struct ksz_device *dev) 575 { 576 return dev->chip_id == LAN9370_CHIP_ID || 577 dev->chip_id == LAN9371_CHIP_ID || 578 dev->chip_id == LAN9372_CHIP_ID || 579 dev->chip_id == LAN9373_CHIP_ID || 580 dev->chip_id == LAN9374_CHIP_ID; 581 } 582 583 /* STP State Defines */ 584 #define PORT_TX_ENABLE BIT(2) 585 #define PORT_RX_ENABLE BIT(1) 586 #define PORT_LEARN_DISABLE BIT(0) 587 588 /* Switch ID Defines */ 589 #define REG_CHIP_ID0 0x00 590 591 #define SW_FAMILY_ID_M GENMASK(15, 8) 592 #define KSZ87_FAMILY_ID 0x87 593 #define KSZ88_FAMILY_ID 0x88 594 595 #define KSZ8_PORT_STATUS_0 0x08 596 #define KSZ8_PORT_FIBER_MODE BIT(7) 597 598 #define SW_CHIP_ID_M GENMASK(7, 4) 599 #define KSZ87_CHIP_ID_94 0x6 600 #define KSZ87_CHIP_ID_95 0x9 601 #define KSZ88_CHIP_ID_63 0x3 602 603 #define SW_REV_ID_M GENMASK(7, 4) 604 605 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 606 #define REG_CHIP_ID4 0x0f 607 #define SKU_ID_KSZ8563 0x3c 608 #define SKU_ID_KSZ9563 0x1c 609 610 /* Driver set switch broadcast storm protection at 10% rate. */ 611 #define BROADCAST_STORM_PROT_RATE 10 612 613 /* 148,800 frames * 67 ms / 100 */ 614 #define BROADCAST_STORM_VALUE 9969 615 616 #define BROADCAST_STORM_RATE_HI 0x07 617 #define BROADCAST_STORM_RATE_LO 0xFF 618 #define BROADCAST_STORM_RATE 0x07FF 619 620 #define MULTICAST_STORM_DISABLE BIT(6) 621 622 #define SW_START 0x01 623 624 /* xMII configuration */ 625 #define P_MII_DUPLEX_M BIT(6) 626 #define P_MII_100MBIT_M BIT(4) 627 628 #define P_GMII_1GBIT_M BIT(6) 629 #define P_RGMII_ID_IG_ENABLE BIT(4) 630 #define P_RGMII_ID_EG_ENABLE BIT(3) 631 #define P_MII_MAC_MODE BIT(2) 632 #define P_MII_SEL_M 0x3 633 634 /* Interrupt */ 635 #define REG_SW_PORT_INT_STATUS__1 0x001B 636 #define REG_SW_PORT_INT_MASK__1 0x001F 637 638 #define REG_PORT_INT_STATUS 0x001B 639 #define REG_PORT_INT_MASK 0x001F 640 641 #define PORT_SRC_PHY_INT 1 642 #define PORT_SRC_PTP_INT 2 643 644 #define KSZ8795_HUGE_PACKET_SIZE 2000 645 #define KSZ8863_HUGE_PACKET_SIZE 1916 646 #define KSZ8863_NORMAL_PACKET_SIZE 1536 647 #define KSZ8_LEGAL_PACKET_SIZE 1518 648 #define KSZ9477_MAX_FRAME_SIZE 9000 649 650 /* Regmap tables generation */ 651 #define KSZ_SPI_OP_RD 3 652 #define KSZ_SPI_OP_WR 2 653 654 #define swabnot_used(x) 0 655 656 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 657 swab##swp((opcode) << ((regbits) + (regpad))) 658 659 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 660 { \ 661 .name = #width, \ 662 .val_bits = (width), \ 663 .reg_stride = 1, \ 664 .reg_bits = (regbits) + (regalign), \ 665 .pad_bits = (regpad), \ 666 .max_register = BIT(regbits) - 1, \ 667 .cache_type = REGCACHE_NONE, \ 668 .read_flag_mask = \ 669 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 670 regbits, regpad), \ 671 .write_flag_mask = \ 672 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 673 regbits, regpad), \ 674 .lock = ksz_regmap_lock, \ 675 .unlock = ksz_regmap_unlock, \ 676 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 677 .val_format_endian = REGMAP_ENDIAN_BIG \ 678 } 679 680 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 681 static const struct regmap_config ksz##_regmap_config[] = { \ 682 KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 683 KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 684 KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 685 } 686 687 #endif 688