1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 17 #define KSZ_MAX_NUM_PORTS 8 18 19 struct vlan_table { 20 u32 table[3]; 21 }; 22 23 struct ksz_port_mib { 24 struct mutex cnt_mutex; /* structure access */ 25 u8 cnt_ptr; 26 u64 *counters; 27 struct rtnl_link_stats64 stats64; 28 struct ethtool_pause_stats pause_stats; 29 struct spinlock stats64_lock; 30 }; 31 32 struct ksz_mib_names { 33 int index; 34 char string[ETH_GSTRING_LEN]; 35 }; 36 37 struct ksz_chip_data { 38 u32 chip_id; 39 const char *dev_name; 40 int num_vlans; 41 int num_alus; 42 int num_statics; 43 int cpu_ports; 44 int port_cnt; 45 const struct ksz_dev_ops *ops; 46 bool phy_errata_9477; 47 bool ksz87xx_eee_link_erratum; 48 const struct ksz_mib_names *mib_names; 49 int mib_cnt; 50 u8 reg_mib_cnt; 51 const u16 *regs; 52 const u32 *masks; 53 const u8 *shifts; 54 const u8 *xmii_ctrl0; 55 const u8 *xmii_ctrl1; 56 int stp_ctrl_reg; 57 int broadcast_ctrl_reg; 58 int multicast_ctrl_reg; 59 int start_ctrl_reg; 60 bool supports_mii[KSZ_MAX_NUM_PORTS]; 61 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 62 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 63 bool internal_phy[KSZ_MAX_NUM_PORTS]; 64 }; 65 66 struct ksz_port { 67 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 68 int stp_state; 69 struct phy_device phydev; 70 71 u32 on:1; /* port is not disabled by hardware */ 72 u32 phy:1; /* port has a PHY */ 73 u32 fiber:1; /* port is fiber */ 74 u32 sgmii:1; /* port is SGMII */ 75 u32 force:1; 76 u32 read:1; /* read MIB counters in background */ 77 u32 freeze:1; /* MIB counter freeze is enabled */ 78 79 struct ksz_port_mib mib; 80 phy_interface_t interface; 81 u16 max_frame; 82 }; 83 84 struct ksz_device { 85 struct dsa_switch *ds; 86 struct ksz_platform_data *pdata; 87 const struct ksz_chip_data *info; 88 89 struct mutex dev_mutex; /* device access */ 90 struct mutex regmap_mutex; /* regmap access */ 91 struct mutex alu_mutex; /* ALU access */ 92 struct mutex vlan_mutex; /* vlan access */ 93 const struct ksz_dev_ops *dev_ops; 94 95 struct device *dev; 96 struct regmap *regmap[3]; 97 98 void *priv; 99 100 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 101 102 /* chip specific data */ 103 u32 chip_id; 104 u8 chip_rev; 105 int cpu_port; /* port connected to CPU */ 106 int phy_port_cnt; 107 phy_interface_t compat_interface; 108 bool synclko_125; 109 bool synclko_disable; 110 111 struct vlan_table *vlan_cache; 112 113 struct ksz_port *ports; 114 struct delayed_work mib_read; 115 unsigned long mib_read_interval; 116 u16 mirror_rx; 117 u16 mirror_tx; 118 u32 features; /* chip specific features */ 119 u16 port_mask; 120 }; 121 122 /* List of supported models */ 123 enum ksz_model { 124 KSZ8795, 125 KSZ8794, 126 KSZ8765, 127 KSZ8830, 128 KSZ9477, 129 KSZ9897, 130 KSZ9893, 131 KSZ9567, 132 LAN9370, 133 LAN9371, 134 LAN9372, 135 LAN9373, 136 LAN9374, 137 }; 138 139 enum ksz_chip_id { 140 KSZ8795_CHIP_ID = 0x8795, 141 KSZ8794_CHIP_ID = 0x8794, 142 KSZ8765_CHIP_ID = 0x8765, 143 KSZ8830_CHIP_ID = 0x8830, 144 KSZ9477_CHIP_ID = 0x00947700, 145 KSZ9897_CHIP_ID = 0x00989700, 146 KSZ9893_CHIP_ID = 0x00989300, 147 KSZ9567_CHIP_ID = 0x00956700, 148 LAN9370_CHIP_ID = 0x00937000, 149 LAN9371_CHIP_ID = 0x00937100, 150 LAN9372_CHIP_ID = 0x00937200, 151 LAN9373_CHIP_ID = 0x00937300, 152 LAN9374_CHIP_ID = 0x00937400, 153 }; 154 155 enum ksz_regs { 156 REG_IND_CTRL_0, 157 REG_IND_DATA_8, 158 REG_IND_DATA_CHECK, 159 REG_IND_DATA_HI, 160 REG_IND_DATA_LO, 161 REG_IND_MIB_CHECK, 162 REG_IND_BYTE, 163 P_FORCE_CTRL, 164 P_LINK_STATUS, 165 P_LOCAL_CTRL, 166 P_NEG_RESTART_CTRL, 167 P_REMOTE_STATUS, 168 P_SPEED_STATUS, 169 S_TAIL_TAG_CTRL, 170 P_STP_CTRL, 171 S_START_CTRL, 172 S_BROADCAST_CTRL, 173 S_MULTICAST_CTRL, 174 P_XMII_CTRL_0, 175 P_XMII_CTRL_1, 176 }; 177 178 enum ksz_masks { 179 PORT_802_1P_REMAPPING, 180 SW_TAIL_TAG_ENABLE, 181 MIB_COUNTER_OVERFLOW, 182 MIB_COUNTER_VALID, 183 VLAN_TABLE_FID, 184 VLAN_TABLE_MEMBERSHIP, 185 VLAN_TABLE_VALID, 186 STATIC_MAC_TABLE_VALID, 187 STATIC_MAC_TABLE_USE_FID, 188 STATIC_MAC_TABLE_FID, 189 STATIC_MAC_TABLE_OVERRIDE, 190 STATIC_MAC_TABLE_FWD_PORTS, 191 DYNAMIC_MAC_TABLE_ENTRIES_H, 192 DYNAMIC_MAC_TABLE_MAC_EMPTY, 193 DYNAMIC_MAC_TABLE_NOT_READY, 194 DYNAMIC_MAC_TABLE_ENTRIES, 195 DYNAMIC_MAC_TABLE_FID, 196 DYNAMIC_MAC_TABLE_SRC_PORT, 197 DYNAMIC_MAC_TABLE_TIMESTAMP, 198 ALU_STAT_WRITE, 199 ALU_STAT_READ, 200 P_MII_TX_FLOW_CTRL, 201 P_MII_RX_FLOW_CTRL, 202 }; 203 204 enum ksz_shifts { 205 VLAN_TABLE_MEMBERSHIP_S, 206 VLAN_TABLE, 207 STATIC_MAC_FWD_PORTS, 208 STATIC_MAC_FID, 209 DYNAMIC_MAC_ENTRIES_H, 210 DYNAMIC_MAC_ENTRIES, 211 DYNAMIC_MAC_FID, 212 DYNAMIC_MAC_TIMESTAMP, 213 DYNAMIC_MAC_SRC_PORT, 214 ALU_STAT_INDEX, 215 }; 216 217 enum ksz_xmii_ctrl0 { 218 P_MII_100MBIT, 219 P_MII_10MBIT, 220 P_MII_FULL_DUPLEX, 221 P_MII_HALF_DUPLEX, 222 }; 223 224 enum ksz_xmii_ctrl1 { 225 P_GMII_1GBIT, 226 P_GMII_NOT_1GBIT, 227 }; 228 229 struct alu_struct { 230 /* entry 1 */ 231 u8 is_static:1; 232 u8 is_src_filter:1; 233 u8 is_dst_filter:1; 234 u8 prio_age:3; 235 u32 _reserv_0_1:23; 236 u8 mstp:3; 237 /* entry 2 */ 238 u8 is_override:1; 239 u8 is_use_fid:1; 240 u32 _reserv_1_1:23; 241 u8 port_forward:7; 242 /* entry 3 & 4*/ 243 u32 _reserv_2_1:9; 244 u8 fid:7; 245 u8 mac[ETH_ALEN]; 246 }; 247 248 struct ksz_dev_ops { 249 int (*setup)(struct dsa_switch *ds); 250 u32 (*get_port_addr)(int port, int offset); 251 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 252 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 253 void (*port_cleanup)(struct ksz_device *dev, int port); 254 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 255 void (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 256 void (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 257 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 258 u64 *cnt); 259 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 260 u64 *dropped, u64 *cnt); 261 void (*r_mib_stat64)(struct ksz_device *dev, int port); 262 int (*vlan_filtering)(struct ksz_device *dev, int port, 263 bool flag, struct netlink_ext_ack *extack); 264 int (*vlan_add)(struct ksz_device *dev, int port, 265 const struct switchdev_obj_port_vlan *vlan, 266 struct netlink_ext_ack *extack); 267 int (*vlan_del)(struct ksz_device *dev, int port, 268 const struct switchdev_obj_port_vlan *vlan); 269 int (*mirror_add)(struct ksz_device *dev, int port, 270 struct dsa_mall_mirror_tc_entry *mirror, 271 bool ingress, struct netlink_ext_ack *extack); 272 void (*mirror_del)(struct ksz_device *dev, int port, 273 struct dsa_mall_mirror_tc_entry *mirror); 274 int (*fdb_add)(struct ksz_device *dev, int port, 275 const unsigned char *addr, u16 vid, struct dsa_db db); 276 int (*fdb_del)(struct ksz_device *dev, int port, 277 const unsigned char *addr, u16 vid, struct dsa_db db); 278 int (*fdb_dump)(struct ksz_device *dev, int port, 279 dsa_fdb_dump_cb_t *cb, void *data); 280 int (*mdb_add)(struct ksz_device *dev, int port, 281 const struct switchdev_obj_port_mdb *mdb, 282 struct dsa_db db); 283 int (*mdb_del)(struct ksz_device *dev, int port, 284 const struct switchdev_obj_port_mdb *mdb, 285 struct dsa_db db); 286 void (*get_caps)(struct ksz_device *dev, int port, 287 struct phylink_config *config); 288 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 289 int (*max_mtu)(struct ksz_device *dev, int port); 290 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 291 void (*port_init_cnt)(struct ksz_device *dev, int port); 292 void (*phylink_mac_config)(struct ksz_device *dev, int port, 293 unsigned int mode, 294 const struct phylink_link_state *state); 295 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 296 unsigned int mode, 297 phy_interface_t interface, 298 struct phy_device *phydev, int speed, 299 int duplex, bool tx_pause, bool rx_pause); 300 void (*config_cpu_port)(struct dsa_switch *ds); 301 int (*enable_stp_addr)(struct ksz_device *dev); 302 int (*reset)(struct ksz_device *dev); 303 int (*init)(struct ksz_device *dev); 304 void (*exit)(struct ksz_device *dev); 305 }; 306 307 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 308 int ksz_switch_register(struct ksz_device *dev); 309 void ksz_switch_remove(struct ksz_device *dev); 310 311 void ksz_init_mib_timer(struct ksz_device *dev); 312 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 313 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 314 bool ksz_get_gbit(struct ksz_device *dev, int port); 315 void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit); 316 extern const struct ksz_chip_data ksz_switch_chips[]; 317 318 /* Common register access functions */ 319 320 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 321 { 322 unsigned int value; 323 int ret = regmap_read(dev->regmap[0], reg, &value); 324 325 *val = value; 326 return ret; 327 } 328 329 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 330 { 331 unsigned int value; 332 int ret = regmap_read(dev->regmap[1], reg, &value); 333 334 *val = value; 335 return ret; 336 } 337 338 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 339 { 340 unsigned int value; 341 int ret = regmap_read(dev->regmap[2], reg, &value); 342 343 *val = value; 344 return ret; 345 } 346 347 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 348 { 349 u32 value[2]; 350 int ret; 351 352 ret = regmap_bulk_read(dev->regmap[2], reg, value, 2); 353 if (!ret) 354 *val = (u64)value[0] << 32 | value[1]; 355 356 return ret; 357 } 358 359 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 360 { 361 return regmap_write(dev->regmap[0], reg, value); 362 } 363 364 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 365 { 366 return regmap_write(dev->regmap[1], reg, value); 367 } 368 369 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 370 { 371 return regmap_write(dev->regmap[2], reg, value); 372 } 373 374 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 375 { 376 u32 val[2]; 377 378 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 379 value = swab64(value); 380 val[0] = swab32(value & 0xffffffffULL); 381 val[1] = swab32(value >> 32ULL); 382 383 return regmap_bulk_write(dev->regmap[2], reg, val, 2); 384 } 385 386 static inline void ksz_pread8(struct ksz_device *dev, int port, int offset, 387 u8 *data) 388 { 389 ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 390 } 391 392 static inline void ksz_pread16(struct ksz_device *dev, int port, int offset, 393 u16 *data) 394 { 395 ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 396 } 397 398 static inline void ksz_pread32(struct ksz_device *dev, int port, int offset, 399 u32 *data) 400 { 401 ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 402 } 403 404 static inline void ksz_pwrite8(struct ksz_device *dev, int port, int offset, 405 u8 data) 406 { 407 ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 408 } 409 410 static inline void ksz_pwrite16(struct ksz_device *dev, int port, int offset, 411 u16 data) 412 { 413 ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), data); 414 } 415 416 static inline void ksz_pwrite32(struct ksz_device *dev, int port, int offset, 417 u32 data) 418 { 419 ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), data); 420 } 421 422 static inline void ksz_prmw8(struct ksz_device *dev, int port, int offset, 423 u8 mask, u8 val) 424 { 425 regmap_update_bits(dev->regmap[0], 426 dev->dev_ops->get_port_addr(port, offset), 427 mask, val); 428 } 429 430 static inline void ksz_regmap_lock(void *__mtx) 431 { 432 struct mutex *mtx = __mtx; 433 mutex_lock(mtx); 434 } 435 436 static inline void ksz_regmap_unlock(void *__mtx) 437 { 438 struct mutex *mtx = __mtx; 439 mutex_unlock(mtx); 440 } 441 442 static inline int is_lan937x(struct ksz_device *dev) 443 { 444 return dev->chip_id == LAN9370_CHIP_ID || 445 dev->chip_id == LAN9371_CHIP_ID || 446 dev->chip_id == LAN9372_CHIP_ID || 447 dev->chip_id == LAN9373_CHIP_ID || 448 dev->chip_id == LAN9374_CHIP_ID; 449 } 450 451 /* STP State Defines */ 452 #define PORT_TX_ENABLE BIT(2) 453 #define PORT_RX_ENABLE BIT(1) 454 #define PORT_LEARN_DISABLE BIT(0) 455 456 /* Switch ID Defines */ 457 #define REG_CHIP_ID0 0x00 458 459 #define SW_FAMILY_ID_M GENMASK(15, 8) 460 #define KSZ87_FAMILY_ID 0x87 461 #define KSZ88_FAMILY_ID 0x88 462 463 #define KSZ8_PORT_STATUS_0 0x08 464 #define KSZ8_PORT_FIBER_MODE BIT(7) 465 466 #define SW_CHIP_ID_M GENMASK(7, 4) 467 #define KSZ87_CHIP_ID_94 0x6 468 #define KSZ87_CHIP_ID_95 0x9 469 #define KSZ88_CHIP_ID_63 0x3 470 471 #define SW_REV_ID_M GENMASK(7, 4) 472 473 /* Driver set switch broadcast storm protection at 10% rate. */ 474 #define BROADCAST_STORM_PROT_RATE 10 475 476 /* 148,800 frames * 67 ms / 100 */ 477 #define BROADCAST_STORM_VALUE 9969 478 479 #define BROADCAST_STORM_RATE_HI 0x07 480 #define BROADCAST_STORM_RATE_LO 0xFF 481 #define BROADCAST_STORM_RATE 0x07FF 482 483 #define MULTICAST_STORM_DISABLE BIT(6) 484 485 #define SW_START 0x01 486 487 /* xMII configuration */ 488 #define P_MII_DUPLEX_M BIT(6) 489 #define P_MII_100MBIT_M BIT(4) 490 491 #define P_GMII_1GBIT_M BIT(6) 492 493 /* Regmap tables generation */ 494 #define KSZ_SPI_OP_RD 3 495 #define KSZ_SPI_OP_WR 2 496 497 #define swabnot_used(x) 0 498 499 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 500 swab##swp((opcode) << ((regbits) + (regpad))) 501 502 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 503 { \ 504 .name = #width, \ 505 .val_bits = (width), \ 506 .reg_stride = 1, \ 507 .reg_bits = (regbits) + (regalign), \ 508 .pad_bits = (regpad), \ 509 .max_register = BIT(regbits) - 1, \ 510 .cache_type = REGCACHE_NONE, \ 511 .read_flag_mask = \ 512 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 513 regbits, regpad), \ 514 .write_flag_mask = \ 515 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 516 regbits, regpad), \ 517 .lock = ksz_regmap_lock, \ 518 .unlock = ksz_regmap_unlock, \ 519 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 520 .val_format_endian = REGMAP_ENDIAN_BIG \ 521 } 522 523 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 524 static const struct regmap_config ksz##_regmap_config[] = { \ 525 KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 526 KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 527 KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 528 } 529 530 #endif 531