1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 #include <linux/irq.h> 17 18 #include "ksz_ptp.h" 19 20 #define KSZ_MAX_NUM_PORTS 8 21 22 struct ksz_device; 23 struct ksz_port; 24 25 struct vlan_table { 26 u32 table[3]; 27 }; 28 29 struct ksz_port_mib { 30 struct mutex cnt_mutex; /* structure access */ 31 u8 cnt_ptr; 32 u64 *counters; 33 struct rtnl_link_stats64 stats64; 34 struct ethtool_pause_stats pause_stats; 35 struct spinlock stats64_lock; 36 }; 37 38 struct ksz_mib_names { 39 int index; 40 char string[ETH_GSTRING_LEN]; 41 }; 42 43 struct ksz_chip_data { 44 u32 chip_id; 45 const char *dev_name; 46 int num_vlans; 47 int num_alus; 48 int num_statics; 49 int cpu_ports; 50 int port_cnt; 51 u8 port_nirqs; 52 const struct ksz_dev_ops *ops; 53 bool phy_errata_9477; 54 bool ksz87xx_eee_link_erratum; 55 const struct ksz_mib_names *mib_names; 56 int mib_cnt; 57 u8 reg_mib_cnt; 58 const u16 *regs; 59 const u32 *masks; 60 const u8 *shifts; 61 const u8 *xmii_ctrl0; 62 const u8 *xmii_ctrl1; 63 int stp_ctrl_reg; 64 int broadcast_ctrl_reg; 65 int multicast_ctrl_reg; 66 int start_ctrl_reg; 67 bool supports_mii[KSZ_MAX_NUM_PORTS]; 68 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 69 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 70 bool internal_phy[KSZ_MAX_NUM_PORTS]; 71 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 72 const struct regmap_access_table *wr_table; 73 const struct regmap_access_table *rd_table; 74 }; 75 76 struct ksz_irq { 77 u16 masked; 78 u16 reg_mask; 79 u16 reg_status; 80 struct irq_domain *domain; 81 int nirqs; 82 int irq_num; 83 char name[16]; 84 struct ksz_device *dev; 85 }; 86 87 struct ksz_ptp_irq { 88 struct ksz_port *port; 89 u16 ts_reg; 90 char name[16]; 91 int num; 92 }; 93 94 struct ksz_port { 95 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 96 bool learning; 97 int stp_state; 98 struct phy_device phydev; 99 100 u32 on:1; /* port is not disabled by hardware */ 101 u32 fiber:1; /* port is fiber */ 102 u32 force:1; 103 u32 read:1; /* read MIB counters in background */ 104 u32 freeze:1; /* MIB counter freeze is enabled */ 105 106 struct ksz_port_mib mib; 107 phy_interface_t interface; 108 u32 rgmii_tx_val; 109 u32 rgmii_rx_val; 110 struct ksz_device *ksz_dev; 111 struct ksz_irq pirq; 112 u8 num; 113 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) 114 struct hwtstamp_config tstamp_config; 115 bool hwts_tx_en; 116 bool hwts_rx_en; 117 struct ksz_irq ptpirq; 118 struct ksz_ptp_irq ptpmsg_irq[3]; 119 #endif 120 }; 121 122 struct ksz_device { 123 struct dsa_switch *ds; 124 struct ksz_platform_data *pdata; 125 const struct ksz_chip_data *info; 126 127 struct mutex dev_mutex; /* device access */ 128 struct mutex regmap_mutex; /* regmap access */ 129 struct mutex alu_mutex; /* ALU access */ 130 struct mutex vlan_mutex; /* vlan access */ 131 const struct ksz_dev_ops *dev_ops; 132 133 struct device *dev; 134 struct regmap *regmap[3]; 135 136 void *priv; 137 int irq; 138 139 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 140 141 /* chip specific data */ 142 u32 chip_id; 143 u8 chip_rev; 144 int cpu_port; /* port connected to CPU */ 145 int phy_port_cnt; 146 phy_interface_t compat_interface; 147 bool synclko_125; 148 bool synclko_disable; 149 150 struct vlan_table *vlan_cache; 151 152 struct ksz_port *ports; 153 struct delayed_work mib_read; 154 unsigned long mib_read_interval; 155 u16 mirror_rx; 156 u16 mirror_tx; 157 u16 port_mask; 158 struct mutex lock_irq; /* IRQ Access */ 159 struct ksz_irq girq; 160 struct ksz_ptp_data ptp_data; 161 }; 162 163 /* List of supported models */ 164 enum ksz_model { 165 KSZ8563, 166 KSZ8795, 167 KSZ8794, 168 KSZ8765, 169 KSZ8830, 170 KSZ9477, 171 KSZ9896, 172 KSZ9897, 173 KSZ9893, 174 KSZ9563, 175 KSZ9567, 176 LAN9370, 177 LAN9371, 178 LAN9372, 179 LAN9373, 180 LAN9374, 181 }; 182 183 enum ksz_chip_id { 184 KSZ8563_CHIP_ID = 0x8563, 185 KSZ8795_CHIP_ID = 0x8795, 186 KSZ8794_CHIP_ID = 0x8794, 187 KSZ8765_CHIP_ID = 0x8765, 188 KSZ8830_CHIP_ID = 0x8830, 189 KSZ9477_CHIP_ID = 0x00947700, 190 KSZ9896_CHIP_ID = 0x00989600, 191 KSZ9897_CHIP_ID = 0x00989700, 192 KSZ9893_CHIP_ID = 0x00989300, 193 KSZ9563_CHIP_ID = 0x00956300, 194 KSZ9567_CHIP_ID = 0x00956700, 195 LAN9370_CHIP_ID = 0x00937000, 196 LAN9371_CHIP_ID = 0x00937100, 197 LAN9372_CHIP_ID = 0x00937200, 198 LAN9373_CHIP_ID = 0x00937300, 199 LAN9374_CHIP_ID = 0x00937400, 200 }; 201 202 enum ksz_regs { 203 REG_IND_CTRL_0, 204 REG_IND_DATA_8, 205 REG_IND_DATA_CHECK, 206 REG_IND_DATA_HI, 207 REG_IND_DATA_LO, 208 REG_IND_MIB_CHECK, 209 REG_IND_BYTE, 210 P_FORCE_CTRL, 211 P_LINK_STATUS, 212 P_LOCAL_CTRL, 213 P_NEG_RESTART_CTRL, 214 P_REMOTE_STATUS, 215 P_SPEED_STATUS, 216 S_TAIL_TAG_CTRL, 217 P_STP_CTRL, 218 S_START_CTRL, 219 S_BROADCAST_CTRL, 220 S_MULTICAST_CTRL, 221 P_XMII_CTRL_0, 222 P_XMII_CTRL_1, 223 }; 224 225 enum ksz_masks { 226 PORT_802_1P_REMAPPING, 227 SW_TAIL_TAG_ENABLE, 228 MIB_COUNTER_OVERFLOW, 229 MIB_COUNTER_VALID, 230 VLAN_TABLE_FID, 231 VLAN_TABLE_MEMBERSHIP, 232 VLAN_TABLE_VALID, 233 STATIC_MAC_TABLE_VALID, 234 STATIC_MAC_TABLE_USE_FID, 235 STATIC_MAC_TABLE_FID, 236 STATIC_MAC_TABLE_OVERRIDE, 237 STATIC_MAC_TABLE_FWD_PORTS, 238 DYNAMIC_MAC_TABLE_ENTRIES_H, 239 DYNAMIC_MAC_TABLE_MAC_EMPTY, 240 DYNAMIC_MAC_TABLE_NOT_READY, 241 DYNAMIC_MAC_TABLE_ENTRIES, 242 DYNAMIC_MAC_TABLE_FID, 243 DYNAMIC_MAC_TABLE_SRC_PORT, 244 DYNAMIC_MAC_TABLE_TIMESTAMP, 245 ALU_STAT_WRITE, 246 ALU_STAT_READ, 247 P_MII_TX_FLOW_CTRL, 248 P_MII_RX_FLOW_CTRL, 249 }; 250 251 enum ksz_shifts { 252 VLAN_TABLE_MEMBERSHIP_S, 253 VLAN_TABLE, 254 STATIC_MAC_FWD_PORTS, 255 STATIC_MAC_FID, 256 DYNAMIC_MAC_ENTRIES_H, 257 DYNAMIC_MAC_ENTRIES, 258 DYNAMIC_MAC_FID, 259 DYNAMIC_MAC_TIMESTAMP, 260 DYNAMIC_MAC_SRC_PORT, 261 ALU_STAT_INDEX, 262 }; 263 264 enum ksz_xmii_ctrl0 { 265 P_MII_100MBIT, 266 P_MII_10MBIT, 267 P_MII_FULL_DUPLEX, 268 P_MII_HALF_DUPLEX, 269 }; 270 271 enum ksz_xmii_ctrl1 { 272 P_RGMII_SEL, 273 P_RMII_SEL, 274 P_GMII_SEL, 275 P_MII_SEL, 276 P_GMII_1GBIT, 277 P_GMII_NOT_1GBIT, 278 }; 279 280 struct alu_struct { 281 /* entry 1 */ 282 u8 is_static:1; 283 u8 is_src_filter:1; 284 u8 is_dst_filter:1; 285 u8 prio_age:3; 286 u32 _reserv_0_1:23; 287 u8 mstp:3; 288 /* entry 2 */ 289 u8 is_override:1; 290 u8 is_use_fid:1; 291 u32 _reserv_1_1:23; 292 u8 port_forward:7; 293 /* entry 3 & 4*/ 294 u32 _reserv_2_1:9; 295 u8 fid:7; 296 u8 mac[ETH_ALEN]; 297 }; 298 299 struct ksz_dev_ops { 300 int (*setup)(struct dsa_switch *ds); 301 void (*teardown)(struct dsa_switch *ds); 302 u32 (*get_port_addr)(int port, int offset); 303 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 304 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 305 void (*port_cleanup)(struct ksz_device *dev, int port); 306 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 307 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); 308 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 309 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 310 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 311 u64 *cnt); 312 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 313 u64 *dropped, u64 *cnt); 314 void (*r_mib_stat64)(struct ksz_device *dev, int port); 315 int (*vlan_filtering)(struct ksz_device *dev, int port, 316 bool flag, struct netlink_ext_ack *extack); 317 int (*vlan_add)(struct ksz_device *dev, int port, 318 const struct switchdev_obj_port_vlan *vlan, 319 struct netlink_ext_ack *extack); 320 int (*vlan_del)(struct ksz_device *dev, int port, 321 const struct switchdev_obj_port_vlan *vlan); 322 int (*mirror_add)(struct ksz_device *dev, int port, 323 struct dsa_mall_mirror_tc_entry *mirror, 324 bool ingress, struct netlink_ext_ack *extack); 325 void (*mirror_del)(struct ksz_device *dev, int port, 326 struct dsa_mall_mirror_tc_entry *mirror); 327 int (*fdb_add)(struct ksz_device *dev, int port, 328 const unsigned char *addr, u16 vid, struct dsa_db db); 329 int (*fdb_del)(struct ksz_device *dev, int port, 330 const unsigned char *addr, u16 vid, struct dsa_db db); 331 int (*fdb_dump)(struct ksz_device *dev, int port, 332 dsa_fdb_dump_cb_t *cb, void *data); 333 int (*mdb_add)(struct ksz_device *dev, int port, 334 const struct switchdev_obj_port_mdb *mdb, 335 struct dsa_db db); 336 int (*mdb_del)(struct ksz_device *dev, int port, 337 const struct switchdev_obj_port_mdb *mdb, 338 struct dsa_db db); 339 void (*get_caps)(struct ksz_device *dev, int port, 340 struct phylink_config *config); 341 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 342 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 343 void (*port_init_cnt)(struct ksz_device *dev, int port); 344 void (*phylink_mac_config)(struct ksz_device *dev, int port, 345 unsigned int mode, 346 const struct phylink_link_state *state); 347 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 348 unsigned int mode, 349 phy_interface_t interface, 350 struct phy_device *phydev, int speed, 351 int duplex, bool tx_pause, bool rx_pause); 352 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 353 void (*config_cpu_port)(struct dsa_switch *ds); 354 int (*enable_stp_addr)(struct ksz_device *dev); 355 int (*reset)(struct ksz_device *dev); 356 int (*init)(struct ksz_device *dev); 357 void (*exit)(struct ksz_device *dev); 358 }; 359 360 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 361 int ksz_switch_register(struct ksz_device *dev); 362 void ksz_switch_remove(struct ksz_device *dev); 363 364 void ksz_init_mib_timer(struct ksz_device *dev); 365 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 366 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port); 367 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 368 bool ksz_get_gbit(struct ksz_device *dev, int port); 369 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 370 extern const struct ksz_chip_data ksz_switch_chips[]; 371 372 /* Common register access functions */ 373 374 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 375 { 376 unsigned int value; 377 int ret = regmap_read(dev->regmap[0], reg, &value); 378 379 if (ret) 380 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 381 ERR_PTR(ret)); 382 383 *val = value; 384 return ret; 385 } 386 387 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 388 { 389 unsigned int value; 390 int ret = regmap_read(dev->regmap[1], reg, &value); 391 392 if (ret) 393 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 394 ERR_PTR(ret)); 395 396 *val = value; 397 return ret; 398 } 399 400 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 401 { 402 unsigned int value; 403 int ret = regmap_read(dev->regmap[2], reg, &value); 404 405 if (ret) 406 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 407 ERR_PTR(ret)); 408 409 *val = value; 410 return ret; 411 } 412 413 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 414 { 415 u32 value[2]; 416 int ret; 417 418 ret = regmap_bulk_read(dev->regmap[2], reg, value, 2); 419 if (ret) 420 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 421 ERR_PTR(ret)); 422 else 423 *val = (u64)value[0] << 32 | value[1]; 424 425 return ret; 426 } 427 428 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 429 { 430 int ret; 431 432 ret = regmap_write(dev->regmap[0], reg, value); 433 if (ret) 434 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 435 ERR_PTR(ret)); 436 437 return ret; 438 } 439 440 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 441 { 442 int ret; 443 444 ret = regmap_write(dev->regmap[1], reg, value); 445 if (ret) 446 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 447 ERR_PTR(ret)); 448 449 return ret; 450 } 451 452 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 453 { 454 int ret; 455 456 ret = regmap_write(dev->regmap[2], reg, value); 457 if (ret) 458 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 459 ERR_PTR(ret)); 460 461 return ret; 462 } 463 464 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, 465 u16 value) 466 { 467 int ret; 468 469 ret = regmap_update_bits(dev->regmap[1], reg, mask, value); 470 if (ret) 471 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg, 472 ERR_PTR(ret)); 473 474 return ret; 475 } 476 477 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 478 { 479 u32 val[2]; 480 481 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 482 value = swab64(value); 483 val[0] = swab32(value & 0xffffffffULL); 484 val[1] = swab32(value >> 32ULL); 485 486 return regmap_bulk_write(dev->regmap[2], reg, val, 2); 487 } 488 489 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val) 490 { 491 return regmap_update_bits(dev->regmap[0], offset, mask, val); 492 } 493 494 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 495 u8 *data) 496 { 497 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 498 } 499 500 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 501 u16 *data) 502 { 503 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 504 } 505 506 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 507 u32 *data) 508 { 509 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 510 } 511 512 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 513 u8 data) 514 { 515 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 516 } 517 518 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 519 u16 data) 520 { 521 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 522 data); 523 } 524 525 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 526 u32 data) 527 { 528 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 529 data); 530 } 531 532 static inline void ksz_prmw8(struct ksz_device *dev, int port, int offset, 533 u8 mask, u8 val) 534 { 535 regmap_update_bits(dev->regmap[0], 536 dev->dev_ops->get_port_addr(port, offset), 537 mask, val); 538 } 539 540 static inline void ksz_regmap_lock(void *__mtx) 541 { 542 struct mutex *mtx = __mtx; 543 mutex_lock(mtx); 544 } 545 546 static inline void ksz_regmap_unlock(void *__mtx) 547 { 548 struct mutex *mtx = __mtx; 549 mutex_unlock(mtx); 550 } 551 552 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 553 { 554 return dev->chip_id == KSZ8830_CHIP_ID; 555 } 556 557 static inline int is_lan937x(struct ksz_device *dev) 558 { 559 return dev->chip_id == LAN9370_CHIP_ID || 560 dev->chip_id == LAN9371_CHIP_ID || 561 dev->chip_id == LAN9372_CHIP_ID || 562 dev->chip_id == LAN9373_CHIP_ID || 563 dev->chip_id == LAN9374_CHIP_ID; 564 } 565 566 /* STP State Defines */ 567 #define PORT_TX_ENABLE BIT(2) 568 #define PORT_RX_ENABLE BIT(1) 569 #define PORT_LEARN_DISABLE BIT(0) 570 571 /* Switch ID Defines */ 572 #define REG_CHIP_ID0 0x00 573 574 #define SW_FAMILY_ID_M GENMASK(15, 8) 575 #define KSZ87_FAMILY_ID 0x87 576 #define KSZ88_FAMILY_ID 0x88 577 578 #define KSZ8_PORT_STATUS_0 0x08 579 #define KSZ8_PORT_FIBER_MODE BIT(7) 580 581 #define SW_CHIP_ID_M GENMASK(7, 4) 582 #define KSZ87_CHIP_ID_94 0x6 583 #define KSZ87_CHIP_ID_95 0x9 584 #define KSZ88_CHIP_ID_63 0x3 585 586 #define SW_REV_ID_M GENMASK(7, 4) 587 588 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 589 #define REG_CHIP_ID4 0x0f 590 #define SKU_ID_KSZ8563 0x3c 591 #define SKU_ID_KSZ9563 0x1c 592 593 /* Driver set switch broadcast storm protection at 10% rate. */ 594 #define BROADCAST_STORM_PROT_RATE 10 595 596 /* 148,800 frames * 67 ms / 100 */ 597 #define BROADCAST_STORM_VALUE 9969 598 599 #define BROADCAST_STORM_RATE_HI 0x07 600 #define BROADCAST_STORM_RATE_LO 0xFF 601 #define BROADCAST_STORM_RATE 0x07FF 602 603 #define MULTICAST_STORM_DISABLE BIT(6) 604 605 #define SW_START 0x01 606 607 /* xMII configuration */ 608 #define P_MII_DUPLEX_M BIT(6) 609 #define P_MII_100MBIT_M BIT(4) 610 611 #define P_GMII_1GBIT_M BIT(6) 612 #define P_RGMII_ID_IG_ENABLE BIT(4) 613 #define P_RGMII_ID_EG_ENABLE BIT(3) 614 #define P_MII_MAC_MODE BIT(2) 615 #define P_MII_SEL_M 0x3 616 617 /* Interrupt */ 618 #define REG_SW_PORT_INT_STATUS__1 0x001B 619 #define REG_SW_PORT_INT_MASK__1 0x001F 620 621 #define REG_PORT_INT_STATUS 0x001B 622 #define REG_PORT_INT_MASK 0x001F 623 624 #define PORT_SRC_PHY_INT 1 625 #define PORT_SRC_PTP_INT 2 626 627 #define KSZ8795_HUGE_PACKET_SIZE 2000 628 #define KSZ8863_HUGE_PACKET_SIZE 1916 629 #define KSZ8863_NORMAL_PACKET_SIZE 1536 630 #define KSZ8_LEGAL_PACKET_SIZE 1518 631 #define KSZ9477_MAX_FRAME_SIZE 9000 632 633 /* Regmap tables generation */ 634 #define KSZ_SPI_OP_RD 3 635 #define KSZ_SPI_OP_WR 2 636 637 #define swabnot_used(x) 0 638 639 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 640 swab##swp((opcode) << ((regbits) + (regpad))) 641 642 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 643 { \ 644 .name = #width, \ 645 .val_bits = (width), \ 646 .reg_stride = 1, \ 647 .reg_bits = (regbits) + (regalign), \ 648 .pad_bits = (regpad), \ 649 .max_register = BIT(regbits) - 1, \ 650 .cache_type = REGCACHE_NONE, \ 651 .read_flag_mask = \ 652 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 653 regbits, regpad), \ 654 .write_flag_mask = \ 655 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 656 regbits, regpad), \ 657 .lock = ksz_regmap_lock, \ 658 .unlock = ksz_regmap_unlock, \ 659 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 660 .val_format_endian = REGMAP_ENDIAN_BIG \ 661 } 662 663 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 664 static const struct regmap_config ksz##_regmap_config[] = { \ 665 KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 666 KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 667 KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 668 } 669 670 #endif 671