1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 17 #define KSZ_MAX_NUM_PORTS 8 18 19 struct vlan_table { 20 u32 table[3]; 21 }; 22 23 struct ksz_port_mib { 24 struct mutex cnt_mutex; /* structure access */ 25 u8 cnt_ptr; 26 u64 *counters; 27 struct rtnl_link_stats64 stats64; 28 struct ethtool_pause_stats pause_stats; 29 struct spinlock stats64_lock; 30 }; 31 32 struct ksz_mib_names { 33 int index; 34 char string[ETH_GSTRING_LEN]; 35 }; 36 37 struct ksz_chip_data { 38 u32 chip_id; 39 const char *dev_name; 40 int num_vlans; 41 int num_alus; 42 int num_statics; 43 int cpu_ports; 44 int port_cnt; 45 const struct ksz_dev_ops *ops; 46 bool phy_errata_9477; 47 bool ksz87xx_eee_link_erratum; 48 const struct ksz_mib_names *mib_names; 49 int mib_cnt; 50 u8 reg_mib_cnt; 51 const u16 *regs; 52 const u32 *masks; 53 const u8 *shifts; 54 const u8 *xmii_ctrl0; 55 const u8 *xmii_ctrl1; 56 int stp_ctrl_reg; 57 int broadcast_ctrl_reg; 58 int multicast_ctrl_reg; 59 int start_ctrl_reg; 60 bool supports_mii[KSZ_MAX_NUM_PORTS]; 61 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 62 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 63 bool internal_phy[KSZ_MAX_NUM_PORTS]; 64 }; 65 66 struct ksz_port { 67 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 68 bool learning; 69 int stp_state; 70 struct phy_device phydev; 71 72 u32 on:1; /* port is not disabled by hardware */ 73 u32 phy:1; /* port has a PHY */ 74 u32 fiber:1; /* port is fiber */ 75 u32 sgmii:1; /* port is SGMII */ 76 u32 force:1; 77 u32 read:1; /* read MIB counters in background */ 78 u32 freeze:1; /* MIB counter freeze is enabled */ 79 80 struct ksz_port_mib mib; 81 phy_interface_t interface; 82 u16 max_frame; 83 u32 rgmii_tx_val; 84 u32 rgmii_rx_val; 85 }; 86 87 struct ksz_device { 88 struct dsa_switch *ds; 89 struct ksz_platform_data *pdata; 90 const struct ksz_chip_data *info; 91 92 struct mutex dev_mutex; /* device access */ 93 struct mutex regmap_mutex; /* regmap access */ 94 struct mutex alu_mutex; /* ALU access */ 95 struct mutex vlan_mutex; /* vlan access */ 96 const struct ksz_dev_ops *dev_ops; 97 98 struct device *dev; 99 struct regmap *regmap[3]; 100 101 void *priv; 102 103 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 104 105 /* chip specific data */ 106 u32 chip_id; 107 u8 chip_rev; 108 int cpu_port; /* port connected to CPU */ 109 int phy_port_cnt; 110 phy_interface_t compat_interface; 111 bool synclko_125; 112 bool synclko_disable; 113 114 struct vlan_table *vlan_cache; 115 116 struct ksz_port *ports; 117 struct delayed_work mib_read; 118 unsigned long mib_read_interval; 119 u16 mirror_rx; 120 u16 mirror_tx; 121 u32 features; /* chip specific features */ 122 u16 port_mask; 123 }; 124 125 /* List of supported models */ 126 enum ksz_model { 127 KSZ8563, 128 KSZ8795, 129 KSZ8794, 130 KSZ8765, 131 KSZ8830, 132 KSZ9477, 133 KSZ9897, 134 KSZ9893, 135 KSZ9567, 136 LAN9370, 137 LAN9371, 138 LAN9372, 139 LAN9373, 140 LAN9374, 141 }; 142 143 enum ksz_chip_id { 144 KSZ8563_CHIP_ID = 0x8563, 145 KSZ8795_CHIP_ID = 0x8795, 146 KSZ8794_CHIP_ID = 0x8794, 147 KSZ8765_CHIP_ID = 0x8765, 148 KSZ8830_CHIP_ID = 0x8830, 149 KSZ9477_CHIP_ID = 0x00947700, 150 KSZ9897_CHIP_ID = 0x00989700, 151 KSZ9893_CHIP_ID = 0x00989300, 152 KSZ9567_CHIP_ID = 0x00956700, 153 LAN9370_CHIP_ID = 0x00937000, 154 LAN9371_CHIP_ID = 0x00937100, 155 LAN9372_CHIP_ID = 0x00937200, 156 LAN9373_CHIP_ID = 0x00937300, 157 LAN9374_CHIP_ID = 0x00937400, 158 }; 159 160 enum ksz_regs { 161 REG_IND_CTRL_0, 162 REG_IND_DATA_8, 163 REG_IND_DATA_CHECK, 164 REG_IND_DATA_HI, 165 REG_IND_DATA_LO, 166 REG_IND_MIB_CHECK, 167 REG_IND_BYTE, 168 P_FORCE_CTRL, 169 P_LINK_STATUS, 170 P_LOCAL_CTRL, 171 P_NEG_RESTART_CTRL, 172 P_REMOTE_STATUS, 173 P_SPEED_STATUS, 174 S_TAIL_TAG_CTRL, 175 P_STP_CTRL, 176 S_START_CTRL, 177 S_BROADCAST_CTRL, 178 S_MULTICAST_CTRL, 179 P_XMII_CTRL_0, 180 P_XMII_CTRL_1, 181 }; 182 183 enum ksz_masks { 184 PORT_802_1P_REMAPPING, 185 SW_TAIL_TAG_ENABLE, 186 MIB_COUNTER_OVERFLOW, 187 MIB_COUNTER_VALID, 188 VLAN_TABLE_FID, 189 VLAN_TABLE_MEMBERSHIP, 190 VLAN_TABLE_VALID, 191 STATIC_MAC_TABLE_VALID, 192 STATIC_MAC_TABLE_USE_FID, 193 STATIC_MAC_TABLE_FID, 194 STATIC_MAC_TABLE_OVERRIDE, 195 STATIC_MAC_TABLE_FWD_PORTS, 196 DYNAMIC_MAC_TABLE_ENTRIES_H, 197 DYNAMIC_MAC_TABLE_MAC_EMPTY, 198 DYNAMIC_MAC_TABLE_NOT_READY, 199 DYNAMIC_MAC_TABLE_ENTRIES, 200 DYNAMIC_MAC_TABLE_FID, 201 DYNAMIC_MAC_TABLE_SRC_PORT, 202 DYNAMIC_MAC_TABLE_TIMESTAMP, 203 ALU_STAT_WRITE, 204 ALU_STAT_READ, 205 P_MII_TX_FLOW_CTRL, 206 P_MII_RX_FLOW_CTRL, 207 }; 208 209 enum ksz_shifts { 210 VLAN_TABLE_MEMBERSHIP_S, 211 VLAN_TABLE, 212 STATIC_MAC_FWD_PORTS, 213 STATIC_MAC_FID, 214 DYNAMIC_MAC_ENTRIES_H, 215 DYNAMIC_MAC_ENTRIES, 216 DYNAMIC_MAC_FID, 217 DYNAMIC_MAC_TIMESTAMP, 218 DYNAMIC_MAC_SRC_PORT, 219 ALU_STAT_INDEX, 220 }; 221 222 enum ksz_xmii_ctrl0 { 223 P_MII_100MBIT, 224 P_MII_10MBIT, 225 P_MII_FULL_DUPLEX, 226 P_MII_HALF_DUPLEX, 227 }; 228 229 enum ksz_xmii_ctrl1 { 230 P_RGMII_SEL, 231 P_RMII_SEL, 232 P_GMII_SEL, 233 P_MII_SEL, 234 P_GMII_1GBIT, 235 P_GMII_NOT_1GBIT, 236 }; 237 238 struct alu_struct { 239 /* entry 1 */ 240 u8 is_static:1; 241 u8 is_src_filter:1; 242 u8 is_dst_filter:1; 243 u8 prio_age:3; 244 u32 _reserv_0_1:23; 245 u8 mstp:3; 246 /* entry 2 */ 247 u8 is_override:1; 248 u8 is_use_fid:1; 249 u32 _reserv_1_1:23; 250 u8 port_forward:7; 251 /* entry 3 & 4*/ 252 u32 _reserv_2_1:9; 253 u8 fid:7; 254 u8 mac[ETH_ALEN]; 255 }; 256 257 struct ksz_dev_ops { 258 int (*setup)(struct dsa_switch *ds); 259 u32 (*get_port_addr)(int port, int offset); 260 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 261 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 262 void (*port_cleanup)(struct ksz_device *dev, int port); 263 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 264 void (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 265 void (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 266 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 267 u64 *cnt); 268 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 269 u64 *dropped, u64 *cnt); 270 void (*r_mib_stat64)(struct ksz_device *dev, int port); 271 int (*vlan_filtering)(struct ksz_device *dev, int port, 272 bool flag, struct netlink_ext_ack *extack); 273 int (*vlan_add)(struct ksz_device *dev, int port, 274 const struct switchdev_obj_port_vlan *vlan, 275 struct netlink_ext_ack *extack); 276 int (*vlan_del)(struct ksz_device *dev, int port, 277 const struct switchdev_obj_port_vlan *vlan); 278 int (*mirror_add)(struct ksz_device *dev, int port, 279 struct dsa_mall_mirror_tc_entry *mirror, 280 bool ingress, struct netlink_ext_ack *extack); 281 void (*mirror_del)(struct ksz_device *dev, int port, 282 struct dsa_mall_mirror_tc_entry *mirror); 283 int (*fdb_add)(struct ksz_device *dev, int port, 284 const unsigned char *addr, u16 vid, struct dsa_db db); 285 int (*fdb_del)(struct ksz_device *dev, int port, 286 const unsigned char *addr, u16 vid, struct dsa_db db); 287 int (*fdb_dump)(struct ksz_device *dev, int port, 288 dsa_fdb_dump_cb_t *cb, void *data); 289 int (*mdb_add)(struct ksz_device *dev, int port, 290 const struct switchdev_obj_port_mdb *mdb, 291 struct dsa_db db); 292 int (*mdb_del)(struct ksz_device *dev, int port, 293 const struct switchdev_obj_port_mdb *mdb, 294 struct dsa_db db); 295 void (*get_caps)(struct ksz_device *dev, int port, 296 struct phylink_config *config); 297 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 298 int (*max_mtu)(struct ksz_device *dev, int port); 299 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 300 void (*port_init_cnt)(struct ksz_device *dev, int port); 301 void (*phylink_mac_config)(struct ksz_device *dev, int port, 302 unsigned int mode, 303 const struct phylink_link_state *state); 304 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 305 unsigned int mode, 306 phy_interface_t interface, 307 struct phy_device *phydev, int speed, 308 int duplex, bool tx_pause, bool rx_pause); 309 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 310 void (*config_cpu_port)(struct dsa_switch *ds); 311 int (*enable_stp_addr)(struct ksz_device *dev); 312 int (*reset)(struct ksz_device *dev); 313 int (*init)(struct ksz_device *dev); 314 void (*exit)(struct ksz_device *dev); 315 }; 316 317 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 318 int ksz_switch_register(struct ksz_device *dev); 319 void ksz_switch_remove(struct ksz_device *dev); 320 321 void ksz_init_mib_timer(struct ksz_device *dev); 322 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 323 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 324 bool ksz_get_gbit(struct ksz_device *dev, int port); 325 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 326 extern const struct ksz_chip_data ksz_switch_chips[]; 327 328 /* Common register access functions */ 329 330 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 331 { 332 unsigned int value; 333 int ret = regmap_read(dev->regmap[0], reg, &value); 334 335 *val = value; 336 return ret; 337 } 338 339 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 340 { 341 unsigned int value; 342 int ret = regmap_read(dev->regmap[1], reg, &value); 343 344 *val = value; 345 return ret; 346 } 347 348 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 349 { 350 unsigned int value; 351 int ret = regmap_read(dev->regmap[2], reg, &value); 352 353 *val = value; 354 return ret; 355 } 356 357 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 358 { 359 u32 value[2]; 360 int ret; 361 362 ret = regmap_bulk_read(dev->regmap[2], reg, value, 2); 363 if (!ret) 364 *val = (u64)value[0] << 32 | value[1]; 365 366 return ret; 367 } 368 369 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 370 { 371 return regmap_write(dev->regmap[0], reg, value); 372 } 373 374 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 375 { 376 return regmap_write(dev->regmap[1], reg, value); 377 } 378 379 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 380 { 381 return regmap_write(dev->regmap[2], reg, value); 382 } 383 384 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 385 { 386 u32 val[2]; 387 388 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 389 value = swab64(value); 390 val[0] = swab32(value & 0xffffffffULL); 391 val[1] = swab32(value >> 32ULL); 392 393 return regmap_bulk_write(dev->regmap[2], reg, val, 2); 394 } 395 396 static inline void ksz_pread8(struct ksz_device *dev, int port, int offset, 397 u8 *data) 398 { 399 ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 400 } 401 402 static inline void ksz_pread16(struct ksz_device *dev, int port, int offset, 403 u16 *data) 404 { 405 ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 406 } 407 408 static inline void ksz_pread32(struct ksz_device *dev, int port, int offset, 409 u32 *data) 410 { 411 ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 412 } 413 414 static inline void ksz_pwrite8(struct ksz_device *dev, int port, int offset, 415 u8 data) 416 { 417 ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 418 } 419 420 static inline void ksz_pwrite16(struct ksz_device *dev, int port, int offset, 421 u16 data) 422 { 423 ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), data); 424 } 425 426 static inline void ksz_pwrite32(struct ksz_device *dev, int port, int offset, 427 u32 data) 428 { 429 ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), data); 430 } 431 432 static inline void ksz_prmw8(struct ksz_device *dev, int port, int offset, 433 u8 mask, u8 val) 434 { 435 regmap_update_bits(dev->regmap[0], 436 dev->dev_ops->get_port_addr(port, offset), 437 mask, val); 438 } 439 440 static inline void ksz_regmap_lock(void *__mtx) 441 { 442 struct mutex *mtx = __mtx; 443 mutex_lock(mtx); 444 } 445 446 static inline void ksz_regmap_unlock(void *__mtx) 447 { 448 struct mutex *mtx = __mtx; 449 mutex_unlock(mtx); 450 } 451 452 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 453 { 454 return dev->chip_id == KSZ8830_CHIP_ID; 455 } 456 457 static inline int is_lan937x(struct ksz_device *dev) 458 { 459 return dev->chip_id == LAN9370_CHIP_ID || 460 dev->chip_id == LAN9371_CHIP_ID || 461 dev->chip_id == LAN9372_CHIP_ID || 462 dev->chip_id == LAN9373_CHIP_ID || 463 dev->chip_id == LAN9374_CHIP_ID; 464 } 465 466 /* STP State Defines */ 467 #define PORT_TX_ENABLE BIT(2) 468 #define PORT_RX_ENABLE BIT(1) 469 #define PORT_LEARN_DISABLE BIT(0) 470 471 /* Switch ID Defines */ 472 #define REG_CHIP_ID0 0x00 473 474 #define SW_FAMILY_ID_M GENMASK(15, 8) 475 #define KSZ87_FAMILY_ID 0x87 476 #define KSZ88_FAMILY_ID 0x88 477 478 #define KSZ8_PORT_STATUS_0 0x08 479 #define KSZ8_PORT_FIBER_MODE BIT(7) 480 481 #define SW_CHIP_ID_M GENMASK(7, 4) 482 #define KSZ87_CHIP_ID_94 0x6 483 #define KSZ87_CHIP_ID_95 0x9 484 #define KSZ88_CHIP_ID_63 0x3 485 486 #define SW_REV_ID_M GENMASK(7, 4) 487 488 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 489 #define REG_CHIP_ID4 0x0f 490 #define SKU_ID_KSZ8563 0x3c 491 492 /* Driver set switch broadcast storm protection at 10% rate. */ 493 #define BROADCAST_STORM_PROT_RATE 10 494 495 /* 148,800 frames * 67 ms / 100 */ 496 #define BROADCAST_STORM_VALUE 9969 497 498 #define BROADCAST_STORM_RATE_HI 0x07 499 #define BROADCAST_STORM_RATE_LO 0xFF 500 #define BROADCAST_STORM_RATE 0x07FF 501 502 #define MULTICAST_STORM_DISABLE BIT(6) 503 504 #define SW_START 0x01 505 506 /* Used with variable features to indicate capabilities. */ 507 #define GBIT_SUPPORT BIT(0) 508 #define IS_9893 BIT(2) 509 510 /* xMII configuration */ 511 #define P_MII_DUPLEX_M BIT(6) 512 #define P_MII_100MBIT_M BIT(4) 513 514 #define P_GMII_1GBIT_M BIT(6) 515 #define P_RGMII_ID_IG_ENABLE BIT(4) 516 #define P_RGMII_ID_EG_ENABLE BIT(3) 517 #define P_MII_MAC_MODE BIT(2) 518 #define P_MII_SEL_M 0x3 519 520 /* Regmap tables generation */ 521 #define KSZ_SPI_OP_RD 3 522 #define KSZ_SPI_OP_WR 2 523 524 #define swabnot_used(x) 0 525 526 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 527 swab##swp((opcode) << ((regbits) + (regpad))) 528 529 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 530 { \ 531 .name = #width, \ 532 .val_bits = (width), \ 533 .reg_stride = 1, \ 534 .reg_bits = (regbits) + (regalign), \ 535 .pad_bits = (regpad), \ 536 .max_register = BIT(regbits) - 1, \ 537 .cache_type = REGCACHE_NONE, \ 538 .read_flag_mask = \ 539 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 540 regbits, regpad), \ 541 .write_flag_mask = \ 542 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 543 regbits, regpad), \ 544 .lock = ksz_regmap_lock, \ 545 .unlock = ksz_regmap_unlock, \ 546 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 547 .val_format_endian = REGMAP_ENDIAN_BIG \ 548 } 549 550 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 551 static const struct regmap_config ksz##_regmap_config[] = { \ 552 KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 553 KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 554 KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 555 } 556 557 #endif 558