1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 17 #define KSZ_MAX_NUM_PORTS 8 18 19 struct vlan_table { 20 u32 table[3]; 21 }; 22 23 struct ksz_port_mib { 24 struct mutex cnt_mutex; /* structure access */ 25 u8 cnt_ptr; 26 u64 *counters; 27 struct rtnl_link_stats64 stats64; 28 struct spinlock stats64_lock; 29 }; 30 31 struct ksz_mib_names { 32 int index; 33 char string[ETH_GSTRING_LEN]; 34 }; 35 36 struct ksz_chip_data { 37 u32 chip_id; 38 const char *dev_name; 39 int num_vlans; 40 int num_alus; 41 int num_statics; 42 int cpu_ports; 43 int port_cnt; 44 bool phy_errata_9477; 45 bool ksz87xx_eee_link_erratum; 46 const struct ksz_mib_names *mib_names; 47 int mib_cnt; 48 u8 reg_mib_cnt; 49 bool supports_mii[KSZ_MAX_NUM_PORTS]; 50 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 51 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 52 bool internal_phy[KSZ_MAX_NUM_PORTS]; 53 }; 54 55 struct ksz_port { 56 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 57 int stp_state; 58 struct phy_device phydev; 59 60 u32 on:1; /* port is not disabled by hardware */ 61 u32 phy:1; /* port has a PHY */ 62 u32 fiber:1; /* port is fiber */ 63 u32 sgmii:1; /* port is SGMII */ 64 u32 force:1; 65 u32 read:1; /* read MIB counters in background */ 66 u32 freeze:1; /* MIB counter freeze is enabled */ 67 68 struct ksz_port_mib mib; 69 phy_interface_t interface; 70 u16 max_frame; 71 }; 72 73 struct ksz_device { 74 struct dsa_switch *ds; 75 struct ksz_platform_data *pdata; 76 const struct ksz_chip_data *info; 77 78 struct mutex dev_mutex; /* device access */ 79 struct mutex regmap_mutex; /* regmap access */ 80 struct mutex alu_mutex; /* ALU access */ 81 struct mutex vlan_mutex; /* vlan access */ 82 const struct ksz_dev_ops *dev_ops; 83 84 struct device *dev; 85 struct regmap *regmap[3]; 86 87 void *priv; 88 89 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 90 91 /* chip specific data */ 92 u32 chip_id; 93 int cpu_port; /* port connected to CPU */ 94 int phy_port_cnt; 95 phy_interface_t compat_interface; 96 bool synclko_125; 97 bool synclko_disable; 98 99 struct vlan_table *vlan_cache; 100 101 struct ksz_port *ports; 102 struct delayed_work mib_read; 103 unsigned long mib_read_interval; 104 u16 mirror_rx; 105 u16 mirror_tx; 106 u32 features; /* chip specific features */ 107 u16 port_mask; 108 }; 109 110 /* List of supported models */ 111 enum ksz_model { 112 KSZ8795, 113 KSZ8794, 114 KSZ8765, 115 KSZ8830, 116 KSZ9477, 117 KSZ9897, 118 KSZ9893, 119 KSZ9567, 120 LAN9370, 121 LAN9371, 122 LAN9372, 123 LAN9373, 124 LAN9374, 125 }; 126 127 enum ksz_chip_id { 128 KSZ8795_CHIP_ID = 0x8795, 129 KSZ8794_CHIP_ID = 0x8794, 130 KSZ8765_CHIP_ID = 0x8765, 131 KSZ8830_CHIP_ID = 0x8830, 132 KSZ9477_CHIP_ID = 0x00947700, 133 KSZ9897_CHIP_ID = 0x00989700, 134 KSZ9893_CHIP_ID = 0x00989300, 135 KSZ9567_CHIP_ID = 0x00956700, 136 LAN9370_CHIP_ID = 0x00937000, 137 LAN9371_CHIP_ID = 0x00937100, 138 LAN9372_CHIP_ID = 0x00937200, 139 LAN9373_CHIP_ID = 0x00937300, 140 LAN9374_CHIP_ID = 0x00937400, 141 }; 142 143 struct alu_struct { 144 /* entry 1 */ 145 u8 is_static:1; 146 u8 is_src_filter:1; 147 u8 is_dst_filter:1; 148 u8 prio_age:3; 149 u32 _reserv_0_1:23; 150 u8 mstp:3; 151 /* entry 2 */ 152 u8 is_override:1; 153 u8 is_use_fid:1; 154 u32 _reserv_1_1:23; 155 u8 port_forward:7; 156 /* entry 3 & 4*/ 157 u32 _reserv_2_1:9; 158 u8 fid:7; 159 u8 mac[ETH_ALEN]; 160 }; 161 162 struct ksz_dev_ops { 163 u32 (*get_port_addr)(int port, int offset); 164 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 165 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 166 void (*port_cleanup)(struct ksz_device *dev, int port); 167 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 168 void (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 169 void (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 170 int (*r_dyn_mac_table)(struct ksz_device *dev, u16 addr, u8 *mac_addr, 171 u8 *fid, u8 *src_port, u8 *timestamp, 172 u16 *entries); 173 int (*r_sta_mac_table)(struct ksz_device *dev, u16 addr, 174 struct alu_struct *alu); 175 void (*w_sta_mac_table)(struct ksz_device *dev, u16 addr, 176 struct alu_struct *alu); 177 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 178 u64 *cnt); 179 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 180 u64 *dropped, u64 *cnt); 181 void (*r_mib_stat64)(struct ksz_device *dev, int port); 182 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 183 void (*port_init_cnt)(struct ksz_device *dev, int port); 184 int (*shutdown)(struct ksz_device *dev); 185 int (*detect)(struct ksz_device *dev); 186 int (*init)(struct ksz_device *dev); 187 void (*exit)(struct ksz_device *dev); 188 }; 189 190 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 191 int ksz_switch_register(struct ksz_device *dev, 192 const struct ksz_dev_ops *ops); 193 void ksz_switch_remove(struct ksz_device *dev); 194 195 int ksz8_switch_register(struct ksz_device *dev); 196 int ksz9477_switch_register(struct ksz_device *dev); 197 198 void ksz_update_port_member(struct ksz_device *dev, int port); 199 void ksz_init_mib_timer(struct ksz_device *dev); 200 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 201 void ksz_get_stats64(struct dsa_switch *ds, int port, 202 struct rtnl_link_stats64 *s); 203 void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 204 struct phylink_config *config); 205 extern const struct ksz_chip_data ksz_switch_chips[]; 206 207 /* Common DSA access functions */ 208 209 int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg); 210 int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val); 211 void ksz_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode, 212 phy_interface_t interface); 213 int ksz_sset_count(struct dsa_switch *ds, int port, int sset); 214 void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *buf); 215 int ksz_port_bridge_join(struct dsa_switch *ds, int port, 216 struct dsa_bridge bridge, bool *tx_fwd_offload, 217 struct netlink_ext_ack *extack); 218 void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 219 struct dsa_bridge bridge); 220 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, 221 u8 state, int reg); 222 void ksz_port_fast_age(struct dsa_switch *ds, int port); 223 int ksz_port_fdb_dump(struct dsa_switch *ds, int port, dsa_fdb_dump_cb_t *cb, 224 void *data); 225 int ksz_port_mdb_add(struct dsa_switch *ds, int port, 226 const struct switchdev_obj_port_mdb *mdb, 227 struct dsa_db db); 228 int ksz_port_mdb_del(struct dsa_switch *ds, int port, 229 const struct switchdev_obj_port_mdb *mdb, 230 struct dsa_db db); 231 int ksz_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy); 232 void ksz_get_strings(struct dsa_switch *ds, int port, 233 u32 stringset, uint8_t *buf); 234 235 /* Common register access functions */ 236 237 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 238 { 239 unsigned int value; 240 int ret = regmap_read(dev->regmap[0], reg, &value); 241 242 *val = value; 243 return ret; 244 } 245 246 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 247 { 248 unsigned int value; 249 int ret = regmap_read(dev->regmap[1], reg, &value); 250 251 *val = value; 252 return ret; 253 } 254 255 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 256 { 257 unsigned int value; 258 int ret = regmap_read(dev->regmap[2], reg, &value); 259 260 *val = value; 261 return ret; 262 } 263 264 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 265 { 266 u32 value[2]; 267 int ret; 268 269 ret = regmap_bulk_read(dev->regmap[2], reg, value, 2); 270 if (!ret) 271 *val = (u64)value[0] << 32 | value[1]; 272 273 return ret; 274 } 275 276 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 277 { 278 return regmap_write(dev->regmap[0], reg, value); 279 } 280 281 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 282 { 283 return regmap_write(dev->regmap[1], reg, value); 284 } 285 286 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 287 { 288 return regmap_write(dev->regmap[2], reg, value); 289 } 290 291 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 292 { 293 u32 val[2]; 294 295 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 296 value = swab64(value); 297 val[0] = swab32(value & 0xffffffffULL); 298 val[1] = swab32(value >> 32ULL); 299 300 return regmap_bulk_write(dev->regmap[2], reg, val, 2); 301 } 302 303 static inline void ksz_pread8(struct ksz_device *dev, int port, int offset, 304 u8 *data) 305 { 306 ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 307 } 308 309 static inline void ksz_pread16(struct ksz_device *dev, int port, int offset, 310 u16 *data) 311 { 312 ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 313 } 314 315 static inline void ksz_pread32(struct ksz_device *dev, int port, int offset, 316 u32 *data) 317 { 318 ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 319 } 320 321 static inline void ksz_pwrite8(struct ksz_device *dev, int port, int offset, 322 u8 data) 323 { 324 ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 325 } 326 327 static inline void ksz_pwrite16(struct ksz_device *dev, int port, int offset, 328 u16 data) 329 { 330 ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), data); 331 } 332 333 static inline void ksz_pwrite32(struct ksz_device *dev, int port, int offset, 334 u32 data) 335 { 336 ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), data); 337 } 338 339 static inline void ksz_regmap_lock(void *__mtx) 340 { 341 struct mutex *mtx = __mtx; 342 mutex_lock(mtx); 343 } 344 345 static inline void ksz_regmap_unlock(void *__mtx) 346 { 347 struct mutex *mtx = __mtx; 348 mutex_unlock(mtx); 349 } 350 351 /* STP State Defines */ 352 #define PORT_TX_ENABLE BIT(2) 353 #define PORT_RX_ENABLE BIT(1) 354 #define PORT_LEARN_DISABLE BIT(0) 355 356 /* Regmap tables generation */ 357 #define KSZ_SPI_OP_RD 3 358 #define KSZ_SPI_OP_WR 2 359 360 #define swabnot_used(x) 0 361 362 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 363 swab##swp((opcode) << ((regbits) + (regpad))) 364 365 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 366 { \ 367 .name = #width, \ 368 .val_bits = (width), \ 369 .reg_stride = 1, \ 370 .reg_bits = (regbits) + (regalign), \ 371 .pad_bits = (regpad), \ 372 .max_register = BIT(regbits) - 1, \ 373 .cache_type = REGCACHE_NONE, \ 374 .read_flag_mask = \ 375 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 376 regbits, regpad), \ 377 .write_flag_mask = \ 378 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 379 regbits, regpad), \ 380 .lock = ksz_regmap_lock, \ 381 .unlock = ksz_regmap_unlock, \ 382 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 383 .val_format_endian = REGMAP_ENDIAN_BIG \ 384 } 385 386 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 387 static const struct regmap_config ksz##_regmap_config[] = { \ 388 KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 389 KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 390 KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 391 } 392 393 #endif 394