1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 #include <linux/irq.h> 17 18 #define KSZ_MAX_NUM_PORTS 8 19 20 struct ksz_device; 21 22 struct vlan_table { 23 u32 table[3]; 24 }; 25 26 struct ksz_port_mib { 27 struct mutex cnt_mutex; /* structure access */ 28 u8 cnt_ptr; 29 u64 *counters; 30 struct rtnl_link_stats64 stats64; 31 struct ethtool_pause_stats pause_stats; 32 struct spinlock stats64_lock; 33 }; 34 35 struct ksz_mib_names { 36 int index; 37 char string[ETH_GSTRING_LEN]; 38 }; 39 40 struct ksz_chip_data { 41 u32 chip_id; 42 const char *dev_name; 43 int num_vlans; 44 int num_alus; 45 int num_statics; 46 int cpu_ports; 47 int port_cnt; 48 u8 port_nirqs; 49 const struct ksz_dev_ops *ops; 50 bool phy_errata_9477; 51 bool ksz87xx_eee_link_erratum; 52 const struct ksz_mib_names *mib_names; 53 int mib_cnt; 54 u8 reg_mib_cnt; 55 const u16 *regs; 56 const u32 *masks; 57 const u8 *shifts; 58 const u8 *xmii_ctrl0; 59 const u8 *xmii_ctrl1; 60 int stp_ctrl_reg; 61 int broadcast_ctrl_reg; 62 int multicast_ctrl_reg; 63 int start_ctrl_reg; 64 bool supports_mii[KSZ_MAX_NUM_PORTS]; 65 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 66 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 67 bool internal_phy[KSZ_MAX_NUM_PORTS]; 68 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 69 const struct regmap_access_table *wr_table; 70 const struct regmap_access_table *rd_table; 71 }; 72 73 struct ksz_irq { 74 u16 masked; 75 u16 reg_mask; 76 u16 reg_status; 77 struct irq_domain *domain; 78 int nirqs; 79 int irq_num; 80 char name[16]; 81 struct ksz_device *dev; 82 }; 83 84 struct ksz_port { 85 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 86 bool learning; 87 int stp_state; 88 struct phy_device phydev; 89 90 u32 on:1; /* port is not disabled by hardware */ 91 u32 fiber:1; /* port is fiber */ 92 u32 force:1; 93 u32 read:1; /* read MIB counters in background */ 94 u32 freeze:1; /* MIB counter freeze is enabled */ 95 96 struct ksz_port_mib mib; 97 phy_interface_t interface; 98 u32 rgmii_tx_val; 99 u32 rgmii_rx_val; 100 struct ksz_device *ksz_dev; 101 struct ksz_irq pirq; 102 u8 num; 103 }; 104 105 struct ksz_device { 106 struct dsa_switch *ds; 107 struct ksz_platform_data *pdata; 108 const struct ksz_chip_data *info; 109 110 struct mutex dev_mutex; /* device access */ 111 struct mutex regmap_mutex; /* regmap access */ 112 struct mutex alu_mutex; /* ALU access */ 113 struct mutex vlan_mutex; /* vlan access */ 114 const struct ksz_dev_ops *dev_ops; 115 116 struct device *dev; 117 struct regmap *regmap[3]; 118 119 void *priv; 120 int irq; 121 122 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 123 124 /* chip specific data */ 125 u32 chip_id; 126 u8 chip_rev; 127 int cpu_port; /* port connected to CPU */ 128 int phy_port_cnt; 129 phy_interface_t compat_interface; 130 bool synclko_125; 131 bool synclko_disable; 132 133 struct vlan_table *vlan_cache; 134 135 struct ksz_port *ports; 136 struct delayed_work mib_read; 137 unsigned long mib_read_interval; 138 u16 mirror_rx; 139 u16 mirror_tx; 140 u16 port_mask; 141 struct mutex lock_irq; /* IRQ Access */ 142 struct ksz_irq girq; 143 }; 144 145 /* List of supported models */ 146 enum ksz_model { 147 KSZ8563, 148 KSZ8795, 149 KSZ8794, 150 KSZ8765, 151 KSZ8830, 152 KSZ9477, 153 KSZ9896, 154 KSZ9897, 155 KSZ9893, 156 KSZ9563, 157 KSZ9567, 158 LAN9370, 159 LAN9371, 160 LAN9372, 161 LAN9373, 162 LAN9374, 163 }; 164 165 enum ksz_chip_id { 166 KSZ8563_CHIP_ID = 0x8563, 167 KSZ8795_CHIP_ID = 0x8795, 168 KSZ8794_CHIP_ID = 0x8794, 169 KSZ8765_CHIP_ID = 0x8765, 170 KSZ8830_CHIP_ID = 0x8830, 171 KSZ9477_CHIP_ID = 0x00947700, 172 KSZ9896_CHIP_ID = 0x00989600, 173 KSZ9897_CHIP_ID = 0x00989700, 174 KSZ9893_CHIP_ID = 0x00989300, 175 KSZ9563_CHIP_ID = 0x00956300, 176 KSZ9567_CHIP_ID = 0x00956700, 177 LAN9370_CHIP_ID = 0x00937000, 178 LAN9371_CHIP_ID = 0x00937100, 179 LAN9372_CHIP_ID = 0x00937200, 180 LAN9373_CHIP_ID = 0x00937300, 181 LAN9374_CHIP_ID = 0x00937400, 182 }; 183 184 enum ksz_regs { 185 REG_IND_CTRL_0, 186 REG_IND_DATA_8, 187 REG_IND_DATA_CHECK, 188 REG_IND_DATA_HI, 189 REG_IND_DATA_LO, 190 REG_IND_MIB_CHECK, 191 REG_IND_BYTE, 192 P_FORCE_CTRL, 193 P_LINK_STATUS, 194 P_LOCAL_CTRL, 195 P_NEG_RESTART_CTRL, 196 P_REMOTE_STATUS, 197 P_SPEED_STATUS, 198 S_TAIL_TAG_CTRL, 199 P_STP_CTRL, 200 S_START_CTRL, 201 S_BROADCAST_CTRL, 202 S_MULTICAST_CTRL, 203 P_XMII_CTRL_0, 204 P_XMII_CTRL_1, 205 }; 206 207 enum ksz_masks { 208 PORT_802_1P_REMAPPING, 209 SW_TAIL_TAG_ENABLE, 210 MIB_COUNTER_OVERFLOW, 211 MIB_COUNTER_VALID, 212 VLAN_TABLE_FID, 213 VLAN_TABLE_MEMBERSHIP, 214 VLAN_TABLE_VALID, 215 STATIC_MAC_TABLE_VALID, 216 STATIC_MAC_TABLE_USE_FID, 217 STATIC_MAC_TABLE_FID, 218 STATIC_MAC_TABLE_OVERRIDE, 219 STATIC_MAC_TABLE_FWD_PORTS, 220 DYNAMIC_MAC_TABLE_ENTRIES_H, 221 DYNAMIC_MAC_TABLE_MAC_EMPTY, 222 DYNAMIC_MAC_TABLE_NOT_READY, 223 DYNAMIC_MAC_TABLE_ENTRIES, 224 DYNAMIC_MAC_TABLE_FID, 225 DYNAMIC_MAC_TABLE_SRC_PORT, 226 DYNAMIC_MAC_TABLE_TIMESTAMP, 227 ALU_STAT_WRITE, 228 ALU_STAT_READ, 229 P_MII_TX_FLOW_CTRL, 230 P_MII_RX_FLOW_CTRL, 231 }; 232 233 enum ksz_shifts { 234 VLAN_TABLE_MEMBERSHIP_S, 235 VLAN_TABLE, 236 STATIC_MAC_FWD_PORTS, 237 STATIC_MAC_FID, 238 DYNAMIC_MAC_ENTRIES_H, 239 DYNAMIC_MAC_ENTRIES, 240 DYNAMIC_MAC_FID, 241 DYNAMIC_MAC_TIMESTAMP, 242 DYNAMIC_MAC_SRC_PORT, 243 ALU_STAT_INDEX, 244 }; 245 246 enum ksz_xmii_ctrl0 { 247 P_MII_100MBIT, 248 P_MII_10MBIT, 249 P_MII_FULL_DUPLEX, 250 P_MII_HALF_DUPLEX, 251 }; 252 253 enum ksz_xmii_ctrl1 { 254 P_RGMII_SEL, 255 P_RMII_SEL, 256 P_GMII_SEL, 257 P_MII_SEL, 258 P_GMII_1GBIT, 259 P_GMII_NOT_1GBIT, 260 }; 261 262 struct alu_struct { 263 /* entry 1 */ 264 u8 is_static:1; 265 u8 is_src_filter:1; 266 u8 is_dst_filter:1; 267 u8 prio_age:3; 268 u32 _reserv_0_1:23; 269 u8 mstp:3; 270 /* entry 2 */ 271 u8 is_override:1; 272 u8 is_use_fid:1; 273 u32 _reserv_1_1:23; 274 u8 port_forward:7; 275 /* entry 3 & 4*/ 276 u32 _reserv_2_1:9; 277 u8 fid:7; 278 u8 mac[ETH_ALEN]; 279 }; 280 281 struct ksz_dev_ops { 282 int (*setup)(struct dsa_switch *ds); 283 void (*teardown)(struct dsa_switch *ds); 284 u32 (*get_port_addr)(int port, int offset); 285 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 286 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 287 void (*port_cleanup)(struct ksz_device *dev, int port); 288 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 289 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); 290 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 291 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 292 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 293 u64 *cnt); 294 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 295 u64 *dropped, u64 *cnt); 296 void (*r_mib_stat64)(struct ksz_device *dev, int port); 297 int (*vlan_filtering)(struct ksz_device *dev, int port, 298 bool flag, struct netlink_ext_ack *extack); 299 int (*vlan_add)(struct ksz_device *dev, int port, 300 const struct switchdev_obj_port_vlan *vlan, 301 struct netlink_ext_ack *extack); 302 int (*vlan_del)(struct ksz_device *dev, int port, 303 const struct switchdev_obj_port_vlan *vlan); 304 int (*mirror_add)(struct ksz_device *dev, int port, 305 struct dsa_mall_mirror_tc_entry *mirror, 306 bool ingress, struct netlink_ext_ack *extack); 307 void (*mirror_del)(struct ksz_device *dev, int port, 308 struct dsa_mall_mirror_tc_entry *mirror); 309 int (*fdb_add)(struct ksz_device *dev, int port, 310 const unsigned char *addr, u16 vid, struct dsa_db db); 311 int (*fdb_del)(struct ksz_device *dev, int port, 312 const unsigned char *addr, u16 vid, struct dsa_db db); 313 int (*fdb_dump)(struct ksz_device *dev, int port, 314 dsa_fdb_dump_cb_t *cb, void *data); 315 int (*mdb_add)(struct ksz_device *dev, int port, 316 const struct switchdev_obj_port_mdb *mdb, 317 struct dsa_db db); 318 int (*mdb_del)(struct ksz_device *dev, int port, 319 const struct switchdev_obj_port_mdb *mdb, 320 struct dsa_db db); 321 void (*get_caps)(struct ksz_device *dev, int port, 322 struct phylink_config *config); 323 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 324 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 325 void (*port_init_cnt)(struct ksz_device *dev, int port); 326 void (*phylink_mac_config)(struct ksz_device *dev, int port, 327 unsigned int mode, 328 const struct phylink_link_state *state); 329 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 330 unsigned int mode, 331 phy_interface_t interface, 332 struct phy_device *phydev, int speed, 333 int duplex, bool tx_pause, bool rx_pause); 334 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 335 void (*config_cpu_port)(struct dsa_switch *ds); 336 int (*enable_stp_addr)(struct ksz_device *dev); 337 int (*reset)(struct ksz_device *dev); 338 int (*init)(struct ksz_device *dev); 339 void (*exit)(struct ksz_device *dev); 340 }; 341 342 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 343 int ksz_switch_register(struct ksz_device *dev); 344 void ksz_switch_remove(struct ksz_device *dev); 345 346 void ksz_init_mib_timer(struct ksz_device *dev); 347 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 348 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port); 349 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 350 bool ksz_get_gbit(struct ksz_device *dev, int port); 351 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 352 extern const struct ksz_chip_data ksz_switch_chips[]; 353 354 /* Common register access functions */ 355 356 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 357 { 358 unsigned int value; 359 int ret = regmap_read(dev->regmap[0], reg, &value); 360 361 if (ret) 362 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 363 ERR_PTR(ret)); 364 365 *val = value; 366 return ret; 367 } 368 369 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 370 { 371 unsigned int value; 372 int ret = regmap_read(dev->regmap[1], reg, &value); 373 374 if (ret) 375 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 376 ERR_PTR(ret)); 377 378 *val = value; 379 return ret; 380 } 381 382 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 383 { 384 unsigned int value; 385 int ret = regmap_read(dev->regmap[2], reg, &value); 386 387 if (ret) 388 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 389 ERR_PTR(ret)); 390 391 *val = value; 392 return ret; 393 } 394 395 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 396 { 397 u32 value[2]; 398 int ret; 399 400 ret = regmap_bulk_read(dev->regmap[2], reg, value, 2); 401 if (ret) 402 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 403 ERR_PTR(ret)); 404 else 405 *val = (u64)value[0] << 32 | value[1]; 406 407 return ret; 408 } 409 410 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 411 { 412 int ret; 413 414 ret = regmap_write(dev->regmap[0], reg, value); 415 if (ret) 416 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 417 ERR_PTR(ret)); 418 419 return ret; 420 } 421 422 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 423 { 424 int ret; 425 426 ret = regmap_write(dev->regmap[1], reg, value); 427 if (ret) 428 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 429 ERR_PTR(ret)); 430 431 return ret; 432 } 433 434 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 435 { 436 int ret; 437 438 ret = regmap_write(dev->regmap[2], reg, value); 439 if (ret) 440 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 441 ERR_PTR(ret)); 442 443 return ret; 444 } 445 446 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 447 { 448 u32 val[2]; 449 450 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 451 value = swab64(value); 452 val[0] = swab32(value & 0xffffffffULL); 453 val[1] = swab32(value >> 32ULL); 454 455 return regmap_bulk_write(dev->regmap[2], reg, val, 2); 456 } 457 458 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val) 459 { 460 return regmap_update_bits(dev->regmap[0], offset, mask, val); 461 } 462 463 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 464 u8 *data) 465 { 466 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 467 } 468 469 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 470 u16 *data) 471 { 472 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 473 } 474 475 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 476 u32 *data) 477 { 478 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 479 } 480 481 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 482 u8 data) 483 { 484 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 485 } 486 487 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 488 u16 data) 489 { 490 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 491 data); 492 } 493 494 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 495 u32 data) 496 { 497 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 498 data); 499 } 500 501 static inline void ksz_prmw8(struct ksz_device *dev, int port, int offset, 502 u8 mask, u8 val) 503 { 504 regmap_update_bits(dev->regmap[0], 505 dev->dev_ops->get_port_addr(port, offset), 506 mask, val); 507 } 508 509 static inline void ksz_regmap_lock(void *__mtx) 510 { 511 struct mutex *mtx = __mtx; 512 mutex_lock(mtx); 513 } 514 515 static inline void ksz_regmap_unlock(void *__mtx) 516 { 517 struct mutex *mtx = __mtx; 518 mutex_unlock(mtx); 519 } 520 521 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 522 { 523 return dev->chip_id == KSZ8830_CHIP_ID; 524 } 525 526 static inline int is_lan937x(struct ksz_device *dev) 527 { 528 return dev->chip_id == LAN9370_CHIP_ID || 529 dev->chip_id == LAN9371_CHIP_ID || 530 dev->chip_id == LAN9372_CHIP_ID || 531 dev->chip_id == LAN9373_CHIP_ID || 532 dev->chip_id == LAN9374_CHIP_ID; 533 } 534 535 /* STP State Defines */ 536 #define PORT_TX_ENABLE BIT(2) 537 #define PORT_RX_ENABLE BIT(1) 538 #define PORT_LEARN_DISABLE BIT(0) 539 540 /* Switch ID Defines */ 541 #define REG_CHIP_ID0 0x00 542 543 #define SW_FAMILY_ID_M GENMASK(15, 8) 544 #define KSZ87_FAMILY_ID 0x87 545 #define KSZ88_FAMILY_ID 0x88 546 547 #define KSZ8_PORT_STATUS_0 0x08 548 #define KSZ8_PORT_FIBER_MODE BIT(7) 549 550 #define SW_CHIP_ID_M GENMASK(7, 4) 551 #define KSZ87_CHIP_ID_94 0x6 552 #define KSZ87_CHIP_ID_95 0x9 553 #define KSZ88_CHIP_ID_63 0x3 554 555 #define SW_REV_ID_M GENMASK(7, 4) 556 557 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 558 #define REG_CHIP_ID4 0x0f 559 #define SKU_ID_KSZ8563 0x3c 560 #define SKU_ID_KSZ9563 0x1c 561 562 /* Driver set switch broadcast storm protection at 10% rate. */ 563 #define BROADCAST_STORM_PROT_RATE 10 564 565 /* 148,800 frames * 67 ms / 100 */ 566 #define BROADCAST_STORM_VALUE 9969 567 568 #define BROADCAST_STORM_RATE_HI 0x07 569 #define BROADCAST_STORM_RATE_LO 0xFF 570 #define BROADCAST_STORM_RATE 0x07FF 571 572 #define MULTICAST_STORM_DISABLE BIT(6) 573 574 #define SW_START 0x01 575 576 /* xMII configuration */ 577 #define P_MII_DUPLEX_M BIT(6) 578 #define P_MII_100MBIT_M BIT(4) 579 580 #define P_GMII_1GBIT_M BIT(6) 581 #define P_RGMII_ID_IG_ENABLE BIT(4) 582 #define P_RGMII_ID_EG_ENABLE BIT(3) 583 #define P_MII_MAC_MODE BIT(2) 584 #define P_MII_SEL_M 0x3 585 586 /* Interrupt */ 587 #define REG_SW_PORT_INT_STATUS__1 0x001B 588 #define REG_SW_PORT_INT_MASK__1 0x001F 589 590 #define REG_PORT_INT_STATUS 0x001B 591 #define REG_PORT_INT_MASK 0x001F 592 593 #define PORT_SRC_PHY_INT 1 594 595 #define KSZ8795_HUGE_PACKET_SIZE 2000 596 #define KSZ8863_HUGE_PACKET_SIZE 1916 597 #define KSZ8863_NORMAL_PACKET_SIZE 1536 598 #define KSZ8_LEGAL_PACKET_SIZE 1518 599 #define KSZ9477_MAX_FRAME_SIZE 9000 600 601 /* Regmap tables generation */ 602 #define KSZ_SPI_OP_RD 3 603 #define KSZ_SPI_OP_WR 2 604 605 #define swabnot_used(x) 0 606 607 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 608 swab##swp((opcode) << ((regbits) + (regpad))) 609 610 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 611 { \ 612 .name = #width, \ 613 .val_bits = (width), \ 614 .reg_stride = 1, \ 615 .reg_bits = (regbits) + (regalign), \ 616 .pad_bits = (regpad), \ 617 .max_register = BIT(regbits) - 1, \ 618 .cache_type = REGCACHE_NONE, \ 619 .read_flag_mask = \ 620 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 621 regbits, regpad), \ 622 .write_flag_mask = \ 623 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 624 regbits, regpad), \ 625 .lock = ksz_regmap_lock, \ 626 .unlock = ksz_regmap_unlock, \ 627 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 628 .val_format_endian = REGMAP_ENDIAN_BIG \ 629 } 630 631 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 632 static const struct regmap_config ksz##_regmap_config[] = { \ 633 KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 634 KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 635 KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 636 } 637 638 #endif 639