1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 #include <linux/irq.h> 17 18 #define KSZ_MAX_NUM_PORTS 8 19 20 struct ksz_device; 21 22 struct vlan_table { 23 u32 table[3]; 24 }; 25 26 struct ksz_port_mib { 27 struct mutex cnt_mutex; /* structure access */ 28 u8 cnt_ptr; 29 u64 *counters; 30 struct rtnl_link_stats64 stats64; 31 struct ethtool_pause_stats pause_stats; 32 struct spinlock stats64_lock; 33 }; 34 35 struct ksz_mib_names { 36 int index; 37 char string[ETH_GSTRING_LEN]; 38 }; 39 40 struct ksz_chip_data { 41 u32 chip_id; 42 const char *dev_name; 43 int num_vlans; 44 int num_alus; 45 int num_statics; 46 int cpu_ports; 47 int port_cnt; 48 u8 port_nirqs; 49 const struct ksz_dev_ops *ops; 50 bool phy_errata_9477; 51 bool ksz87xx_eee_link_erratum; 52 const struct ksz_mib_names *mib_names; 53 int mib_cnt; 54 u8 reg_mib_cnt; 55 const u16 *regs; 56 const u32 *masks; 57 const u8 *shifts; 58 const u8 *xmii_ctrl0; 59 const u8 *xmii_ctrl1; 60 int stp_ctrl_reg; 61 int broadcast_ctrl_reg; 62 int multicast_ctrl_reg; 63 int start_ctrl_reg; 64 bool supports_mii[KSZ_MAX_NUM_PORTS]; 65 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 66 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 67 bool internal_phy[KSZ_MAX_NUM_PORTS]; 68 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 69 const struct regmap_access_table *wr_table; 70 const struct regmap_access_table *rd_table; 71 }; 72 73 struct ksz_irq { 74 u16 masked; 75 u16 reg_mask; 76 u16 reg_status; 77 struct irq_domain *domain; 78 int nirqs; 79 int irq_num; 80 char name[16]; 81 struct ksz_device *dev; 82 }; 83 84 struct ksz_port { 85 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 86 bool learning; 87 int stp_state; 88 struct phy_device phydev; 89 90 u32 on:1; /* port is not disabled by hardware */ 91 u32 fiber:1; /* port is fiber */ 92 u32 force:1; 93 u32 read:1; /* read MIB counters in background */ 94 u32 freeze:1; /* MIB counter freeze is enabled */ 95 96 struct ksz_port_mib mib; 97 phy_interface_t interface; 98 u16 max_frame; 99 u32 rgmii_tx_val; 100 u32 rgmii_rx_val; 101 struct ksz_device *ksz_dev; 102 struct ksz_irq pirq; 103 u8 num; 104 }; 105 106 struct ksz_device { 107 struct dsa_switch *ds; 108 struct ksz_platform_data *pdata; 109 const struct ksz_chip_data *info; 110 111 struct mutex dev_mutex; /* device access */ 112 struct mutex regmap_mutex; /* regmap access */ 113 struct mutex alu_mutex; /* ALU access */ 114 struct mutex vlan_mutex; /* vlan access */ 115 const struct ksz_dev_ops *dev_ops; 116 117 struct device *dev; 118 struct regmap *regmap[3]; 119 120 void *priv; 121 int irq; 122 123 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 124 125 /* chip specific data */ 126 u32 chip_id; 127 u8 chip_rev; 128 int cpu_port; /* port connected to CPU */ 129 int phy_port_cnt; 130 phy_interface_t compat_interface; 131 bool synclko_125; 132 bool synclko_disable; 133 134 struct vlan_table *vlan_cache; 135 136 struct ksz_port *ports; 137 struct delayed_work mib_read; 138 unsigned long mib_read_interval; 139 u16 mirror_rx; 140 u16 mirror_tx; 141 u16 port_mask; 142 struct mutex lock_irq; /* IRQ Access */ 143 struct ksz_irq girq; 144 }; 145 146 /* List of supported models */ 147 enum ksz_model { 148 KSZ8563, 149 KSZ8795, 150 KSZ8794, 151 KSZ8765, 152 KSZ8830, 153 KSZ9477, 154 KSZ9896, 155 KSZ9897, 156 KSZ9893, 157 KSZ9563, 158 KSZ9567, 159 LAN9370, 160 LAN9371, 161 LAN9372, 162 LAN9373, 163 LAN9374, 164 }; 165 166 enum ksz_chip_id { 167 KSZ8563_CHIP_ID = 0x8563, 168 KSZ8795_CHIP_ID = 0x8795, 169 KSZ8794_CHIP_ID = 0x8794, 170 KSZ8765_CHIP_ID = 0x8765, 171 KSZ8830_CHIP_ID = 0x8830, 172 KSZ9477_CHIP_ID = 0x00947700, 173 KSZ9896_CHIP_ID = 0x00989600, 174 KSZ9897_CHIP_ID = 0x00989700, 175 KSZ9893_CHIP_ID = 0x00989300, 176 KSZ9563_CHIP_ID = 0x00956300, 177 KSZ9567_CHIP_ID = 0x00956700, 178 LAN9370_CHIP_ID = 0x00937000, 179 LAN9371_CHIP_ID = 0x00937100, 180 LAN9372_CHIP_ID = 0x00937200, 181 LAN9373_CHIP_ID = 0x00937300, 182 LAN9374_CHIP_ID = 0x00937400, 183 }; 184 185 enum ksz_regs { 186 REG_IND_CTRL_0, 187 REG_IND_DATA_8, 188 REG_IND_DATA_CHECK, 189 REG_IND_DATA_HI, 190 REG_IND_DATA_LO, 191 REG_IND_MIB_CHECK, 192 REG_IND_BYTE, 193 P_FORCE_CTRL, 194 P_LINK_STATUS, 195 P_LOCAL_CTRL, 196 P_NEG_RESTART_CTRL, 197 P_REMOTE_STATUS, 198 P_SPEED_STATUS, 199 S_TAIL_TAG_CTRL, 200 P_STP_CTRL, 201 S_START_CTRL, 202 S_BROADCAST_CTRL, 203 S_MULTICAST_CTRL, 204 P_XMII_CTRL_0, 205 P_XMII_CTRL_1, 206 }; 207 208 enum ksz_masks { 209 PORT_802_1P_REMAPPING, 210 SW_TAIL_TAG_ENABLE, 211 MIB_COUNTER_OVERFLOW, 212 MIB_COUNTER_VALID, 213 VLAN_TABLE_FID, 214 VLAN_TABLE_MEMBERSHIP, 215 VLAN_TABLE_VALID, 216 STATIC_MAC_TABLE_VALID, 217 STATIC_MAC_TABLE_USE_FID, 218 STATIC_MAC_TABLE_FID, 219 STATIC_MAC_TABLE_OVERRIDE, 220 STATIC_MAC_TABLE_FWD_PORTS, 221 DYNAMIC_MAC_TABLE_ENTRIES_H, 222 DYNAMIC_MAC_TABLE_MAC_EMPTY, 223 DYNAMIC_MAC_TABLE_NOT_READY, 224 DYNAMIC_MAC_TABLE_ENTRIES, 225 DYNAMIC_MAC_TABLE_FID, 226 DYNAMIC_MAC_TABLE_SRC_PORT, 227 DYNAMIC_MAC_TABLE_TIMESTAMP, 228 ALU_STAT_WRITE, 229 ALU_STAT_READ, 230 P_MII_TX_FLOW_CTRL, 231 P_MII_RX_FLOW_CTRL, 232 }; 233 234 enum ksz_shifts { 235 VLAN_TABLE_MEMBERSHIP_S, 236 VLAN_TABLE, 237 STATIC_MAC_FWD_PORTS, 238 STATIC_MAC_FID, 239 DYNAMIC_MAC_ENTRIES_H, 240 DYNAMIC_MAC_ENTRIES, 241 DYNAMIC_MAC_FID, 242 DYNAMIC_MAC_TIMESTAMP, 243 DYNAMIC_MAC_SRC_PORT, 244 ALU_STAT_INDEX, 245 }; 246 247 enum ksz_xmii_ctrl0 { 248 P_MII_100MBIT, 249 P_MII_10MBIT, 250 P_MII_FULL_DUPLEX, 251 P_MII_HALF_DUPLEX, 252 }; 253 254 enum ksz_xmii_ctrl1 { 255 P_RGMII_SEL, 256 P_RMII_SEL, 257 P_GMII_SEL, 258 P_MII_SEL, 259 P_GMII_1GBIT, 260 P_GMII_NOT_1GBIT, 261 }; 262 263 struct alu_struct { 264 /* entry 1 */ 265 u8 is_static:1; 266 u8 is_src_filter:1; 267 u8 is_dst_filter:1; 268 u8 prio_age:3; 269 u32 _reserv_0_1:23; 270 u8 mstp:3; 271 /* entry 2 */ 272 u8 is_override:1; 273 u8 is_use_fid:1; 274 u32 _reserv_1_1:23; 275 u8 port_forward:7; 276 /* entry 3 & 4*/ 277 u32 _reserv_2_1:9; 278 u8 fid:7; 279 u8 mac[ETH_ALEN]; 280 }; 281 282 struct ksz_dev_ops { 283 int (*setup)(struct dsa_switch *ds); 284 void (*teardown)(struct dsa_switch *ds); 285 u32 (*get_port_addr)(int port, int offset); 286 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 287 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 288 void (*port_cleanup)(struct ksz_device *dev, int port); 289 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 290 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); 291 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 292 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 293 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 294 u64 *cnt); 295 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 296 u64 *dropped, u64 *cnt); 297 void (*r_mib_stat64)(struct ksz_device *dev, int port); 298 int (*vlan_filtering)(struct ksz_device *dev, int port, 299 bool flag, struct netlink_ext_ack *extack); 300 int (*vlan_add)(struct ksz_device *dev, int port, 301 const struct switchdev_obj_port_vlan *vlan, 302 struct netlink_ext_ack *extack); 303 int (*vlan_del)(struct ksz_device *dev, int port, 304 const struct switchdev_obj_port_vlan *vlan); 305 int (*mirror_add)(struct ksz_device *dev, int port, 306 struct dsa_mall_mirror_tc_entry *mirror, 307 bool ingress, struct netlink_ext_ack *extack); 308 void (*mirror_del)(struct ksz_device *dev, int port, 309 struct dsa_mall_mirror_tc_entry *mirror); 310 int (*fdb_add)(struct ksz_device *dev, int port, 311 const unsigned char *addr, u16 vid, struct dsa_db db); 312 int (*fdb_del)(struct ksz_device *dev, int port, 313 const unsigned char *addr, u16 vid, struct dsa_db db); 314 int (*fdb_dump)(struct ksz_device *dev, int port, 315 dsa_fdb_dump_cb_t *cb, void *data); 316 int (*mdb_add)(struct ksz_device *dev, int port, 317 const struct switchdev_obj_port_mdb *mdb, 318 struct dsa_db db); 319 int (*mdb_del)(struct ksz_device *dev, int port, 320 const struct switchdev_obj_port_mdb *mdb, 321 struct dsa_db db); 322 void (*get_caps)(struct ksz_device *dev, int port, 323 struct phylink_config *config); 324 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 325 int (*max_mtu)(struct ksz_device *dev, int port); 326 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 327 void (*port_init_cnt)(struct ksz_device *dev, int port); 328 void (*phylink_mac_config)(struct ksz_device *dev, int port, 329 unsigned int mode, 330 const struct phylink_link_state *state); 331 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 332 unsigned int mode, 333 phy_interface_t interface, 334 struct phy_device *phydev, int speed, 335 int duplex, bool tx_pause, bool rx_pause); 336 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 337 void (*config_cpu_port)(struct dsa_switch *ds); 338 int (*enable_stp_addr)(struct ksz_device *dev); 339 int (*reset)(struct ksz_device *dev); 340 int (*init)(struct ksz_device *dev); 341 void (*exit)(struct ksz_device *dev); 342 }; 343 344 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 345 int ksz_switch_register(struct ksz_device *dev); 346 void ksz_switch_remove(struct ksz_device *dev); 347 348 void ksz_init_mib_timer(struct ksz_device *dev); 349 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 350 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 351 bool ksz_get_gbit(struct ksz_device *dev, int port); 352 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 353 extern const struct ksz_chip_data ksz_switch_chips[]; 354 355 /* Common register access functions */ 356 357 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 358 { 359 unsigned int value; 360 int ret = regmap_read(dev->regmap[0], reg, &value); 361 362 if (ret) 363 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 364 ERR_PTR(ret)); 365 366 *val = value; 367 return ret; 368 } 369 370 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 371 { 372 unsigned int value; 373 int ret = regmap_read(dev->regmap[1], reg, &value); 374 375 if (ret) 376 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 377 ERR_PTR(ret)); 378 379 *val = value; 380 return ret; 381 } 382 383 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 384 { 385 unsigned int value; 386 int ret = regmap_read(dev->regmap[2], reg, &value); 387 388 if (ret) 389 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 390 ERR_PTR(ret)); 391 392 *val = value; 393 return ret; 394 } 395 396 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 397 { 398 u32 value[2]; 399 int ret; 400 401 ret = regmap_bulk_read(dev->regmap[2], reg, value, 2); 402 if (ret) 403 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 404 ERR_PTR(ret)); 405 else 406 *val = (u64)value[0] << 32 | value[1]; 407 408 return ret; 409 } 410 411 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 412 { 413 int ret; 414 415 ret = regmap_write(dev->regmap[0], reg, value); 416 if (ret) 417 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 418 ERR_PTR(ret)); 419 420 return ret; 421 } 422 423 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 424 { 425 int ret; 426 427 ret = regmap_write(dev->regmap[1], reg, value); 428 if (ret) 429 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 430 ERR_PTR(ret)); 431 432 return ret; 433 } 434 435 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 436 { 437 int ret; 438 439 ret = regmap_write(dev->regmap[2], reg, value); 440 if (ret) 441 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 442 ERR_PTR(ret)); 443 444 return ret; 445 } 446 447 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 448 { 449 u32 val[2]; 450 451 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 452 value = swab64(value); 453 val[0] = swab32(value & 0xffffffffULL); 454 val[1] = swab32(value >> 32ULL); 455 456 return regmap_bulk_write(dev->regmap[2], reg, val, 2); 457 } 458 459 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 460 u8 *data) 461 { 462 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 463 } 464 465 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 466 u16 *data) 467 { 468 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 469 } 470 471 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 472 u32 *data) 473 { 474 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 475 } 476 477 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 478 u8 data) 479 { 480 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 481 } 482 483 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 484 u16 data) 485 { 486 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 487 data); 488 } 489 490 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 491 u32 data) 492 { 493 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 494 data); 495 } 496 497 static inline void ksz_prmw8(struct ksz_device *dev, int port, int offset, 498 u8 mask, u8 val) 499 { 500 regmap_update_bits(dev->regmap[0], 501 dev->dev_ops->get_port_addr(port, offset), 502 mask, val); 503 } 504 505 static inline void ksz_regmap_lock(void *__mtx) 506 { 507 struct mutex *mtx = __mtx; 508 mutex_lock(mtx); 509 } 510 511 static inline void ksz_regmap_unlock(void *__mtx) 512 { 513 struct mutex *mtx = __mtx; 514 mutex_unlock(mtx); 515 } 516 517 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 518 { 519 return dev->chip_id == KSZ8830_CHIP_ID; 520 } 521 522 static inline int is_lan937x(struct ksz_device *dev) 523 { 524 return dev->chip_id == LAN9370_CHIP_ID || 525 dev->chip_id == LAN9371_CHIP_ID || 526 dev->chip_id == LAN9372_CHIP_ID || 527 dev->chip_id == LAN9373_CHIP_ID || 528 dev->chip_id == LAN9374_CHIP_ID; 529 } 530 531 /* STP State Defines */ 532 #define PORT_TX_ENABLE BIT(2) 533 #define PORT_RX_ENABLE BIT(1) 534 #define PORT_LEARN_DISABLE BIT(0) 535 536 /* Switch ID Defines */ 537 #define REG_CHIP_ID0 0x00 538 539 #define SW_FAMILY_ID_M GENMASK(15, 8) 540 #define KSZ87_FAMILY_ID 0x87 541 #define KSZ88_FAMILY_ID 0x88 542 543 #define KSZ8_PORT_STATUS_0 0x08 544 #define KSZ8_PORT_FIBER_MODE BIT(7) 545 546 #define SW_CHIP_ID_M GENMASK(7, 4) 547 #define KSZ87_CHIP_ID_94 0x6 548 #define KSZ87_CHIP_ID_95 0x9 549 #define KSZ88_CHIP_ID_63 0x3 550 551 #define SW_REV_ID_M GENMASK(7, 4) 552 553 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 554 #define REG_CHIP_ID4 0x0f 555 #define SKU_ID_KSZ8563 0x3c 556 #define SKU_ID_KSZ9563 0x1c 557 558 /* Driver set switch broadcast storm protection at 10% rate. */ 559 #define BROADCAST_STORM_PROT_RATE 10 560 561 /* 148,800 frames * 67 ms / 100 */ 562 #define BROADCAST_STORM_VALUE 9969 563 564 #define BROADCAST_STORM_RATE_HI 0x07 565 #define BROADCAST_STORM_RATE_LO 0xFF 566 #define BROADCAST_STORM_RATE 0x07FF 567 568 #define MULTICAST_STORM_DISABLE BIT(6) 569 570 #define SW_START 0x01 571 572 /* xMII configuration */ 573 #define P_MII_DUPLEX_M BIT(6) 574 #define P_MII_100MBIT_M BIT(4) 575 576 #define P_GMII_1GBIT_M BIT(6) 577 #define P_RGMII_ID_IG_ENABLE BIT(4) 578 #define P_RGMII_ID_EG_ENABLE BIT(3) 579 #define P_MII_MAC_MODE BIT(2) 580 #define P_MII_SEL_M 0x3 581 582 /* Interrupt */ 583 #define REG_SW_PORT_INT_STATUS__1 0x001B 584 #define REG_SW_PORT_INT_MASK__1 0x001F 585 586 #define REG_PORT_INT_STATUS 0x001B 587 #define REG_PORT_INT_MASK 0x001F 588 589 #define PORT_SRC_PHY_INT 1 590 591 /* Regmap tables generation */ 592 #define KSZ_SPI_OP_RD 3 593 #define KSZ_SPI_OP_WR 2 594 595 #define swabnot_used(x) 0 596 597 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 598 swab##swp((opcode) << ((regbits) + (regpad))) 599 600 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 601 { \ 602 .name = #width, \ 603 .val_bits = (width), \ 604 .reg_stride = 1, \ 605 .reg_bits = (regbits) + (regalign), \ 606 .pad_bits = (regpad), \ 607 .max_register = BIT(regbits) - 1, \ 608 .cache_type = REGCACHE_NONE, \ 609 .read_flag_mask = \ 610 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 611 regbits, regpad), \ 612 .write_flag_mask = \ 613 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 614 regbits, regpad), \ 615 .lock = ksz_regmap_lock, \ 616 .unlock = ksz_regmap_unlock, \ 617 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 618 .val_format_endian = REGMAP_ENDIAN_BIG \ 619 } 620 621 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 622 static const struct regmap_config ksz##_regmap_config[] = { \ 623 KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 624 KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 625 KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 626 } 627 628 #endif 629