1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 17 #define KSZ_MAX_NUM_PORTS 8 18 19 struct vlan_table { 20 u32 table[3]; 21 }; 22 23 struct ksz_port_mib { 24 struct mutex cnt_mutex; /* structure access */ 25 u8 cnt_ptr; 26 u64 *counters; 27 struct rtnl_link_stats64 stats64; 28 struct ethtool_pause_stats pause_stats; 29 struct spinlock stats64_lock; 30 }; 31 32 struct ksz_mib_names { 33 int index; 34 char string[ETH_GSTRING_LEN]; 35 }; 36 37 struct ksz_chip_data { 38 u32 chip_id; 39 const char *dev_name; 40 int num_vlans; 41 int num_alus; 42 int num_statics; 43 int cpu_ports; 44 int port_cnt; 45 const struct ksz_dev_ops *ops; 46 bool phy_errata_9477; 47 bool ksz87xx_eee_link_erratum; 48 const struct ksz_mib_names *mib_names; 49 int mib_cnt; 50 u8 reg_mib_cnt; 51 const u16 *regs; 52 const u32 *masks; 53 const u8 *shifts; 54 const u8 *xmii_ctrl0; 55 const u8 *xmii_ctrl1; 56 int stp_ctrl_reg; 57 int broadcast_ctrl_reg; 58 int multicast_ctrl_reg; 59 int start_ctrl_reg; 60 bool supports_mii[KSZ_MAX_NUM_PORTS]; 61 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 62 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 63 bool internal_phy[KSZ_MAX_NUM_PORTS]; 64 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 65 }; 66 67 struct ksz_port { 68 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 69 bool learning; 70 int stp_state; 71 struct phy_device phydev; 72 73 u32 on:1; /* port is not disabled by hardware */ 74 u32 phy:1; /* port has a PHY */ 75 u32 fiber:1; /* port is fiber */ 76 u32 sgmii:1; /* port is SGMII */ 77 u32 force:1; 78 u32 read:1; /* read MIB counters in background */ 79 u32 freeze:1; /* MIB counter freeze is enabled */ 80 81 struct ksz_port_mib mib; 82 phy_interface_t interface; 83 u16 max_frame; 84 u32 rgmii_tx_val; 85 u32 rgmii_rx_val; 86 }; 87 88 struct ksz_device { 89 struct dsa_switch *ds; 90 struct ksz_platform_data *pdata; 91 const struct ksz_chip_data *info; 92 93 struct mutex dev_mutex; /* device access */ 94 struct mutex regmap_mutex; /* regmap access */ 95 struct mutex alu_mutex; /* ALU access */ 96 struct mutex vlan_mutex; /* vlan access */ 97 const struct ksz_dev_ops *dev_ops; 98 99 struct device *dev; 100 struct regmap *regmap[3]; 101 102 void *priv; 103 104 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 105 106 /* chip specific data */ 107 u32 chip_id; 108 u8 chip_rev; 109 int cpu_port; /* port connected to CPU */ 110 int phy_port_cnt; 111 phy_interface_t compat_interface; 112 bool synclko_125; 113 bool synclko_disable; 114 115 struct vlan_table *vlan_cache; 116 117 struct ksz_port *ports; 118 struct delayed_work mib_read; 119 unsigned long mib_read_interval; 120 u16 mirror_rx; 121 u16 mirror_tx; 122 u32 features; /* chip specific features */ 123 u16 port_mask; 124 }; 125 126 /* List of supported models */ 127 enum ksz_model { 128 KSZ8563, 129 KSZ8795, 130 KSZ8794, 131 KSZ8765, 132 KSZ8830, 133 KSZ9477, 134 KSZ9897, 135 KSZ9893, 136 KSZ9567, 137 LAN9370, 138 LAN9371, 139 LAN9372, 140 LAN9373, 141 LAN9374, 142 }; 143 144 enum ksz_chip_id { 145 KSZ8563_CHIP_ID = 0x8563, 146 KSZ8795_CHIP_ID = 0x8795, 147 KSZ8794_CHIP_ID = 0x8794, 148 KSZ8765_CHIP_ID = 0x8765, 149 KSZ8830_CHIP_ID = 0x8830, 150 KSZ9477_CHIP_ID = 0x00947700, 151 KSZ9897_CHIP_ID = 0x00989700, 152 KSZ9893_CHIP_ID = 0x00989300, 153 KSZ9567_CHIP_ID = 0x00956700, 154 LAN9370_CHIP_ID = 0x00937000, 155 LAN9371_CHIP_ID = 0x00937100, 156 LAN9372_CHIP_ID = 0x00937200, 157 LAN9373_CHIP_ID = 0x00937300, 158 LAN9374_CHIP_ID = 0x00937400, 159 }; 160 161 enum ksz_regs { 162 REG_IND_CTRL_0, 163 REG_IND_DATA_8, 164 REG_IND_DATA_CHECK, 165 REG_IND_DATA_HI, 166 REG_IND_DATA_LO, 167 REG_IND_MIB_CHECK, 168 REG_IND_BYTE, 169 P_FORCE_CTRL, 170 P_LINK_STATUS, 171 P_LOCAL_CTRL, 172 P_NEG_RESTART_CTRL, 173 P_REMOTE_STATUS, 174 P_SPEED_STATUS, 175 S_TAIL_TAG_CTRL, 176 P_STP_CTRL, 177 S_START_CTRL, 178 S_BROADCAST_CTRL, 179 S_MULTICAST_CTRL, 180 P_XMII_CTRL_0, 181 P_XMII_CTRL_1, 182 }; 183 184 enum ksz_masks { 185 PORT_802_1P_REMAPPING, 186 SW_TAIL_TAG_ENABLE, 187 MIB_COUNTER_OVERFLOW, 188 MIB_COUNTER_VALID, 189 VLAN_TABLE_FID, 190 VLAN_TABLE_MEMBERSHIP, 191 VLAN_TABLE_VALID, 192 STATIC_MAC_TABLE_VALID, 193 STATIC_MAC_TABLE_USE_FID, 194 STATIC_MAC_TABLE_FID, 195 STATIC_MAC_TABLE_OVERRIDE, 196 STATIC_MAC_TABLE_FWD_PORTS, 197 DYNAMIC_MAC_TABLE_ENTRIES_H, 198 DYNAMIC_MAC_TABLE_MAC_EMPTY, 199 DYNAMIC_MAC_TABLE_NOT_READY, 200 DYNAMIC_MAC_TABLE_ENTRIES, 201 DYNAMIC_MAC_TABLE_FID, 202 DYNAMIC_MAC_TABLE_SRC_PORT, 203 DYNAMIC_MAC_TABLE_TIMESTAMP, 204 ALU_STAT_WRITE, 205 ALU_STAT_READ, 206 P_MII_TX_FLOW_CTRL, 207 P_MII_RX_FLOW_CTRL, 208 }; 209 210 enum ksz_shifts { 211 VLAN_TABLE_MEMBERSHIP_S, 212 VLAN_TABLE, 213 STATIC_MAC_FWD_PORTS, 214 STATIC_MAC_FID, 215 DYNAMIC_MAC_ENTRIES_H, 216 DYNAMIC_MAC_ENTRIES, 217 DYNAMIC_MAC_FID, 218 DYNAMIC_MAC_TIMESTAMP, 219 DYNAMIC_MAC_SRC_PORT, 220 ALU_STAT_INDEX, 221 }; 222 223 enum ksz_xmii_ctrl0 { 224 P_MII_100MBIT, 225 P_MII_10MBIT, 226 P_MII_FULL_DUPLEX, 227 P_MII_HALF_DUPLEX, 228 }; 229 230 enum ksz_xmii_ctrl1 { 231 P_RGMII_SEL, 232 P_RMII_SEL, 233 P_GMII_SEL, 234 P_MII_SEL, 235 P_GMII_1GBIT, 236 P_GMII_NOT_1GBIT, 237 }; 238 239 struct alu_struct { 240 /* entry 1 */ 241 u8 is_static:1; 242 u8 is_src_filter:1; 243 u8 is_dst_filter:1; 244 u8 prio_age:3; 245 u32 _reserv_0_1:23; 246 u8 mstp:3; 247 /* entry 2 */ 248 u8 is_override:1; 249 u8 is_use_fid:1; 250 u32 _reserv_1_1:23; 251 u8 port_forward:7; 252 /* entry 3 & 4*/ 253 u32 _reserv_2_1:9; 254 u8 fid:7; 255 u8 mac[ETH_ALEN]; 256 }; 257 258 struct ksz_dev_ops { 259 int (*setup)(struct dsa_switch *ds); 260 u32 (*get_port_addr)(int port, int offset); 261 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 262 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 263 void (*port_cleanup)(struct ksz_device *dev, int port); 264 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 265 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 266 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 267 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 268 u64 *cnt); 269 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 270 u64 *dropped, u64 *cnt); 271 void (*r_mib_stat64)(struct ksz_device *dev, int port); 272 int (*vlan_filtering)(struct ksz_device *dev, int port, 273 bool flag, struct netlink_ext_ack *extack); 274 int (*vlan_add)(struct ksz_device *dev, int port, 275 const struct switchdev_obj_port_vlan *vlan, 276 struct netlink_ext_ack *extack); 277 int (*vlan_del)(struct ksz_device *dev, int port, 278 const struct switchdev_obj_port_vlan *vlan); 279 int (*mirror_add)(struct ksz_device *dev, int port, 280 struct dsa_mall_mirror_tc_entry *mirror, 281 bool ingress, struct netlink_ext_ack *extack); 282 void (*mirror_del)(struct ksz_device *dev, int port, 283 struct dsa_mall_mirror_tc_entry *mirror); 284 int (*fdb_add)(struct ksz_device *dev, int port, 285 const unsigned char *addr, u16 vid, struct dsa_db db); 286 int (*fdb_del)(struct ksz_device *dev, int port, 287 const unsigned char *addr, u16 vid, struct dsa_db db); 288 int (*fdb_dump)(struct ksz_device *dev, int port, 289 dsa_fdb_dump_cb_t *cb, void *data); 290 int (*mdb_add)(struct ksz_device *dev, int port, 291 const struct switchdev_obj_port_mdb *mdb, 292 struct dsa_db db); 293 int (*mdb_del)(struct ksz_device *dev, int port, 294 const struct switchdev_obj_port_mdb *mdb, 295 struct dsa_db db); 296 void (*get_caps)(struct ksz_device *dev, int port, 297 struct phylink_config *config); 298 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 299 int (*max_mtu)(struct ksz_device *dev, int port); 300 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 301 void (*port_init_cnt)(struct ksz_device *dev, int port); 302 void (*phylink_mac_config)(struct ksz_device *dev, int port, 303 unsigned int mode, 304 const struct phylink_link_state *state); 305 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 306 unsigned int mode, 307 phy_interface_t interface, 308 struct phy_device *phydev, int speed, 309 int duplex, bool tx_pause, bool rx_pause); 310 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 311 void (*config_cpu_port)(struct dsa_switch *ds); 312 int (*enable_stp_addr)(struct ksz_device *dev); 313 int (*reset)(struct ksz_device *dev); 314 int (*init)(struct ksz_device *dev); 315 void (*exit)(struct ksz_device *dev); 316 }; 317 318 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 319 int ksz_switch_register(struct ksz_device *dev); 320 void ksz_switch_remove(struct ksz_device *dev); 321 322 void ksz_init_mib_timer(struct ksz_device *dev); 323 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 324 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 325 bool ksz_get_gbit(struct ksz_device *dev, int port); 326 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 327 extern const struct ksz_chip_data ksz_switch_chips[]; 328 329 /* Common register access functions */ 330 331 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 332 { 333 unsigned int value; 334 int ret = regmap_read(dev->regmap[0], reg, &value); 335 336 *val = value; 337 return ret; 338 } 339 340 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 341 { 342 unsigned int value; 343 int ret = regmap_read(dev->regmap[1], reg, &value); 344 345 *val = value; 346 return ret; 347 } 348 349 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 350 { 351 unsigned int value; 352 int ret = regmap_read(dev->regmap[2], reg, &value); 353 354 *val = value; 355 return ret; 356 } 357 358 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 359 { 360 u32 value[2]; 361 int ret; 362 363 ret = regmap_bulk_read(dev->regmap[2], reg, value, 2); 364 if (!ret) 365 *val = (u64)value[0] << 32 | value[1]; 366 367 return ret; 368 } 369 370 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 371 { 372 return regmap_write(dev->regmap[0], reg, value); 373 } 374 375 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 376 { 377 return regmap_write(dev->regmap[1], reg, value); 378 } 379 380 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 381 { 382 return regmap_write(dev->regmap[2], reg, value); 383 } 384 385 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 386 { 387 u32 val[2]; 388 389 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 390 value = swab64(value); 391 val[0] = swab32(value & 0xffffffffULL); 392 val[1] = swab32(value >> 32ULL); 393 394 return regmap_bulk_write(dev->regmap[2], reg, val, 2); 395 } 396 397 static inline void ksz_pread8(struct ksz_device *dev, int port, int offset, 398 u8 *data) 399 { 400 ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 401 } 402 403 static inline void ksz_pread16(struct ksz_device *dev, int port, int offset, 404 u16 *data) 405 { 406 ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 407 } 408 409 static inline void ksz_pread32(struct ksz_device *dev, int port, int offset, 410 u32 *data) 411 { 412 ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 413 } 414 415 static inline void ksz_pwrite8(struct ksz_device *dev, int port, int offset, 416 u8 data) 417 { 418 ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 419 } 420 421 static inline void ksz_pwrite16(struct ksz_device *dev, int port, int offset, 422 u16 data) 423 { 424 ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), data); 425 } 426 427 static inline void ksz_pwrite32(struct ksz_device *dev, int port, int offset, 428 u32 data) 429 { 430 ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), data); 431 } 432 433 static inline void ksz_prmw8(struct ksz_device *dev, int port, int offset, 434 u8 mask, u8 val) 435 { 436 regmap_update_bits(dev->regmap[0], 437 dev->dev_ops->get_port_addr(port, offset), 438 mask, val); 439 } 440 441 static inline void ksz_regmap_lock(void *__mtx) 442 { 443 struct mutex *mtx = __mtx; 444 mutex_lock(mtx); 445 } 446 447 static inline void ksz_regmap_unlock(void *__mtx) 448 { 449 struct mutex *mtx = __mtx; 450 mutex_unlock(mtx); 451 } 452 453 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 454 { 455 return dev->chip_id == KSZ8830_CHIP_ID; 456 } 457 458 static inline int is_lan937x(struct ksz_device *dev) 459 { 460 return dev->chip_id == LAN9370_CHIP_ID || 461 dev->chip_id == LAN9371_CHIP_ID || 462 dev->chip_id == LAN9372_CHIP_ID || 463 dev->chip_id == LAN9373_CHIP_ID || 464 dev->chip_id == LAN9374_CHIP_ID; 465 } 466 467 /* STP State Defines */ 468 #define PORT_TX_ENABLE BIT(2) 469 #define PORT_RX_ENABLE BIT(1) 470 #define PORT_LEARN_DISABLE BIT(0) 471 472 /* Switch ID Defines */ 473 #define REG_CHIP_ID0 0x00 474 475 #define SW_FAMILY_ID_M GENMASK(15, 8) 476 #define KSZ87_FAMILY_ID 0x87 477 #define KSZ88_FAMILY_ID 0x88 478 479 #define KSZ8_PORT_STATUS_0 0x08 480 #define KSZ8_PORT_FIBER_MODE BIT(7) 481 482 #define SW_CHIP_ID_M GENMASK(7, 4) 483 #define KSZ87_CHIP_ID_94 0x6 484 #define KSZ87_CHIP_ID_95 0x9 485 #define KSZ88_CHIP_ID_63 0x3 486 487 #define SW_REV_ID_M GENMASK(7, 4) 488 489 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 490 #define REG_CHIP_ID4 0x0f 491 #define SKU_ID_KSZ8563 0x3c 492 493 /* Driver set switch broadcast storm protection at 10% rate. */ 494 #define BROADCAST_STORM_PROT_RATE 10 495 496 /* 148,800 frames * 67 ms / 100 */ 497 #define BROADCAST_STORM_VALUE 9969 498 499 #define BROADCAST_STORM_RATE_HI 0x07 500 #define BROADCAST_STORM_RATE_LO 0xFF 501 #define BROADCAST_STORM_RATE 0x07FF 502 503 #define MULTICAST_STORM_DISABLE BIT(6) 504 505 #define SW_START 0x01 506 507 /* Used with variable features to indicate capabilities. */ 508 #define IS_9893 BIT(2) 509 510 /* xMII configuration */ 511 #define P_MII_DUPLEX_M BIT(6) 512 #define P_MII_100MBIT_M BIT(4) 513 514 #define P_GMII_1GBIT_M BIT(6) 515 #define P_RGMII_ID_IG_ENABLE BIT(4) 516 #define P_RGMII_ID_EG_ENABLE BIT(3) 517 #define P_MII_MAC_MODE BIT(2) 518 #define P_MII_SEL_M 0x3 519 520 /* Regmap tables generation */ 521 #define KSZ_SPI_OP_RD 3 522 #define KSZ_SPI_OP_WR 2 523 524 #define swabnot_used(x) 0 525 526 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 527 swab##swp((opcode) << ((regbits) + (regpad))) 528 529 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 530 { \ 531 .name = #width, \ 532 .val_bits = (width), \ 533 .reg_stride = 1, \ 534 .reg_bits = (regbits) + (regalign), \ 535 .pad_bits = (regpad), \ 536 .max_register = BIT(regbits) - 1, \ 537 .cache_type = REGCACHE_NONE, \ 538 .read_flag_mask = \ 539 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 540 regbits, regpad), \ 541 .write_flag_mask = \ 542 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 543 regbits, regpad), \ 544 .lock = ksz_regmap_lock, \ 545 .unlock = ksz_regmap_unlock, \ 546 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 547 .val_format_endian = REGMAP_ENDIAN_BIG \ 548 } 549 550 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 551 static const struct regmap_config ksz##_regmap_config[] = { \ 552 KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 553 KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 554 KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 555 } 556 557 #endif 558