1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 17 #define KSZ_MAX_NUM_PORTS 8 18 19 struct vlan_table { 20 u32 table[3]; 21 }; 22 23 struct ksz_port_mib { 24 struct mutex cnt_mutex; /* structure access */ 25 u8 cnt_ptr; 26 u64 *counters; 27 struct rtnl_link_stats64 stats64; 28 struct ethtool_pause_stats pause_stats; 29 struct spinlock stats64_lock; 30 }; 31 32 struct ksz_mib_names { 33 int index; 34 char string[ETH_GSTRING_LEN]; 35 }; 36 37 struct ksz_chip_data { 38 u32 chip_id; 39 const char *dev_name; 40 int num_vlans; 41 int num_alus; 42 int num_statics; 43 int cpu_ports; 44 int port_cnt; 45 const struct ksz_dev_ops *ops; 46 bool phy_errata_9477; 47 bool ksz87xx_eee_link_erratum; 48 const struct ksz_mib_names *mib_names; 49 int mib_cnt; 50 u8 reg_mib_cnt; 51 const u16 *regs; 52 const u32 *masks; 53 const u8 *shifts; 54 const u8 *xmii_ctrl0; 55 const u8 *xmii_ctrl1; 56 int stp_ctrl_reg; 57 int broadcast_ctrl_reg; 58 int multicast_ctrl_reg; 59 int start_ctrl_reg; 60 bool supports_mii[KSZ_MAX_NUM_PORTS]; 61 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 62 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 63 bool internal_phy[KSZ_MAX_NUM_PORTS]; 64 }; 65 66 struct ksz_port { 67 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 68 bool learning; 69 int stp_state; 70 struct phy_device phydev; 71 72 u32 on:1; /* port is not disabled by hardware */ 73 u32 phy:1; /* port has a PHY */ 74 u32 fiber:1; /* port is fiber */ 75 u32 sgmii:1; /* port is SGMII */ 76 u32 force:1; 77 u32 read:1; /* read MIB counters in background */ 78 u32 freeze:1; /* MIB counter freeze is enabled */ 79 80 struct ksz_port_mib mib; 81 phy_interface_t interface; 82 u16 max_frame; 83 u32 rgmii_tx_val; 84 u32 rgmii_rx_val; 85 }; 86 87 struct ksz_device { 88 struct dsa_switch *ds; 89 struct ksz_platform_data *pdata; 90 const struct ksz_chip_data *info; 91 92 struct mutex dev_mutex; /* device access */ 93 struct mutex regmap_mutex; /* regmap access */ 94 struct mutex alu_mutex; /* ALU access */ 95 struct mutex vlan_mutex; /* vlan access */ 96 const struct ksz_dev_ops *dev_ops; 97 98 struct device *dev; 99 struct regmap *regmap[3]; 100 101 void *priv; 102 103 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 104 105 /* chip specific data */ 106 u32 chip_id; 107 u8 chip_rev; 108 int cpu_port; /* port connected to CPU */ 109 int phy_port_cnt; 110 phy_interface_t compat_interface; 111 bool synclko_125; 112 bool synclko_disable; 113 114 struct vlan_table *vlan_cache; 115 116 struct ksz_port *ports; 117 struct delayed_work mib_read; 118 unsigned long mib_read_interval; 119 u16 mirror_rx; 120 u16 mirror_tx; 121 u32 features; /* chip specific features */ 122 u16 port_mask; 123 }; 124 125 /* List of supported models */ 126 enum ksz_model { 127 KSZ8795, 128 KSZ8794, 129 KSZ8765, 130 KSZ8830, 131 KSZ9477, 132 KSZ9897, 133 KSZ9893, 134 KSZ9567, 135 LAN9370, 136 LAN9371, 137 LAN9372, 138 LAN9373, 139 LAN9374, 140 }; 141 142 enum ksz_chip_id { 143 KSZ8795_CHIP_ID = 0x8795, 144 KSZ8794_CHIP_ID = 0x8794, 145 KSZ8765_CHIP_ID = 0x8765, 146 KSZ8830_CHIP_ID = 0x8830, 147 KSZ9477_CHIP_ID = 0x00947700, 148 KSZ9897_CHIP_ID = 0x00989700, 149 KSZ9893_CHIP_ID = 0x00989300, 150 KSZ9567_CHIP_ID = 0x00956700, 151 LAN9370_CHIP_ID = 0x00937000, 152 LAN9371_CHIP_ID = 0x00937100, 153 LAN9372_CHIP_ID = 0x00937200, 154 LAN9373_CHIP_ID = 0x00937300, 155 LAN9374_CHIP_ID = 0x00937400, 156 }; 157 158 enum ksz_regs { 159 REG_IND_CTRL_0, 160 REG_IND_DATA_8, 161 REG_IND_DATA_CHECK, 162 REG_IND_DATA_HI, 163 REG_IND_DATA_LO, 164 REG_IND_MIB_CHECK, 165 REG_IND_BYTE, 166 P_FORCE_CTRL, 167 P_LINK_STATUS, 168 P_LOCAL_CTRL, 169 P_NEG_RESTART_CTRL, 170 P_REMOTE_STATUS, 171 P_SPEED_STATUS, 172 S_TAIL_TAG_CTRL, 173 P_STP_CTRL, 174 S_START_CTRL, 175 S_BROADCAST_CTRL, 176 S_MULTICAST_CTRL, 177 P_XMII_CTRL_0, 178 P_XMII_CTRL_1, 179 }; 180 181 enum ksz_masks { 182 PORT_802_1P_REMAPPING, 183 SW_TAIL_TAG_ENABLE, 184 MIB_COUNTER_OVERFLOW, 185 MIB_COUNTER_VALID, 186 VLAN_TABLE_FID, 187 VLAN_TABLE_MEMBERSHIP, 188 VLAN_TABLE_VALID, 189 STATIC_MAC_TABLE_VALID, 190 STATIC_MAC_TABLE_USE_FID, 191 STATIC_MAC_TABLE_FID, 192 STATIC_MAC_TABLE_OVERRIDE, 193 STATIC_MAC_TABLE_FWD_PORTS, 194 DYNAMIC_MAC_TABLE_ENTRIES_H, 195 DYNAMIC_MAC_TABLE_MAC_EMPTY, 196 DYNAMIC_MAC_TABLE_NOT_READY, 197 DYNAMIC_MAC_TABLE_ENTRIES, 198 DYNAMIC_MAC_TABLE_FID, 199 DYNAMIC_MAC_TABLE_SRC_PORT, 200 DYNAMIC_MAC_TABLE_TIMESTAMP, 201 ALU_STAT_WRITE, 202 ALU_STAT_READ, 203 P_MII_TX_FLOW_CTRL, 204 P_MII_RX_FLOW_CTRL, 205 }; 206 207 enum ksz_shifts { 208 VLAN_TABLE_MEMBERSHIP_S, 209 VLAN_TABLE, 210 STATIC_MAC_FWD_PORTS, 211 STATIC_MAC_FID, 212 DYNAMIC_MAC_ENTRIES_H, 213 DYNAMIC_MAC_ENTRIES, 214 DYNAMIC_MAC_FID, 215 DYNAMIC_MAC_TIMESTAMP, 216 DYNAMIC_MAC_SRC_PORT, 217 ALU_STAT_INDEX, 218 }; 219 220 enum ksz_xmii_ctrl0 { 221 P_MII_100MBIT, 222 P_MII_10MBIT, 223 P_MII_FULL_DUPLEX, 224 P_MII_HALF_DUPLEX, 225 }; 226 227 enum ksz_xmii_ctrl1 { 228 P_RGMII_SEL, 229 P_RMII_SEL, 230 P_GMII_SEL, 231 P_MII_SEL, 232 P_GMII_1GBIT, 233 P_GMII_NOT_1GBIT, 234 }; 235 236 struct alu_struct { 237 /* entry 1 */ 238 u8 is_static:1; 239 u8 is_src_filter:1; 240 u8 is_dst_filter:1; 241 u8 prio_age:3; 242 u32 _reserv_0_1:23; 243 u8 mstp:3; 244 /* entry 2 */ 245 u8 is_override:1; 246 u8 is_use_fid:1; 247 u32 _reserv_1_1:23; 248 u8 port_forward:7; 249 /* entry 3 & 4*/ 250 u32 _reserv_2_1:9; 251 u8 fid:7; 252 u8 mac[ETH_ALEN]; 253 }; 254 255 struct ksz_dev_ops { 256 int (*setup)(struct dsa_switch *ds); 257 u32 (*get_port_addr)(int port, int offset); 258 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 259 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 260 void (*port_cleanup)(struct ksz_device *dev, int port); 261 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 262 void (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 263 void (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 264 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 265 u64 *cnt); 266 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 267 u64 *dropped, u64 *cnt); 268 void (*r_mib_stat64)(struct ksz_device *dev, int port); 269 int (*vlan_filtering)(struct ksz_device *dev, int port, 270 bool flag, struct netlink_ext_ack *extack); 271 int (*vlan_add)(struct ksz_device *dev, int port, 272 const struct switchdev_obj_port_vlan *vlan, 273 struct netlink_ext_ack *extack); 274 int (*vlan_del)(struct ksz_device *dev, int port, 275 const struct switchdev_obj_port_vlan *vlan); 276 int (*mirror_add)(struct ksz_device *dev, int port, 277 struct dsa_mall_mirror_tc_entry *mirror, 278 bool ingress, struct netlink_ext_ack *extack); 279 void (*mirror_del)(struct ksz_device *dev, int port, 280 struct dsa_mall_mirror_tc_entry *mirror); 281 int (*fdb_add)(struct ksz_device *dev, int port, 282 const unsigned char *addr, u16 vid, struct dsa_db db); 283 int (*fdb_del)(struct ksz_device *dev, int port, 284 const unsigned char *addr, u16 vid, struct dsa_db db); 285 int (*fdb_dump)(struct ksz_device *dev, int port, 286 dsa_fdb_dump_cb_t *cb, void *data); 287 int (*mdb_add)(struct ksz_device *dev, int port, 288 const struct switchdev_obj_port_mdb *mdb, 289 struct dsa_db db); 290 int (*mdb_del)(struct ksz_device *dev, int port, 291 const struct switchdev_obj_port_mdb *mdb, 292 struct dsa_db db); 293 void (*get_caps)(struct ksz_device *dev, int port, 294 struct phylink_config *config); 295 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 296 int (*max_mtu)(struct ksz_device *dev, int port); 297 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 298 void (*port_init_cnt)(struct ksz_device *dev, int port); 299 void (*phylink_mac_config)(struct ksz_device *dev, int port, 300 unsigned int mode, 301 const struct phylink_link_state *state); 302 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 303 unsigned int mode, 304 phy_interface_t interface, 305 struct phy_device *phydev, int speed, 306 int duplex, bool tx_pause, bool rx_pause); 307 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 308 void (*config_cpu_port)(struct dsa_switch *ds); 309 int (*enable_stp_addr)(struct ksz_device *dev); 310 int (*reset)(struct ksz_device *dev); 311 int (*init)(struct ksz_device *dev); 312 void (*exit)(struct ksz_device *dev); 313 }; 314 315 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 316 int ksz_switch_register(struct ksz_device *dev); 317 void ksz_switch_remove(struct ksz_device *dev); 318 319 void ksz_init_mib_timer(struct ksz_device *dev); 320 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 321 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 322 bool ksz_get_gbit(struct ksz_device *dev, int port); 323 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 324 extern const struct ksz_chip_data ksz_switch_chips[]; 325 326 /* Common register access functions */ 327 328 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 329 { 330 unsigned int value; 331 int ret = regmap_read(dev->regmap[0], reg, &value); 332 333 *val = value; 334 return ret; 335 } 336 337 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 338 { 339 unsigned int value; 340 int ret = regmap_read(dev->regmap[1], reg, &value); 341 342 *val = value; 343 return ret; 344 } 345 346 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 347 { 348 unsigned int value; 349 int ret = regmap_read(dev->regmap[2], reg, &value); 350 351 *val = value; 352 return ret; 353 } 354 355 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 356 { 357 u32 value[2]; 358 int ret; 359 360 ret = regmap_bulk_read(dev->regmap[2], reg, value, 2); 361 if (!ret) 362 *val = (u64)value[0] << 32 | value[1]; 363 364 return ret; 365 } 366 367 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 368 { 369 return regmap_write(dev->regmap[0], reg, value); 370 } 371 372 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 373 { 374 return regmap_write(dev->regmap[1], reg, value); 375 } 376 377 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 378 { 379 return regmap_write(dev->regmap[2], reg, value); 380 } 381 382 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 383 { 384 u32 val[2]; 385 386 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 387 value = swab64(value); 388 val[0] = swab32(value & 0xffffffffULL); 389 val[1] = swab32(value >> 32ULL); 390 391 return regmap_bulk_write(dev->regmap[2], reg, val, 2); 392 } 393 394 static inline void ksz_pread8(struct ksz_device *dev, int port, int offset, 395 u8 *data) 396 { 397 ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 398 } 399 400 static inline void ksz_pread16(struct ksz_device *dev, int port, int offset, 401 u16 *data) 402 { 403 ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 404 } 405 406 static inline void ksz_pread32(struct ksz_device *dev, int port, int offset, 407 u32 *data) 408 { 409 ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 410 } 411 412 static inline void ksz_pwrite8(struct ksz_device *dev, int port, int offset, 413 u8 data) 414 { 415 ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 416 } 417 418 static inline void ksz_pwrite16(struct ksz_device *dev, int port, int offset, 419 u16 data) 420 { 421 ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), data); 422 } 423 424 static inline void ksz_pwrite32(struct ksz_device *dev, int port, int offset, 425 u32 data) 426 { 427 ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), data); 428 } 429 430 static inline void ksz_prmw8(struct ksz_device *dev, int port, int offset, 431 u8 mask, u8 val) 432 { 433 regmap_update_bits(dev->regmap[0], 434 dev->dev_ops->get_port_addr(port, offset), 435 mask, val); 436 } 437 438 static inline void ksz_regmap_lock(void *__mtx) 439 { 440 struct mutex *mtx = __mtx; 441 mutex_lock(mtx); 442 } 443 444 static inline void ksz_regmap_unlock(void *__mtx) 445 { 446 struct mutex *mtx = __mtx; 447 mutex_unlock(mtx); 448 } 449 450 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 451 { 452 return dev->chip_id == KSZ8830_CHIP_ID; 453 } 454 455 static inline int is_lan937x(struct ksz_device *dev) 456 { 457 return dev->chip_id == LAN9370_CHIP_ID || 458 dev->chip_id == LAN9371_CHIP_ID || 459 dev->chip_id == LAN9372_CHIP_ID || 460 dev->chip_id == LAN9373_CHIP_ID || 461 dev->chip_id == LAN9374_CHIP_ID; 462 } 463 464 /* STP State Defines */ 465 #define PORT_TX_ENABLE BIT(2) 466 #define PORT_RX_ENABLE BIT(1) 467 #define PORT_LEARN_DISABLE BIT(0) 468 469 /* Switch ID Defines */ 470 #define REG_CHIP_ID0 0x00 471 472 #define SW_FAMILY_ID_M GENMASK(15, 8) 473 #define KSZ87_FAMILY_ID 0x87 474 #define KSZ88_FAMILY_ID 0x88 475 476 #define KSZ8_PORT_STATUS_0 0x08 477 #define KSZ8_PORT_FIBER_MODE BIT(7) 478 479 #define SW_CHIP_ID_M GENMASK(7, 4) 480 #define KSZ87_CHIP_ID_94 0x6 481 #define KSZ87_CHIP_ID_95 0x9 482 #define KSZ88_CHIP_ID_63 0x3 483 484 #define SW_REV_ID_M GENMASK(7, 4) 485 486 /* Driver set switch broadcast storm protection at 10% rate. */ 487 #define BROADCAST_STORM_PROT_RATE 10 488 489 /* 148,800 frames * 67 ms / 100 */ 490 #define BROADCAST_STORM_VALUE 9969 491 492 #define BROADCAST_STORM_RATE_HI 0x07 493 #define BROADCAST_STORM_RATE_LO 0xFF 494 #define BROADCAST_STORM_RATE 0x07FF 495 496 #define MULTICAST_STORM_DISABLE BIT(6) 497 498 #define SW_START 0x01 499 500 /* Used with variable features to indicate capabilities. */ 501 #define GBIT_SUPPORT BIT(0) 502 #define IS_9893 BIT(2) 503 504 /* xMII configuration */ 505 #define P_MII_DUPLEX_M BIT(6) 506 #define P_MII_100MBIT_M BIT(4) 507 508 #define P_GMII_1GBIT_M BIT(6) 509 #define P_RGMII_ID_IG_ENABLE BIT(4) 510 #define P_RGMII_ID_EG_ENABLE BIT(3) 511 #define P_MII_MAC_MODE BIT(2) 512 #define P_MII_SEL_M 0x3 513 514 /* Regmap tables generation */ 515 #define KSZ_SPI_OP_RD 3 516 #define KSZ_SPI_OP_WR 2 517 518 #define swabnot_used(x) 0 519 520 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 521 swab##swp((opcode) << ((regbits) + (regpad))) 522 523 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 524 { \ 525 .name = #width, \ 526 .val_bits = (width), \ 527 .reg_stride = 1, \ 528 .reg_bits = (regbits) + (regalign), \ 529 .pad_bits = (regpad), \ 530 .max_register = BIT(regbits) - 1, \ 531 .cache_type = REGCACHE_NONE, \ 532 .read_flag_mask = \ 533 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 534 regbits, regpad), \ 535 .write_flag_mask = \ 536 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 537 regbits, regpad), \ 538 .lock = ksz_regmap_lock, \ 539 .unlock = ksz_regmap_unlock, \ 540 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 541 .val_format_endian = REGMAP_ENDIAN_BIG \ 542 } 543 544 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 545 static const struct regmap_config ksz##_regmap_config[] = { \ 546 KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 547 KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 548 KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 549 } 550 551 #endif 552