1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 17 struct vlan_table { 18 u32 table[3]; 19 }; 20 21 struct ksz_port_mib { 22 struct mutex cnt_mutex; /* structure access */ 23 u8 cnt_ptr; 24 u64 *counters; 25 struct rtnl_link_stats64 stats64; 26 struct spinlock stats64_lock; 27 }; 28 29 struct ksz_chip_data { 30 u32 chip_id; 31 const char *dev_name; 32 int num_vlans; 33 int num_alus; 34 int num_statics; 35 int cpu_ports; 36 int port_cnt; 37 bool phy_errata_9477; 38 bool ksz87xx_eee_link_erratum; 39 }; 40 41 struct ksz_port { 42 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 43 int stp_state; 44 struct phy_device phydev; 45 46 u32 on:1; /* port is not disabled by hardware */ 47 u32 phy:1; /* port has a PHY */ 48 u32 fiber:1; /* port is fiber */ 49 u32 sgmii:1; /* port is SGMII */ 50 u32 force:1; 51 u32 read:1; /* read MIB counters in background */ 52 u32 freeze:1; /* MIB counter freeze is enabled */ 53 54 struct ksz_port_mib mib; 55 phy_interface_t interface; 56 u16 max_frame; 57 }; 58 59 struct ksz_device { 60 struct dsa_switch *ds; 61 struct ksz_platform_data *pdata; 62 const char *name; 63 const struct ksz_chip_data *info; 64 65 struct mutex dev_mutex; /* device access */ 66 struct mutex regmap_mutex; /* regmap access */ 67 struct mutex alu_mutex; /* ALU access */ 68 struct mutex vlan_mutex; /* vlan access */ 69 const struct ksz_dev_ops *dev_ops; 70 71 struct device *dev; 72 struct regmap *regmap[3]; 73 74 void *priv; 75 76 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 77 78 /* chip specific data */ 79 u32 chip_id; 80 int cpu_port; /* port connected to CPU */ 81 int phy_port_cnt; 82 u8 reg_mib_cnt; 83 int mib_cnt; 84 const struct mib_names *mib_names; 85 phy_interface_t compat_interface; 86 u32 regs_size; 87 bool synclko_125; 88 bool synclko_disable; 89 90 struct vlan_table *vlan_cache; 91 92 struct ksz_port *ports; 93 struct delayed_work mib_read; 94 unsigned long mib_read_interval; 95 u16 mirror_rx; 96 u16 mirror_tx; 97 u32 features; /* chip specific features */ 98 u32 overrides; /* chip functions set by user */ 99 u16 host_mask; 100 u16 port_mask; 101 }; 102 103 /* List of supported models */ 104 enum ksz_model { 105 KSZ8795, 106 KSZ8794, 107 KSZ8765, 108 KSZ8830, 109 KSZ9477, 110 KSZ9897, 111 KSZ9893, 112 KSZ9567, 113 LAN9370, 114 LAN9371, 115 LAN9372, 116 LAN9373, 117 LAN9374, 118 }; 119 120 enum ksz_chip_id { 121 KSZ8795_CHIP_ID = 0x8795, 122 KSZ8794_CHIP_ID = 0x8794, 123 KSZ8765_CHIP_ID = 0x8765, 124 KSZ8830_CHIP_ID = 0x8830, 125 KSZ9477_CHIP_ID = 0x00947700, 126 KSZ9897_CHIP_ID = 0x00989700, 127 KSZ9893_CHIP_ID = 0x00989300, 128 KSZ9567_CHIP_ID = 0x00956700, 129 LAN9370_CHIP_ID = 0x00937000, 130 LAN9371_CHIP_ID = 0x00937100, 131 LAN9372_CHIP_ID = 0x00937200, 132 LAN9373_CHIP_ID = 0x00937300, 133 LAN9374_CHIP_ID = 0x00937400, 134 }; 135 136 struct alu_struct { 137 /* entry 1 */ 138 u8 is_static:1; 139 u8 is_src_filter:1; 140 u8 is_dst_filter:1; 141 u8 prio_age:3; 142 u32 _reserv_0_1:23; 143 u8 mstp:3; 144 /* entry 2 */ 145 u8 is_override:1; 146 u8 is_use_fid:1; 147 u32 _reserv_1_1:23; 148 u8 port_forward:7; 149 /* entry 3 & 4*/ 150 u32 _reserv_2_1:9; 151 u8 fid:7; 152 u8 mac[ETH_ALEN]; 153 }; 154 155 struct ksz_dev_ops { 156 u32 (*get_port_addr)(int port, int offset); 157 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 158 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 159 void (*port_cleanup)(struct ksz_device *dev, int port); 160 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 161 void (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 162 void (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 163 int (*r_dyn_mac_table)(struct ksz_device *dev, u16 addr, u8 *mac_addr, 164 u8 *fid, u8 *src_port, u8 *timestamp, 165 u16 *entries); 166 int (*r_sta_mac_table)(struct ksz_device *dev, u16 addr, 167 struct alu_struct *alu); 168 void (*w_sta_mac_table)(struct ksz_device *dev, u16 addr, 169 struct alu_struct *alu); 170 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 171 u64 *cnt); 172 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 173 u64 *dropped, u64 *cnt); 174 void (*r_mib_stat64)(struct ksz_device *dev, int port); 175 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 176 void (*port_init_cnt)(struct ksz_device *dev, int port); 177 int (*shutdown)(struct ksz_device *dev); 178 int (*detect)(struct ksz_device *dev); 179 int (*init)(struct ksz_device *dev); 180 void (*exit)(struct ksz_device *dev); 181 }; 182 183 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 184 int ksz_switch_register(struct ksz_device *dev, 185 const struct ksz_dev_ops *ops); 186 void ksz_switch_remove(struct ksz_device *dev); 187 188 int ksz8_switch_register(struct ksz_device *dev); 189 int ksz9477_switch_register(struct ksz_device *dev); 190 191 void ksz_update_port_member(struct ksz_device *dev, int port); 192 void ksz_init_mib_timer(struct ksz_device *dev); 193 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 194 void ksz_get_stats64(struct dsa_switch *ds, int port, 195 struct rtnl_link_stats64 *s); 196 197 /* Common DSA access functions */ 198 199 int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg); 200 int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val); 201 void ksz_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode, 202 phy_interface_t interface); 203 int ksz_sset_count(struct dsa_switch *ds, int port, int sset); 204 void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *buf); 205 int ksz_port_bridge_join(struct dsa_switch *ds, int port, 206 struct dsa_bridge bridge, bool *tx_fwd_offload, 207 struct netlink_ext_ack *extack); 208 void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 209 struct dsa_bridge bridge); 210 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, 211 u8 state, int reg); 212 void ksz_port_fast_age(struct dsa_switch *ds, int port); 213 int ksz_port_fdb_dump(struct dsa_switch *ds, int port, dsa_fdb_dump_cb_t *cb, 214 void *data); 215 int ksz_port_mdb_add(struct dsa_switch *ds, int port, 216 const struct switchdev_obj_port_mdb *mdb, 217 struct dsa_db db); 218 int ksz_port_mdb_del(struct dsa_switch *ds, int port, 219 const struct switchdev_obj_port_mdb *mdb, 220 struct dsa_db db); 221 int ksz_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy); 222 223 /* Common register access functions */ 224 225 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 226 { 227 unsigned int value; 228 int ret = regmap_read(dev->regmap[0], reg, &value); 229 230 *val = value; 231 return ret; 232 } 233 234 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 235 { 236 unsigned int value; 237 int ret = regmap_read(dev->regmap[1], reg, &value); 238 239 *val = value; 240 return ret; 241 } 242 243 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 244 { 245 unsigned int value; 246 int ret = regmap_read(dev->regmap[2], reg, &value); 247 248 *val = value; 249 return ret; 250 } 251 252 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 253 { 254 u32 value[2]; 255 int ret; 256 257 ret = regmap_bulk_read(dev->regmap[2], reg, value, 2); 258 if (!ret) 259 *val = (u64)value[0] << 32 | value[1]; 260 261 return ret; 262 } 263 264 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 265 { 266 return regmap_write(dev->regmap[0], reg, value); 267 } 268 269 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 270 { 271 return regmap_write(dev->regmap[1], reg, value); 272 } 273 274 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 275 { 276 return regmap_write(dev->regmap[2], reg, value); 277 } 278 279 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 280 { 281 u32 val[2]; 282 283 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 284 value = swab64(value); 285 val[0] = swab32(value & 0xffffffffULL); 286 val[1] = swab32(value >> 32ULL); 287 288 return regmap_bulk_write(dev->regmap[2], reg, val, 2); 289 } 290 291 static inline void ksz_pread8(struct ksz_device *dev, int port, int offset, 292 u8 *data) 293 { 294 ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 295 } 296 297 static inline void ksz_pread16(struct ksz_device *dev, int port, int offset, 298 u16 *data) 299 { 300 ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 301 } 302 303 static inline void ksz_pread32(struct ksz_device *dev, int port, int offset, 304 u32 *data) 305 { 306 ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 307 } 308 309 static inline void ksz_pwrite8(struct ksz_device *dev, int port, int offset, 310 u8 data) 311 { 312 ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 313 } 314 315 static inline void ksz_pwrite16(struct ksz_device *dev, int port, int offset, 316 u16 data) 317 { 318 ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), data); 319 } 320 321 static inline void ksz_pwrite32(struct ksz_device *dev, int port, int offset, 322 u32 data) 323 { 324 ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), data); 325 } 326 327 static inline void ksz_regmap_lock(void *__mtx) 328 { 329 struct mutex *mtx = __mtx; 330 mutex_lock(mtx); 331 } 332 333 static inline void ksz_regmap_unlock(void *__mtx) 334 { 335 struct mutex *mtx = __mtx; 336 mutex_unlock(mtx); 337 } 338 339 /* STP State Defines */ 340 #define PORT_TX_ENABLE BIT(2) 341 #define PORT_RX_ENABLE BIT(1) 342 #define PORT_LEARN_DISABLE BIT(0) 343 344 /* Regmap tables generation */ 345 #define KSZ_SPI_OP_RD 3 346 #define KSZ_SPI_OP_WR 2 347 348 #define swabnot_used(x) 0 349 350 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 351 swab##swp((opcode) << ((regbits) + (regpad))) 352 353 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 354 { \ 355 .name = #width, \ 356 .val_bits = (width), \ 357 .reg_stride = 1, \ 358 .reg_bits = (regbits) + (regalign), \ 359 .pad_bits = (regpad), \ 360 .max_register = BIT(regbits) - 1, \ 361 .cache_type = REGCACHE_NONE, \ 362 .read_flag_mask = \ 363 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 364 regbits, regpad), \ 365 .write_flag_mask = \ 366 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 367 regbits, regpad), \ 368 .lock = ksz_regmap_lock, \ 369 .unlock = ksz_regmap_unlock, \ 370 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 371 .val_format_endian = REGMAP_ENDIAN_BIG \ 372 } 373 374 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 375 static const struct regmap_config ksz##_regmap_config[] = { \ 376 KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 377 KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 378 KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 379 } 380 381 #endif 382