1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 #include <linux/irq.h> 17 18 #include "ksz_ptp.h" 19 20 #define KSZ_MAX_NUM_PORTS 8 21 22 struct ksz_device; 23 struct ksz_port; 24 25 struct vlan_table { 26 u32 table[3]; 27 }; 28 29 struct ksz_port_mib { 30 struct mutex cnt_mutex; /* structure access */ 31 u8 cnt_ptr; 32 u64 *counters; 33 struct rtnl_link_stats64 stats64; 34 struct ethtool_pause_stats pause_stats; 35 struct spinlock stats64_lock; 36 }; 37 38 struct ksz_mib_names { 39 int index; 40 char string[ETH_GSTRING_LEN]; 41 }; 42 43 struct ksz_chip_data { 44 u32 chip_id; 45 const char *dev_name; 46 int num_vlans; 47 int num_alus; 48 int num_statics; 49 int cpu_ports; 50 int port_cnt; 51 u8 port_nirqs; 52 u8 num_tx_queues; 53 bool tc_cbs_supported; 54 const struct ksz_dev_ops *ops; 55 bool phy_errata_9477; 56 bool ksz87xx_eee_link_erratum; 57 const struct ksz_mib_names *mib_names; 58 int mib_cnt; 59 u8 reg_mib_cnt; 60 const u16 *regs; 61 const u32 *masks; 62 const u8 *shifts; 63 const u8 *xmii_ctrl0; 64 const u8 *xmii_ctrl1; 65 int stp_ctrl_reg; 66 int broadcast_ctrl_reg; 67 int multicast_ctrl_reg; 68 int start_ctrl_reg; 69 bool supports_mii[KSZ_MAX_NUM_PORTS]; 70 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 71 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 72 bool internal_phy[KSZ_MAX_NUM_PORTS]; 73 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 74 const struct regmap_access_table *wr_table; 75 const struct regmap_access_table *rd_table; 76 }; 77 78 struct ksz_irq { 79 u16 masked; 80 u16 reg_mask; 81 u16 reg_status; 82 struct irq_domain *domain; 83 int nirqs; 84 int irq_num; 85 char name[16]; 86 struct ksz_device *dev; 87 }; 88 89 struct ksz_ptp_irq { 90 struct ksz_port *port; 91 u16 ts_reg; 92 bool ts_en; 93 char name[16]; 94 int num; 95 }; 96 97 struct ksz_port { 98 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 99 bool learning; 100 int stp_state; 101 struct phy_device phydev; 102 103 u32 on:1; /* port is not disabled by hardware */ 104 u32 fiber:1; /* port is fiber */ 105 u32 force:1; 106 u32 read:1; /* read MIB counters in background */ 107 u32 freeze:1; /* MIB counter freeze is enabled */ 108 109 struct ksz_port_mib mib; 110 phy_interface_t interface; 111 u32 rgmii_tx_val; 112 u32 rgmii_rx_val; 113 struct ksz_device *ksz_dev; 114 struct ksz_irq pirq; 115 u8 num; 116 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) 117 struct hwtstamp_config tstamp_config; 118 bool hwts_tx_en; 119 bool hwts_rx_en; 120 struct ksz_irq ptpirq; 121 struct ksz_ptp_irq ptpmsg_irq[3]; 122 ktime_t tstamp_msg; 123 struct completion tstamp_msg_comp; 124 #endif 125 }; 126 127 struct ksz_device { 128 struct dsa_switch *ds; 129 struct ksz_platform_data *pdata; 130 const struct ksz_chip_data *info; 131 132 struct mutex dev_mutex; /* device access */ 133 struct mutex regmap_mutex; /* regmap access */ 134 struct mutex alu_mutex; /* ALU access */ 135 struct mutex vlan_mutex; /* vlan access */ 136 const struct ksz_dev_ops *dev_ops; 137 138 struct device *dev; 139 struct regmap *regmap[3]; 140 141 void *priv; 142 int irq; 143 144 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 145 146 /* chip specific data */ 147 u32 chip_id; 148 u8 chip_rev; 149 int cpu_port; /* port connected to CPU */ 150 int phy_port_cnt; 151 phy_interface_t compat_interface; 152 bool synclko_125; 153 bool synclko_disable; 154 155 struct vlan_table *vlan_cache; 156 157 struct ksz_port *ports; 158 struct delayed_work mib_read; 159 unsigned long mib_read_interval; 160 u16 mirror_rx; 161 u16 mirror_tx; 162 u16 port_mask; 163 struct mutex lock_irq; /* IRQ Access */ 164 struct ksz_irq girq; 165 struct ksz_ptp_data ptp_data; 166 }; 167 168 /* List of supported models */ 169 enum ksz_model { 170 KSZ8563, 171 KSZ8795, 172 KSZ8794, 173 KSZ8765, 174 KSZ8830, 175 KSZ9477, 176 KSZ9896, 177 KSZ9897, 178 KSZ9893, 179 KSZ9563, 180 KSZ9567, 181 LAN9370, 182 LAN9371, 183 LAN9372, 184 LAN9373, 185 LAN9374, 186 }; 187 188 enum ksz_chip_id { 189 KSZ8563_CHIP_ID = 0x8563, 190 KSZ8795_CHIP_ID = 0x8795, 191 KSZ8794_CHIP_ID = 0x8794, 192 KSZ8765_CHIP_ID = 0x8765, 193 KSZ8830_CHIP_ID = 0x8830, 194 KSZ9477_CHIP_ID = 0x00947700, 195 KSZ9896_CHIP_ID = 0x00989600, 196 KSZ9897_CHIP_ID = 0x00989700, 197 KSZ9893_CHIP_ID = 0x00989300, 198 KSZ9563_CHIP_ID = 0x00956300, 199 KSZ9567_CHIP_ID = 0x00956700, 200 LAN9370_CHIP_ID = 0x00937000, 201 LAN9371_CHIP_ID = 0x00937100, 202 LAN9372_CHIP_ID = 0x00937200, 203 LAN9373_CHIP_ID = 0x00937300, 204 LAN9374_CHIP_ID = 0x00937400, 205 }; 206 207 enum ksz_regs { 208 REG_IND_CTRL_0, 209 REG_IND_DATA_8, 210 REG_IND_DATA_CHECK, 211 REG_IND_DATA_HI, 212 REG_IND_DATA_LO, 213 REG_IND_MIB_CHECK, 214 REG_IND_BYTE, 215 P_FORCE_CTRL, 216 P_LINK_STATUS, 217 P_LOCAL_CTRL, 218 P_NEG_RESTART_CTRL, 219 P_REMOTE_STATUS, 220 P_SPEED_STATUS, 221 S_TAIL_TAG_CTRL, 222 P_STP_CTRL, 223 S_START_CTRL, 224 S_BROADCAST_CTRL, 225 S_MULTICAST_CTRL, 226 P_XMII_CTRL_0, 227 P_XMII_CTRL_1, 228 }; 229 230 enum ksz_masks { 231 PORT_802_1P_REMAPPING, 232 SW_TAIL_TAG_ENABLE, 233 MIB_COUNTER_OVERFLOW, 234 MIB_COUNTER_VALID, 235 VLAN_TABLE_FID, 236 VLAN_TABLE_MEMBERSHIP, 237 VLAN_TABLE_VALID, 238 STATIC_MAC_TABLE_VALID, 239 STATIC_MAC_TABLE_USE_FID, 240 STATIC_MAC_TABLE_FID, 241 STATIC_MAC_TABLE_OVERRIDE, 242 STATIC_MAC_TABLE_FWD_PORTS, 243 DYNAMIC_MAC_TABLE_ENTRIES_H, 244 DYNAMIC_MAC_TABLE_MAC_EMPTY, 245 DYNAMIC_MAC_TABLE_NOT_READY, 246 DYNAMIC_MAC_TABLE_ENTRIES, 247 DYNAMIC_MAC_TABLE_FID, 248 DYNAMIC_MAC_TABLE_SRC_PORT, 249 DYNAMIC_MAC_TABLE_TIMESTAMP, 250 ALU_STAT_WRITE, 251 ALU_STAT_READ, 252 P_MII_TX_FLOW_CTRL, 253 P_MII_RX_FLOW_CTRL, 254 }; 255 256 enum ksz_shifts { 257 VLAN_TABLE_MEMBERSHIP_S, 258 VLAN_TABLE, 259 STATIC_MAC_FWD_PORTS, 260 STATIC_MAC_FID, 261 DYNAMIC_MAC_ENTRIES_H, 262 DYNAMIC_MAC_ENTRIES, 263 DYNAMIC_MAC_FID, 264 DYNAMIC_MAC_TIMESTAMP, 265 DYNAMIC_MAC_SRC_PORT, 266 ALU_STAT_INDEX, 267 }; 268 269 enum ksz_xmii_ctrl0 { 270 P_MII_100MBIT, 271 P_MII_10MBIT, 272 P_MII_FULL_DUPLEX, 273 P_MII_HALF_DUPLEX, 274 }; 275 276 enum ksz_xmii_ctrl1 { 277 P_RGMII_SEL, 278 P_RMII_SEL, 279 P_GMII_SEL, 280 P_MII_SEL, 281 P_GMII_1GBIT, 282 P_GMII_NOT_1GBIT, 283 }; 284 285 struct alu_struct { 286 /* entry 1 */ 287 u8 is_static:1; 288 u8 is_src_filter:1; 289 u8 is_dst_filter:1; 290 u8 prio_age:3; 291 u32 _reserv_0_1:23; 292 u8 mstp:3; 293 /* entry 2 */ 294 u8 is_override:1; 295 u8 is_use_fid:1; 296 u32 _reserv_1_1:23; 297 u8 port_forward:7; 298 /* entry 3 & 4*/ 299 u32 _reserv_2_1:9; 300 u8 fid:7; 301 u8 mac[ETH_ALEN]; 302 }; 303 304 struct ksz_dev_ops { 305 int (*setup)(struct dsa_switch *ds); 306 void (*teardown)(struct dsa_switch *ds); 307 u32 (*get_port_addr)(int port, int offset); 308 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 309 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 310 void (*port_cleanup)(struct ksz_device *dev, int port); 311 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 312 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); 313 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 314 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 315 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 316 u64 *cnt); 317 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 318 u64 *dropped, u64 *cnt); 319 void (*r_mib_stat64)(struct ksz_device *dev, int port); 320 int (*vlan_filtering)(struct ksz_device *dev, int port, 321 bool flag, struct netlink_ext_ack *extack); 322 int (*vlan_add)(struct ksz_device *dev, int port, 323 const struct switchdev_obj_port_vlan *vlan, 324 struct netlink_ext_ack *extack); 325 int (*vlan_del)(struct ksz_device *dev, int port, 326 const struct switchdev_obj_port_vlan *vlan); 327 int (*mirror_add)(struct ksz_device *dev, int port, 328 struct dsa_mall_mirror_tc_entry *mirror, 329 bool ingress, struct netlink_ext_ack *extack); 330 void (*mirror_del)(struct ksz_device *dev, int port, 331 struct dsa_mall_mirror_tc_entry *mirror); 332 int (*fdb_add)(struct ksz_device *dev, int port, 333 const unsigned char *addr, u16 vid, struct dsa_db db); 334 int (*fdb_del)(struct ksz_device *dev, int port, 335 const unsigned char *addr, u16 vid, struct dsa_db db); 336 int (*fdb_dump)(struct ksz_device *dev, int port, 337 dsa_fdb_dump_cb_t *cb, void *data); 338 int (*mdb_add)(struct ksz_device *dev, int port, 339 const struct switchdev_obj_port_mdb *mdb, 340 struct dsa_db db); 341 int (*mdb_del)(struct ksz_device *dev, int port, 342 const struct switchdev_obj_port_mdb *mdb, 343 struct dsa_db db); 344 void (*get_caps)(struct ksz_device *dev, int port, 345 struct phylink_config *config); 346 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 347 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 348 void (*port_init_cnt)(struct ksz_device *dev, int port); 349 void (*phylink_mac_config)(struct ksz_device *dev, int port, 350 unsigned int mode, 351 const struct phylink_link_state *state); 352 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 353 unsigned int mode, 354 phy_interface_t interface, 355 struct phy_device *phydev, int speed, 356 int duplex, bool tx_pause, bool rx_pause); 357 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 358 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val); 359 void (*config_cpu_port)(struct dsa_switch *ds); 360 int (*enable_stp_addr)(struct ksz_device *dev); 361 int (*reset)(struct ksz_device *dev); 362 int (*init)(struct ksz_device *dev); 363 void (*exit)(struct ksz_device *dev); 364 }; 365 366 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 367 int ksz_switch_register(struct ksz_device *dev); 368 void ksz_switch_remove(struct ksz_device *dev); 369 370 void ksz_init_mib_timer(struct ksz_device *dev); 371 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 372 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port); 373 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 374 bool ksz_get_gbit(struct ksz_device *dev, int port); 375 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 376 extern const struct ksz_chip_data ksz_switch_chips[]; 377 378 /* Common register access functions */ 379 380 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 381 { 382 unsigned int value; 383 int ret = regmap_read(dev->regmap[0], reg, &value); 384 385 if (ret) 386 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 387 ERR_PTR(ret)); 388 389 *val = value; 390 return ret; 391 } 392 393 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 394 { 395 unsigned int value; 396 int ret = regmap_read(dev->regmap[1], reg, &value); 397 398 if (ret) 399 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 400 ERR_PTR(ret)); 401 402 *val = value; 403 return ret; 404 } 405 406 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 407 { 408 unsigned int value; 409 int ret = regmap_read(dev->regmap[2], reg, &value); 410 411 if (ret) 412 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 413 ERR_PTR(ret)); 414 415 *val = value; 416 return ret; 417 } 418 419 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 420 { 421 u32 value[2]; 422 int ret; 423 424 ret = regmap_bulk_read(dev->regmap[2], reg, value, 2); 425 if (ret) 426 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 427 ERR_PTR(ret)); 428 else 429 *val = (u64)value[0] << 32 | value[1]; 430 431 return ret; 432 } 433 434 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 435 { 436 int ret; 437 438 ret = regmap_write(dev->regmap[0], reg, value); 439 if (ret) 440 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 441 ERR_PTR(ret)); 442 443 return ret; 444 } 445 446 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 447 { 448 int ret; 449 450 ret = regmap_write(dev->regmap[1], reg, value); 451 if (ret) 452 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 453 ERR_PTR(ret)); 454 455 return ret; 456 } 457 458 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 459 { 460 int ret; 461 462 ret = regmap_write(dev->regmap[2], reg, value); 463 if (ret) 464 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 465 ERR_PTR(ret)); 466 467 return ret; 468 } 469 470 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, 471 u16 value) 472 { 473 int ret; 474 475 ret = regmap_update_bits(dev->regmap[1], reg, mask, value); 476 if (ret) 477 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg, 478 ERR_PTR(ret)); 479 480 return ret; 481 } 482 483 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask, 484 u32 value) 485 { 486 int ret; 487 488 ret = regmap_update_bits(dev->regmap[2], reg, mask, value); 489 if (ret) 490 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg, 491 ERR_PTR(ret)); 492 493 return ret; 494 } 495 496 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 497 { 498 u32 val[2]; 499 500 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 501 value = swab64(value); 502 val[0] = swab32(value & 0xffffffffULL); 503 val[1] = swab32(value >> 32ULL); 504 505 return regmap_bulk_write(dev->regmap[2], reg, val, 2); 506 } 507 508 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val) 509 { 510 return regmap_update_bits(dev->regmap[0], offset, mask, val); 511 } 512 513 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 514 u8 *data) 515 { 516 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 517 } 518 519 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 520 u16 *data) 521 { 522 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 523 } 524 525 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 526 u32 *data) 527 { 528 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 529 } 530 531 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 532 u8 data) 533 { 534 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 535 } 536 537 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 538 u16 data) 539 { 540 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 541 data); 542 } 543 544 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 545 u32 data) 546 { 547 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 548 data); 549 } 550 551 static inline void ksz_prmw8(struct ksz_device *dev, int port, int offset, 552 u8 mask, u8 val) 553 { 554 regmap_update_bits(dev->regmap[0], 555 dev->dev_ops->get_port_addr(port, offset), 556 mask, val); 557 } 558 559 static inline void ksz_regmap_lock(void *__mtx) 560 { 561 struct mutex *mtx = __mtx; 562 mutex_lock(mtx); 563 } 564 565 static inline void ksz_regmap_unlock(void *__mtx) 566 { 567 struct mutex *mtx = __mtx; 568 mutex_unlock(mtx); 569 } 570 571 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 572 { 573 return dev->chip_id == KSZ8830_CHIP_ID; 574 } 575 576 static inline int is_lan937x(struct ksz_device *dev) 577 { 578 return dev->chip_id == LAN9370_CHIP_ID || 579 dev->chip_id == LAN9371_CHIP_ID || 580 dev->chip_id == LAN9372_CHIP_ID || 581 dev->chip_id == LAN9373_CHIP_ID || 582 dev->chip_id == LAN9374_CHIP_ID; 583 } 584 585 /* STP State Defines */ 586 #define PORT_TX_ENABLE BIT(2) 587 #define PORT_RX_ENABLE BIT(1) 588 #define PORT_LEARN_DISABLE BIT(0) 589 590 /* Switch ID Defines */ 591 #define REG_CHIP_ID0 0x00 592 593 #define SW_FAMILY_ID_M GENMASK(15, 8) 594 #define KSZ87_FAMILY_ID 0x87 595 #define KSZ88_FAMILY_ID 0x88 596 597 #define KSZ8_PORT_STATUS_0 0x08 598 #define KSZ8_PORT_FIBER_MODE BIT(7) 599 600 #define SW_CHIP_ID_M GENMASK(7, 4) 601 #define KSZ87_CHIP_ID_94 0x6 602 #define KSZ87_CHIP_ID_95 0x9 603 #define KSZ88_CHIP_ID_63 0x3 604 605 #define SW_REV_ID_M GENMASK(7, 4) 606 607 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 608 #define REG_CHIP_ID4 0x0f 609 #define SKU_ID_KSZ8563 0x3c 610 #define SKU_ID_KSZ9563 0x1c 611 612 /* Driver set switch broadcast storm protection at 10% rate. */ 613 #define BROADCAST_STORM_PROT_RATE 10 614 615 /* 148,800 frames * 67 ms / 100 */ 616 #define BROADCAST_STORM_VALUE 9969 617 618 #define BROADCAST_STORM_RATE_HI 0x07 619 #define BROADCAST_STORM_RATE_LO 0xFF 620 #define BROADCAST_STORM_RATE 0x07FF 621 622 #define MULTICAST_STORM_DISABLE BIT(6) 623 624 #define SW_START 0x01 625 626 /* xMII configuration */ 627 #define P_MII_DUPLEX_M BIT(6) 628 #define P_MII_100MBIT_M BIT(4) 629 630 #define P_GMII_1GBIT_M BIT(6) 631 #define P_RGMII_ID_IG_ENABLE BIT(4) 632 #define P_RGMII_ID_EG_ENABLE BIT(3) 633 #define P_MII_MAC_MODE BIT(2) 634 #define P_MII_SEL_M 0x3 635 636 /* Interrupt */ 637 #define REG_SW_PORT_INT_STATUS__1 0x001B 638 #define REG_SW_PORT_INT_MASK__1 0x001F 639 640 #define REG_PORT_INT_STATUS 0x001B 641 #define REG_PORT_INT_MASK 0x001F 642 643 #define PORT_SRC_PHY_INT 1 644 #define PORT_SRC_PTP_INT 2 645 646 #define KSZ8795_HUGE_PACKET_SIZE 2000 647 #define KSZ8863_HUGE_PACKET_SIZE 1916 648 #define KSZ8863_NORMAL_PACKET_SIZE 1536 649 #define KSZ8_LEGAL_PACKET_SIZE 1518 650 #define KSZ9477_MAX_FRAME_SIZE 9000 651 652 /* CBS related registers */ 653 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900 654 655 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914 656 657 #define MTI_SCHEDULE_MODE_M 0x3 658 #define MTI_SCHEDULE_MODE_S 6 659 #define MTI_SCHEDULE_STRICT_PRIO 0 660 #define MTI_SCHEDULE_WRR 2 661 #define MTI_SHAPING_M 0x3 662 #define MTI_SHAPING_S 4 663 #define MTI_SHAPING_OFF 0 664 #define MTI_SHAPING_SRP 1 665 #define MTI_SHAPING_TIME_AWARE 2 666 667 #define REG_PORT_MTI_HI_WATER_MARK 0x0916 668 #define REG_PORT_MTI_LO_WATER_MARK 0x0918 669 670 /* Regmap tables generation */ 671 #define KSZ_SPI_OP_RD 3 672 #define KSZ_SPI_OP_WR 2 673 674 #define swabnot_used(x) 0 675 676 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 677 swab##swp((opcode) << ((regbits) + (regpad))) 678 679 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 680 { \ 681 .name = #width, \ 682 .val_bits = (width), \ 683 .reg_stride = 1, \ 684 .reg_bits = (regbits) + (regalign), \ 685 .pad_bits = (regpad), \ 686 .max_register = BIT(regbits) - 1, \ 687 .cache_type = REGCACHE_NONE, \ 688 .read_flag_mask = \ 689 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 690 regbits, regpad), \ 691 .write_flag_mask = \ 692 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 693 regbits, regpad), \ 694 .lock = ksz_regmap_lock, \ 695 .unlock = ksz_regmap_unlock, \ 696 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 697 .val_format_endian = REGMAP_ENDIAN_BIG \ 698 } 699 700 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 701 static const struct regmap_config ksz##_regmap_config[] = { \ 702 KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 703 KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 704 KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 705 } 706 707 #endif 708