1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2019 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 17 #define KSZ_MAX_NUM_PORTS 8 18 19 struct vlan_table { 20 u32 table[3]; 21 }; 22 23 struct ksz_port_mib { 24 struct mutex cnt_mutex; /* structure access */ 25 u8 cnt_ptr; 26 u64 *counters; 27 struct rtnl_link_stats64 stats64; 28 struct ethtool_pause_stats pause_stats; 29 struct spinlock stats64_lock; 30 }; 31 32 struct ksz_mib_names { 33 int index; 34 char string[ETH_GSTRING_LEN]; 35 }; 36 37 struct ksz_chip_data { 38 u32 chip_id; 39 const char *dev_name; 40 int num_vlans; 41 int num_alus; 42 int num_statics; 43 int cpu_ports; 44 int port_cnt; 45 const struct ksz_dev_ops *ops; 46 bool phy_errata_9477; 47 bool ksz87xx_eee_link_erratum; 48 const struct ksz_mib_names *mib_names; 49 int mib_cnt; 50 u8 reg_mib_cnt; 51 const u16 *regs; 52 const u32 *masks; 53 const u8 *shifts; 54 const u8 *xmii_ctrl0; 55 const u8 *xmii_ctrl1; 56 int stp_ctrl_reg; 57 int broadcast_ctrl_reg; 58 int multicast_ctrl_reg; 59 int start_ctrl_reg; 60 bool supports_mii[KSZ_MAX_NUM_PORTS]; 61 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 62 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 63 bool internal_phy[KSZ_MAX_NUM_PORTS]; 64 }; 65 66 struct ksz_port { 67 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 68 int stp_state; 69 struct phy_device phydev; 70 71 u32 on:1; /* port is not disabled by hardware */ 72 u32 phy:1; /* port has a PHY */ 73 u32 fiber:1; /* port is fiber */ 74 u32 sgmii:1; /* port is SGMII */ 75 u32 force:1; 76 u32 read:1; /* read MIB counters in background */ 77 u32 freeze:1; /* MIB counter freeze is enabled */ 78 79 struct ksz_port_mib mib; 80 phy_interface_t interface; 81 u16 max_frame; 82 u32 rgmii_tx_val; 83 u32 rgmii_rx_val; 84 }; 85 86 struct ksz_device { 87 struct dsa_switch *ds; 88 struct ksz_platform_data *pdata; 89 const struct ksz_chip_data *info; 90 91 struct mutex dev_mutex; /* device access */ 92 struct mutex regmap_mutex; /* regmap access */ 93 struct mutex alu_mutex; /* ALU access */ 94 struct mutex vlan_mutex; /* vlan access */ 95 const struct ksz_dev_ops *dev_ops; 96 97 struct device *dev; 98 struct regmap *regmap[3]; 99 100 void *priv; 101 102 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 103 104 /* chip specific data */ 105 u32 chip_id; 106 u8 chip_rev; 107 int cpu_port; /* port connected to CPU */ 108 int phy_port_cnt; 109 phy_interface_t compat_interface; 110 bool synclko_125; 111 bool synclko_disable; 112 113 struct vlan_table *vlan_cache; 114 115 struct ksz_port *ports; 116 struct delayed_work mib_read; 117 unsigned long mib_read_interval; 118 u16 mirror_rx; 119 u16 mirror_tx; 120 u32 features; /* chip specific features */ 121 u16 port_mask; 122 }; 123 124 /* List of supported models */ 125 enum ksz_model { 126 KSZ8795, 127 KSZ8794, 128 KSZ8765, 129 KSZ8830, 130 KSZ9477, 131 KSZ9897, 132 KSZ9893, 133 KSZ9567, 134 LAN9370, 135 LAN9371, 136 LAN9372, 137 LAN9373, 138 LAN9374, 139 }; 140 141 enum ksz_chip_id { 142 KSZ8795_CHIP_ID = 0x8795, 143 KSZ8794_CHIP_ID = 0x8794, 144 KSZ8765_CHIP_ID = 0x8765, 145 KSZ8830_CHIP_ID = 0x8830, 146 KSZ9477_CHIP_ID = 0x00947700, 147 KSZ9897_CHIP_ID = 0x00989700, 148 KSZ9893_CHIP_ID = 0x00989300, 149 KSZ9567_CHIP_ID = 0x00956700, 150 LAN9370_CHIP_ID = 0x00937000, 151 LAN9371_CHIP_ID = 0x00937100, 152 LAN9372_CHIP_ID = 0x00937200, 153 LAN9373_CHIP_ID = 0x00937300, 154 LAN9374_CHIP_ID = 0x00937400, 155 }; 156 157 enum ksz_regs { 158 REG_IND_CTRL_0, 159 REG_IND_DATA_8, 160 REG_IND_DATA_CHECK, 161 REG_IND_DATA_HI, 162 REG_IND_DATA_LO, 163 REG_IND_MIB_CHECK, 164 REG_IND_BYTE, 165 P_FORCE_CTRL, 166 P_LINK_STATUS, 167 P_LOCAL_CTRL, 168 P_NEG_RESTART_CTRL, 169 P_REMOTE_STATUS, 170 P_SPEED_STATUS, 171 S_TAIL_TAG_CTRL, 172 P_STP_CTRL, 173 S_START_CTRL, 174 S_BROADCAST_CTRL, 175 S_MULTICAST_CTRL, 176 P_XMII_CTRL_0, 177 P_XMII_CTRL_1, 178 }; 179 180 enum ksz_masks { 181 PORT_802_1P_REMAPPING, 182 SW_TAIL_TAG_ENABLE, 183 MIB_COUNTER_OVERFLOW, 184 MIB_COUNTER_VALID, 185 VLAN_TABLE_FID, 186 VLAN_TABLE_MEMBERSHIP, 187 VLAN_TABLE_VALID, 188 STATIC_MAC_TABLE_VALID, 189 STATIC_MAC_TABLE_USE_FID, 190 STATIC_MAC_TABLE_FID, 191 STATIC_MAC_TABLE_OVERRIDE, 192 STATIC_MAC_TABLE_FWD_PORTS, 193 DYNAMIC_MAC_TABLE_ENTRIES_H, 194 DYNAMIC_MAC_TABLE_MAC_EMPTY, 195 DYNAMIC_MAC_TABLE_NOT_READY, 196 DYNAMIC_MAC_TABLE_ENTRIES, 197 DYNAMIC_MAC_TABLE_FID, 198 DYNAMIC_MAC_TABLE_SRC_PORT, 199 DYNAMIC_MAC_TABLE_TIMESTAMP, 200 ALU_STAT_WRITE, 201 ALU_STAT_READ, 202 P_MII_TX_FLOW_CTRL, 203 P_MII_RX_FLOW_CTRL, 204 }; 205 206 enum ksz_shifts { 207 VLAN_TABLE_MEMBERSHIP_S, 208 VLAN_TABLE, 209 STATIC_MAC_FWD_PORTS, 210 STATIC_MAC_FID, 211 DYNAMIC_MAC_ENTRIES_H, 212 DYNAMIC_MAC_ENTRIES, 213 DYNAMIC_MAC_FID, 214 DYNAMIC_MAC_TIMESTAMP, 215 DYNAMIC_MAC_SRC_PORT, 216 ALU_STAT_INDEX, 217 }; 218 219 enum ksz_xmii_ctrl0 { 220 P_MII_100MBIT, 221 P_MII_10MBIT, 222 P_MII_FULL_DUPLEX, 223 P_MII_HALF_DUPLEX, 224 }; 225 226 enum ksz_xmii_ctrl1 { 227 P_RGMII_SEL, 228 P_RMII_SEL, 229 P_GMII_SEL, 230 P_MII_SEL, 231 P_GMII_1GBIT, 232 P_GMII_NOT_1GBIT, 233 }; 234 235 struct alu_struct { 236 /* entry 1 */ 237 u8 is_static:1; 238 u8 is_src_filter:1; 239 u8 is_dst_filter:1; 240 u8 prio_age:3; 241 u32 _reserv_0_1:23; 242 u8 mstp:3; 243 /* entry 2 */ 244 u8 is_override:1; 245 u8 is_use_fid:1; 246 u32 _reserv_1_1:23; 247 u8 port_forward:7; 248 /* entry 3 & 4*/ 249 u32 _reserv_2_1:9; 250 u8 fid:7; 251 u8 mac[ETH_ALEN]; 252 }; 253 254 struct ksz_dev_ops { 255 int (*setup)(struct dsa_switch *ds); 256 u32 (*get_port_addr)(int port, int offset); 257 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 258 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 259 void (*port_cleanup)(struct ksz_device *dev, int port); 260 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 261 void (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 262 void (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 263 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 264 u64 *cnt); 265 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 266 u64 *dropped, u64 *cnt); 267 void (*r_mib_stat64)(struct ksz_device *dev, int port); 268 int (*vlan_filtering)(struct ksz_device *dev, int port, 269 bool flag, struct netlink_ext_ack *extack); 270 int (*vlan_add)(struct ksz_device *dev, int port, 271 const struct switchdev_obj_port_vlan *vlan, 272 struct netlink_ext_ack *extack); 273 int (*vlan_del)(struct ksz_device *dev, int port, 274 const struct switchdev_obj_port_vlan *vlan); 275 int (*mirror_add)(struct ksz_device *dev, int port, 276 struct dsa_mall_mirror_tc_entry *mirror, 277 bool ingress, struct netlink_ext_ack *extack); 278 void (*mirror_del)(struct ksz_device *dev, int port, 279 struct dsa_mall_mirror_tc_entry *mirror); 280 int (*fdb_add)(struct ksz_device *dev, int port, 281 const unsigned char *addr, u16 vid, struct dsa_db db); 282 int (*fdb_del)(struct ksz_device *dev, int port, 283 const unsigned char *addr, u16 vid, struct dsa_db db); 284 int (*fdb_dump)(struct ksz_device *dev, int port, 285 dsa_fdb_dump_cb_t *cb, void *data); 286 int (*mdb_add)(struct ksz_device *dev, int port, 287 const struct switchdev_obj_port_mdb *mdb, 288 struct dsa_db db); 289 int (*mdb_del)(struct ksz_device *dev, int port, 290 const struct switchdev_obj_port_mdb *mdb, 291 struct dsa_db db); 292 void (*get_caps)(struct ksz_device *dev, int port, 293 struct phylink_config *config); 294 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 295 int (*max_mtu)(struct ksz_device *dev, int port); 296 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 297 void (*port_init_cnt)(struct ksz_device *dev, int port); 298 void (*phylink_mac_config)(struct ksz_device *dev, int port, 299 unsigned int mode, 300 const struct phylink_link_state *state); 301 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 302 unsigned int mode, 303 phy_interface_t interface, 304 struct phy_device *phydev, int speed, 305 int duplex, bool tx_pause, bool rx_pause); 306 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 307 void (*config_cpu_port)(struct dsa_switch *ds); 308 int (*enable_stp_addr)(struct ksz_device *dev); 309 int (*reset)(struct ksz_device *dev); 310 int (*init)(struct ksz_device *dev); 311 void (*exit)(struct ksz_device *dev); 312 }; 313 314 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 315 int ksz_switch_register(struct ksz_device *dev); 316 void ksz_switch_remove(struct ksz_device *dev); 317 318 void ksz_init_mib_timer(struct ksz_device *dev); 319 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 320 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 321 bool ksz_get_gbit(struct ksz_device *dev, int port); 322 void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface); 323 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 324 extern const struct ksz_chip_data ksz_switch_chips[]; 325 326 /* Common register access functions */ 327 328 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 329 { 330 unsigned int value; 331 int ret = regmap_read(dev->regmap[0], reg, &value); 332 333 *val = value; 334 return ret; 335 } 336 337 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 338 { 339 unsigned int value; 340 int ret = regmap_read(dev->regmap[1], reg, &value); 341 342 *val = value; 343 return ret; 344 } 345 346 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 347 { 348 unsigned int value; 349 int ret = regmap_read(dev->regmap[2], reg, &value); 350 351 *val = value; 352 return ret; 353 } 354 355 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 356 { 357 u32 value[2]; 358 int ret; 359 360 ret = regmap_bulk_read(dev->regmap[2], reg, value, 2); 361 if (!ret) 362 *val = (u64)value[0] << 32 | value[1]; 363 364 return ret; 365 } 366 367 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 368 { 369 return regmap_write(dev->regmap[0], reg, value); 370 } 371 372 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 373 { 374 return regmap_write(dev->regmap[1], reg, value); 375 } 376 377 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 378 { 379 return regmap_write(dev->regmap[2], reg, value); 380 } 381 382 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 383 { 384 u32 val[2]; 385 386 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 387 value = swab64(value); 388 val[0] = swab32(value & 0xffffffffULL); 389 val[1] = swab32(value >> 32ULL); 390 391 return regmap_bulk_write(dev->regmap[2], reg, val, 2); 392 } 393 394 static inline void ksz_pread8(struct ksz_device *dev, int port, int offset, 395 u8 *data) 396 { 397 ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 398 } 399 400 static inline void ksz_pread16(struct ksz_device *dev, int port, int offset, 401 u16 *data) 402 { 403 ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 404 } 405 406 static inline void ksz_pread32(struct ksz_device *dev, int port, int offset, 407 u32 *data) 408 { 409 ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 410 } 411 412 static inline void ksz_pwrite8(struct ksz_device *dev, int port, int offset, 413 u8 data) 414 { 415 ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 416 } 417 418 static inline void ksz_pwrite16(struct ksz_device *dev, int port, int offset, 419 u16 data) 420 { 421 ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), data); 422 } 423 424 static inline void ksz_pwrite32(struct ksz_device *dev, int port, int offset, 425 u32 data) 426 { 427 ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), data); 428 } 429 430 static inline void ksz_prmw8(struct ksz_device *dev, int port, int offset, 431 u8 mask, u8 val) 432 { 433 regmap_update_bits(dev->regmap[0], 434 dev->dev_ops->get_port_addr(port, offset), 435 mask, val); 436 } 437 438 static inline void ksz_regmap_lock(void *__mtx) 439 { 440 struct mutex *mtx = __mtx; 441 mutex_lock(mtx); 442 } 443 444 static inline void ksz_regmap_unlock(void *__mtx) 445 { 446 struct mutex *mtx = __mtx; 447 mutex_unlock(mtx); 448 } 449 450 static inline int is_lan937x(struct ksz_device *dev) 451 { 452 return dev->chip_id == LAN9370_CHIP_ID || 453 dev->chip_id == LAN9371_CHIP_ID || 454 dev->chip_id == LAN9372_CHIP_ID || 455 dev->chip_id == LAN9373_CHIP_ID || 456 dev->chip_id == LAN9374_CHIP_ID; 457 } 458 459 /* STP State Defines */ 460 #define PORT_TX_ENABLE BIT(2) 461 #define PORT_RX_ENABLE BIT(1) 462 #define PORT_LEARN_DISABLE BIT(0) 463 464 /* Switch ID Defines */ 465 #define REG_CHIP_ID0 0x00 466 467 #define SW_FAMILY_ID_M GENMASK(15, 8) 468 #define KSZ87_FAMILY_ID 0x87 469 #define KSZ88_FAMILY_ID 0x88 470 471 #define KSZ8_PORT_STATUS_0 0x08 472 #define KSZ8_PORT_FIBER_MODE BIT(7) 473 474 #define SW_CHIP_ID_M GENMASK(7, 4) 475 #define KSZ87_CHIP_ID_94 0x6 476 #define KSZ87_CHIP_ID_95 0x9 477 #define KSZ88_CHIP_ID_63 0x3 478 479 #define SW_REV_ID_M GENMASK(7, 4) 480 481 /* Driver set switch broadcast storm protection at 10% rate. */ 482 #define BROADCAST_STORM_PROT_RATE 10 483 484 /* 148,800 frames * 67 ms / 100 */ 485 #define BROADCAST_STORM_VALUE 9969 486 487 #define BROADCAST_STORM_RATE_HI 0x07 488 #define BROADCAST_STORM_RATE_LO 0xFF 489 #define BROADCAST_STORM_RATE 0x07FF 490 491 #define MULTICAST_STORM_DISABLE BIT(6) 492 493 #define SW_START 0x01 494 495 /* Used with variable features to indicate capabilities. */ 496 #define GBIT_SUPPORT BIT(0) 497 #define IS_9893 BIT(2) 498 499 /* xMII configuration */ 500 #define P_MII_DUPLEX_M BIT(6) 501 #define P_MII_100MBIT_M BIT(4) 502 503 #define P_GMII_1GBIT_M BIT(6) 504 #define P_RGMII_ID_IG_ENABLE BIT(4) 505 #define P_RGMII_ID_EG_ENABLE BIT(3) 506 #define P_MII_MAC_MODE BIT(2) 507 #define P_MII_SEL_M 0x3 508 509 /* Regmap tables generation */ 510 #define KSZ_SPI_OP_RD 3 511 #define KSZ_SPI_OP_WR 2 512 513 #define swabnot_used(x) 0 514 515 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 516 swab##swp((opcode) << ((regbits) + (regpad))) 517 518 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 519 { \ 520 .name = #width, \ 521 .val_bits = (width), \ 522 .reg_stride = 1, \ 523 .reg_bits = (regbits) + (regalign), \ 524 .pad_bits = (regpad), \ 525 .max_register = BIT(regbits) - 1, \ 526 .cache_type = REGCACHE_NONE, \ 527 .read_flag_mask = \ 528 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 529 regbits, regpad), \ 530 .write_flag_mask = \ 531 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 532 regbits, regpad), \ 533 .lock = ksz_regmap_lock, \ 534 .unlock = ksz_regmap_unlock, \ 535 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 536 .val_format_endian = REGMAP_ENDIAN_BIG \ 537 } 538 539 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 540 static const struct regmap_config ksz##_regmap_config[] = { \ 541 KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 542 KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 543 KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 544 } 545 546 #endif 547