1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/export.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/platform_data/microchip-ksz.h> 14 #include <linux/phy.h> 15 #include <linux/etherdevice.h> 16 #include <linux/if_bridge.h> 17 #include <linux/of_device.h> 18 #include <linux/of_net.h> 19 #include <linux/micrel_phy.h> 20 #include <net/dsa.h> 21 #include <net/switchdev.h> 22 23 #include "ksz_common.h" 24 #include "ksz8.h" 25 #include "ksz9477.h" 26 #include "lan937x.h" 27 28 #define MIB_COUNTER_NUM 0x20 29 30 struct ksz_stats_raw { 31 u64 rx_hi; 32 u64 rx_undersize; 33 u64 rx_fragments; 34 u64 rx_oversize; 35 u64 rx_jabbers; 36 u64 rx_symbol_err; 37 u64 rx_crc_err; 38 u64 rx_align_err; 39 u64 rx_mac_ctrl; 40 u64 rx_pause; 41 u64 rx_bcast; 42 u64 rx_mcast; 43 u64 rx_ucast; 44 u64 rx_64_or_less; 45 u64 rx_65_127; 46 u64 rx_128_255; 47 u64 rx_256_511; 48 u64 rx_512_1023; 49 u64 rx_1024_1522; 50 u64 rx_1523_2000; 51 u64 rx_2001; 52 u64 tx_hi; 53 u64 tx_late_col; 54 u64 tx_pause; 55 u64 tx_bcast; 56 u64 tx_mcast; 57 u64 tx_ucast; 58 u64 tx_deferred; 59 u64 tx_total_col; 60 u64 tx_exc_col; 61 u64 tx_single_col; 62 u64 tx_mult_col; 63 u64 rx_total; 64 u64 tx_total; 65 u64 rx_discards; 66 u64 tx_discards; 67 }; 68 69 static const struct ksz_mib_names ksz88xx_mib_names[] = { 70 { 0x00, "rx" }, 71 { 0x01, "rx_hi" }, 72 { 0x02, "rx_undersize" }, 73 { 0x03, "rx_fragments" }, 74 { 0x04, "rx_oversize" }, 75 { 0x05, "rx_jabbers" }, 76 { 0x06, "rx_symbol_err" }, 77 { 0x07, "rx_crc_err" }, 78 { 0x08, "rx_align_err" }, 79 { 0x09, "rx_mac_ctrl" }, 80 { 0x0a, "rx_pause" }, 81 { 0x0b, "rx_bcast" }, 82 { 0x0c, "rx_mcast" }, 83 { 0x0d, "rx_ucast" }, 84 { 0x0e, "rx_64_or_less" }, 85 { 0x0f, "rx_65_127" }, 86 { 0x10, "rx_128_255" }, 87 { 0x11, "rx_256_511" }, 88 { 0x12, "rx_512_1023" }, 89 { 0x13, "rx_1024_1522" }, 90 { 0x14, "tx" }, 91 { 0x15, "tx_hi" }, 92 { 0x16, "tx_late_col" }, 93 { 0x17, "tx_pause" }, 94 { 0x18, "tx_bcast" }, 95 { 0x19, "tx_mcast" }, 96 { 0x1a, "tx_ucast" }, 97 { 0x1b, "tx_deferred" }, 98 { 0x1c, "tx_total_col" }, 99 { 0x1d, "tx_exc_col" }, 100 { 0x1e, "tx_single_col" }, 101 { 0x1f, "tx_mult_col" }, 102 { 0x100, "rx_discards" }, 103 { 0x101, "tx_discards" }, 104 }; 105 106 static const struct ksz_mib_names ksz9477_mib_names[] = { 107 { 0x00, "rx_hi" }, 108 { 0x01, "rx_undersize" }, 109 { 0x02, "rx_fragments" }, 110 { 0x03, "rx_oversize" }, 111 { 0x04, "rx_jabbers" }, 112 { 0x05, "rx_symbol_err" }, 113 { 0x06, "rx_crc_err" }, 114 { 0x07, "rx_align_err" }, 115 { 0x08, "rx_mac_ctrl" }, 116 { 0x09, "rx_pause" }, 117 { 0x0A, "rx_bcast" }, 118 { 0x0B, "rx_mcast" }, 119 { 0x0C, "rx_ucast" }, 120 { 0x0D, "rx_64_or_less" }, 121 { 0x0E, "rx_65_127" }, 122 { 0x0F, "rx_128_255" }, 123 { 0x10, "rx_256_511" }, 124 { 0x11, "rx_512_1023" }, 125 { 0x12, "rx_1024_1522" }, 126 { 0x13, "rx_1523_2000" }, 127 { 0x14, "rx_2001" }, 128 { 0x15, "tx_hi" }, 129 { 0x16, "tx_late_col" }, 130 { 0x17, "tx_pause" }, 131 { 0x18, "tx_bcast" }, 132 { 0x19, "tx_mcast" }, 133 { 0x1A, "tx_ucast" }, 134 { 0x1B, "tx_deferred" }, 135 { 0x1C, "tx_total_col" }, 136 { 0x1D, "tx_exc_col" }, 137 { 0x1E, "tx_single_col" }, 138 { 0x1F, "tx_mult_col" }, 139 { 0x80, "rx_total" }, 140 { 0x81, "tx_total" }, 141 { 0x82, "rx_discards" }, 142 { 0x83, "tx_discards" }, 143 }; 144 145 static const struct ksz_dev_ops ksz8_dev_ops = { 146 .setup = ksz8_setup, 147 .get_port_addr = ksz8_get_port_addr, 148 .cfg_port_member = ksz8_cfg_port_member, 149 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 150 .port_setup = ksz8_port_setup, 151 .r_phy = ksz8_r_phy, 152 .w_phy = ksz8_w_phy, 153 .r_mib_cnt = ksz8_r_mib_cnt, 154 .r_mib_pkt = ksz8_r_mib_pkt, 155 .freeze_mib = ksz8_freeze_mib, 156 .port_init_cnt = ksz8_port_init_cnt, 157 .fdb_dump = ksz8_fdb_dump, 158 .mdb_add = ksz8_mdb_add, 159 .mdb_del = ksz8_mdb_del, 160 .vlan_filtering = ksz8_port_vlan_filtering, 161 .vlan_add = ksz8_port_vlan_add, 162 .vlan_del = ksz8_port_vlan_del, 163 .mirror_add = ksz8_port_mirror_add, 164 .mirror_del = ksz8_port_mirror_del, 165 .get_caps = ksz8_get_caps, 166 .config_cpu_port = ksz8_config_cpu_port, 167 .enable_stp_addr = ksz8_enable_stp_addr, 168 .reset = ksz8_reset_switch, 169 .init = ksz8_switch_init, 170 .exit = ksz8_switch_exit, 171 }; 172 173 static const struct ksz_dev_ops ksz9477_dev_ops = { 174 .setup = ksz9477_setup, 175 .get_port_addr = ksz9477_get_port_addr, 176 .cfg_port_member = ksz9477_cfg_port_member, 177 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 178 .port_setup = ksz9477_port_setup, 179 .r_phy = ksz9477_r_phy, 180 .w_phy = ksz9477_w_phy, 181 .r_mib_cnt = ksz9477_r_mib_cnt, 182 .r_mib_pkt = ksz9477_r_mib_pkt, 183 .r_mib_stat64 = ksz_r_mib_stats64, 184 .freeze_mib = ksz9477_freeze_mib, 185 .port_init_cnt = ksz9477_port_init_cnt, 186 .vlan_filtering = ksz9477_port_vlan_filtering, 187 .vlan_add = ksz9477_port_vlan_add, 188 .vlan_del = ksz9477_port_vlan_del, 189 .mirror_add = ksz9477_port_mirror_add, 190 .mirror_del = ksz9477_port_mirror_del, 191 .get_caps = ksz9477_get_caps, 192 .fdb_dump = ksz9477_fdb_dump, 193 .fdb_add = ksz9477_fdb_add, 194 .fdb_del = ksz9477_fdb_del, 195 .mdb_add = ksz9477_mdb_add, 196 .mdb_del = ksz9477_mdb_del, 197 .change_mtu = ksz9477_change_mtu, 198 .max_mtu = ksz9477_max_mtu, 199 .config_cpu_port = ksz9477_config_cpu_port, 200 .enable_stp_addr = ksz9477_enable_stp_addr, 201 .reset = ksz9477_reset_switch, 202 .init = ksz9477_switch_init, 203 .exit = ksz9477_switch_exit, 204 }; 205 206 static const struct ksz_dev_ops lan937x_dev_ops = { 207 .setup = lan937x_setup, 208 .get_port_addr = ksz9477_get_port_addr, 209 .cfg_port_member = ksz9477_cfg_port_member, 210 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 211 .port_setup = lan937x_port_setup, 212 .r_phy = lan937x_r_phy, 213 .w_phy = lan937x_w_phy, 214 .r_mib_cnt = ksz9477_r_mib_cnt, 215 .r_mib_pkt = ksz9477_r_mib_pkt, 216 .r_mib_stat64 = ksz_r_mib_stats64, 217 .freeze_mib = ksz9477_freeze_mib, 218 .port_init_cnt = ksz9477_port_init_cnt, 219 .vlan_filtering = ksz9477_port_vlan_filtering, 220 .vlan_add = ksz9477_port_vlan_add, 221 .vlan_del = ksz9477_port_vlan_del, 222 .mirror_add = ksz9477_port_mirror_add, 223 .mirror_del = ksz9477_port_mirror_del, 224 .get_caps = lan937x_phylink_get_caps, 225 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 226 .fdb_dump = ksz9477_fdb_dump, 227 .fdb_add = ksz9477_fdb_add, 228 .fdb_del = ksz9477_fdb_del, 229 .mdb_add = ksz9477_mdb_add, 230 .mdb_del = ksz9477_mdb_del, 231 .change_mtu = lan937x_change_mtu, 232 .max_mtu = ksz9477_max_mtu, 233 .config_cpu_port = lan937x_config_cpu_port, 234 .enable_stp_addr = ksz9477_enable_stp_addr, 235 .reset = lan937x_reset_switch, 236 .init = lan937x_switch_init, 237 .exit = lan937x_switch_exit, 238 }; 239 240 static const u16 ksz8795_regs[] = { 241 [REG_IND_CTRL_0] = 0x6E, 242 [REG_IND_DATA_8] = 0x70, 243 [REG_IND_DATA_CHECK] = 0x72, 244 [REG_IND_DATA_HI] = 0x71, 245 [REG_IND_DATA_LO] = 0x75, 246 [REG_IND_MIB_CHECK] = 0x74, 247 [REG_IND_BYTE] = 0xA0, 248 [P_FORCE_CTRL] = 0x0C, 249 [P_LINK_STATUS] = 0x0E, 250 [P_LOCAL_CTRL] = 0x07, 251 [P_NEG_RESTART_CTRL] = 0x0D, 252 [P_REMOTE_STATUS] = 0x08, 253 [P_SPEED_STATUS] = 0x09, 254 [S_TAIL_TAG_CTRL] = 0x0C, 255 [P_STP_CTRL] = 0x02, 256 [S_START_CTRL] = 0x01, 257 [S_BROADCAST_CTRL] = 0x06, 258 [S_MULTICAST_CTRL] = 0x04, 259 [P_XMII_CTRL_0] = 0x06, 260 [P_XMII_CTRL_1] = 0x56, 261 }; 262 263 static const u32 ksz8795_masks[] = { 264 [PORT_802_1P_REMAPPING] = BIT(7), 265 [SW_TAIL_TAG_ENABLE] = BIT(1), 266 [MIB_COUNTER_OVERFLOW] = BIT(6), 267 [MIB_COUNTER_VALID] = BIT(5), 268 [VLAN_TABLE_FID] = GENMASK(6, 0), 269 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 270 [VLAN_TABLE_VALID] = BIT(12), 271 [STATIC_MAC_TABLE_VALID] = BIT(21), 272 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 273 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 274 [STATIC_MAC_TABLE_OVERRIDE] = BIT(26), 275 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(24, 20), 276 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 277 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(8), 278 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 279 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 280 [DYNAMIC_MAC_TABLE_FID] = GENMASK(26, 20), 281 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 282 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 283 [P_MII_TX_FLOW_CTRL] = BIT(5), 284 [P_MII_RX_FLOW_CTRL] = BIT(5), 285 }; 286 287 static const u8 ksz8795_xmii_ctrl0[] = { 288 [P_MII_100MBIT] = 0, 289 [P_MII_10MBIT] = 1, 290 [P_MII_FULL_DUPLEX] = 0, 291 [P_MII_HALF_DUPLEX] = 1, 292 }; 293 294 static const u8 ksz8795_xmii_ctrl1[] = { 295 [P_RGMII_SEL] = 3, 296 [P_GMII_SEL] = 2, 297 [P_RMII_SEL] = 1, 298 [P_MII_SEL] = 0, 299 [P_GMII_1GBIT] = 1, 300 [P_GMII_NOT_1GBIT] = 0, 301 }; 302 303 static const u8 ksz8795_shifts[] = { 304 [VLAN_TABLE_MEMBERSHIP_S] = 7, 305 [VLAN_TABLE] = 16, 306 [STATIC_MAC_FWD_PORTS] = 16, 307 [STATIC_MAC_FID] = 24, 308 [DYNAMIC_MAC_ENTRIES_H] = 3, 309 [DYNAMIC_MAC_ENTRIES] = 29, 310 [DYNAMIC_MAC_FID] = 16, 311 [DYNAMIC_MAC_TIMESTAMP] = 27, 312 [DYNAMIC_MAC_SRC_PORT] = 24, 313 }; 314 315 static const u16 ksz8863_regs[] = { 316 [REG_IND_CTRL_0] = 0x79, 317 [REG_IND_DATA_8] = 0x7B, 318 [REG_IND_DATA_CHECK] = 0x7B, 319 [REG_IND_DATA_HI] = 0x7C, 320 [REG_IND_DATA_LO] = 0x80, 321 [REG_IND_MIB_CHECK] = 0x80, 322 [P_FORCE_CTRL] = 0x0C, 323 [P_LINK_STATUS] = 0x0E, 324 [P_LOCAL_CTRL] = 0x0C, 325 [P_NEG_RESTART_CTRL] = 0x0D, 326 [P_REMOTE_STATUS] = 0x0E, 327 [P_SPEED_STATUS] = 0x0F, 328 [S_TAIL_TAG_CTRL] = 0x03, 329 [P_STP_CTRL] = 0x02, 330 [S_START_CTRL] = 0x01, 331 [S_BROADCAST_CTRL] = 0x06, 332 [S_MULTICAST_CTRL] = 0x04, 333 }; 334 335 static const u32 ksz8863_masks[] = { 336 [PORT_802_1P_REMAPPING] = BIT(3), 337 [SW_TAIL_TAG_ENABLE] = BIT(6), 338 [MIB_COUNTER_OVERFLOW] = BIT(7), 339 [MIB_COUNTER_VALID] = BIT(6), 340 [VLAN_TABLE_FID] = GENMASK(15, 12), 341 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 342 [VLAN_TABLE_VALID] = BIT(19), 343 [STATIC_MAC_TABLE_VALID] = BIT(19), 344 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 345 [STATIC_MAC_TABLE_FID] = GENMASK(29, 26), 346 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 347 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 348 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(5, 0), 349 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 350 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 351 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 28), 352 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 353 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 354 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 355 }; 356 357 static u8 ksz8863_shifts[] = { 358 [VLAN_TABLE_MEMBERSHIP_S] = 16, 359 [STATIC_MAC_FWD_PORTS] = 16, 360 [STATIC_MAC_FID] = 22, 361 [DYNAMIC_MAC_ENTRIES_H] = 3, 362 [DYNAMIC_MAC_ENTRIES] = 24, 363 [DYNAMIC_MAC_FID] = 16, 364 [DYNAMIC_MAC_TIMESTAMP] = 24, 365 [DYNAMIC_MAC_SRC_PORT] = 20, 366 }; 367 368 static const u16 ksz9477_regs[] = { 369 [P_STP_CTRL] = 0x0B04, 370 [S_START_CTRL] = 0x0300, 371 [S_BROADCAST_CTRL] = 0x0332, 372 [S_MULTICAST_CTRL] = 0x0331, 373 [P_XMII_CTRL_0] = 0x0300, 374 [P_XMII_CTRL_1] = 0x0301, 375 }; 376 377 static const u32 ksz9477_masks[] = { 378 [ALU_STAT_WRITE] = 0, 379 [ALU_STAT_READ] = 1, 380 [P_MII_TX_FLOW_CTRL] = BIT(5), 381 [P_MII_RX_FLOW_CTRL] = BIT(3), 382 }; 383 384 static const u8 ksz9477_shifts[] = { 385 [ALU_STAT_INDEX] = 16, 386 }; 387 388 static const u8 ksz9477_xmii_ctrl0[] = { 389 [P_MII_100MBIT] = 1, 390 [P_MII_10MBIT] = 0, 391 [P_MII_FULL_DUPLEX] = 1, 392 [P_MII_HALF_DUPLEX] = 0, 393 }; 394 395 static const u8 ksz9477_xmii_ctrl1[] = { 396 [P_RGMII_SEL] = 0, 397 [P_RMII_SEL] = 1, 398 [P_GMII_SEL] = 2, 399 [P_MII_SEL] = 3, 400 [P_GMII_1GBIT] = 0, 401 [P_GMII_NOT_1GBIT] = 1, 402 }; 403 404 static const u32 lan937x_masks[] = { 405 [ALU_STAT_WRITE] = 1, 406 [ALU_STAT_READ] = 2, 407 [P_MII_TX_FLOW_CTRL] = BIT(5), 408 [P_MII_RX_FLOW_CTRL] = BIT(3), 409 }; 410 411 static const u8 lan937x_shifts[] = { 412 [ALU_STAT_INDEX] = 8, 413 }; 414 415 static const struct regmap_range ksz8563_valid_regs[] = { 416 regmap_reg_range(0x0000, 0x0003), 417 regmap_reg_range(0x0006, 0x0006), 418 regmap_reg_range(0x000f, 0x001f), 419 regmap_reg_range(0x0100, 0x0100), 420 regmap_reg_range(0x0104, 0x0107), 421 regmap_reg_range(0x010d, 0x010d), 422 regmap_reg_range(0x0110, 0x0113), 423 regmap_reg_range(0x0120, 0x012b), 424 regmap_reg_range(0x0201, 0x0201), 425 regmap_reg_range(0x0210, 0x0213), 426 regmap_reg_range(0x0300, 0x0300), 427 regmap_reg_range(0x0302, 0x031b), 428 regmap_reg_range(0x0320, 0x032b), 429 regmap_reg_range(0x0330, 0x0336), 430 regmap_reg_range(0x0338, 0x033e), 431 regmap_reg_range(0x0340, 0x035f), 432 regmap_reg_range(0x0370, 0x0370), 433 regmap_reg_range(0x0378, 0x0378), 434 regmap_reg_range(0x037c, 0x037d), 435 regmap_reg_range(0x0390, 0x0393), 436 regmap_reg_range(0x0400, 0x040e), 437 regmap_reg_range(0x0410, 0x042f), 438 regmap_reg_range(0x0500, 0x0519), 439 regmap_reg_range(0x0520, 0x054b), 440 regmap_reg_range(0x0550, 0x05b3), 441 442 /* port 1 */ 443 regmap_reg_range(0x1000, 0x1001), 444 regmap_reg_range(0x1004, 0x100b), 445 regmap_reg_range(0x1013, 0x1013), 446 regmap_reg_range(0x1017, 0x1017), 447 regmap_reg_range(0x101b, 0x101b), 448 regmap_reg_range(0x101f, 0x1021), 449 regmap_reg_range(0x1030, 0x1030), 450 regmap_reg_range(0x1100, 0x1111), 451 regmap_reg_range(0x111a, 0x111d), 452 regmap_reg_range(0x1122, 0x1127), 453 regmap_reg_range(0x112a, 0x112b), 454 regmap_reg_range(0x1136, 0x1139), 455 regmap_reg_range(0x113e, 0x113f), 456 regmap_reg_range(0x1400, 0x1401), 457 regmap_reg_range(0x1403, 0x1403), 458 regmap_reg_range(0x1410, 0x1417), 459 regmap_reg_range(0x1420, 0x1423), 460 regmap_reg_range(0x1500, 0x1507), 461 regmap_reg_range(0x1600, 0x1612), 462 regmap_reg_range(0x1800, 0x180f), 463 regmap_reg_range(0x1900, 0x1907), 464 regmap_reg_range(0x1914, 0x191b), 465 regmap_reg_range(0x1a00, 0x1a03), 466 regmap_reg_range(0x1a04, 0x1a08), 467 regmap_reg_range(0x1b00, 0x1b01), 468 regmap_reg_range(0x1b04, 0x1b04), 469 regmap_reg_range(0x1c00, 0x1c05), 470 regmap_reg_range(0x1c08, 0x1c1b), 471 472 /* port 2 */ 473 regmap_reg_range(0x2000, 0x2001), 474 regmap_reg_range(0x2004, 0x200b), 475 regmap_reg_range(0x2013, 0x2013), 476 regmap_reg_range(0x2017, 0x2017), 477 regmap_reg_range(0x201b, 0x201b), 478 regmap_reg_range(0x201f, 0x2021), 479 regmap_reg_range(0x2030, 0x2030), 480 regmap_reg_range(0x2100, 0x2111), 481 regmap_reg_range(0x211a, 0x211d), 482 regmap_reg_range(0x2122, 0x2127), 483 regmap_reg_range(0x212a, 0x212b), 484 regmap_reg_range(0x2136, 0x2139), 485 regmap_reg_range(0x213e, 0x213f), 486 regmap_reg_range(0x2400, 0x2401), 487 regmap_reg_range(0x2403, 0x2403), 488 regmap_reg_range(0x2410, 0x2417), 489 regmap_reg_range(0x2420, 0x2423), 490 regmap_reg_range(0x2500, 0x2507), 491 regmap_reg_range(0x2600, 0x2612), 492 regmap_reg_range(0x2800, 0x280f), 493 regmap_reg_range(0x2900, 0x2907), 494 regmap_reg_range(0x2914, 0x291b), 495 regmap_reg_range(0x2a00, 0x2a03), 496 regmap_reg_range(0x2a04, 0x2a08), 497 regmap_reg_range(0x2b00, 0x2b01), 498 regmap_reg_range(0x2b04, 0x2b04), 499 regmap_reg_range(0x2c00, 0x2c05), 500 regmap_reg_range(0x2c08, 0x2c1b), 501 502 /* port 3 */ 503 regmap_reg_range(0x3000, 0x3001), 504 regmap_reg_range(0x3004, 0x300b), 505 regmap_reg_range(0x3013, 0x3013), 506 regmap_reg_range(0x3017, 0x3017), 507 regmap_reg_range(0x301b, 0x301b), 508 regmap_reg_range(0x301f, 0x3021), 509 regmap_reg_range(0x3030, 0x3030), 510 regmap_reg_range(0x3300, 0x3301), 511 regmap_reg_range(0x3303, 0x3303), 512 regmap_reg_range(0x3400, 0x3401), 513 regmap_reg_range(0x3403, 0x3403), 514 regmap_reg_range(0x3410, 0x3417), 515 regmap_reg_range(0x3420, 0x3423), 516 regmap_reg_range(0x3500, 0x3507), 517 regmap_reg_range(0x3600, 0x3612), 518 regmap_reg_range(0x3800, 0x380f), 519 regmap_reg_range(0x3900, 0x3907), 520 regmap_reg_range(0x3914, 0x391b), 521 regmap_reg_range(0x3a00, 0x3a03), 522 regmap_reg_range(0x3a04, 0x3a08), 523 regmap_reg_range(0x3b00, 0x3b01), 524 regmap_reg_range(0x3b04, 0x3b04), 525 regmap_reg_range(0x3c00, 0x3c05), 526 regmap_reg_range(0x3c08, 0x3c1b), 527 }; 528 529 static const struct regmap_access_table ksz8563_register_set = { 530 .yes_ranges = ksz8563_valid_regs, 531 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), 532 }; 533 534 static const struct regmap_range ksz9477_valid_regs[] = { 535 regmap_reg_range(0x0000, 0x0003), 536 regmap_reg_range(0x0006, 0x0006), 537 regmap_reg_range(0x0010, 0x001f), 538 regmap_reg_range(0x0100, 0x0100), 539 regmap_reg_range(0x0103, 0x0107), 540 regmap_reg_range(0x010d, 0x010d), 541 regmap_reg_range(0x0110, 0x0113), 542 regmap_reg_range(0x0120, 0x012b), 543 regmap_reg_range(0x0201, 0x0201), 544 regmap_reg_range(0x0210, 0x0213), 545 regmap_reg_range(0x0300, 0x0300), 546 regmap_reg_range(0x0302, 0x031b), 547 regmap_reg_range(0x0320, 0x032b), 548 regmap_reg_range(0x0330, 0x0336), 549 regmap_reg_range(0x0338, 0x033e), 550 regmap_reg_range(0x0340, 0x035f), 551 regmap_reg_range(0x0370, 0x0370), 552 regmap_reg_range(0x0378, 0x0378), 553 regmap_reg_range(0x037c, 0x037d), 554 regmap_reg_range(0x0390, 0x0393), 555 regmap_reg_range(0x0400, 0x040e), 556 regmap_reg_range(0x0410, 0x042f), 557 regmap_reg_range(0x0444, 0x044b), 558 regmap_reg_range(0x0450, 0x046f), 559 regmap_reg_range(0x0500, 0x0519), 560 regmap_reg_range(0x0520, 0x054b), 561 regmap_reg_range(0x0550, 0x05b3), 562 regmap_reg_range(0x0604, 0x060b), 563 regmap_reg_range(0x0610, 0x0612), 564 regmap_reg_range(0x0614, 0x062c), 565 regmap_reg_range(0x0640, 0x0645), 566 regmap_reg_range(0x0648, 0x064d), 567 568 /* port 1 */ 569 regmap_reg_range(0x1000, 0x1001), 570 regmap_reg_range(0x1013, 0x1013), 571 regmap_reg_range(0x1017, 0x1017), 572 regmap_reg_range(0x101b, 0x101b), 573 regmap_reg_range(0x101f, 0x1020), 574 regmap_reg_range(0x1030, 0x1030), 575 regmap_reg_range(0x1100, 0x1115), 576 regmap_reg_range(0x111a, 0x111f), 577 regmap_reg_range(0x1122, 0x1127), 578 regmap_reg_range(0x112a, 0x112b), 579 regmap_reg_range(0x1136, 0x1139), 580 regmap_reg_range(0x113e, 0x113f), 581 regmap_reg_range(0x1400, 0x1401), 582 regmap_reg_range(0x1403, 0x1403), 583 regmap_reg_range(0x1410, 0x1417), 584 regmap_reg_range(0x1420, 0x1423), 585 regmap_reg_range(0x1500, 0x1507), 586 regmap_reg_range(0x1600, 0x1613), 587 regmap_reg_range(0x1800, 0x180f), 588 regmap_reg_range(0x1820, 0x1827), 589 regmap_reg_range(0x1830, 0x1837), 590 regmap_reg_range(0x1840, 0x184b), 591 regmap_reg_range(0x1900, 0x1907), 592 regmap_reg_range(0x1914, 0x191b), 593 regmap_reg_range(0x1920, 0x1920), 594 regmap_reg_range(0x1923, 0x1927), 595 regmap_reg_range(0x1a00, 0x1a03), 596 regmap_reg_range(0x1a04, 0x1a07), 597 regmap_reg_range(0x1b00, 0x1b01), 598 regmap_reg_range(0x1b04, 0x1b04), 599 regmap_reg_range(0x1c00, 0x1c05), 600 regmap_reg_range(0x1c08, 0x1c1b), 601 602 /* port 2 */ 603 regmap_reg_range(0x2000, 0x2001), 604 regmap_reg_range(0x2013, 0x2013), 605 regmap_reg_range(0x2017, 0x2017), 606 regmap_reg_range(0x201b, 0x201b), 607 regmap_reg_range(0x201f, 0x2020), 608 regmap_reg_range(0x2030, 0x2030), 609 regmap_reg_range(0x2100, 0x2115), 610 regmap_reg_range(0x211a, 0x211f), 611 regmap_reg_range(0x2122, 0x2127), 612 regmap_reg_range(0x212a, 0x212b), 613 regmap_reg_range(0x2136, 0x2139), 614 regmap_reg_range(0x213e, 0x213f), 615 regmap_reg_range(0x2400, 0x2401), 616 regmap_reg_range(0x2403, 0x2403), 617 regmap_reg_range(0x2410, 0x2417), 618 regmap_reg_range(0x2420, 0x2423), 619 regmap_reg_range(0x2500, 0x2507), 620 regmap_reg_range(0x2600, 0x2613), 621 regmap_reg_range(0x2800, 0x280f), 622 regmap_reg_range(0x2820, 0x2827), 623 regmap_reg_range(0x2830, 0x2837), 624 regmap_reg_range(0x2840, 0x284b), 625 regmap_reg_range(0x2900, 0x2907), 626 regmap_reg_range(0x2914, 0x291b), 627 regmap_reg_range(0x2920, 0x2920), 628 regmap_reg_range(0x2923, 0x2927), 629 regmap_reg_range(0x2a00, 0x2a03), 630 regmap_reg_range(0x2a04, 0x2a07), 631 regmap_reg_range(0x2b00, 0x2b01), 632 regmap_reg_range(0x2b04, 0x2b04), 633 regmap_reg_range(0x2c00, 0x2c05), 634 regmap_reg_range(0x2c08, 0x2c1b), 635 636 /* port 3 */ 637 regmap_reg_range(0x3000, 0x3001), 638 regmap_reg_range(0x3013, 0x3013), 639 regmap_reg_range(0x3017, 0x3017), 640 regmap_reg_range(0x301b, 0x301b), 641 regmap_reg_range(0x301f, 0x3020), 642 regmap_reg_range(0x3030, 0x3030), 643 regmap_reg_range(0x3100, 0x3115), 644 regmap_reg_range(0x311a, 0x311f), 645 regmap_reg_range(0x3122, 0x3127), 646 regmap_reg_range(0x312a, 0x312b), 647 regmap_reg_range(0x3136, 0x3139), 648 regmap_reg_range(0x313e, 0x313f), 649 regmap_reg_range(0x3400, 0x3401), 650 regmap_reg_range(0x3403, 0x3403), 651 regmap_reg_range(0x3410, 0x3417), 652 regmap_reg_range(0x3420, 0x3423), 653 regmap_reg_range(0x3500, 0x3507), 654 regmap_reg_range(0x3600, 0x3613), 655 regmap_reg_range(0x3800, 0x380f), 656 regmap_reg_range(0x3820, 0x3827), 657 regmap_reg_range(0x3830, 0x3837), 658 regmap_reg_range(0x3840, 0x384b), 659 regmap_reg_range(0x3900, 0x3907), 660 regmap_reg_range(0x3914, 0x391b), 661 regmap_reg_range(0x3920, 0x3920), 662 regmap_reg_range(0x3923, 0x3927), 663 regmap_reg_range(0x3a00, 0x3a03), 664 regmap_reg_range(0x3a04, 0x3a07), 665 regmap_reg_range(0x3b00, 0x3b01), 666 regmap_reg_range(0x3b04, 0x3b04), 667 regmap_reg_range(0x3c00, 0x3c05), 668 regmap_reg_range(0x3c08, 0x3c1b), 669 670 /* port 4 */ 671 regmap_reg_range(0x4000, 0x4001), 672 regmap_reg_range(0x4013, 0x4013), 673 regmap_reg_range(0x4017, 0x4017), 674 regmap_reg_range(0x401b, 0x401b), 675 regmap_reg_range(0x401f, 0x4020), 676 regmap_reg_range(0x4030, 0x4030), 677 regmap_reg_range(0x4100, 0x4115), 678 regmap_reg_range(0x411a, 0x411f), 679 regmap_reg_range(0x4122, 0x4127), 680 regmap_reg_range(0x412a, 0x412b), 681 regmap_reg_range(0x4136, 0x4139), 682 regmap_reg_range(0x413e, 0x413f), 683 regmap_reg_range(0x4400, 0x4401), 684 regmap_reg_range(0x4403, 0x4403), 685 regmap_reg_range(0x4410, 0x4417), 686 regmap_reg_range(0x4420, 0x4423), 687 regmap_reg_range(0x4500, 0x4507), 688 regmap_reg_range(0x4600, 0x4613), 689 regmap_reg_range(0x4800, 0x480f), 690 regmap_reg_range(0x4820, 0x4827), 691 regmap_reg_range(0x4830, 0x4837), 692 regmap_reg_range(0x4840, 0x484b), 693 regmap_reg_range(0x4900, 0x4907), 694 regmap_reg_range(0x4914, 0x491b), 695 regmap_reg_range(0x4920, 0x4920), 696 regmap_reg_range(0x4923, 0x4927), 697 regmap_reg_range(0x4a00, 0x4a03), 698 regmap_reg_range(0x4a04, 0x4a07), 699 regmap_reg_range(0x4b00, 0x4b01), 700 regmap_reg_range(0x4b04, 0x4b04), 701 regmap_reg_range(0x4c00, 0x4c05), 702 regmap_reg_range(0x4c08, 0x4c1b), 703 704 /* port 5 */ 705 regmap_reg_range(0x5000, 0x5001), 706 regmap_reg_range(0x5013, 0x5013), 707 regmap_reg_range(0x5017, 0x5017), 708 regmap_reg_range(0x501b, 0x501b), 709 regmap_reg_range(0x501f, 0x5020), 710 regmap_reg_range(0x5030, 0x5030), 711 regmap_reg_range(0x5100, 0x5115), 712 regmap_reg_range(0x511a, 0x511f), 713 regmap_reg_range(0x5122, 0x5127), 714 regmap_reg_range(0x512a, 0x512b), 715 regmap_reg_range(0x5136, 0x5139), 716 regmap_reg_range(0x513e, 0x513f), 717 regmap_reg_range(0x5400, 0x5401), 718 regmap_reg_range(0x5403, 0x5403), 719 regmap_reg_range(0x5410, 0x5417), 720 regmap_reg_range(0x5420, 0x5423), 721 regmap_reg_range(0x5500, 0x5507), 722 regmap_reg_range(0x5600, 0x5613), 723 regmap_reg_range(0x5800, 0x580f), 724 regmap_reg_range(0x5820, 0x5827), 725 regmap_reg_range(0x5830, 0x5837), 726 regmap_reg_range(0x5840, 0x584b), 727 regmap_reg_range(0x5900, 0x5907), 728 regmap_reg_range(0x5914, 0x591b), 729 regmap_reg_range(0x5920, 0x5920), 730 regmap_reg_range(0x5923, 0x5927), 731 regmap_reg_range(0x5a00, 0x5a03), 732 regmap_reg_range(0x5a04, 0x5a07), 733 regmap_reg_range(0x5b00, 0x5b01), 734 regmap_reg_range(0x5b04, 0x5b04), 735 regmap_reg_range(0x5c00, 0x5c05), 736 regmap_reg_range(0x5c08, 0x5c1b), 737 738 /* port 6 */ 739 regmap_reg_range(0x6000, 0x6001), 740 regmap_reg_range(0x6013, 0x6013), 741 regmap_reg_range(0x6017, 0x6017), 742 regmap_reg_range(0x601b, 0x601b), 743 regmap_reg_range(0x601f, 0x6020), 744 regmap_reg_range(0x6030, 0x6030), 745 regmap_reg_range(0x6300, 0x6301), 746 regmap_reg_range(0x6400, 0x6401), 747 regmap_reg_range(0x6403, 0x6403), 748 regmap_reg_range(0x6410, 0x6417), 749 regmap_reg_range(0x6420, 0x6423), 750 regmap_reg_range(0x6500, 0x6507), 751 regmap_reg_range(0x6600, 0x6613), 752 regmap_reg_range(0x6800, 0x680f), 753 regmap_reg_range(0x6820, 0x6827), 754 regmap_reg_range(0x6830, 0x6837), 755 regmap_reg_range(0x6840, 0x684b), 756 regmap_reg_range(0x6900, 0x6907), 757 regmap_reg_range(0x6914, 0x691b), 758 regmap_reg_range(0x6920, 0x6920), 759 regmap_reg_range(0x6923, 0x6927), 760 regmap_reg_range(0x6a00, 0x6a03), 761 regmap_reg_range(0x6a04, 0x6a07), 762 regmap_reg_range(0x6b00, 0x6b01), 763 regmap_reg_range(0x6b04, 0x6b04), 764 regmap_reg_range(0x6c00, 0x6c05), 765 regmap_reg_range(0x6c08, 0x6c1b), 766 767 /* port 7 */ 768 regmap_reg_range(0x7000, 0x7001), 769 regmap_reg_range(0x7013, 0x7013), 770 regmap_reg_range(0x7017, 0x7017), 771 regmap_reg_range(0x701b, 0x701b), 772 regmap_reg_range(0x701f, 0x7020), 773 regmap_reg_range(0x7030, 0x7030), 774 regmap_reg_range(0x7200, 0x7203), 775 regmap_reg_range(0x7206, 0x7207), 776 regmap_reg_range(0x7300, 0x7301), 777 regmap_reg_range(0x7400, 0x7401), 778 regmap_reg_range(0x7403, 0x7403), 779 regmap_reg_range(0x7410, 0x7417), 780 regmap_reg_range(0x7420, 0x7423), 781 regmap_reg_range(0x7500, 0x7507), 782 regmap_reg_range(0x7600, 0x7613), 783 regmap_reg_range(0x7800, 0x780f), 784 regmap_reg_range(0x7820, 0x7827), 785 regmap_reg_range(0x7830, 0x7837), 786 regmap_reg_range(0x7840, 0x784b), 787 regmap_reg_range(0x7900, 0x7907), 788 regmap_reg_range(0x7914, 0x791b), 789 regmap_reg_range(0x7920, 0x7920), 790 regmap_reg_range(0x7923, 0x7927), 791 regmap_reg_range(0x7a00, 0x7a03), 792 regmap_reg_range(0x7a04, 0x7a07), 793 regmap_reg_range(0x7b00, 0x7b01), 794 regmap_reg_range(0x7b04, 0x7b04), 795 regmap_reg_range(0x7c00, 0x7c05), 796 regmap_reg_range(0x7c08, 0x7c1b), 797 }; 798 799 static const struct regmap_access_table ksz9477_register_set = { 800 .yes_ranges = ksz9477_valid_regs, 801 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), 802 }; 803 804 const struct ksz_chip_data ksz_switch_chips[] = { 805 [KSZ8563] = { 806 .chip_id = KSZ8563_CHIP_ID, 807 .dev_name = "KSZ8563", 808 .num_vlans = 4096, 809 .num_alus = 4096, 810 .num_statics = 16, 811 .cpu_ports = 0x07, /* can be configured as cpu port */ 812 .port_cnt = 3, /* total port count */ 813 .ops = &ksz9477_dev_ops, 814 .mib_names = ksz9477_mib_names, 815 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 816 .reg_mib_cnt = MIB_COUNTER_NUM, 817 .regs = ksz9477_regs, 818 .masks = ksz9477_masks, 819 .shifts = ksz9477_shifts, 820 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 821 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 822 .supports_mii = {false, false, true}, 823 .supports_rmii = {false, false, true}, 824 .supports_rgmii = {false, false, true}, 825 .internal_phy = {true, true, false}, 826 .gbit_capable = {false, false, true}, 827 .wr_table = &ksz8563_register_set, 828 .rd_table = &ksz8563_register_set, 829 }, 830 831 [KSZ8795] = { 832 .chip_id = KSZ8795_CHIP_ID, 833 .dev_name = "KSZ8795", 834 .num_vlans = 4096, 835 .num_alus = 0, 836 .num_statics = 8, 837 .cpu_ports = 0x10, /* can be configured as cpu port */ 838 .port_cnt = 5, /* total cpu and user ports */ 839 .ops = &ksz8_dev_ops, 840 .ksz87xx_eee_link_erratum = true, 841 .mib_names = ksz9477_mib_names, 842 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 843 .reg_mib_cnt = MIB_COUNTER_NUM, 844 .regs = ksz8795_regs, 845 .masks = ksz8795_masks, 846 .shifts = ksz8795_shifts, 847 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 848 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 849 .supports_mii = {false, false, false, false, true}, 850 .supports_rmii = {false, false, false, false, true}, 851 .supports_rgmii = {false, false, false, false, true}, 852 .internal_phy = {true, true, true, true, false}, 853 }, 854 855 [KSZ8794] = { 856 /* WARNING 857 * ======= 858 * KSZ8794 is similar to KSZ8795, except the port map 859 * contains a gap between external and CPU ports, the 860 * port map is NOT continuous. The per-port register 861 * map is shifted accordingly too, i.e. registers at 862 * offset 0x40 are NOT used on KSZ8794 and they ARE 863 * used on KSZ8795 for external port 3. 864 * external cpu 865 * KSZ8794 0,1,2 4 866 * KSZ8795 0,1,2,3 4 867 * KSZ8765 0,1,2,3 4 868 * port_cnt is configured as 5, even though it is 4 869 */ 870 .chip_id = KSZ8794_CHIP_ID, 871 .dev_name = "KSZ8794", 872 .num_vlans = 4096, 873 .num_alus = 0, 874 .num_statics = 8, 875 .cpu_ports = 0x10, /* can be configured as cpu port */ 876 .port_cnt = 5, /* total cpu and user ports */ 877 .ops = &ksz8_dev_ops, 878 .ksz87xx_eee_link_erratum = true, 879 .mib_names = ksz9477_mib_names, 880 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 881 .reg_mib_cnt = MIB_COUNTER_NUM, 882 .regs = ksz8795_regs, 883 .masks = ksz8795_masks, 884 .shifts = ksz8795_shifts, 885 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 886 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 887 .supports_mii = {false, false, false, false, true}, 888 .supports_rmii = {false, false, false, false, true}, 889 .supports_rgmii = {false, false, false, false, true}, 890 .internal_phy = {true, true, true, false, false}, 891 }, 892 893 [KSZ8765] = { 894 .chip_id = KSZ8765_CHIP_ID, 895 .dev_name = "KSZ8765", 896 .num_vlans = 4096, 897 .num_alus = 0, 898 .num_statics = 8, 899 .cpu_ports = 0x10, /* can be configured as cpu port */ 900 .port_cnt = 5, /* total cpu and user ports */ 901 .ops = &ksz8_dev_ops, 902 .ksz87xx_eee_link_erratum = true, 903 .mib_names = ksz9477_mib_names, 904 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 905 .reg_mib_cnt = MIB_COUNTER_NUM, 906 .regs = ksz8795_regs, 907 .masks = ksz8795_masks, 908 .shifts = ksz8795_shifts, 909 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 910 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 911 .supports_mii = {false, false, false, false, true}, 912 .supports_rmii = {false, false, false, false, true}, 913 .supports_rgmii = {false, false, false, false, true}, 914 .internal_phy = {true, true, true, true, false}, 915 }, 916 917 [KSZ8830] = { 918 .chip_id = KSZ8830_CHIP_ID, 919 .dev_name = "KSZ8863/KSZ8873", 920 .num_vlans = 16, 921 .num_alus = 0, 922 .num_statics = 8, 923 .cpu_ports = 0x4, /* can be configured as cpu port */ 924 .port_cnt = 3, 925 .ops = &ksz8_dev_ops, 926 .mib_names = ksz88xx_mib_names, 927 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 928 .reg_mib_cnt = MIB_COUNTER_NUM, 929 .regs = ksz8863_regs, 930 .masks = ksz8863_masks, 931 .shifts = ksz8863_shifts, 932 .supports_mii = {false, false, true}, 933 .supports_rmii = {false, false, true}, 934 .internal_phy = {true, true, false}, 935 }, 936 937 [KSZ9477] = { 938 .chip_id = KSZ9477_CHIP_ID, 939 .dev_name = "KSZ9477", 940 .num_vlans = 4096, 941 .num_alus = 4096, 942 .num_statics = 16, 943 .cpu_ports = 0x7F, /* can be configured as cpu port */ 944 .port_cnt = 7, /* total physical port count */ 945 .ops = &ksz9477_dev_ops, 946 .phy_errata_9477 = true, 947 .mib_names = ksz9477_mib_names, 948 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 949 .reg_mib_cnt = MIB_COUNTER_NUM, 950 .regs = ksz9477_regs, 951 .masks = ksz9477_masks, 952 .shifts = ksz9477_shifts, 953 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 954 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 955 .supports_mii = {false, false, false, false, 956 false, true, false}, 957 .supports_rmii = {false, false, false, false, 958 false, true, false}, 959 .supports_rgmii = {false, false, false, false, 960 false, true, false}, 961 .internal_phy = {true, true, true, true, 962 true, false, false}, 963 .gbit_capable = {true, true, true, true, true, true, true}, 964 .wr_table = &ksz9477_register_set, 965 .rd_table = &ksz9477_register_set, 966 }, 967 968 [KSZ9897] = { 969 .chip_id = KSZ9897_CHIP_ID, 970 .dev_name = "KSZ9897", 971 .num_vlans = 4096, 972 .num_alus = 4096, 973 .num_statics = 16, 974 .cpu_ports = 0x7F, /* can be configured as cpu port */ 975 .port_cnt = 7, /* total physical port count */ 976 .ops = &ksz9477_dev_ops, 977 .phy_errata_9477 = true, 978 .mib_names = ksz9477_mib_names, 979 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 980 .reg_mib_cnt = MIB_COUNTER_NUM, 981 .regs = ksz9477_regs, 982 .masks = ksz9477_masks, 983 .shifts = ksz9477_shifts, 984 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 985 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 986 .supports_mii = {false, false, false, false, 987 false, true, true}, 988 .supports_rmii = {false, false, false, false, 989 false, true, true}, 990 .supports_rgmii = {false, false, false, false, 991 false, true, true}, 992 .internal_phy = {true, true, true, true, 993 true, false, false}, 994 .gbit_capable = {true, true, true, true, true, true, true}, 995 }, 996 997 [KSZ9893] = { 998 .chip_id = KSZ9893_CHIP_ID, 999 .dev_name = "KSZ9893", 1000 .num_vlans = 4096, 1001 .num_alus = 4096, 1002 .num_statics = 16, 1003 .cpu_ports = 0x07, /* can be configured as cpu port */ 1004 .port_cnt = 3, /* total port count */ 1005 .ops = &ksz9477_dev_ops, 1006 .mib_names = ksz9477_mib_names, 1007 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1008 .reg_mib_cnt = MIB_COUNTER_NUM, 1009 .regs = ksz9477_regs, 1010 .masks = ksz9477_masks, 1011 .shifts = ksz9477_shifts, 1012 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1013 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1014 .supports_mii = {false, false, true}, 1015 .supports_rmii = {false, false, true}, 1016 .supports_rgmii = {false, false, true}, 1017 .internal_phy = {true, true, false}, 1018 .gbit_capable = {true, true, true}, 1019 }, 1020 1021 [KSZ9567] = { 1022 .chip_id = KSZ9567_CHIP_ID, 1023 .dev_name = "KSZ9567", 1024 .num_vlans = 4096, 1025 .num_alus = 4096, 1026 .num_statics = 16, 1027 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1028 .port_cnt = 7, /* total physical port count */ 1029 .ops = &ksz9477_dev_ops, 1030 .phy_errata_9477 = true, 1031 .mib_names = ksz9477_mib_names, 1032 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1033 .reg_mib_cnt = MIB_COUNTER_NUM, 1034 .regs = ksz9477_regs, 1035 .masks = ksz9477_masks, 1036 .shifts = ksz9477_shifts, 1037 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1038 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1039 .supports_mii = {false, false, false, false, 1040 false, true, true}, 1041 .supports_rmii = {false, false, false, false, 1042 false, true, true}, 1043 .supports_rgmii = {false, false, false, false, 1044 false, true, true}, 1045 .internal_phy = {true, true, true, true, 1046 true, false, false}, 1047 .gbit_capable = {true, true, true, true, true, true, true}, 1048 }, 1049 1050 [LAN9370] = { 1051 .chip_id = LAN9370_CHIP_ID, 1052 .dev_name = "LAN9370", 1053 .num_vlans = 4096, 1054 .num_alus = 1024, 1055 .num_statics = 256, 1056 .cpu_ports = 0x10, /* can be configured as cpu port */ 1057 .port_cnt = 5, /* total physical port count */ 1058 .ops = &lan937x_dev_ops, 1059 .mib_names = ksz9477_mib_names, 1060 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1061 .reg_mib_cnt = MIB_COUNTER_NUM, 1062 .regs = ksz9477_regs, 1063 .masks = lan937x_masks, 1064 .shifts = lan937x_shifts, 1065 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1066 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1067 .supports_mii = {false, false, false, false, true}, 1068 .supports_rmii = {false, false, false, false, true}, 1069 .supports_rgmii = {false, false, false, false, true}, 1070 .internal_phy = {true, true, true, true, false}, 1071 }, 1072 1073 [LAN9371] = { 1074 .chip_id = LAN9371_CHIP_ID, 1075 .dev_name = "LAN9371", 1076 .num_vlans = 4096, 1077 .num_alus = 1024, 1078 .num_statics = 256, 1079 .cpu_ports = 0x30, /* can be configured as cpu port */ 1080 .port_cnt = 6, /* total physical port count */ 1081 .ops = &lan937x_dev_ops, 1082 .mib_names = ksz9477_mib_names, 1083 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1084 .reg_mib_cnt = MIB_COUNTER_NUM, 1085 .regs = ksz9477_regs, 1086 .masks = lan937x_masks, 1087 .shifts = lan937x_shifts, 1088 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1089 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1090 .supports_mii = {false, false, false, false, true, true}, 1091 .supports_rmii = {false, false, false, false, true, true}, 1092 .supports_rgmii = {false, false, false, false, true, true}, 1093 .internal_phy = {true, true, true, true, false, false}, 1094 }, 1095 1096 [LAN9372] = { 1097 .chip_id = LAN9372_CHIP_ID, 1098 .dev_name = "LAN9372", 1099 .num_vlans = 4096, 1100 .num_alus = 1024, 1101 .num_statics = 256, 1102 .cpu_ports = 0x30, /* can be configured as cpu port */ 1103 .port_cnt = 8, /* total physical port count */ 1104 .ops = &lan937x_dev_ops, 1105 .mib_names = ksz9477_mib_names, 1106 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1107 .reg_mib_cnt = MIB_COUNTER_NUM, 1108 .regs = ksz9477_regs, 1109 .masks = lan937x_masks, 1110 .shifts = lan937x_shifts, 1111 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1112 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1113 .supports_mii = {false, false, false, false, 1114 true, true, false, false}, 1115 .supports_rmii = {false, false, false, false, 1116 true, true, false, false}, 1117 .supports_rgmii = {false, false, false, false, 1118 true, true, false, false}, 1119 .internal_phy = {true, true, true, true, 1120 false, false, true, true}, 1121 }, 1122 1123 [LAN9373] = { 1124 .chip_id = LAN9373_CHIP_ID, 1125 .dev_name = "LAN9373", 1126 .num_vlans = 4096, 1127 .num_alus = 1024, 1128 .num_statics = 256, 1129 .cpu_ports = 0x38, /* can be configured as cpu port */ 1130 .port_cnt = 5, /* total physical port count */ 1131 .ops = &lan937x_dev_ops, 1132 .mib_names = ksz9477_mib_names, 1133 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1134 .reg_mib_cnt = MIB_COUNTER_NUM, 1135 .regs = ksz9477_regs, 1136 .masks = lan937x_masks, 1137 .shifts = lan937x_shifts, 1138 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1139 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1140 .supports_mii = {false, false, false, false, 1141 true, true, false, false}, 1142 .supports_rmii = {false, false, false, false, 1143 true, true, false, false}, 1144 .supports_rgmii = {false, false, false, false, 1145 true, true, false, false}, 1146 .internal_phy = {true, true, true, false, 1147 false, false, true, true}, 1148 }, 1149 1150 [LAN9374] = { 1151 .chip_id = LAN9374_CHIP_ID, 1152 .dev_name = "LAN9374", 1153 .num_vlans = 4096, 1154 .num_alus = 1024, 1155 .num_statics = 256, 1156 .cpu_ports = 0x30, /* can be configured as cpu port */ 1157 .port_cnt = 8, /* total physical port count */ 1158 .ops = &lan937x_dev_ops, 1159 .mib_names = ksz9477_mib_names, 1160 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1161 .reg_mib_cnt = MIB_COUNTER_NUM, 1162 .regs = ksz9477_regs, 1163 .masks = lan937x_masks, 1164 .shifts = lan937x_shifts, 1165 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1166 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1167 .supports_mii = {false, false, false, false, 1168 true, true, false, false}, 1169 .supports_rmii = {false, false, false, false, 1170 true, true, false, false}, 1171 .supports_rgmii = {false, false, false, false, 1172 true, true, false, false}, 1173 .internal_phy = {true, true, true, true, 1174 false, false, true, true}, 1175 }, 1176 }; 1177 EXPORT_SYMBOL_GPL(ksz_switch_chips); 1178 1179 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 1180 { 1181 int i; 1182 1183 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 1184 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 1185 1186 if (chip->chip_id == prod_num) 1187 return chip; 1188 } 1189 1190 return NULL; 1191 } 1192 1193 static int ksz_check_device_id(struct ksz_device *dev) 1194 { 1195 const struct ksz_chip_data *dt_chip_data; 1196 1197 dt_chip_data = of_device_get_match_data(dev->dev); 1198 1199 /* Check for Device Tree and Chip ID */ 1200 if (dt_chip_data->chip_id != dev->chip_id) { 1201 dev_err(dev->dev, 1202 "Device tree specifies chip %s but found %s, please fix it!\n", 1203 dt_chip_data->dev_name, dev->info->dev_name); 1204 return -ENODEV; 1205 } 1206 1207 return 0; 1208 } 1209 1210 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 1211 struct phylink_config *config) 1212 { 1213 struct ksz_device *dev = ds->priv; 1214 1215 config->legacy_pre_march2020 = false; 1216 1217 if (dev->info->supports_mii[port]) 1218 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1219 1220 if (dev->info->supports_rmii[port]) 1221 __set_bit(PHY_INTERFACE_MODE_RMII, 1222 config->supported_interfaces); 1223 1224 if (dev->info->supports_rgmii[port]) 1225 phy_interface_set_rgmii(config->supported_interfaces); 1226 1227 if (dev->info->internal_phy[port]) { 1228 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1229 config->supported_interfaces); 1230 /* Compatibility for phylib's default interface type when the 1231 * phy-mode property is absent 1232 */ 1233 __set_bit(PHY_INTERFACE_MODE_GMII, 1234 config->supported_interfaces); 1235 } 1236 1237 if (dev->dev_ops->get_caps) 1238 dev->dev_ops->get_caps(dev, port, config); 1239 } 1240 1241 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 1242 { 1243 struct ethtool_pause_stats *pstats; 1244 struct rtnl_link_stats64 *stats; 1245 struct ksz_stats_raw *raw; 1246 struct ksz_port_mib *mib; 1247 1248 mib = &dev->ports[port].mib; 1249 stats = &mib->stats64; 1250 pstats = &mib->pause_stats; 1251 raw = (struct ksz_stats_raw *)mib->counters; 1252 1253 spin_lock(&mib->stats64_lock); 1254 1255 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1256 raw->rx_pause; 1257 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1258 raw->tx_pause; 1259 1260 /* HW counters are counting bytes + FCS which is not acceptable 1261 * for rtnl_link_stats64 interface 1262 */ 1263 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 1264 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 1265 1266 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 1267 raw->rx_oversize; 1268 1269 stats->rx_crc_errors = raw->rx_crc_err; 1270 stats->rx_frame_errors = raw->rx_align_err; 1271 stats->rx_dropped = raw->rx_discards; 1272 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 1273 stats->rx_frame_errors + stats->rx_dropped; 1274 1275 stats->tx_window_errors = raw->tx_late_col; 1276 stats->tx_fifo_errors = raw->tx_discards; 1277 stats->tx_aborted_errors = raw->tx_exc_col; 1278 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 1279 stats->tx_aborted_errors; 1280 1281 stats->multicast = raw->rx_mcast; 1282 stats->collisions = raw->tx_total_col; 1283 1284 pstats->tx_pause_frames = raw->tx_pause; 1285 pstats->rx_pause_frames = raw->rx_pause; 1286 1287 spin_unlock(&mib->stats64_lock); 1288 } 1289 1290 static void ksz_get_stats64(struct dsa_switch *ds, int port, 1291 struct rtnl_link_stats64 *s) 1292 { 1293 struct ksz_device *dev = ds->priv; 1294 struct ksz_port_mib *mib; 1295 1296 mib = &dev->ports[port].mib; 1297 1298 spin_lock(&mib->stats64_lock); 1299 memcpy(s, &mib->stats64, sizeof(*s)); 1300 spin_unlock(&mib->stats64_lock); 1301 } 1302 1303 static void ksz_get_pause_stats(struct dsa_switch *ds, int port, 1304 struct ethtool_pause_stats *pause_stats) 1305 { 1306 struct ksz_device *dev = ds->priv; 1307 struct ksz_port_mib *mib; 1308 1309 mib = &dev->ports[port].mib; 1310 1311 spin_lock(&mib->stats64_lock); 1312 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 1313 spin_unlock(&mib->stats64_lock); 1314 } 1315 1316 static void ksz_get_strings(struct dsa_switch *ds, int port, 1317 u32 stringset, uint8_t *buf) 1318 { 1319 struct ksz_device *dev = ds->priv; 1320 int i; 1321 1322 if (stringset != ETH_SS_STATS) 1323 return; 1324 1325 for (i = 0; i < dev->info->mib_cnt; i++) { 1326 memcpy(buf + i * ETH_GSTRING_LEN, 1327 dev->info->mib_names[i].string, ETH_GSTRING_LEN); 1328 } 1329 } 1330 1331 static void ksz_update_port_member(struct ksz_device *dev, int port) 1332 { 1333 struct ksz_port *p = &dev->ports[port]; 1334 struct dsa_switch *ds = dev->ds; 1335 u8 port_member = 0, cpu_port; 1336 const struct dsa_port *dp; 1337 int i, j; 1338 1339 if (!dsa_is_user_port(ds, port)) 1340 return; 1341 1342 dp = dsa_to_port(ds, port); 1343 cpu_port = BIT(dsa_upstream_port(ds, port)); 1344 1345 for (i = 0; i < ds->num_ports; i++) { 1346 const struct dsa_port *other_dp = dsa_to_port(ds, i); 1347 struct ksz_port *other_p = &dev->ports[i]; 1348 u8 val = 0; 1349 1350 if (!dsa_is_user_port(ds, i)) 1351 continue; 1352 if (port == i) 1353 continue; 1354 if (!dsa_port_bridge_same(dp, other_dp)) 1355 continue; 1356 if (other_p->stp_state != BR_STATE_FORWARDING) 1357 continue; 1358 1359 if (p->stp_state == BR_STATE_FORWARDING) { 1360 val |= BIT(port); 1361 port_member |= BIT(i); 1362 } 1363 1364 /* Retain port [i]'s relationship to other ports than [port] */ 1365 for (j = 0; j < ds->num_ports; j++) { 1366 const struct dsa_port *third_dp; 1367 struct ksz_port *third_p; 1368 1369 if (j == i) 1370 continue; 1371 if (j == port) 1372 continue; 1373 if (!dsa_is_user_port(ds, j)) 1374 continue; 1375 third_p = &dev->ports[j]; 1376 if (third_p->stp_state != BR_STATE_FORWARDING) 1377 continue; 1378 third_dp = dsa_to_port(ds, j); 1379 if (dsa_port_bridge_same(other_dp, third_dp)) 1380 val |= BIT(j); 1381 } 1382 1383 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 1384 } 1385 1386 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 1387 } 1388 1389 static int ksz_setup(struct dsa_switch *ds) 1390 { 1391 struct ksz_device *dev = ds->priv; 1392 struct ksz_port *p; 1393 const u16 *regs; 1394 int ret; 1395 1396 regs = dev->info->regs; 1397 1398 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 1399 dev->info->num_vlans, GFP_KERNEL); 1400 if (!dev->vlan_cache) 1401 return -ENOMEM; 1402 1403 ret = dev->dev_ops->reset(dev); 1404 if (ret) { 1405 dev_err(ds->dev, "failed to reset switch\n"); 1406 return ret; 1407 } 1408 1409 /* set broadcast storm protection 10% rate */ 1410 regmap_update_bits(dev->regmap[1], regs[S_BROADCAST_CTRL], 1411 BROADCAST_STORM_RATE, 1412 (BROADCAST_STORM_VALUE * 1413 BROADCAST_STORM_PROT_RATE) / 100); 1414 1415 dev->dev_ops->config_cpu_port(ds); 1416 1417 dev->dev_ops->enable_stp_addr(dev); 1418 1419 regmap_update_bits(dev->regmap[0], regs[S_MULTICAST_CTRL], 1420 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 1421 1422 ksz_init_mib_timer(dev); 1423 1424 ds->configure_vlan_while_not_filtering = false; 1425 1426 if (dev->dev_ops->setup) { 1427 ret = dev->dev_ops->setup(ds); 1428 if (ret) 1429 return ret; 1430 } 1431 1432 /* Start with learning disabled on standalone user ports, and enabled 1433 * on the CPU port. In lack of other finer mechanisms, learning on the 1434 * CPU port will avoid flooding bridge local addresses on the network 1435 * in some cases. 1436 */ 1437 p = &dev->ports[dev->cpu_port]; 1438 p->learning = true; 1439 1440 /* start switch */ 1441 regmap_update_bits(dev->regmap[0], regs[S_START_CTRL], 1442 SW_START, SW_START); 1443 1444 return 0; 1445 } 1446 1447 static void port_r_cnt(struct ksz_device *dev, int port) 1448 { 1449 struct ksz_port_mib *mib = &dev->ports[port].mib; 1450 u64 *dropped; 1451 1452 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 1453 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 1454 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 1455 &mib->counters[mib->cnt_ptr]); 1456 ++mib->cnt_ptr; 1457 } 1458 1459 /* last one in storage */ 1460 dropped = &mib->counters[dev->info->mib_cnt]; 1461 1462 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 1463 while (mib->cnt_ptr < dev->info->mib_cnt) { 1464 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 1465 dropped, &mib->counters[mib->cnt_ptr]); 1466 ++mib->cnt_ptr; 1467 } 1468 mib->cnt_ptr = 0; 1469 } 1470 1471 static void ksz_mib_read_work(struct work_struct *work) 1472 { 1473 struct ksz_device *dev = container_of(work, struct ksz_device, 1474 mib_read.work); 1475 struct ksz_port_mib *mib; 1476 struct ksz_port *p; 1477 int i; 1478 1479 for (i = 0; i < dev->info->port_cnt; i++) { 1480 if (dsa_is_unused_port(dev->ds, i)) 1481 continue; 1482 1483 p = &dev->ports[i]; 1484 mib = &p->mib; 1485 mutex_lock(&mib->cnt_mutex); 1486 1487 /* Only read MIB counters when the port is told to do. 1488 * If not, read only dropped counters when link is not up. 1489 */ 1490 if (!p->read) { 1491 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 1492 1493 if (!netif_carrier_ok(dp->slave)) 1494 mib->cnt_ptr = dev->info->reg_mib_cnt; 1495 } 1496 port_r_cnt(dev, i); 1497 p->read = false; 1498 1499 if (dev->dev_ops->r_mib_stat64) 1500 dev->dev_ops->r_mib_stat64(dev, i); 1501 1502 mutex_unlock(&mib->cnt_mutex); 1503 } 1504 1505 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 1506 } 1507 1508 void ksz_init_mib_timer(struct ksz_device *dev) 1509 { 1510 int i; 1511 1512 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 1513 1514 for (i = 0; i < dev->info->port_cnt; i++) { 1515 struct ksz_port_mib *mib = &dev->ports[i].mib; 1516 1517 dev->dev_ops->port_init_cnt(dev, i); 1518 1519 mib->cnt_ptr = 0; 1520 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 1521 } 1522 } 1523 1524 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 1525 { 1526 struct ksz_device *dev = ds->priv; 1527 u16 val = 0xffff; 1528 int ret; 1529 1530 ret = dev->dev_ops->r_phy(dev, addr, reg, &val); 1531 if (ret) 1532 return ret; 1533 1534 return val; 1535 } 1536 1537 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 1538 { 1539 struct ksz_device *dev = ds->priv; 1540 int ret; 1541 1542 ret = dev->dev_ops->w_phy(dev, addr, reg, val); 1543 if (ret) 1544 return ret; 1545 1546 return 0; 1547 } 1548 1549 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 1550 { 1551 struct ksz_device *dev = ds->priv; 1552 1553 if (dev->chip_id == KSZ8830_CHIP_ID) { 1554 /* Silicon Errata Sheet (DS80000830A): 1555 * Port 1 does not work with LinkMD Cable-Testing. 1556 * Port 1 does not respond to received PAUSE control frames. 1557 */ 1558 if (!port) 1559 return MICREL_KSZ8_P1_ERRATA; 1560 } 1561 1562 return 0; 1563 } 1564 1565 static void ksz_mac_link_down(struct dsa_switch *ds, int port, 1566 unsigned int mode, phy_interface_t interface) 1567 { 1568 struct ksz_device *dev = ds->priv; 1569 struct ksz_port *p = &dev->ports[port]; 1570 1571 /* Read all MIB counters when the link is going down. */ 1572 p->read = true; 1573 /* timer started */ 1574 if (dev->mib_read_interval) 1575 schedule_delayed_work(&dev->mib_read, 0); 1576 } 1577 1578 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 1579 { 1580 struct ksz_device *dev = ds->priv; 1581 1582 if (sset != ETH_SS_STATS) 1583 return 0; 1584 1585 return dev->info->mib_cnt; 1586 } 1587 1588 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 1589 uint64_t *buf) 1590 { 1591 const struct dsa_port *dp = dsa_to_port(ds, port); 1592 struct ksz_device *dev = ds->priv; 1593 struct ksz_port_mib *mib; 1594 1595 mib = &dev->ports[port].mib; 1596 mutex_lock(&mib->cnt_mutex); 1597 1598 /* Only read dropped counters if no link. */ 1599 if (!netif_carrier_ok(dp->slave)) 1600 mib->cnt_ptr = dev->info->reg_mib_cnt; 1601 port_r_cnt(dev, port); 1602 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 1603 mutex_unlock(&mib->cnt_mutex); 1604 } 1605 1606 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 1607 struct dsa_bridge bridge, 1608 bool *tx_fwd_offload, 1609 struct netlink_ext_ack *extack) 1610 { 1611 /* port_stp_state_set() will be called after to put the port in 1612 * appropriate state so there is no need to do anything. 1613 */ 1614 1615 return 0; 1616 } 1617 1618 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 1619 struct dsa_bridge bridge) 1620 { 1621 /* port_stp_state_set() will be called after to put the port in 1622 * forwarding state so there is no need to do anything. 1623 */ 1624 } 1625 1626 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 1627 { 1628 struct ksz_device *dev = ds->priv; 1629 1630 dev->dev_ops->flush_dyn_mac_table(dev, port); 1631 } 1632 1633 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 1634 const unsigned char *addr, u16 vid, 1635 struct dsa_db db) 1636 { 1637 struct ksz_device *dev = ds->priv; 1638 1639 if (!dev->dev_ops->fdb_add) 1640 return -EOPNOTSUPP; 1641 1642 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 1643 } 1644 1645 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 1646 const unsigned char *addr, 1647 u16 vid, struct dsa_db db) 1648 { 1649 struct ksz_device *dev = ds->priv; 1650 1651 if (!dev->dev_ops->fdb_del) 1652 return -EOPNOTSUPP; 1653 1654 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 1655 } 1656 1657 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 1658 dsa_fdb_dump_cb_t *cb, void *data) 1659 { 1660 struct ksz_device *dev = ds->priv; 1661 1662 if (!dev->dev_ops->fdb_dump) 1663 return -EOPNOTSUPP; 1664 1665 return dev->dev_ops->fdb_dump(dev, port, cb, data); 1666 } 1667 1668 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 1669 const struct switchdev_obj_port_mdb *mdb, 1670 struct dsa_db db) 1671 { 1672 struct ksz_device *dev = ds->priv; 1673 1674 if (!dev->dev_ops->mdb_add) 1675 return -EOPNOTSUPP; 1676 1677 return dev->dev_ops->mdb_add(dev, port, mdb, db); 1678 } 1679 1680 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 1681 const struct switchdev_obj_port_mdb *mdb, 1682 struct dsa_db db) 1683 { 1684 struct ksz_device *dev = ds->priv; 1685 1686 if (!dev->dev_ops->mdb_del) 1687 return -EOPNOTSUPP; 1688 1689 return dev->dev_ops->mdb_del(dev, port, mdb, db); 1690 } 1691 1692 static int ksz_enable_port(struct dsa_switch *ds, int port, 1693 struct phy_device *phy) 1694 { 1695 struct ksz_device *dev = ds->priv; 1696 1697 if (!dsa_is_user_port(ds, port)) 1698 return 0; 1699 1700 /* setup slave port */ 1701 dev->dev_ops->port_setup(dev, port, false); 1702 1703 /* port_stp_state_set() will be called after to enable the port so 1704 * there is no need to do anything. 1705 */ 1706 1707 return 0; 1708 } 1709 1710 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1711 { 1712 struct ksz_device *dev = ds->priv; 1713 struct ksz_port *p; 1714 const u16 *regs; 1715 u8 data; 1716 1717 regs = dev->info->regs; 1718 1719 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 1720 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 1721 1722 p = &dev->ports[port]; 1723 1724 switch (state) { 1725 case BR_STATE_DISABLED: 1726 data |= PORT_LEARN_DISABLE; 1727 break; 1728 case BR_STATE_LISTENING: 1729 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 1730 break; 1731 case BR_STATE_LEARNING: 1732 data |= PORT_RX_ENABLE; 1733 if (!p->learning) 1734 data |= PORT_LEARN_DISABLE; 1735 break; 1736 case BR_STATE_FORWARDING: 1737 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 1738 if (!p->learning) 1739 data |= PORT_LEARN_DISABLE; 1740 break; 1741 case BR_STATE_BLOCKING: 1742 data |= PORT_LEARN_DISABLE; 1743 break; 1744 default: 1745 dev_err(ds->dev, "invalid STP state: %d\n", state); 1746 return; 1747 } 1748 1749 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 1750 1751 p->stp_state = state; 1752 1753 ksz_update_port_member(dev, port); 1754 } 1755 1756 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1757 struct switchdev_brport_flags flags, 1758 struct netlink_ext_ack *extack) 1759 { 1760 if (flags.mask & ~BR_LEARNING) 1761 return -EINVAL; 1762 1763 return 0; 1764 } 1765 1766 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 1767 struct switchdev_brport_flags flags, 1768 struct netlink_ext_ack *extack) 1769 { 1770 struct ksz_device *dev = ds->priv; 1771 struct ksz_port *p = &dev->ports[port]; 1772 1773 if (flags.mask & BR_LEARNING) { 1774 p->learning = !!(flags.val & BR_LEARNING); 1775 1776 /* Make the change take effect immediately */ 1777 ksz_port_stp_state_set(ds, port, p->stp_state); 1778 } 1779 1780 return 0; 1781 } 1782 1783 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 1784 int port, 1785 enum dsa_tag_protocol mp) 1786 { 1787 struct ksz_device *dev = ds->priv; 1788 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 1789 1790 if (dev->chip_id == KSZ8795_CHIP_ID || 1791 dev->chip_id == KSZ8794_CHIP_ID || 1792 dev->chip_id == KSZ8765_CHIP_ID) 1793 proto = DSA_TAG_PROTO_KSZ8795; 1794 1795 if (dev->chip_id == KSZ8830_CHIP_ID || 1796 dev->chip_id == KSZ8563_CHIP_ID || 1797 dev->chip_id == KSZ9893_CHIP_ID) 1798 proto = DSA_TAG_PROTO_KSZ9893; 1799 1800 if (dev->chip_id == KSZ9477_CHIP_ID || 1801 dev->chip_id == KSZ9897_CHIP_ID || 1802 dev->chip_id == KSZ9567_CHIP_ID) 1803 proto = DSA_TAG_PROTO_KSZ9477; 1804 1805 if (is_lan937x(dev)) 1806 proto = DSA_TAG_PROTO_LAN937X_VALUE; 1807 1808 return proto; 1809 } 1810 1811 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 1812 bool flag, struct netlink_ext_ack *extack) 1813 { 1814 struct ksz_device *dev = ds->priv; 1815 1816 if (!dev->dev_ops->vlan_filtering) 1817 return -EOPNOTSUPP; 1818 1819 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 1820 } 1821 1822 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 1823 const struct switchdev_obj_port_vlan *vlan, 1824 struct netlink_ext_ack *extack) 1825 { 1826 struct ksz_device *dev = ds->priv; 1827 1828 if (!dev->dev_ops->vlan_add) 1829 return -EOPNOTSUPP; 1830 1831 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 1832 } 1833 1834 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 1835 const struct switchdev_obj_port_vlan *vlan) 1836 { 1837 struct ksz_device *dev = ds->priv; 1838 1839 if (!dev->dev_ops->vlan_del) 1840 return -EOPNOTSUPP; 1841 1842 return dev->dev_ops->vlan_del(dev, port, vlan); 1843 } 1844 1845 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 1846 struct dsa_mall_mirror_tc_entry *mirror, 1847 bool ingress, struct netlink_ext_ack *extack) 1848 { 1849 struct ksz_device *dev = ds->priv; 1850 1851 if (!dev->dev_ops->mirror_add) 1852 return -EOPNOTSUPP; 1853 1854 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 1855 } 1856 1857 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 1858 struct dsa_mall_mirror_tc_entry *mirror) 1859 { 1860 struct ksz_device *dev = ds->priv; 1861 1862 if (dev->dev_ops->mirror_del) 1863 dev->dev_ops->mirror_del(dev, port, mirror); 1864 } 1865 1866 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 1867 { 1868 struct ksz_device *dev = ds->priv; 1869 1870 if (!dev->dev_ops->change_mtu) 1871 return -EOPNOTSUPP; 1872 1873 return dev->dev_ops->change_mtu(dev, port, mtu); 1874 } 1875 1876 static int ksz_max_mtu(struct dsa_switch *ds, int port) 1877 { 1878 struct ksz_device *dev = ds->priv; 1879 1880 if (!dev->dev_ops->max_mtu) 1881 return -EOPNOTSUPP; 1882 1883 return dev->dev_ops->max_mtu(dev, port); 1884 } 1885 1886 static void ksz_set_xmii(struct ksz_device *dev, int port, 1887 phy_interface_t interface) 1888 { 1889 const u8 *bitval = dev->info->xmii_ctrl1; 1890 struct ksz_port *p = &dev->ports[port]; 1891 const u16 *regs = dev->info->regs; 1892 u8 data8; 1893 1894 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 1895 1896 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 1897 P_RGMII_ID_EG_ENABLE); 1898 1899 switch (interface) { 1900 case PHY_INTERFACE_MODE_MII: 1901 data8 |= bitval[P_MII_SEL]; 1902 break; 1903 case PHY_INTERFACE_MODE_RMII: 1904 data8 |= bitval[P_RMII_SEL]; 1905 break; 1906 case PHY_INTERFACE_MODE_GMII: 1907 data8 |= bitval[P_GMII_SEL]; 1908 break; 1909 case PHY_INTERFACE_MODE_RGMII: 1910 case PHY_INTERFACE_MODE_RGMII_ID: 1911 case PHY_INTERFACE_MODE_RGMII_TXID: 1912 case PHY_INTERFACE_MODE_RGMII_RXID: 1913 data8 |= bitval[P_RGMII_SEL]; 1914 /* On KSZ9893, disable RGMII in-band status support */ 1915 if (dev->chip_id == KSZ9893_CHIP_ID || 1916 dev->chip_id == KSZ8563_CHIP_ID) 1917 data8 &= ~P_MII_MAC_MODE; 1918 break; 1919 default: 1920 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 1921 phy_modes(interface), port); 1922 return; 1923 } 1924 1925 if (p->rgmii_tx_val) 1926 data8 |= P_RGMII_ID_EG_ENABLE; 1927 1928 if (p->rgmii_rx_val) 1929 data8 |= P_RGMII_ID_IG_ENABLE; 1930 1931 /* Write the updated value */ 1932 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 1933 } 1934 1935 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 1936 { 1937 const u8 *bitval = dev->info->xmii_ctrl1; 1938 const u16 *regs = dev->info->regs; 1939 phy_interface_t interface; 1940 u8 data8; 1941 u8 val; 1942 1943 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 1944 1945 val = FIELD_GET(P_MII_SEL_M, data8); 1946 1947 if (val == bitval[P_MII_SEL]) { 1948 if (gbit) 1949 interface = PHY_INTERFACE_MODE_GMII; 1950 else 1951 interface = PHY_INTERFACE_MODE_MII; 1952 } else if (val == bitval[P_RMII_SEL]) { 1953 interface = PHY_INTERFACE_MODE_RGMII; 1954 } else { 1955 interface = PHY_INTERFACE_MODE_RGMII; 1956 if (data8 & P_RGMII_ID_EG_ENABLE) 1957 interface = PHY_INTERFACE_MODE_RGMII_TXID; 1958 if (data8 & P_RGMII_ID_IG_ENABLE) { 1959 interface = PHY_INTERFACE_MODE_RGMII_RXID; 1960 if (data8 & P_RGMII_ID_EG_ENABLE) 1961 interface = PHY_INTERFACE_MODE_RGMII_ID; 1962 } 1963 } 1964 1965 return interface; 1966 } 1967 1968 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port, 1969 unsigned int mode, 1970 const struct phylink_link_state *state) 1971 { 1972 struct ksz_device *dev = ds->priv; 1973 1974 if (ksz_is_ksz88x3(dev)) 1975 return; 1976 1977 /* Internal PHYs */ 1978 if (dev->info->internal_phy[port]) 1979 return; 1980 1981 if (phylink_autoneg_inband(mode)) { 1982 dev_err(dev->dev, "In-band AN not supported!\n"); 1983 return; 1984 } 1985 1986 ksz_set_xmii(dev, port, state->interface); 1987 1988 if (dev->dev_ops->phylink_mac_config) 1989 dev->dev_ops->phylink_mac_config(dev, port, mode, state); 1990 1991 if (dev->dev_ops->setup_rgmii_delay) 1992 dev->dev_ops->setup_rgmii_delay(dev, port); 1993 } 1994 1995 bool ksz_get_gbit(struct ksz_device *dev, int port) 1996 { 1997 const u8 *bitval = dev->info->xmii_ctrl1; 1998 const u16 *regs = dev->info->regs; 1999 bool gbit = false; 2000 u8 data8; 2001 bool val; 2002 2003 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2004 2005 val = FIELD_GET(P_GMII_1GBIT_M, data8); 2006 2007 if (val == bitval[P_GMII_1GBIT]) 2008 gbit = true; 2009 2010 return gbit; 2011 } 2012 2013 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) 2014 { 2015 const u8 *bitval = dev->info->xmii_ctrl1; 2016 const u16 *regs = dev->info->regs; 2017 u8 data8; 2018 2019 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2020 2021 data8 &= ~P_GMII_1GBIT_M; 2022 2023 if (gbit) 2024 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 2025 else 2026 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 2027 2028 /* Write the updated value */ 2029 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 2030 } 2031 2032 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) 2033 { 2034 const u8 *bitval = dev->info->xmii_ctrl0; 2035 const u16 *regs = dev->info->regs; 2036 u8 data8; 2037 2038 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 2039 2040 data8 &= ~P_MII_100MBIT_M; 2041 2042 if (speed == SPEED_100) 2043 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 2044 else 2045 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 2046 2047 /* Write the updated value */ 2048 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 2049 } 2050 2051 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) 2052 { 2053 if (speed == SPEED_1000) 2054 ksz_set_gbit(dev, port, true); 2055 else 2056 ksz_set_gbit(dev, port, false); 2057 2058 if (speed == SPEED_100 || speed == SPEED_10) 2059 ksz_set_100_10mbit(dev, port, speed); 2060 } 2061 2062 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 2063 bool tx_pause, bool rx_pause) 2064 { 2065 const u8 *bitval = dev->info->xmii_ctrl0; 2066 const u32 *masks = dev->info->masks; 2067 const u16 *regs = dev->info->regs; 2068 u8 mask; 2069 u8 val; 2070 2071 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 2072 masks[P_MII_RX_FLOW_CTRL]; 2073 2074 if (duplex == DUPLEX_FULL) 2075 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 2076 else 2077 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 2078 2079 if (tx_pause) 2080 val |= masks[P_MII_TX_FLOW_CTRL]; 2081 2082 if (rx_pause) 2083 val |= masks[P_MII_RX_FLOW_CTRL]; 2084 2085 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 2086 } 2087 2088 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port, 2089 unsigned int mode, 2090 phy_interface_t interface, 2091 struct phy_device *phydev, int speed, 2092 int duplex, bool tx_pause, bool rx_pause) 2093 { 2094 struct ksz_device *dev = ds->priv; 2095 struct ksz_port *p; 2096 2097 p = &dev->ports[port]; 2098 2099 /* Internal PHYs */ 2100 if (dev->info->internal_phy[port]) 2101 return; 2102 2103 p->phydev.speed = speed; 2104 2105 ksz_port_set_xmii_speed(dev, port, speed); 2106 2107 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 2108 2109 if (dev->dev_ops->phylink_mac_link_up) 2110 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface, 2111 phydev, speed, duplex, 2112 tx_pause, rx_pause); 2113 } 2114 2115 static int ksz_switch_detect(struct ksz_device *dev) 2116 { 2117 u8 id1, id2, id4; 2118 u16 id16; 2119 u32 id32; 2120 int ret; 2121 2122 /* read chip id */ 2123 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 2124 if (ret) 2125 return ret; 2126 2127 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 2128 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 2129 2130 switch (id1) { 2131 case KSZ87_FAMILY_ID: 2132 if (id2 == KSZ87_CHIP_ID_95) { 2133 u8 val; 2134 2135 dev->chip_id = KSZ8795_CHIP_ID; 2136 2137 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 2138 if (val & KSZ8_PORT_FIBER_MODE) 2139 dev->chip_id = KSZ8765_CHIP_ID; 2140 } else if (id2 == KSZ87_CHIP_ID_94) { 2141 dev->chip_id = KSZ8794_CHIP_ID; 2142 } else { 2143 return -ENODEV; 2144 } 2145 break; 2146 case KSZ88_FAMILY_ID: 2147 if (id2 == KSZ88_CHIP_ID_63) 2148 dev->chip_id = KSZ8830_CHIP_ID; 2149 else 2150 return -ENODEV; 2151 break; 2152 default: 2153 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 2154 if (ret) 2155 return ret; 2156 2157 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 2158 id32 &= ~0xFF; 2159 2160 switch (id32) { 2161 case KSZ9477_CHIP_ID: 2162 case KSZ9897_CHIP_ID: 2163 case KSZ9567_CHIP_ID: 2164 case LAN9370_CHIP_ID: 2165 case LAN9371_CHIP_ID: 2166 case LAN9372_CHIP_ID: 2167 case LAN9373_CHIP_ID: 2168 case LAN9374_CHIP_ID: 2169 dev->chip_id = id32; 2170 break; 2171 case KSZ9893_CHIP_ID: 2172 ret = ksz_read8(dev, REG_CHIP_ID4, 2173 &id4); 2174 if (ret) 2175 return ret; 2176 2177 if (id4 == SKU_ID_KSZ8563) 2178 dev->chip_id = KSZ8563_CHIP_ID; 2179 else 2180 dev->chip_id = KSZ9893_CHIP_ID; 2181 2182 break; 2183 default: 2184 dev_err(dev->dev, 2185 "unsupported switch detected %x)\n", id32); 2186 return -ENODEV; 2187 } 2188 } 2189 return 0; 2190 } 2191 2192 static const struct dsa_switch_ops ksz_switch_ops = { 2193 .get_tag_protocol = ksz_get_tag_protocol, 2194 .get_phy_flags = ksz_get_phy_flags, 2195 .setup = ksz_setup, 2196 .phy_read = ksz_phy_read16, 2197 .phy_write = ksz_phy_write16, 2198 .phylink_get_caps = ksz_phylink_get_caps, 2199 .phylink_mac_config = ksz_phylink_mac_config, 2200 .phylink_mac_link_up = ksz_phylink_mac_link_up, 2201 .phylink_mac_link_down = ksz_mac_link_down, 2202 .port_enable = ksz_enable_port, 2203 .get_strings = ksz_get_strings, 2204 .get_ethtool_stats = ksz_get_ethtool_stats, 2205 .get_sset_count = ksz_sset_count, 2206 .port_bridge_join = ksz_port_bridge_join, 2207 .port_bridge_leave = ksz_port_bridge_leave, 2208 .port_stp_state_set = ksz_port_stp_state_set, 2209 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 2210 .port_bridge_flags = ksz_port_bridge_flags, 2211 .port_fast_age = ksz_port_fast_age, 2212 .port_vlan_filtering = ksz_port_vlan_filtering, 2213 .port_vlan_add = ksz_port_vlan_add, 2214 .port_vlan_del = ksz_port_vlan_del, 2215 .port_fdb_dump = ksz_port_fdb_dump, 2216 .port_fdb_add = ksz_port_fdb_add, 2217 .port_fdb_del = ksz_port_fdb_del, 2218 .port_mdb_add = ksz_port_mdb_add, 2219 .port_mdb_del = ksz_port_mdb_del, 2220 .port_mirror_add = ksz_port_mirror_add, 2221 .port_mirror_del = ksz_port_mirror_del, 2222 .get_stats64 = ksz_get_stats64, 2223 .get_pause_stats = ksz_get_pause_stats, 2224 .port_change_mtu = ksz_change_mtu, 2225 .port_max_mtu = ksz_max_mtu, 2226 }; 2227 2228 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 2229 { 2230 struct dsa_switch *ds; 2231 struct ksz_device *swdev; 2232 2233 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 2234 if (!ds) 2235 return NULL; 2236 2237 ds->dev = base; 2238 ds->num_ports = DSA_MAX_PORTS; 2239 ds->ops = &ksz_switch_ops; 2240 2241 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 2242 if (!swdev) 2243 return NULL; 2244 2245 ds->priv = swdev; 2246 swdev->dev = base; 2247 2248 swdev->ds = ds; 2249 swdev->priv = priv; 2250 2251 return swdev; 2252 } 2253 EXPORT_SYMBOL(ksz_switch_alloc); 2254 2255 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 2256 struct device_node *port_dn) 2257 { 2258 phy_interface_t phy_mode = dev->ports[port_num].interface; 2259 int rx_delay = -1, tx_delay = -1; 2260 2261 if (!phy_interface_mode_is_rgmii(phy_mode)) 2262 return; 2263 2264 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 2265 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 2266 2267 if (rx_delay == -1 && tx_delay == -1) { 2268 dev_warn(dev->dev, 2269 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 2270 "please update device tree to specify \"rx-internal-delay-ps\" and " 2271 "\"tx-internal-delay-ps\"", 2272 port_num); 2273 2274 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 2275 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 2276 rx_delay = 2000; 2277 2278 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 2279 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 2280 tx_delay = 2000; 2281 } 2282 2283 if (rx_delay < 0) 2284 rx_delay = 0; 2285 if (tx_delay < 0) 2286 tx_delay = 0; 2287 2288 dev->ports[port_num].rgmii_rx_val = rx_delay; 2289 dev->ports[port_num].rgmii_tx_val = tx_delay; 2290 } 2291 2292 int ksz_switch_register(struct ksz_device *dev) 2293 { 2294 const struct ksz_chip_data *info; 2295 struct device_node *port, *ports; 2296 phy_interface_t interface; 2297 unsigned int port_num; 2298 int ret; 2299 int i; 2300 2301 if (dev->pdata) 2302 dev->chip_id = dev->pdata->chip_id; 2303 2304 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 2305 GPIOD_OUT_LOW); 2306 if (IS_ERR(dev->reset_gpio)) 2307 return PTR_ERR(dev->reset_gpio); 2308 2309 if (dev->reset_gpio) { 2310 gpiod_set_value_cansleep(dev->reset_gpio, 1); 2311 usleep_range(10000, 12000); 2312 gpiod_set_value_cansleep(dev->reset_gpio, 0); 2313 msleep(100); 2314 } 2315 2316 mutex_init(&dev->dev_mutex); 2317 mutex_init(&dev->regmap_mutex); 2318 mutex_init(&dev->alu_mutex); 2319 mutex_init(&dev->vlan_mutex); 2320 2321 ret = ksz_switch_detect(dev); 2322 if (ret) 2323 return ret; 2324 2325 info = ksz_lookup_info(dev->chip_id); 2326 if (!info) 2327 return -ENODEV; 2328 2329 /* Update the compatible info with the probed one */ 2330 dev->info = info; 2331 2332 dev_info(dev->dev, "found switch: %s, rev %i\n", 2333 dev->info->dev_name, dev->chip_rev); 2334 2335 ret = ksz_check_device_id(dev); 2336 if (ret) 2337 return ret; 2338 2339 dev->dev_ops = dev->info->ops; 2340 2341 ret = dev->dev_ops->init(dev); 2342 if (ret) 2343 return ret; 2344 2345 dev->ports = devm_kzalloc(dev->dev, 2346 dev->info->port_cnt * sizeof(struct ksz_port), 2347 GFP_KERNEL); 2348 if (!dev->ports) 2349 return -ENOMEM; 2350 2351 for (i = 0; i < dev->info->port_cnt; i++) { 2352 spin_lock_init(&dev->ports[i].mib.stats64_lock); 2353 mutex_init(&dev->ports[i].mib.cnt_mutex); 2354 dev->ports[i].mib.counters = 2355 devm_kzalloc(dev->dev, 2356 sizeof(u64) * (dev->info->mib_cnt + 1), 2357 GFP_KERNEL); 2358 if (!dev->ports[i].mib.counters) 2359 return -ENOMEM; 2360 } 2361 2362 /* set the real number of ports */ 2363 dev->ds->num_ports = dev->info->port_cnt; 2364 2365 /* Host port interface will be self detected, or specifically set in 2366 * device tree. 2367 */ 2368 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 2369 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 2370 if (dev->dev->of_node) { 2371 ret = of_get_phy_mode(dev->dev->of_node, &interface); 2372 if (ret == 0) 2373 dev->compat_interface = interface; 2374 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 2375 if (!ports) 2376 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 2377 if (ports) { 2378 for_each_available_child_of_node(ports, port) { 2379 if (of_property_read_u32(port, "reg", 2380 &port_num)) 2381 continue; 2382 if (!(dev->port_mask & BIT(port_num))) { 2383 of_node_put(port); 2384 of_node_put(ports); 2385 return -EINVAL; 2386 } 2387 of_get_phy_mode(port, 2388 &dev->ports[port_num].interface); 2389 2390 ksz_parse_rgmii_delay(dev, port_num, port); 2391 } 2392 of_node_put(ports); 2393 } 2394 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 2395 "microchip,synclko-125"); 2396 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 2397 "microchip,synclko-disable"); 2398 if (dev->synclko_125 && dev->synclko_disable) { 2399 dev_err(dev->dev, "inconsistent synclko settings\n"); 2400 return -EINVAL; 2401 } 2402 } 2403 2404 ret = dsa_register_switch(dev->ds); 2405 if (ret) { 2406 dev->dev_ops->exit(dev); 2407 return ret; 2408 } 2409 2410 /* Read MIB counters every 30 seconds to avoid overflow. */ 2411 dev->mib_read_interval = msecs_to_jiffies(5000); 2412 2413 /* Start the MIB timer. */ 2414 schedule_delayed_work(&dev->mib_read, 0); 2415 2416 return ret; 2417 } 2418 EXPORT_SYMBOL(ksz_switch_register); 2419 2420 void ksz_switch_remove(struct ksz_device *dev) 2421 { 2422 /* timer started */ 2423 if (dev->mib_read_interval) { 2424 dev->mib_read_interval = 0; 2425 cancel_delayed_work_sync(&dev->mib_read); 2426 } 2427 2428 dev->dev_ops->exit(dev); 2429 dsa_unregister_switch(dev->ds); 2430 2431 if (dev->reset_gpio) 2432 gpiod_set_value_cansleep(dev->reset_gpio, 1); 2433 2434 } 2435 EXPORT_SYMBOL(ksz_switch_remove); 2436 2437 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 2438 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 2439 MODULE_LICENSE("GPL"); 2440