1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/export.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/platform_data/microchip-ksz.h> 14 #include <linux/phy.h> 15 #include <linux/etherdevice.h> 16 #include <linux/if_bridge.h> 17 #include <linux/of_device.h> 18 #include <linux/of_net.h> 19 #include <linux/micrel_phy.h> 20 #include <net/dsa.h> 21 #include <net/switchdev.h> 22 23 #include "ksz_common.h" 24 #include "ksz8.h" 25 #include "ksz9477.h" 26 27 #define MIB_COUNTER_NUM 0x20 28 29 struct ksz_stats_raw { 30 u64 rx_hi; 31 u64 rx_undersize; 32 u64 rx_fragments; 33 u64 rx_oversize; 34 u64 rx_jabbers; 35 u64 rx_symbol_err; 36 u64 rx_crc_err; 37 u64 rx_align_err; 38 u64 rx_mac_ctrl; 39 u64 rx_pause; 40 u64 rx_bcast; 41 u64 rx_mcast; 42 u64 rx_ucast; 43 u64 rx_64_or_less; 44 u64 rx_65_127; 45 u64 rx_128_255; 46 u64 rx_256_511; 47 u64 rx_512_1023; 48 u64 rx_1024_1522; 49 u64 rx_1523_2000; 50 u64 rx_2001; 51 u64 tx_hi; 52 u64 tx_late_col; 53 u64 tx_pause; 54 u64 tx_bcast; 55 u64 tx_mcast; 56 u64 tx_ucast; 57 u64 tx_deferred; 58 u64 tx_total_col; 59 u64 tx_exc_col; 60 u64 tx_single_col; 61 u64 tx_mult_col; 62 u64 rx_total; 63 u64 tx_total; 64 u64 rx_discards; 65 u64 tx_discards; 66 }; 67 68 static const struct ksz_mib_names ksz88xx_mib_names[] = { 69 { 0x00, "rx" }, 70 { 0x01, "rx_hi" }, 71 { 0x02, "rx_undersize" }, 72 { 0x03, "rx_fragments" }, 73 { 0x04, "rx_oversize" }, 74 { 0x05, "rx_jabbers" }, 75 { 0x06, "rx_symbol_err" }, 76 { 0x07, "rx_crc_err" }, 77 { 0x08, "rx_align_err" }, 78 { 0x09, "rx_mac_ctrl" }, 79 { 0x0a, "rx_pause" }, 80 { 0x0b, "rx_bcast" }, 81 { 0x0c, "rx_mcast" }, 82 { 0x0d, "rx_ucast" }, 83 { 0x0e, "rx_64_or_less" }, 84 { 0x0f, "rx_65_127" }, 85 { 0x10, "rx_128_255" }, 86 { 0x11, "rx_256_511" }, 87 { 0x12, "rx_512_1023" }, 88 { 0x13, "rx_1024_1522" }, 89 { 0x14, "tx" }, 90 { 0x15, "tx_hi" }, 91 { 0x16, "tx_late_col" }, 92 { 0x17, "tx_pause" }, 93 { 0x18, "tx_bcast" }, 94 { 0x19, "tx_mcast" }, 95 { 0x1a, "tx_ucast" }, 96 { 0x1b, "tx_deferred" }, 97 { 0x1c, "tx_total_col" }, 98 { 0x1d, "tx_exc_col" }, 99 { 0x1e, "tx_single_col" }, 100 { 0x1f, "tx_mult_col" }, 101 { 0x100, "rx_discards" }, 102 { 0x101, "tx_discards" }, 103 }; 104 105 static const struct ksz_mib_names ksz9477_mib_names[] = { 106 { 0x00, "rx_hi" }, 107 { 0x01, "rx_undersize" }, 108 { 0x02, "rx_fragments" }, 109 { 0x03, "rx_oversize" }, 110 { 0x04, "rx_jabbers" }, 111 { 0x05, "rx_symbol_err" }, 112 { 0x06, "rx_crc_err" }, 113 { 0x07, "rx_align_err" }, 114 { 0x08, "rx_mac_ctrl" }, 115 { 0x09, "rx_pause" }, 116 { 0x0A, "rx_bcast" }, 117 { 0x0B, "rx_mcast" }, 118 { 0x0C, "rx_ucast" }, 119 { 0x0D, "rx_64_or_less" }, 120 { 0x0E, "rx_65_127" }, 121 { 0x0F, "rx_128_255" }, 122 { 0x10, "rx_256_511" }, 123 { 0x11, "rx_512_1023" }, 124 { 0x12, "rx_1024_1522" }, 125 { 0x13, "rx_1523_2000" }, 126 { 0x14, "rx_2001" }, 127 { 0x15, "tx_hi" }, 128 { 0x16, "tx_late_col" }, 129 { 0x17, "tx_pause" }, 130 { 0x18, "tx_bcast" }, 131 { 0x19, "tx_mcast" }, 132 { 0x1A, "tx_ucast" }, 133 { 0x1B, "tx_deferred" }, 134 { 0x1C, "tx_total_col" }, 135 { 0x1D, "tx_exc_col" }, 136 { 0x1E, "tx_single_col" }, 137 { 0x1F, "tx_mult_col" }, 138 { 0x80, "rx_total" }, 139 { 0x81, "tx_total" }, 140 { 0x82, "rx_discards" }, 141 { 0x83, "tx_discards" }, 142 }; 143 144 static const struct ksz_dev_ops ksz8_dev_ops = { 145 .setup = ksz8_setup, 146 .get_port_addr = ksz8_get_port_addr, 147 .cfg_port_member = ksz8_cfg_port_member, 148 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 149 .port_setup = ksz8_port_setup, 150 .r_phy = ksz8_r_phy, 151 .w_phy = ksz8_w_phy, 152 .r_mib_pkt = ksz8_r_mib_pkt, 153 .freeze_mib = ksz8_freeze_mib, 154 .port_init_cnt = ksz8_port_init_cnt, 155 .fdb_dump = ksz8_fdb_dump, 156 .mdb_add = ksz8_mdb_add, 157 .mdb_del = ksz8_mdb_del, 158 .vlan_filtering = ksz8_port_vlan_filtering, 159 .vlan_add = ksz8_port_vlan_add, 160 .vlan_del = ksz8_port_vlan_del, 161 .mirror_add = ksz8_port_mirror_add, 162 .mirror_del = ksz8_port_mirror_del, 163 .get_caps = ksz8_get_caps, 164 .config_cpu_port = ksz8_config_cpu_port, 165 .enable_stp_addr = ksz8_enable_stp_addr, 166 .reset = ksz8_reset_switch, 167 .init = ksz8_switch_init, 168 .exit = ksz8_switch_exit, 169 }; 170 171 static const struct ksz_dev_ops ksz9477_dev_ops = { 172 .setup = ksz9477_setup, 173 .get_port_addr = ksz9477_get_port_addr, 174 .cfg_port_member = ksz9477_cfg_port_member, 175 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 176 .port_setup = ksz9477_port_setup, 177 .r_phy = ksz9477_r_phy, 178 .w_phy = ksz9477_w_phy, 179 .r_mib_cnt = ksz9477_r_mib_cnt, 180 .r_mib_pkt = ksz9477_r_mib_pkt, 181 .r_mib_stat64 = ksz_r_mib_stats64, 182 .freeze_mib = ksz9477_freeze_mib, 183 .port_init_cnt = ksz9477_port_init_cnt, 184 .vlan_filtering = ksz9477_port_vlan_filtering, 185 .vlan_add = ksz9477_port_vlan_add, 186 .vlan_del = ksz9477_port_vlan_del, 187 .mirror_add = ksz9477_port_mirror_add, 188 .mirror_del = ksz9477_port_mirror_del, 189 .get_caps = ksz9477_get_caps, 190 .fdb_dump = ksz9477_fdb_dump, 191 .fdb_add = ksz9477_fdb_add, 192 .fdb_del = ksz9477_fdb_del, 193 .mdb_add = ksz9477_mdb_add, 194 .mdb_del = ksz9477_mdb_del, 195 .change_mtu = ksz9477_change_mtu, 196 .max_mtu = ksz9477_max_mtu, 197 .config_cpu_port = ksz9477_config_cpu_port, 198 .enable_stp_addr = ksz9477_enable_stp_addr, 199 .reset = ksz9477_reset_switch, 200 .init = ksz9477_switch_init, 201 .exit = ksz9477_switch_exit, 202 }; 203 204 const struct ksz_chip_data ksz_switch_chips[] = { 205 [KSZ8795] = { 206 .chip_id = KSZ8795_CHIP_ID, 207 .dev_name = "KSZ8795", 208 .num_vlans = 4096, 209 .num_alus = 0, 210 .num_statics = 8, 211 .cpu_ports = 0x10, /* can be configured as cpu port */ 212 .port_cnt = 5, /* total cpu and user ports */ 213 .ops = &ksz8_dev_ops, 214 .ksz87xx_eee_link_erratum = true, 215 .mib_names = ksz9477_mib_names, 216 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 217 .reg_mib_cnt = MIB_COUNTER_NUM, 218 .stp_ctrl_reg = 0x02, 219 .broadcast_ctrl_reg = 0x06, 220 .multicast_ctrl_reg = 0x04, 221 .start_ctrl_reg = 0x01, 222 .supports_mii = {false, false, false, false, true}, 223 .supports_rmii = {false, false, false, false, true}, 224 .supports_rgmii = {false, false, false, false, true}, 225 .internal_phy = {true, true, true, true, false}, 226 }, 227 228 [KSZ8794] = { 229 /* WARNING 230 * ======= 231 * KSZ8794 is similar to KSZ8795, except the port map 232 * contains a gap between external and CPU ports, the 233 * port map is NOT continuous. The per-port register 234 * map is shifted accordingly too, i.e. registers at 235 * offset 0x40 are NOT used on KSZ8794 and they ARE 236 * used on KSZ8795 for external port 3. 237 * external cpu 238 * KSZ8794 0,1,2 4 239 * KSZ8795 0,1,2,3 4 240 * KSZ8765 0,1,2,3 4 241 * port_cnt is configured as 5, even though it is 4 242 */ 243 .chip_id = KSZ8794_CHIP_ID, 244 .dev_name = "KSZ8794", 245 .num_vlans = 4096, 246 .num_alus = 0, 247 .num_statics = 8, 248 .cpu_ports = 0x10, /* can be configured as cpu port */ 249 .port_cnt = 5, /* total cpu and user ports */ 250 .ops = &ksz8_dev_ops, 251 .ksz87xx_eee_link_erratum = true, 252 .mib_names = ksz9477_mib_names, 253 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 254 .reg_mib_cnt = MIB_COUNTER_NUM, 255 .stp_ctrl_reg = 0x02, 256 .broadcast_ctrl_reg = 0x06, 257 .multicast_ctrl_reg = 0x04, 258 .start_ctrl_reg = 0x01, 259 .supports_mii = {false, false, false, false, true}, 260 .supports_rmii = {false, false, false, false, true}, 261 .supports_rgmii = {false, false, false, false, true}, 262 .internal_phy = {true, true, true, false, false}, 263 }, 264 265 [KSZ8765] = { 266 .chip_id = KSZ8765_CHIP_ID, 267 .dev_name = "KSZ8765", 268 .num_vlans = 4096, 269 .num_alus = 0, 270 .num_statics = 8, 271 .cpu_ports = 0x10, /* can be configured as cpu port */ 272 .port_cnt = 5, /* total cpu and user ports */ 273 .ops = &ksz8_dev_ops, 274 .ksz87xx_eee_link_erratum = true, 275 .mib_names = ksz9477_mib_names, 276 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 277 .reg_mib_cnt = MIB_COUNTER_NUM, 278 .stp_ctrl_reg = 0x02, 279 .broadcast_ctrl_reg = 0x06, 280 .multicast_ctrl_reg = 0x04, 281 .start_ctrl_reg = 0x01, 282 .supports_mii = {false, false, false, false, true}, 283 .supports_rmii = {false, false, false, false, true}, 284 .supports_rgmii = {false, false, false, false, true}, 285 .internal_phy = {true, true, true, true, false}, 286 }, 287 288 [KSZ8830] = { 289 .chip_id = KSZ8830_CHIP_ID, 290 .dev_name = "KSZ8863/KSZ8873", 291 .num_vlans = 16, 292 .num_alus = 0, 293 .num_statics = 8, 294 .cpu_ports = 0x4, /* can be configured as cpu port */ 295 .port_cnt = 3, 296 .ops = &ksz8_dev_ops, 297 .mib_names = ksz88xx_mib_names, 298 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 299 .reg_mib_cnt = MIB_COUNTER_NUM, 300 .stp_ctrl_reg = 0x02, 301 .broadcast_ctrl_reg = 0x06, 302 .multicast_ctrl_reg = 0x04, 303 .start_ctrl_reg = 0x01, 304 .supports_mii = {false, false, true}, 305 .supports_rmii = {false, false, true}, 306 .internal_phy = {true, true, false}, 307 }, 308 309 [KSZ9477] = { 310 .chip_id = KSZ9477_CHIP_ID, 311 .dev_name = "KSZ9477", 312 .num_vlans = 4096, 313 .num_alus = 4096, 314 .num_statics = 16, 315 .cpu_ports = 0x7F, /* can be configured as cpu port */ 316 .port_cnt = 7, /* total physical port count */ 317 .ops = &ksz9477_dev_ops, 318 .phy_errata_9477 = true, 319 .mib_names = ksz9477_mib_names, 320 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 321 .reg_mib_cnt = MIB_COUNTER_NUM, 322 .stp_ctrl_reg = 0x0B04, 323 .broadcast_ctrl_reg = 0x0332, 324 .multicast_ctrl_reg = 0x0331, 325 .start_ctrl_reg = 0x0300, 326 .supports_mii = {false, false, false, false, 327 false, true, false}, 328 .supports_rmii = {false, false, false, false, 329 false, true, false}, 330 .supports_rgmii = {false, false, false, false, 331 false, true, false}, 332 .internal_phy = {true, true, true, true, 333 true, false, false}, 334 }, 335 336 [KSZ9897] = { 337 .chip_id = KSZ9897_CHIP_ID, 338 .dev_name = "KSZ9897", 339 .num_vlans = 4096, 340 .num_alus = 4096, 341 .num_statics = 16, 342 .cpu_ports = 0x7F, /* can be configured as cpu port */ 343 .port_cnt = 7, /* total physical port count */ 344 .ops = &ksz9477_dev_ops, 345 .phy_errata_9477 = true, 346 .mib_names = ksz9477_mib_names, 347 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 348 .reg_mib_cnt = MIB_COUNTER_NUM, 349 .stp_ctrl_reg = 0x0B04, 350 .broadcast_ctrl_reg = 0x0332, 351 .multicast_ctrl_reg = 0x0331, 352 .start_ctrl_reg = 0x0300, 353 .supports_mii = {false, false, false, false, 354 false, true, true}, 355 .supports_rmii = {false, false, false, false, 356 false, true, true}, 357 .supports_rgmii = {false, false, false, false, 358 false, true, true}, 359 .internal_phy = {true, true, true, true, 360 true, false, false}, 361 }, 362 363 [KSZ9893] = { 364 .chip_id = KSZ9893_CHIP_ID, 365 .dev_name = "KSZ9893", 366 .num_vlans = 4096, 367 .num_alus = 4096, 368 .num_statics = 16, 369 .cpu_ports = 0x07, /* can be configured as cpu port */ 370 .port_cnt = 3, /* total port count */ 371 .ops = &ksz9477_dev_ops, 372 .mib_names = ksz9477_mib_names, 373 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 374 .reg_mib_cnt = MIB_COUNTER_NUM, 375 .stp_ctrl_reg = 0x0B04, 376 .broadcast_ctrl_reg = 0x0332, 377 .multicast_ctrl_reg = 0x0331, 378 .start_ctrl_reg = 0x0300, 379 .supports_mii = {false, false, true}, 380 .supports_rmii = {false, false, true}, 381 .supports_rgmii = {false, false, true}, 382 .internal_phy = {true, true, false}, 383 }, 384 385 [KSZ9567] = { 386 .chip_id = KSZ9567_CHIP_ID, 387 .dev_name = "KSZ9567", 388 .num_vlans = 4096, 389 .num_alus = 4096, 390 .num_statics = 16, 391 .cpu_ports = 0x7F, /* can be configured as cpu port */ 392 .port_cnt = 7, /* total physical port count */ 393 .ops = &ksz9477_dev_ops, 394 .phy_errata_9477 = true, 395 .mib_names = ksz9477_mib_names, 396 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 397 .reg_mib_cnt = MIB_COUNTER_NUM, 398 .stp_ctrl_reg = 0x0B04, 399 .broadcast_ctrl_reg = 0x0332, 400 .multicast_ctrl_reg = 0x0331, 401 .start_ctrl_reg = 0x0300, 402 .supports_mii = {false, false, false, false, 403 false, true, true}, 404 .supports_rmii = {false, false, false, false, 405 false, true, true}, 406 .supports_rgmii = {false, false, false, false, 407 false, true, true}, 408 .internal_phy = {true, true, true, true, 409 true, false, false}, 410 }, 411 412 [LAN9370] = { 413 .chip_id = LAN9370_CHIP_ID, 414 .dev_name = "LAN9370", 415 .num_vlans = 4096, 416 .num_alus = 1024, 417 .num_statics = 256, 418 .cpu_ports = 0x10, /* can be configured as cpu port */ 419 .port_cnt = 5, /* total physical port count */ 420 .mib_names = ksz9477_mib_names, 421 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 422 .reg_mib_cnt = MIB_COUNTER_NUM, 423 .stp_ctrl_reg = 0x0B04, 424 .broadcast_ctrl_reg = 0x0332, 425 .multicast_ctrl_reg = 0x0331, 426 .start_ctrl_reg = 0x0300, 427 .supports_mii = {false, false, false, false, true}, 428 .supports_rmii = {false, false, false, false, true}, 429 .supports_rgmii = {false, false, false, false, true}, 430 .internal_phy = {true, true, true, true, false}, 431 }, 432 433 [LAN9371] = { 434 .chip_id = LAN9371_CHIP_ID, 435 .dev_name = "LAN9371", 436 .num_vlans = 4096, 437 .num_alus = 1024, 438 .num_statics = 256, 439 .cpu_ports = 0x30, /* can be configured as cpu port */ 440 .port_cnt = 6, /* total physical port count */ 441 .mib_names = ksz9477_mib_names, 442 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 443 .reg_mib_cnt = MIB_COUNTER_NUM, 444 .stp_ctrl_reg = 0x0B04, 445 .broadcast_ctrl_reg = 0x0332, 446 .multicast_ctrl_reg = 0x0331, 447 .start_ctrl_reg = 0x0300, 448 .supports_mii = {false, false, false, false, true, true}, 449 .supports_rmii = {false, false, false, false, true, true}, 450 .supports_rgmii = {false, false, false, false, true, true}, 451 .internal_phy = {true, true, true, true, false, false}, 452 }, 453 454 [LAN9372] = { 455 .chip_id = LAN9372_CHIP_ID, 456 .dev_name = "LAN9372", 457 .num_vlans = 4096, 458 .num_alus = 1024, 459 .num_statics = 256, 460 .cpu_ports = 0x30, /* can be configured as cpu port */ 461 .port_cnt = 8, /* total physical port count */ 462 .mib_names = ksz9477_mib_names, 463 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 464 .reg_mib_cnt = MIB_COUNTER_NUM, 465 .stp_ctrl_reg = 0x0B04, 466 .broadcast_ctrl_reg = 0x0332, 467 .multicast_ctrl_reg = 0x0331, 468 .start_ctrl_reg = 0x0300, 469 .supports_mii = {false, false, false, false, 470 true, true, false, false}, 471 .supports_rmii = {false, false, false, false, 472 true, true, false, false}, 473 .supports_rgmii = {false, false, false, false, 474 true, true, false, false}, 475 .internal_phy = {true, true, true, true, 476 false, false, true, true}, 477 }, 478 479 [LAN9373] = { 480 .chip_id = LAN9373_CHIP_ID, 481 .dev_name = "LAN9373", 482 .num_vlans = 4096, 483 .num_alus = 1024, 484 .num_statics = 256, 485 .cpu_ports = 0x38, /* can be configured as cpu port */ 486 .port_cnt = 5, /* total physical port count */ 487 .mib_names = ksz9477_mib_names, 488 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 489 .reg_mib_cnt = MIB_COUNTER_NUM, 490 .stp_ctrl_reg = 0x0B04, 491 .broadcast_ctrl_reg = 0x0332, 492 .multicast_ctrl_reg = 0x0331, 493 .start_ctrl_reg = 0x0300, 494 .supports_mii = {false, false, false, false, 495 true, true, false, false}, 496 .supports_rmii = {false, false, false, false, 497 true, true, false, false}, 498 .supports_rgmii = {false, false, false, false, 499 true, true, false, false}, 500 .internal_phy = {true, true, true, false, 501 false, false, true, true}, 502 }, 503 504 [LAN9374] = { 505 .chip_id = LAN9374_CHIP_ID, 506 .dev_name = "LAN9374", 507 .num_vlans = 4096, 508 .num_alus = 1024, 509 .num_statics = 256, 510 .cpu_ports = 0x30, /* can be configured as cpu port */ 511 .port_cnt = 8, /* total physical port count */ 512 .mib_names = ksz9477_mib_names, 513 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 514 .reg_mib_cnt = MIB_COUNTER_NUM, 515 .stp_ctrl_reg = 0x0B04, 516 .broadcast_ctrl_reg = 0x0332, 517 .multicast_ctrl_reg = 0x0331, 518 .start_ctrl_reg = 0x0300, 519 .supports_mii = {false, false, false, false, 520 true, true, false, false}, 521 .supports_rmii = {false, false, false, false, 522 true, true, false, false}, 523 .supports_rgmii = {false, false, false, false, 524 true, true, false, false}, 525 .internal_phy = {true, true, true, true, 526 false, false, true, true}, 527 }, 528 }; 529 EXPORT_SYMBOL_GPL(ksz_switch_chips); 530 531 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 532 { 533 int i; 534 535 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 536 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 537 538 if (chip->chip_id == prod_num) 539 return chip; 540 } 541 542 return NULL; 543 } 544 545 static int ksz_check_device_id(struct ksz_device *dev) 546 { 547 const struct ksz_chip_data *dt_chip_data; 548 549 dt_chip_data = of_device_get_match_data(dev->dev); 550 551 /* Check for Device Tree and Chip ID */ 552 if (dt_chip_data->chip_id != dev->chip_id) { 553 dev_err(dev->dev, 554 "Device tree specifies chip %s but found %s, please fix it!\n", 555 dt_chip_data->dev_name, dev->info->dev_name); 556 return -ENODEV; 557 } 558 559 return 0; 560 } 561 562 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 563 struct phylink_config *config) 564 { 565 struct ksz_device *dev = ds->priv; 566 567 config->legacy_pre_march2020 = false; 568 569 if (dev->info->supports_mii[port]) 570 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 571 572 if (dev->info->supports_rmii[port]) 573 __set_bit(PHY_INTERFACE_MODE_RMII, 574 config->supported_interfaces); 575 576 if (dev->info->supports_rgmii[port]) 577 phy_interface_set_rgmii(config->supported_interfaces); 578 579 if (dev->info->internal_phy[port]) 580 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 581 config->supported_interfaces); 582 583 if (dev->dev_ops->get_caps) 584 dev->dev_ops->get_caps(dev, port, config); 585 } 586 587 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 588 { 589 struct rtnl_link_stats64 *stats; 590 struct ksz_stats_raw *raw; 591 struct ksz_port_mib *mib; 592 593 mib = &dev->ports[port].mib; 594 stats = &mib->stats64; 595 raw = (struct ksz_stats_raw *)mib->counters; 596 597 spin_lock(&mib->stats64_lock); 598 599 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast; 600 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast; 601 602 /* HW counters are counting bytes + FCS which is not acceptable 603 * for rtnl_link_stats64 interface 604 */ 605 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 606 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 607 608 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 609 raw->rx_oversize; 610 611 stats->rx_crc_errors = raw->rx_crc_err; 612 stats->rx_frame_errors = raw->rx_align_err; 613 stats->rx_dropped = raw->rx_discards; 614 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 615 stats->rx_frame_errors + stats->rx_dropped; 616 617 stats->tx_window_errors = raw->tx_late_col; 618 stats->tx_fifo_errors = raw->tx_discards; 619 stats->tx_aborted_errors = raw->tx_exc_col; 620 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 621 stats->tx_aborted_errors; 622 623 stats->multicast = raw->rx_mcast; 624 stats->collisions = raw->tx_total_col; 625 626 spin_unlock(&mib->stats64_lock); 627 } 628 629 static void ksz_get_stats64(struct dsa_switch *ds, int port, 630 struct rtnl_link_stats64 *s) 631 { 632 struct ksz_device *dev = ds->priv; 633 struct ksz_port_mib *mib; 634 635 mib = &dev->ports[port].mib; 636 637 spin_lock(&mib->stats64_lock); 638 memcpy(s, &mib->stats64, sizeof(*s)); 639 spin_unlock(&mib->stats64_lock); 640 } 641 642 static void ksz_get_strings(struct dsa_switch *ds, int port, 643 u32 stringset, uint8_t *buf) 644 { 645 struct ksz_device *dev = ds->priv; 646 int i; 647 648 if (stringset != ETH_SS_STATS) 649 return; 650 651 for (i = 0; i < dev->info->mib_cnt; i++) { 652 memcpy(buf + i * ETH_GSTRING_LEN, 653 dev->info->mib_names[i].string, ETH_GSTRING_LEN); 654 } 655 } 656 657 static void ksz_update_port_member(struct ksz_device *dev, int port) 658 { 659 struct ksz_port *p = &dev->ports[port]; 660 struct dsa_switch *ds = dev->ds; 661 u8 port_member = 0, cpu_port; 662 const struct dsa_port *dp; 663 int i, j; 664 665 if (!dsa_is_user_port(ds, port)) 666 return; 667 668 dp = dsa_to_port(ds, port); 669 cpu_port = BIT(dsa_upstream_port(ds, port)); 670 671 for (i = 0; i < ds->num_ports; i++) { 672 const struct dsa_port *other_dp = dsa_to_port(ds, i); 673 struct ksz_port *other_p = &dev->ports[i]; 674 u8 val = 0; 675 676 if (!dsa_is_user_port(ds, i)) 677 continue; 678 if (port == i) 679 continue; 680 if (!dsa_port_bridge_same(dp, other_dp)) 681 continue; 682 if (other_p->stp_state != BR_STATE_FORWARDING) 683 continue; 684 685 if (p->stp_state == BR_STATE_FORWARDING) { 686 val |= BIT(port); 687 port_member |= BIT(i); 688 } 689 690 /* Retain port [i]'s relationship to other ports than [port] */ 691 for (j = 0; j < ds->num_ports; j++) { 692 const struct dsa_port *third_dp; 693 struct ksz_port *third_p; 694 695 if (j == i) 696 continue; 697 if (j == port) 698 continue; 699 if (!dsa_is_user_port(ds, j)) 700 continue; 701 third_p = &dev->ports[j]; 702 if (third_p->stp_state != BR_STATE_FORWARDING) 703 continue; 704 third_dp = dsa_to_port(ds, j); 705 if (dsa_port_bridge_same(other_dp, third_dp)) 706 val |= BIT(j); 707 } 708 709 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 710 } 711 712 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 713 } 714 715 static int ksz_setup(struct dsa_switch *ds) 716 { 717 struct ksz_device *dev = ds->priv; 718 int ret; 719 720 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 721 dev->info->num_vlans, GFP_KERNEL); 722 if (!dev->vlan_cache) 723 return -ENOMEM; 724 725 ret = dev->dev_ops->reset(dev); 726 if (ret) { 727 dev_err(ds->dev, "failed to reset switch\n"); 728 return ret; 729 } 730 731 /* set broadcast storm protection 10% rate */ 732 regmap_update_bits(dev->regmap[1], dev->info->broadcast_ctrl_reg, 733 BROADCAST_STORM_RATE, 734 (BROADCAST_STORM_VALUE * 735 BROADCAST_STORM_PROT_RATE) / 100); 736 737 dev->dev_ops->config_cpu_port(ds); 738 739 dev->dev_ops->enable_stp_addr(dev); 740 741 regmap_update_bits(dev->regmap[0], dev->info->multicast_ctrl_reg, 742 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 743 744 ksz_init_mib_timer(dev); 745 746 ds->configure_vlan_while_not_filtering = false; 747 748 if (dev->dev_ops->setup) { 749 ret = dev->dev_ops->setup(ds); 750 if (ret) 751 return ret; 752 } 753 754 /* start switch */ 755 regmap_update_bits(dev->regmap[0], dev->info->start_ctrl_reg, 756 SW_START, SW_START); 757 758 return 0; 759 } 760 761 static void port_r_cnt(struct ksz_device *dev, int port) 762 { 763 struct ksz_port_mib *mib = &dev->ports[port].mib; 764 u64 *dropped; 765 766 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 767 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 768 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 769 &mib->counters[mib->cnt_ptr]); 770 ++mib->cnt_ptr; 771 } 772 773 /* last one in storage */ 774 dropped = &mib->counters[dev->info->mib_cnt]; 775 776 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 777 while (mib->cnt_ptr < dev->info->mib_cnt) { 778 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 779 dropped, &mib->counters[mib->cnt_ptr]); 780 ++mib->cnt_ptr; 781 } 782 mib->cnt_ptr = 0; 783 } 784 785 static void ksz_mib_read_work(struct work_struct *work) 786 { 787 struct ksz_device *dev = container_of(work, struct ksz_device, 788 mib_read.work); 789 struct ksz_port_mib *mib; 790 struct ksz_port *p; 791 int i; 792 793 for (i = 0; i < dev->info->port_cnt; i++) { 794 if (dsa_is_unused_port(dev->ds, i)) 795 continue; 796 797 p = &dev->ports[i]; 798 mib = &p->mib; 799 mutex_lock(&mib->cnt_mutex); 800 801 /* Only read MIB counters when the port is told to do. 802 * If not, read only dropped counters when link is not up. 803 */ 804 if (!p->read) { 805 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 806 807 if (!netif_carrier_ok(dp->slave)) 808 mib->cnt_ptr = dev->info->reg_mib_cnt; 809 } 810 port_r_cnt(dev, i); 811 p->read = false; 812 813 if (dev->dev_ops->r_mib_stat64) 814 dev->dev_ops->r_mib_stat64(dev, i); 815 816 mutex_unlock(&mib->cnt_mutex); 817 } 818 819 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 820 } 821 822 void ksz_init_mib_timer(struct ksz_device *dev) 823 { 824 int i; 825 826 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 827 828 for (i = 0; i < dev->info->port_cnt; i++) { 829 struct ksz_port_mib *mib = &dev->ports[i].mib; 830 831 dev->dev_ops->port_init_cnt(dev, i); 832 833 mib->cnt_ptr = 0; 834 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 835 } 836 } 837 838 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 839 { 840 struct ksz_device *dev = ds->priv; 841 u16 val = 0xffff; 842 843 dev->dev_ops->r_phy(dev, addr, reg, &val); 844 845 return val; 846 } 847 848 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 849 { 850 struct ksz_device *dev = ds->priv; 851 852 dev->dev_ops->w_phy(dev, addr, reg, val); 853 854 return 0; 855 } 856 857 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 858 { 859 struct ksz_device *dev = ds->priv; 860 861 if (dev->chip_id == KSZ8830_CHIP_ID) { 862 /* Silicon Errata Sheet (DS80000830A): 863 * Port 1 does not work with LinkMD Cable-Testing. 864 * Port 1 does not respond to received PAUSE control frames. 865 */ 866 if (!port) 867 return MICREL_KSZ8_P1_ERRATA; 868 } 869 870 return 0; 871 } 872 873 static void ksz_mac_link_down(struct dsa_switch *ds, int port, 874 unsigned int mode, phy_interface_t interface) 875 { 876 struct ksz_device *dev = ds->priv; 877 struct ksz_port *p = &dev->ports[port]; 878 879 /* Read all MIB counters when the link is going down. */ 880 p->read = true; 881 /* timer started */ 882 if (dev->mib_read_interval) 883 schedule_delayed_work(&dev->mib_read, 0); 884 } 885 886 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 887 { 888 struct ksz_device *dev = ds->priv; 889 890 if (sset != ETH_SS_STATS) 891 return 0; 892 893 return dev->info->mib_cnt; 894 } 895 896 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 897 uint64_t *buf) 898 { 899 const struct dsa_port *dp = dsa_to_port(ds, port); 900 struct ksz_device *dev = ds->priv; 901 struct ksz_port_mib *mib; 902 903 mib = &dev->ports[port].mib; 904 mutex_lock(&mib->cnt_mutex); 905 906 /* Only read dropped counters if no link. */ 907 if (!netif_carrier_ok(dp->slave)) 908 mib->cnt_ptr = dev->info->reg_mib_cnt; 909 port_r_cnt(dev, port); 910 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 911 mutex_unlock(&mib->cnt_mutex); 912 } 913 914 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 915 struct dsa_bridge bridge, 916 bool *tx_fwd_offload, 917 struct netlink_ext_ack *extack) 918 { 919 /* port_stp_state_set() will be called after to put the port in 920 * appropriate state so there is no need to do anything. 921 */ 922 923 return 0; 924 } 925 926 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 927 struct dsa_bridge bridge) 928 { 929 /* port_stp_state_set() will be called after to put the port in 930 * forwarding state so there is no need to do anything. 931 */ 932 } 933 934 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 935 { 936 struct ksz_device *dev = ds->priv; 937 938 dev->dev_ops->flush_dyn_mac_table(dev, port); 939 } 940 941 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 942 const unsigned char *addr, u16 vid, 943 struct dsa_db db) 944 { 945 struct ksz_device *dev = ds->priv; 946 947 if (!dev->dev_ops->fdb_add) 948 return -EOPNOTSUPP; 949 950 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 951 } 952 953 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 954 const unsigned char *addr, 955 u16 vid, struct dsa_db db) 956 { 957 struct ksz_device *dev = ds->priv; 958 959 if (!dev->dev_ops->fdb_del) 960 return -EOPNOTSUPP; 961 962 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 963 } 964 965 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 966 dsa_fdb_dump_cb_t *cb, void *data) 967 { 968 struct ksz_device *dev = ds->priv; 969 970 if (!dev->dev_ops->fdb_dump) 971 return -EOPNOTSUPP; 972 973 return dev->dev_ops->fdb_dump(dev, port, cb, data); 974 } 975 976 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 977 const struct switchdev_obj_port_mdb *mdb, 978 struct dsa_db db) 979 { 980 struct ksz_device *dev = ds->priv; 981 982 if (!dev->dev_ops->mdb_add) 983 return -EOPNOTSUPP; 984 985 return dev->dev_ops->mdb_add(dev, port, mdb, db); 986 } 987 988 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 989 const struct switchdev_obj_port_mdb *mdb, 990 struct dsa_db db) 991 { 992 struct ksz_device *dev = ds->priv; 993 994 if (!dev->dev_ops->mdb_del) 995 return -EOPNOTSUPP; 996 997 return dev->dev_ops->mdb_del(dev, port, mdb, db); 998 } 999 1000 static int ksz_enable_port(struct dsa_switch *ds, int port, 1001 struct phy_device *phy) 1002 { 1003 struct ksz_device *dev = ds->priv; 1004 1005 if (!dsa_is_user_port(ds, port)) 1006 return 0; 1007 1008 /* setup slave port */ 1009 dev->dev_ops->port_setup(dev, port, false); 1010 1011 /* port_stp_state_set() will be called after to enable the port so 1012 * there is no need to do anything. 1013 */ 1014 1015 return 0; 1016 } 1017 1018 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1019 { 1020 struct ksz_device *dev = ds->priv; 1021 struct ksz_port *p; 1022 u8 data; 1023 int reg; 1024 1025 reg = dev->info->stp_ctrl_reg; 1026 1027 ksz_pread8(dev, port, reg, &data); 1028 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 1029 1030 switch (state) { 1031 case BR_STATE_DISABLED: 1032 data |= PORT_LEARN_DISABLE; 1033 break; 1034 case BR_STATE_LISTENING: 1035 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 1036 break; 1037 case BR_STATE_LEARNING: 1038 data |= PORT_RX_ENABLE; 1039 break; 1040 case BR_STATE_FORWARDING: 1041 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 1042 break; 1043 case BR_STATE_BLOCKING: 1044 data |= PORT_LEARN_DISABLE; 1045 break; 1046 default: 1047 dev_err(ds->dev, "invalid STP state: %d\n", state); 1048 return; 1049 } 1050 1051 ksz_pwrite8(dev, port, reg, data); 1052 1053 p = &dev->ports[port]; 1054 p->stp_state = state; 1055 1056 ksz_update_port_member(dev, port); 1057 } 1058 1059 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 1060 int port, 1061 enum dsa_tag_protocol mp) 1062 { 1063 struct ksz_device *dev = ds->priv; 1064 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 1065 1066 if (dev->chip_id == KSZ8795_CHIP_ID || 1067 dev->chip_id == KSZ8794_CHIP_ID || 1068 dev->chip_id == KSZ8765_CHIP_ID) 1069 proto = DSA_TAG_PROTO_KSZ8795; 1070 1071 if (dev->chip_id == KSZ8830_CHIP_ID || 1072 dev->chip_id == KSZ9893_CHIP_ID) 1073 proto = DSA_TAG_PROTO_KSZ9893; 1074 1075 if (dev->chip_id == KSZ9477_CHIP_ID || 1076 dev->chip_id == KSZ9897_CHIP_ID || 1077 dev->chip_id == KSZ9567_CHIP_ID) 1078 proto = DSA_TAG_PROTO_KSZ9477; 1079 1080 return proto; 1081 } 1082 1083 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 1084 bool flag, struct netlink_ext_ack *extack) 1085 { 1086 struct ksz_device *dev = ds->priv; 1087 1088 if (!dev->dev_ops->vlan_filtering) 1089 return -EOPNOTSUPP; 1090 1091 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 1092 } 1093 1094 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 1095 const struct switchdev_obj_port_vlan *vlan, 1096 struct netlink_ext_ack *extack) 1097 { 1098 struct ksz_device *dev = ds->priv; 1099 1100 if (!dev->dev_ops->vlan_add) 1101 return -EOPNOTSUPP; 1102 1103 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 1104 } 1105 1106 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 1107 const struct switchdev_obj_port_vlan *vlan) 1108 { 1109 struct ksz_device *dev = ds->priv; 1110 1111 if (!dev->dev_ops->vlan_del) 1112 return -EOPNOTSUPP; 1113 1114 return dev->dev_ops->vlan_del(dev, port, vlan); 1115 } 1116 1117 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 1118 struct dsa_mall_mirror_tc_entry *mirror, 1119 bool ingress, struct netlink_ext_ack *extack) 1120 { 1121 struct ksz_device *dev = ds->priv; 1122 1123 if (!dev->dev_ops->mirror_add) 1124 return -EOPNOTSUPP; 1125 1126 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 1127 } 1128 1129 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 1130 struct dsa_mall_mirror_tc_entry *mirror) 1131 { 1132 struct ksz_device *dev = ds->priv; 1133 1134 if (dev->dev_ops->mirror_del) 1135 dev->dev_ops->mirror_del(dev, port, mirror); 1136 } 1137 1138 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 1139 { 1140 struct ksz_device *dev = ds->priv; 1141 1142 if (!dev->dev_ops->change_mtu) 1143 return -EOPNOTSUPP; 1144 1145 return dev->dev_ops->change_mtu(dev, port, mtu); 1146 } 1147 1148 static int ksz_max_mtu(struct dsa_switch *ds, int port) 1149 { 1150 struct ksz_device *dev = ds->priv; 1151 1152 if (!dev->dev_ops->max_mtu) 1153 return -EOPNOTSUPP; 1154 1155 return dev->dev_ops->max_mtu(dev, port); 1156 } 1157 1158 static int ksz_switch_detect(struct ksz_device *dev) 1159 { 1160 u8 id1, id2; 1161 u16 id16; 1162 u32 id32; 1163 int ret; 1164 1165 /* read chip id */ 1166 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 1167 if (ret) 1168 return ret; 1169 1170 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 1171 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 1172 1173 switch (id1) { 1174 case KSZ87_FAMILY_ID: 1175 if (id2 == KSZ87_CHIP_ID_95) { 1176 u8 val; 1177 1178 dev->chip_id = KSZ8795_CHIP_ID; 1179 1180 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 1181 if (val & KSZ8_PORT_FIBER_MODE) 1182 dev->chip_id = KSZ8765_CHIP_ID; 1183 } else if (id2 == KSZ87_CHIP_ID_94) { 1184 dev->chip_id = KSZ8794_CHIP_ID; 1185 } else { 1186 return -ENODEV; 1187 } 1188 break; 1189 case KSZ88_FAMILY_ID: 1190 if (id2 == KSZ88_CHIP_ID_63) 1191 dev->chip_id = KSZ8830_CHIP_ID; 1192 else 1193 return -ENODEV; 1194 break; 1195 default: 1196 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 1197 if (ret) 1198 return ret; 1199 1200 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 1201 id32 &= ~0xFF; 1202 1203 switch (id32) { 1204 case KSZ9477_CHIP_ID: 1205 case KSZ9897_CHIP_ID: 1206 case KSZ9893_CHIP_ID: 1207 case KSZ9567_CHIP_ID: 1208 case LAN9370_CHIP_ID: 1209 case LAN9371_CHIP_ID: 1210 case LAN9372_CHIP_ID: 1211 case LAN9373_CHIP_ID: 1212 case LAN9374_CHIP_ID: 1213 dev->chip_id = id32; 1214 break; 1215 default: 1216 dev_err(dev->dev, 1217 "unsupported switch detected %x)\n", id32); 1218 return -ENODEV; 1219 } 1220 } 1221 return 0; 1222 } 1223 1224 static const struct dsa_switch_ops ksz_switch_ops = { 1225 .get_tag_protocol = ksz_get_tag_protocol, 1226 .get_phy_flags = ksz_get_phy_flags, 1227 .setup = ksz_setup, 1228 .phy_read = ksz_phy_read16, 1229 .phy_write = ksz_phy_write16, 1230 .phylink_get_caps = ksz_phylink_get_caps, 1231 .phylink_mac_link_down = ksz_mac_link_down, 1232 .port_enable = ksz_enable_port, 1233 .get_strings = ksz_get_strings, 1234 .get_ethtool_stats = ksz_get_ethtool_stats, 1235 .get_sset_count = ksz_sset_count, 1236 .port_bridge_join = ksz_port_bridge_join, 1237 .port_bridge_leave = ksz_port_bridge_leave, 1238 .port_stp_state_set = ksz_port_stp_state_set, 1239 .port_fast_age = ksz_port_fast_age, 1240 .port_vlan_filtering = ksz_port_vlan_filtering, 1241 .port_vlan_add = ksz_port_vlan_add, 1242 .port_vlan_del = ksz_port_vlan_del, 1243 .port_fdb_dump = ksz_port_fdb_dump, 1244 .port_fdb_add = ksz_port_fdb_add, 1245 .port_fdb_del = ksz_port_fdb_del, 1246 .port_mdb_add = ksz_port_mdb_add, 1247 .port_mdb_del = ksz_port_mdb_del, 1248 .port_mirror_add = ksz_port_mirror_add, 1249 .port_mirror_del = ksz_port_mirror_del, 1250 .get_stats64 = ksz_get_stats64, 1251 .port_change_mtu = ksz_change_mtu, 1252 .port_max_mtu = ksz_max_mtu, 1253 }; 1254 1255 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 1256 { 1257 struct dsa_switch *ds; 1258 struct ksz_device *swdev; 1259 1260 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 1261 if (!ds) 1262 return NULL; 1263 1264 ds->dev = base; 1265 ds->num_ports = DSA_MAX_PORTS; 1266 ds->ops = &ksz_switch_ops; 1267 1268 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 1269 if (!swdev) 1270 return NULL; 1271 1272 ds->priv = swdev; 1273 swdev->dev = base; 1274 1275 swdev->ds = ds; 1276 swdev->priv = priv; 1277 1278 return swdev; 1279 } 1280 EXPORT_SYMBOL(ksz_switch_alloc); 1281 1282 int ksz_switch_register(struct ksz_device *dev) 1283 { 1284 const struct ksz_chip_data *info; 1285 struct device_node *port, *ports; 1286 phy_interface_t interface; 1287 unsigned int port_num; 1288 int ret; 1289 int i; 1290 1291 if (dev->pdata) 1292 dev->chip_id = dev->pdata->chip_id; 1293 1294 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 1295 GPIOD_OUT_LOW); 1296 if (IS_ERR(dev->reset_gpio)) 1297 return PTR_ERR(dev->reset_gpio); 1298 1299 if (dev->reset_gpio) { 1300 gpiod_set_value_cansleep(dev->reset_gpio, 1); 1301 usleep_range(10000, 12000); 1302 gpiod_set_value_cansleep(dev->reset_gpio, 0); 1303 msleep(100); 1304 } 1305 1306 mutex_init(&dev->dev_mutex); 1307 mutex_init(&dev->regmap_mutex); 1308 mutex_init(&dev->alu_mutex); 1309 mutex_init(&dev->vlan_mutex); 1310 1311 ret = ksz_switch_detect(dev); 1312 if (ret) 1313 return ret; 1314 1315 info = ksz_lookup_info(dev->chip_id); 1316 if (!info) 1317 return -ENODEV; 1318 1319 /* Update the compatible info with the probed one */ 1320 dev->info = info; 1321 1322 dev_info(dev->dev, "found switch: %s, rev %i\n", 1323 dev->info->dev_name, dev->chip_rev); 1324 1325 ret = ksz_check_device_id(dev); 1326 if (ret) 1327 return ret; 1328 1329 dev->dev_ops = dev->info->ops; 1330 1331 ret = dev->dev_ops->init(dev); 1332 if (ret) 1333 return ret; 1334 1335 dev->ports = devm_kzalloc(dev->dev, 1336 dev->info->port_cnt * sizeof(struct ksz_port), 1337 GFP_KERNEL); 1338 if (!dev->ports) 1339 return -ENOMEM; 1340 1341 for (i = 0; i < dev->info->port_cnt; i++) { 1342 spin_lock_init(&dev->ports[i].mib.stats64_lock); 1343 mutex_init(&dev->ports[i].mib.cnt_mutex); 1344 dev->ports[i].mib.counters = 1345 devm_kzalloc(dev->dev, 1346 sizeof(u64) * (dev->info->mib_cnt + 1), 1347 GFP_KERNEL); 1348 if (!dev->ports[i].mib.counters) 1349 return -ENOMEM; 1350 } 1351 1352 /* set the real number of ports */ 1353 dev->ds->num_ports = dev->info->port_cnt; 1354 1355 /* Host port interface will be self detected, or specifically set in 1356 * device tree. 1357 */ 1358 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 1359 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 1360 if (dev->dev->of_node) { 1361 ret = of_get_phy_mode(dev->dev->of_node, &interface); 1362 if (ret == 0) 1363 dev->compat_interface = interface; 1364 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 1365 if (!ports) 1366 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 1367 if (ports) 1368 for_each_available_child_of_node(ports, port) { 1369 if (of_property_read_u32(port, "reg", 1370 &port_num)) 1371 continue; 1372 if (!(dev->port_mask & BIT(port_num))) { 1373 of_node_put(port); 1374 return -EINVAL; 1375 } 1376 of_get_phy_mode(port, 1377 &dev->ports[port_num].interface); 1378 } 1379 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 1380 "microchip,synclko-125"); 1381 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 1382 "microchip,synclko-disable"); 1383 if (dev->synclko_125 && dev->synclko_disable) { 1384 dev_err(dev->dev, "inconsistent synclko settings\n"); 1385 return -EINVAL; 1386 } 1387 } 1388 1389 ret = dsa_register_switch(dev->ds); 1390 if (ret) { 1391 dev->dev_ops->exit(dev); 1392 return ret; 1393 } 1394 1395 /* Read MIB counters every 30 seconds to avoid overflow. */ 1396 dev->mib_read_interval = msecs_to_jiffies(5000); 1397 1398 /* Start the MIB timer. */ 1399 schedule_delayed_work(&dev->mib_read, 0); 1400 1401 return ret; 1402 } 1403 EXPORT_SYMBOL(ksz_switch_register); 1404 1405 void ksz_switch_remove(struct ksz_device *dev) 1406 { 1407 /* timer started */ 1408 if (dev->mib_read_interval) { 1409 dev->mib_read_interval = 0; 1410 cancel_delayed_work_sync(&dev->mib_read); 1411 } 1412 1413 dev->dev_ops->exit(dev); 1414 dsa_unregister_switch(dev->ds); 1415 1416 if (dev->reset_gpio) 1417 gpiod_set_value_cansleep(dev->reset_gpio, 1); 1418 1419 } 1420 EXPORT_SYMBOL(ksz_switch_remove); 1421 1422 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 1423 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 1424 MODULE_LICENSE("GPL"); 1425