1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/dsa/ksz_common.h> 10 #include <linux/export.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/platform_data/microchip-ksz.h> 15 #include <linux/phy.h> 16 #include <linux/etherdevice.h> 17 #include <linux/if_bridge.h> 18 #include <linux/if_vlan.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/of_mdio.h> 22 #include <linux/of_device.h> 23 #include <linux/of_net.h> 24 #include <linux/micrel_phy.h> 25 #include <net/dsa.h> 26 #include <net/pkt_cls.h> 27 #include <net/switchdev.h> 28 29 #include "ksz_common.h" 30 #include "ksz_ptp.h" 31 #include "ksz8.h" 32 #include "ksz9477.h" 33 #include "lan937x.h" 34 35 #define MIB_COUNTER_NUM 0x20 36 37 struct ksz_stats_raw { 38 u64 rx_hi; 39 u64 rx_undersize; 40 u64 rx_fragments; 41 u64 rx_oversize; 42 u64 rx_jabbers; 43 u64 rx_symbol_err; 44 u64 rx_crc_err; 45 u64 rx_align_err; 46 u64 rx_mac_ctrl; 47 u64 rx_pause; 48 u64 rx_bcast; 49 u64 rx_mcast; 50 u64 rx_ucast; 51 u64 rx_64_or_less; 52 u64 rx_65_127; 53 u64 rx_128_255; 54 u64 rx_256_511; 55 u64 rx_512_1023; 56 u64 rx_1024_1522; 57 u64 rx_1523_2000; 58 u64 rx_2001; 59 u64 tx_hi; 60 u64 tx_late_col; 61 u64 tx_pause; 62 u64 tx_bcast; 63 u64 tx_mcast; 64 u64 tx_ucast; 65 u64 tx_deferred; 66 u64 tx_total_col; 67 u64 tx_exc_col; 68 u64 tx_single_col; 69 u64 tx_mult_col; 70 u64 rx_total; 71 u64 tx_total; 72 u64 rx_discards; 73 u64 tx_discards; 74 }; 75 76 struct ksz88xx_stats_raw { 77 u64 rx; 78 u64 rx_hi; 79 u64 rx_undersize; 80 u64 rx_fragments; 81 u64 rx_oversize; 82 u64 rx_jabbers; 83 u64 rx_symbol_err; 84 u64 rx_crc_err; 85 u64 rx_align_err; 86 u64 rx_mac_ctrl; 87 u64 rx_pause; 88 u64 rx_bcast; 89 u64 rx_mcast; 90 u64 rx_ucast; 91 u64 rx_64_or_less; 92 u64 rx_65_127; 93 u64 rx_128_255; 94 u64 rx_256_511; 95 u64 rx_512_1023; 96 u64 rx_1024_1522; 97 u64 tx; 98 u64 tx_hi; 99 u64 tx_late_col; 100 u64 tx_pause; 101 u64 tx_bcast; 102 u64 tx_mcast; 103 u64 tx_ucast; 104 u64 tx_deferred; 105 u64 tx_total_col; 106 u64 tx_exc_col; 107 u64 tx_single_col; 108 u64 tx_mult_col; 109 u64 rx_discards; 110 u64 tx_discards; 111 }; 112 113 static const struct ksz_mib_names ksz88xx_mib_names[] = { 114 { 0x00, "rx" }, 115 { 0x01, "rx_hi" }, 116 { 0x02, "rx_undersize" }, 117 { 0x03, "rx_fragments" }, 118 { 0x04, "rx_oversize" }, 119 { 0x05, "rx_jabbers" }, 120 { 0x06, "rx_symbol_err" }, 121 { 0x07, "rx_crc_err" }, 122 { 0x08, "rx_align_err" }, 123 { 0x09, "rx_mac_ctrl" }, 124 { 0x0a, "rx_pause" }, 125 { 0x0b, "rx_bcast" }, 126 { 0x0c, "rx_mcast" }, 127 { 0x0d, "rx_ucast" }, 128 { 0x0e, "rx_64_or_less" }, 129 { 0x0f, "rx_65_127" }, 130 { 0x10, "rx_128_255" }, 131 { 0x11, "rx_256_511" }, 132 { 0x12, "rx_512_1023" }, 133 { 0x13, "rx_1024_1522" }, 134 { 0x14, "tx" }, 135 { 0x15, "tx_hi" }, 136 { 0x16, "tx_late_col" }, 137 { 0x17, "tx_pause" }, 138 { 0x18, "tx_bcast" }, 139 { 0x19, "tx_mcast" }, 140 { 0x1a, "tx_ucast" }, 141 { 0x1b, "tx_deferred" }, 142 { 0x1c, "tx_total_col" }, 143 { 0x1d, "tx_exc_col" }, 144 { 0x1e, "tx_single_col" }, 145 { 0x1f, "tx_mult_col" }, 146 { 0x100, "rx_discards" }, 147 { 0x101, "tx_discards" }, 148 }; 149 150 static const struct ksz_mib_names ksz9477_mib_names[] = { 151 { 0x00, "rx_hi" }, 152 { 0x01, "rx_undersize" }, 153 { 0x02, "rx_fragments" }, 154 { 0x03, "rx_oversize" }, 155 { 0x04, "rx_jabbers" }, 156 { 0x05, "rx_symbol_err" }, 157 { 0x06, "rx_crc_err" }, 158 { 0x07, "rx_align_err" }, 159 { 0x08, "rx_mac_ctrl" }, 160 { 0x09, "rx_pause" }, 161 { 0x0A, "rx_bcast" }, 162 { 0x0B, "rx_mcast" }, 163 { 0x0C, "rx_ucast" }, 164 { 0x0D, "rx_64_or_less" }, 165 { 0x0E, "rx_65_127" }, 166 { 0x0F, "rx_128_255" }, 167 { 0x10, "rx_256_511" }, 168 { 0x11, "rx_512_1023" }, 169 { 0x12, "rx_1024_1522" }, 170 { 0x13, "rx_1523_2000" }, 171 { 0x14, "rx_2001" }, 172 { 0x15, "tx_hi" }, 173 { 0x16, "tx_late_col" }, 174 { 0x17, "tx_pause" }, 175 { 0x18, "tx_bcast" }, 176 { 0x19, "tx_mcast" }, 177 { 0x1A, "tx_ucast" }, 178 { 0x1B, "tx_deferred" }, 179 { 0x1C, "tx_total_col" }, 180 { 0x1D, "tx_exc_col" }, 181 { 0x1E, "tx_single_col" }, 182 { 0x1F, "tx_mult_col" }, 183 { 0x80, "rx_total" }, 184 { 0x81, "tx_total" }, 185 { 0x82, "rx_discards" }, 186 { 0x83, "tx_discards" }, 187 }; 188 189 static const struct ksz_dev_ops ksz8_dev_ops = { 190 .setup = ksz8_setup, 191 .get_port_addr = ksz8_get_port_addr, 192 .cfg_port_member = ksz8_cfg_port_member, 193 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 194 .port_setup = ksz8_port_setup, 195 .r_phy = ksz8_r_phy, 196 .w_phy = ksz8_w_phy, 197 .r_mib_cnt = ksz8_r_mib_cnt, 198 .r_mib_pkt = ksz8_r_mib_pkt, 199 .r_mib_stat64 = ksz88xx_r_mib_stats64, 200 .freeze_mib = ksz8_freeze_mib, 201 .port_init_cnt = ksz8_port_init_cnt, 202 .fdb_dump = ksz8_fdb_dump, 203 .fdb_add = ksz8_fdb_add, 204 .fdb_del = ksz8_fdb_del, 205 .mdb_add = ksz8_mdb_add, 206 .mdb_del = ksz8_mdb_del, 207 .vlan_filtering = ksz8_port_vlan_filtering, 208 .vlan_add = ksz8_port_vlan_add, 209 .vlan_del = ksz8_port_vlan_del, 210 .mirror_add = ksz8_port_mirror_add, 211 .mirror_del = ksz8_port_mirror_del, 212 .get_caps = ksz8_get_caps, 213 .config_cpu_port = ksz8_config_cpu_port, 214 .enable_stp_addr = ksz8_enable_stp_addr, 215 .reset = ksz8_reset_switch, 216 .init = ksz8_switch_init, 217 .exit = ksz8_switch_exit, 218 .change_mtu = ksz8_change_mtu, 219 }; 220 221 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, 222 unsigned int mode, 223 phy_interface_t interface, 224 struct phy_device *phydev, int speed, 225 int duplex, bool tx_pause, 226 bool rx_pause); 227 228 static const struct ksz_dev_ops ksz9477_dev_ops = { 229 .setup = ksz9477_setup, 230 .get_port_addr = ksz9477_get_port_addr, 231 .cfg_port_member = ksz9477_cfg_port_member, 232 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 233 .port_setup = ksz9477_port_setup, 234 .set_ageing_time = ksz9477_set_ageing_time, 235 .r_phy = ksz9477_r_phy, 236 .w_phy = ksz9477_w_phy, 237 .r_mib_cnt = ksz9477_r_mib_cnt, 238 .r_mib_pkt = ksz9477_r_mib_pkt, 239 .r_mib_stat64 = ksz_r_mib_stats64, 240 .freeze_mib = ksz9477_freeze_mib, 241 .port_init_cnt = ksz9477_port_init_cnt, 242 .vlan_filtering = ksz9477_port_vlan_filtering, 243 .vlan_add = ksz9477_port_vlan_add, 244 .vlan_del = ksz9477_port_vlan_del, 245 .mirror_add = ksz9477_port_mirror_add, 246 .mirror_del = ksz9477_port_mirror_del, 247 .get_caps = ksz9477_get_caps, 248 .fdb_dump = ksz9477_fdb_dump, 249 .fdb_add = ksz9477_fdb_add, 250 .fdb_del = ksz9477_fdb_del, 251 .mdb_add = ksz9477_mdb_add, 252 .mdb_del = ksz9477_mdb_del, 253 .change_mtu = ksz9477_change_mtu, 254 .phylink_mac_link_up = ksz9477_phylink_mac_link_up, 255 .config_cpu_port = ksz9477_config_cpu_port, 256 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc, 257 .enable_stp_addr = ksz9477_enable_stp_addr, 258 .reset = ksz9477_reset_switch, 259 .init = ksz9477_switch_init, 260 .exit = ksz9477_switch_exit, 261 }; 262 263 static const struct ksz_dev_ops lan937x_dev_ops = { 264 .setup = lan937x_setup, 265 .teardown = lan937x_teardown, 266 .get_port_addr = ksz9477_get_port_addr, 267 .cfg_port_member = ksz9477_cfg_port_member, 268 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 269 .port_setup = lan937x_port_setup, 270 .set_ageing_time = lan937x_set_ageing_time, 271 .r_phy = lan937x_r_phy, 272 .w_phy = lan937x_w_phy, 273 .r_mib_cnt = ksz9477_r_mib_cnt, 274 .r_mib_pkt = ksz9477_r_mib_pkt, 275 .r_mib_stat64 = ksz_r_mib_stats64, 276 .freeze_mib = ksz9477_freeze_mib, 277 .port_init_cnt = ksz9477_port_init_cnt, 278 .vlan_filtering = ksz9477_port_vlan_filtering, 279 .vlan_add = ksz9477_port_vlan_add, 280 .vlan_del = ksz9477_port_vlan_del, 281 .mirror_add = ksz9477_port_mirror_add, 282 .mirror_del = ksz9477_port_mirror_del, 283 .get_caps = lan937x_phylink_get_caps, 284 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 285 .fdb_dump = ksz9477_fdb_dump, 286 .fdb_add = ksz9477_fdb_add, 287 .fdb_del = ksz9477_fdb_del, 288 .mdb_add = ksz9477_mdb_add, 289 .mdb_del = ksz9477_mdb_del, 290 .change_mtu = lan937x_change_mtu, 291 .phylink_mac_link_up = ksz9477_phylink_mac_link_up, 292 .config_cpu_port = lan937x_config_cpu_port, 293 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc, 294 .enable_stp_addr = ksz9477_enable_stp_addr, 295 .reset = lan937x_reset_switch, 296 .init = lan937x_switch_init, 297 .exit = lan937x_switch_exit, 298 }; 299 300 static const u16 ksz8795_regs[] = { 301 [REG_IND_CTRL_0] = 0x6E, 302 [REG_IND_DATA_8] = 0x70, 303 [REG_IND_DATA_CHECK] = 0x72, 304 [REG_IND_DATA_HI] = 0x71, 305 [REG_IND_DATA_LO] = 0x75, 306 [REG_IND_MIB_CHECK] = 0x74, 307 [REG_IND_BYTE] = 0xA0, 308 [P_FORCE_CTRL] = 0x0C, 309 [P_LINK_STATUS] = 0x0E, 310 [P_LOCAL_CTRL] = 0x07, 311 [P_NEG_RESTART_CTRL] = 0x0D, 312 [P_REMOTE_STATUS] = 0x08, 313 [P_SPEED_STATUS] = 0x09, 314 [S_TAIL_TAG_CTRL] = 0x0C, 315 [P_STP_CTRL] = 0x02, 316 [S_START_CTRL] = 0x01, 317 [S_BROADCAST_CTRL] = 0x06, 318 [S_MULTICAST_CTRL] = 0x04, 319 [P_XMII_CTRL_0] = 0x06, 320 [P_XMII_CTRL_1] = 0x06, 321 }; 322 323 static const u32 ksz8795_masks[] = { 324 [PORT_802_1P_REMAPPING] = BIT(7), 325 [SW_TAIL_TAG_ENABLE] = BIT(1), 326 [MIB_COUNTER_OVERFLOW] = BIT(6), 327 [MIB_COUNTER_VALID] = BIT(5), 328 [VLAN_TABLE_FID] = GENMASK(6, 0), 329 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 330 [VLAN_TABLE_VALID] = BIT(12), 331 [STATIC_MAC_TABLE_VALID] = BIT(21), 332 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 333 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 334 [STATIC_MAC_TABLE_OVERRIDE] = BIT(26), 335 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(24, 20), 336 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 337 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(8), 338 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 339 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 340 [DYNAMIC_MAC_TABLE_FID] = GENMASK(26, 20), 341 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 342 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 343 [P_MII_TX_FLOW_CTRL] = BIT(5), 344 [P_MII_RX_FLOW_CTRL] = BIT(5), 345 }; 346 347 static const u8 ksz8795_xmii_ctrl0[] = { 348 [P_MII_100MBIT] = 0, 349 [P_MII_10MBIT] = 1, 350 [P_MII_FULL_DUPLEX] = 0, 351 [P_MII_HALF_DUPLEX] = 1, 352 }; 353 354 static const u8 ksz8795_xmii_ctrl1[] = { 355 [P_RGMII_SEL] = 3, 356 [P_GMII_SEL] = 2, 357 [P_RMII_SEL] = 1, 358 [P_MII_SEL] = 0, 359 [P_GMII_1GBIT] = 1, 360 [P_GMII_NOT_1GBIT] = 0, 361 }; 362 363 static const u8 ksz8795_shifts[] = { 364 [VLAN_TABLE_MEMBERSHIP_S] = 7, 365 [VLAN_TABLE] = 16, 366 [STATIC_MAC_FWD_PORTS] = 16, 367 [STATIC_MAC_FID] = 24, 368 [DYNAMIC_MAC_ENTRIES_H] = 3, 369 [DYNAMIC_MAC_ENTRIES] = 29, 370 [DYNAMIC_MAC_FID] = 16, 371 [DYNAMIC_MAC_TIMESTAMP] = 27, 372 [DYNAMIC_MAC_SRC_PORT] = 24, 373 }; 374 375 static const u16 ksz8863_regs[] = { 376 [REG_IND_CTRL_0] = 0x79, 377 [REG_IND_DATA_8] = 0x7B, 378 [REG_IND_DATA_CHECK] = 0x7B, 379 [REG_IND_DATA_HI] = 0x7C, 380 [REG_IND_DATA_LO] = 0x80, 381 [REG_IND_MIB_CHECK] = 0x80, 382 [P_FORCE_CTRL] = 0x0C, 383 [P_LINK_STATUS] = 0x0E, 384 [P_LOCAL_CTRL] = 0x0C, 385 [P_NEG_RESTART_CTRL] = 0x0D, 386 [P_REMOTE_STATUS] = 0x0E, 387 [P_SPEED_STATUS] = 0x0F, 388 [S_TAIL_TAG_CTRL] = 0x03, 389 [P_STP_CTRL] = 0x02, 390 [S_START_CTRL] = 0x01, 391 [S_BROADCAST_CTRL] = 0x06, 392 [S_MULTICAST_CTRL] = 0x04, 393 }; 394 395 static const u32 ksz8863_masks[] = { 396 [PORT_802_1P_REMAPPING] = BIT(3), 397 [SW_TAIL_TAG_ENABLE] = BIT(6), 398 [MIB_COUNTER_OVERFLOW] = BIT(7), 399 [MIB_COUNTER_VALID] = BIT(6), 400 [VLAN_TABLE_FID] = GENMASK(15, 12), 401 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 402 [VLAN_TABLE_VALID] = BIT(19), 403 [STATIC_MAC_TABLE_VALID] = BIT(19), 404 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 405 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), 406 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 407 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 408 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), 409 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), 410 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 411 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), 412 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 413 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 414 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 415 }; 416 417 static u8 ksz8863_shifts[] = { 418 [VLAN_TABLE_MEMBERSHIP_S] = 16, 419 [STATIC_MAC_FWD_PORTS] = 16, 420 [STATIC_MAC_FID] = 22, 421 [DYNAMIC_MAC_ENTRIES_H] = 8, 422 [DYNAMIC_MAC_ENTRIES] = 24, 423 [DYNAMIC_MAC_FID] = 16, 424 [DYNAMIC_MAC_TIMESTAMP] = 22, 425 [DYNAMIC_MAC_SRC_PORT] = 20, 426 }; 427 428 static const u16 ksz9477_regs[] = { 429 [P_STP_CTRL] = 0x0B04, 430 [S_START_CTRL] = 0x0300, 431 [S_BROADCAST_CTRL] = 0x0332, 432 [S_MULTICAST_CTRL] = 0x0331, 433 [P_XMII_CTRL_0] = 0x0300, 434 [P_XMII_CTRL_1] = 0x0301, 435 }; 436 437 static const u32 ksz9477_masks[] = { 438 [ALU_STAT_WRITE] = 0, 439 [ALU_STAT_READ] = 1, 440 [P_MII_TX_FLOW_CTRL] = BIT(5), 441 [P_MII_RX_FLOW_CTRL] = BIT(3), 442 }; 443 444 static const u8 ksz9477_shifts[] = { 445 [ALU_STAT_INDEX] = 16, 446 }; 447 448 static const u8 ksz9477_xmii_ctrl0[] = { 449 [P_MII_100MBIT] = 1, 450 [P_MII_10MBIT] = 0, 451 [P_MII_FULL_DUPLEX] = 1, 452 [P_MII_HALF_DUPLEX] = 0, 453 }; 454 455 static const u8 ksz9477_xmii_ctrl1[] = { 456 [P_RGMII_SEL] = 0, 457 [P_RMII_SEL] = 1, 458 [P_GMII_SEL] = 2, 459 [P_MII_SEL] = 3, 460 [P_GMII_1GBIT] = 0, 461 [P_GMII_NOT_1GBIT] = 1, 462 }; 463 464 static const u32 lan937x_masks[] = { 465 [ALU_STAT_WRITE] = 1, 466 [ALU_STAT_READ] = 2, 467 [P_MII_TX_FLOW_CTRL] = BIT(5), 468 [P_MII_RX_FLOW_CTRL] = BIT(3), 469 }; 470 471 static const u8 lan937x_shifts[] = { 472 [ALU_STAT_INDEX] = 8, 473 }; 474 475 static const struct regmap_range ksz8563_valid_regs[] = { 476 regmap_reg_range(0x0000, 0x0003), 477 regmap_reg_range(0x0006, 0x0006), 478 regmap_reg_range(0x000f, 0x001f), 479 regmap_reg_range(0x0100, 0x0100), 480 regmap_reg_range(0x0104, 0x0107), 481 regmap_reg_range(0x010d, 0x010d), 482 regmap_reg_range(0x0110, 0x0113), 483 regmap_reg_range(0x0120, 0x012b), 484 regmap_reg_range(0x0201, 0x0201), 485 regmap_reg_range(0x0210, 0x0213), 486 regmap_reg_range(0x0300, 0x0300), 487 regmap_reg_range(0x0302, 0x031b), 488 regmap_reg_range(0x0320, 0x032b), 489 regmap_reg_range(0x0330, 0x0336), 490 regmap_reg_range(0x0338, 0x033e), 491 regmap_reg_range(0x0340, 0x035f), 492 regmap_reg_range(0x0370, 0x0370), 493 regmap_reg_range(0x0378, 0x0378), 494 regmap_reg_range(0x037c, 0x037d), 495 regmap_reg_range(0x0390, 0x0393), 496 regmap_reg_range(0x0400, 0x040e), 497 regmap_reg_range(0x0410, 0x042f), 498 regmap_reg_range(0x0500, 0x0519), 499 regmap_reg_range(0x0520, 0x054b), 500 regmap_reg_range(0x0550, 0x05b3), 501 502 /* port 1 */ 503 regmap_reg_range(0x1000, 0x1001), 504 regmap_reg_range(0x1004, 0x100b), 505 regmap_reg_range(0x1013, 0x1013), 506 regmap_reg_range(0x1017, 0x1017), 507 regmap_reg_range(0x101b, 0x101b), 508 regmap_reg_range(0x101f, 0x1021), 509 regmap_reg_range(0x1030, 0x1030), 510 regmap_reg_range(0x1100, 0x1111), 511 regmap_reg_range(0x111a, 0x111d), 512 regmap_reg_range(0x1122, 0x1127), 513 regmap_reg_range(0x112a, 0x112b), 514 regmap_reg_range(0x1136, 0x1139), 515 regmap_reg_range(0x113e, 0x113f), 516 regmap_reg_range(0x1400, 0x1401), 517 regmap_reg_range(0x1403, 0x1403), 518 regmap_reg_range(0x1410, 0x1417), 519 regmap_reg_range(0x1420, 0x1423), 520 regmap_reg_range(0x1500, 0x1507), 521 regmap_reg_range(0x1600, 0x1612), 522 regmap_reg_range(0x1800, 0x180f), 523 regmap_reg_range(0x1900, 0x1907), 524 regmap_reg_range(0x1914, 0x191b), 525 regmap_reg_range(0x1a00, 0x1a03), 526 regmap_reg_range(0x1a04, 0x1a08), 527 regmap_reg_range(0x1b00, 0x1b01), 528 regmap_reg_range(0x1b04, 0x1b04), 529 regmap_reg_range(0x1c00, 0x1c05), 530 regmap_reg_range(0x1c08, 0x1c1b), 531 532 /* port 2 */ 533 regmap_reg_range(0x2000, 0x2001), 534 regmap_reg_range(0x2004, 0x200b), 535 regmap_reg_range(0x2013, 0x2013), 536 regmap_reg_range(0x2017, 0x2017), 537 regmap_reg_range(0x201b, 0x201b), 538 regmap_reg_range(0x201f, 0x2021), 539 regmap_reg_range(0x2030, 0x2030), 540 regmap_reg_range(0x2100, 0x2111), 541 regmap_reg_range(0x211a, 0x211d), 542 regmap_reg_range(0x2122, 0x2127), 543 regmap_reg_range(0x212a, 0x212b), 544 regmap_reg_range(0x2136, 0x2139), 545 regmap_reg_range(0x213e, 0x213f), 546 regmap_reg_range(0x2400, 0x2401), 547 regmap_reg_range(0x2403, 0x2403), 548 regmap_reg_range(0x2410, 0x2417), 549 regmap_reg_range(0x2420, 0x2423), 550 regmap_reg_range(0x2500, 0x2507), 551 regmap_reg_range(0x2600, 0x2612), 552 regmap_reg_range(0x2800, 0x280f), 553 regmap_reg_range(0x2900, 0x2907), 554 regmap_reg_range(0x2914, 0x291b), 555 regmap_reg_range(0x2a00, 0x2a03), 556 regmap_reg_range(0x2a04, 0x2a08), 557 regmap_reg_range(0x2b00, 0x2b01), 558 regmap_reg_range(0x2b04, 0x2b04), 559 regmap_reg_range(0x2c00, 0x2c05), 560 regmap_reg_range(0x2c08, 0x2c1b), 561 562 /* port 3 */ 563 regmap_reg_range(0x3000, 0x3001), 564 regmap_reg_range(0x3004, 0x300b), 565 regmap_reg_range(0x3013, 0x3013), 566 regmap_reg_range(0x3017, 0x3017), 567 regmap_reg_range(0x301b, 0x301b), 568 regmap_reg_range(0x301f, 0x3021), 569 regmap_reg_range(0x3030, 0x3030), 570 regmap_reg_range(0x3300, 0x3301), 571 regmap_reg_range(0x3303, 0x3303), 572 regmap_reg_range(0x3400, 0x3401), 573 regmap_reg_range(0x3403, 0x3403), 574 regmap_reg_range(0x3410, 0x3417), 575 regmap_reg_range(0x3420, 0x3423), 576 regmap_reg_range(0x3500, 0x3507), 577 regmap_reg_range(0x3600, 0x3612), 578 regmap_reg_range(0x3800, 0x380f), 579 regmap_reg_range(0x3900, 0x3907), 580 regmap_reg_range(0x3914, 0x391b), 581 regmap_reg_range(0x3a00, 0x3a03), 582 regmap_reg_range(0x3a04, 0x3a08), 583 regmap_reg_range(0x3b00, 0x3b01), 584 regmap_reg_range(0x3b04, 0x3b04), 585 regmap_reg_range(0x3c00, 0x3c05), 586 regmap_reg_range(0x3c08, 0x3c1b), 587 }; 588 589 static const struct regmap_access_table ksz8563_register_set = { 590 .yes_ranges = ksz8563_valid_regs, 591 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), 592 }; 593 594 static const struct regmap_range ksz9477_valid_regs[] = { 595 regmap_reg_range(0x0000, 0x0003), 596 regmap_reg_range(0x0006, 0x0006), 597 regmap_reg_range(0x0010, 0x001f), 598 regmap_reg_range(0x0100, 0x0100), 599 regmap_reg_range(0x0103, 0x0107), 600 regmap_reg_range(0x010d, 0x010d), 601 regmap_reg_range(0x0110, 0x0113), 602 regmap_reg_range(0x0120, 0x012b), 603 regmap_reg_range(0x0201, 0x0201), 604 regmap_reg_range(0x0210, 0x0213), 605 regmap_reg_range(0x0300, 0x0300), 606 regmap_reg_range(0x0302, 0x031b), 607 regmap_reg_range(0x0320, 0x032b), 608 regmap_reg_range(0x0330, 0x0336), 609 regmap_reg_range(0x0338, 0x033b), 610 regmap_reg_range(0x033e, 0x033e), 611 regmap_reg_range(0x0340, 0x035f), 612 regmap_reg_range(0x0370, 0x0370), 613 regmap_reg_range(0x0378, 0x0378), 614 regmap_reg_range(0x037c, 0x037d), 615 regmap_reg_range(0x0390, 0x0393), 616 regmap_reg_range(0x0400, 0x040e), 617 regmap_reg_range(0x0410, 0x042f), 618 regmap_reg_range(0x0444, 0x044b), 619 regmap_reg_range(0x0450, 0x046f), 620 regmap_reg_range(0x0500, 0x0519), 621 regmap_reg_range(0x0520, 0x054b), 622 regmap_reg_range(0x0550, 0x05b3), 623 regmap_reg_range(0x0604, 0x060b), 624 regmap_reg_range(0x0610, 0x0612), 625 regmap_reg_range(0x0614, 0x062c), 626 regmap_reg_range(0x0640, 0x0645), 627 regmap_reg_range(0x0648, 0x064d), 628 629 /* port 1 */ 630 regmap_reg_range(0x1000, 0x1001), 631 regmap_reg_range(0x1013, 0x1013), 632 regmap_reg_range(0x1017, 0x1017), 633 regmap_reg_range(0x101b, 0x101b), 634 regmap_reg_range(0x101f, 0x1020), 635 regmap_reg_range(0x1030, 0x1030), 636 regmap_reg_range(0x1100, 0x1115), 637 regmap_reg_range(0x111a, 0x111f), 638 regmap_reg_range(0x1122, 0x1127), 639 regmap_reg_range(0x112a, 0x112b), 640 regmap_reg_range(0x1136, 0x1139), 641 regmap_reg_range(0x113e, 0x113f), 642 regmap_reg_range(0x1400, 0x1401), 643 regmap_reg_range(0x1403, 0x1403), 644 regmap_reg_range(0x1410, 0x1417), 645 regmap_reg_range(0x1420, 0x1423), 646 regmap_reg_range(0x1500, 0x1507), 647 regmap_reg_range(0x1600, 0x1613), 648 regmap_reg_range(0x1800, 0x180f), 649 regmap_reg_range(0x1820, 0x1827), 650 regmap_reg_range(0x1830, 0x1837), 651 regmap_reg_range(0x1840, 0x184b), 652 regmap_reg_range(0x1900, 0x1907), 653 regmap_reg_range(0x1914, 0x191b), 654 regmap_reg_range(0x1920, 0x1920), 655 regmap_reg_range(0x1923, 0x1927), 656 regmap_reg_range(0x1a00, 0x1a03), 657 regmap_reg_range(0x1a04, 0x1a07), 658 regmap_reg_range(0x1b00, 0x1b01), 659 regmap_reg_range(0x1b04, 0x1b04), 660 regmap_reg_range(0x1c00, 0x1c05), 661 regmap_reg_range(0x1c08, 0x1c1b), 662 663 /* port 2 */ 664 regmap_reg_range(0x2000, 0x2001), 665 regmap_reg_range(0x2013, 0x2013), 666 regmap_reg_range(0x2017, 0x2017), 667 regmap_reg_range(0x201b, 0x201b), 668 regmap_reg_range(0x201f, 0x2020), 669 regmap_reg_range(0x2030, 0x2030), 670 regmap_reg_range(0x2100, 0x2115), 671 regmap_reg_range(0x211a, 0x211f), 672 regmap_reg_range(0x2122, 0x2127), 673 regmap_reg_range(0x212a, 0x212b), 674 regmap_reg_range(0x2136, 0x2139), 675 regmap_reg_range(0x213e, 0x213f), 676 regmap_reg_range(0x2400, 0x2401), 677 regmap_reg_range(0x2403, 0x2403), 678 regmap_reg_range(0x2410, 0x2417), 679 regmap_reg_range(0x2420, 0x2423), 680 regmap_reg_range(0x2500, 0x2507), 681 regmap_reg_range(0x2600, 0x2613), 682 regmap_reg_range(0x2800, 0x280f), 683 regmap_reg_range(0x2820, 0x2827), 684 regmap_reg_range(0x2830, 0x2837), 685 regmap_reg_range(0x2840, 0x284b), 686 regmap_reg_range(0x2900, 0x2907), 687 regmap_reg_range(0x2914, 0x291b), 688 regmap_reg_range(0x2920, 0x2920), 689 regmap_reg_range(0x2923, 0x2927), 690 regmap_reg_range(0x2a00, 0x2a03), 691 regmap_reg_range(0x2a04, 0x2a07), 692 regmap_reg_range(0x2b00, 0x2b01), 693 regmap_reg_range(0x2b04, 0x2b04), 694 regmap_reg_range(0x2c00, 0x2c05), 695 regmap_reg_range(0x2c08, 0x2c1b), 696 697 /* port 3 */ 698 regmap_reg_range(0x3000, 0x3001), 699 regmap_reg_range(0x3013, 0x3013), 700 regmap_reg_range(0x3017, 0x3017), 701 regmap_reg_range(0x301b, 0x301b), 702 regmap_reg_range(0x301f, 0x3020), 703 regmap_reg_range(0x3030, 0x3030), 704 regmap_reg_range(0x3100, 0x3115), 705 regmap_reg_range(0x311a, 0x311f), 706 regmap_reg_range(0x3122, 0x3127), 707 regmap_reg_range(0x312a, 0x312b), 708 regmap_reg_range(0x3136, 0x3139), 709 regmap_reg_range(0x313e, 0x313f), 710 regmap_reg_range(0x3400, 0x3401), 711 regmap_reg_range(0x3403, 0x3403), 712 regmap_reg_range(0x3410, 0x3417), 713 regmap_reg_range(0x3420, 0x3423), 714 regmap_reg_range(0x3500, 0x3507), 715 regmap_reg_range(0x3600, 0x3613), 716 regmap_reg_range(0x3800, 0x380f), 717 regmap_reg_range(0x3820, 0x3827), 718 regmap_reg_range(0x3830, 0x3837), 719 regmap_reg_range(0x3840, 0x384b), 720 regmap_reg_range(0x3900, 0x3907), 721 regmap_reg_range(0x3914, 0x391b), 722 regmap_reg_range(0x3920, 0x3920), 723 regmap_reg_range(0x3923, 0x3927), 724 regmap_reg_range(0x3a00, 0x3a03), 725 regmap_reg_range(0x3a04, 0x3a07), 726 regmap_reg_range(0x3b00, 0x3b01), 727 regmap_reg_range(0x3b04, 0x3b04), 728 regmap_reg_range(0x3c00, 0x3c05), 729 regmap_reg_range(0x3c08, 0x3c1b), 730 731 /* port 4 */ 732 regmap_reg_range(0x4000, 0x4001), 733 regmap_reg_range(0x4013, 0x4013), 734 regmap_reg_range(0x4017, 0x4017), 735 regmap_reg_range(0x401b, 0x401b), 736 regmap_reg_range(0x401f, 0x4020), 737 regmap_reg_range(0x4030, 0x4030), 738 regmap_reg_range(0x4100, 0x4115), 739 regmap_reg_range(0x411a, 0x411f), 740 regmap_reg_range(0x4122, 0x4127), 741 regmap_reg_range(0x412a, 0x412b), 742 regmap_reg_range(0x4136, 0x4139), 743 regmap_reg_range(0x413e, 0x413f), 744 regmap_reg_range(0x4400, 0x4401), 745 regmap_reg_range(0x4403, 0x4403), 746 regmap_reg_range(0x4410, 0x4417), 747 regmap_reg_range(0x4420, 0x4423), 748 regmap_reg_range(0x4500, 0x4507), 749 regmap_reg_range(0x4600, 0x4613), 750 regmap_reg_range(0x4800, 0x480f), 751 regmap_reg_range(0x4820, 0x4827), 752 regmap_reg_range(0x4830, 0x4837), 753 regmap_reg_range(0x4840, 0x484b), 754 regmap_reg_range(0x4900, 0x4907), 755 regmap_reg_range(0x4914, 0x491b), 756 regmap_reg_range(0x4920, 0x4920), 757 regmap_reg_range(0x4923, 0x4927), 758 regmap_reg_range(0x4a00, 0x4a03), 759 regmap_reg_range(0x4a04, 0x4a07), 760 regmap_reg_range(0x4b00, 0x4b01), 761 regmap_reg_range(0x4b04, 0x4b04), 762 regmap_reg_range(0x4c00, 0x4c05), 763 regmap_reg_range(0x4c08, 0x4c1b), 764 765 /* port 5 */ 766 regmap_reg_range(0x5000, 0x5001), 767 regmap_reg_range(0x5013, 0x5013), 768 regmap_reg_range(0x5017, 0x5017), 769 regmap_reg_range(0x501b, 0x501b), 770 regmap_reg_range(0x501f, 0x5020), 771 regmap_reg_range(0x5030, 0x5030), 772 regmap_reg_range(0x5100, 0x5115), 773 regmap_reg_range(0x511a, 0x511f), 774 regmap_reg_range(0x5122, 0x5127), 775 regmap_reg_range(0x512a, 0x512b), 776 regmap_reg_range(0x5136, 0x5139), 777 regmap_reg_range(0x513e, 0x513f), 778 regmap_reg_range(0x5400, 0x5401), 779 regmap_reg_range(0x5403, 0x5403), 780 regmap_reg_range(0x5410, 0x5417), 781 regmap_reg_range(0x5420, 0x5423), 782 regmap_reg_range(0x5500, 0x5507), 783 regmap_reg_range(0x5600, 0x5613), 784 regmap_reg_range(0x5800, 0x580f), 785 regmap_reg_range(0x5820, 0x5827), 786 regmap_reg_range(0x5830, 0x5837), 787 regmap_reg_range(0x5840, 0x584b), 788 regmap_reg_range(0x5900, 0x5907), 789 regmap_reg_range(0x5914, 0x591b), 790 regmap_reg_range(0x5920, 0x5920), 791 regmap_reg_range(0x5923, 0x5927), 792 regmap_reg_range(0x5a00, 0x5a03), 793 regmap_reg_range(0x5a04, 0x5a07), 794 regmap_reg_range(0x5b00, 0x5b01), 795 regmap_reg_range(0x5b04, 0x5b04), 796 regmap_reg_range(0x5c00, 0x5c05), 797 regmap_reg_range(0x5c08, 0x5c1b), 798 799 /* port 6 */ 800 regmap_reg_range(0x6000, 0x6001), 801 regmap_reg_range(0x6013, 0x6013), 802 regmap_reg_range(0x6017, 0x6017), 803 regmap_reg_range(0x601b, 0x601b), 804 regmap_reg_range(0x601f, 0x6020), 805 regmap_reg_range(0x6030, 0x6030), 806 regmap_reg_range(0x6300, 0x6301), 807 regmap_reg_range(0x6400, 0x6401), 808 regmap_reg_range(0x6403, 0x6403), 809 regmap_reg_range(0x6410, 0x6417), 810 regmap_reg_range(0x6420, 0x6423), 811 regmap_reg_range(0x6500, 0x6507), 812 regmap_reg_range(0x6600, 0x6613), 813 regmap_reg_range(0x6800, 0x680f), 814 regmap_reg_range(0x6820, 0x6827), 815 regmap_reg_range(0x6830, 0x6837), 816 regmap_reg_range(0x6840, 0x684b), 817 regmap_reg_range(0x6900, 0x6907), 818 regmap_reg_range(0x6914, 0x691b), 819 regmap_reg_range(0x6920, 0x6920), 820 regmap_reg_range(0x6923, 0x6927), 821 regmap_reg_range(0x6a00, 0x6a03), 822 regmap_reg_range(0x6a04, 0x6a07), 823 regmap_reg_range(0x6b00, 0x6b01), 824 regmap_reg_range(0x6b04, 0x6b04), 825 regmap_reg_range(0x6c00, 0x6c05), 826 regmap_reg_range(0x6c08, 0x6c1b), 827 828 /* port 7 */ 829 regmap_reg_range(0x7000, 0x7001), 830 regmap_reg_range(0x7013, 0x7013), 831 regmap_reg_range(0x7017, 0x7017), 832 regmap_reg_range(0x701b, 0x701b), 833 regmap_reg_range(0x701f, 0x7020), 834 regmap_reg_range(0x7030, 0x7030), 835 regmap_reg_range(0x7200, 0x7203), 836 regmap_reg_range(0x7206, 0x7207), 837 regmap_reg_range(0x7300, 0x7301), 838 regmap_reg_range(0x7400, 0x7401), 839 regmap_reg_range(0x7403, 0x7403), 840 regmap_reg_range(0x7410, 0x7417), 841 regmap_reg_range(0x7420, 0x7423), 842 regmap_reg_range(0x7500, 0x7507), 843 regmap_reg_range(0x7600, 0x7613), 844 regmap_reg_range(0x7800, 0x780f), 845 regmap_reg_range(0x7820, 0x7827), 846 regmap_reg_range(0x7830, 0x7837), 847 regmap_reg_range(0x7840, 0x784b), 848 regmap_reg_range(0x7900, 0x7907), 849 regmap_reg_range(0x7914, 0x791b), 850 regmap_reg_range(0x7920, 0x7920), 851 regmap_reg_range(0x7923, 0x7927), 852 regmap_reg_range(0x7a00, 0x7a03), 853 regmap_reg_range(0x7a04, 0x7a07), 854 regmap_reg_range(0x7b00, 0x7b01), 855 regmap_reg_range(0x7b04, 0x7b04), 856 regmap_reg_range(0x7c00, 0x7c05), 857 regmap_reg_range(0x7c08, 0x7c1b), 858 }; 859 860 static const struct regmap_access_table ksz9477_register_set = { 861 .yes_ranges = ksz9477_valid_regs, 862 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), 863 }; 864 865 static const struct regmap_range ksz9896_valid_regs[] = { 866 regmap_reg_range(0x0000, 0x0003), 867 regmap_reg_range(0x0006, 0x0006), 868 regmap_reg_range(0x0010, 0x001f), 869 regmap_reg_range(0x0100, 0x0100), 870 regmap_reg_range(0x0103, 0x0107), 871 regmap_reg_range(0x010d, 0x010d), 872 regmap_reg_range(0x0110, 0x0113), 873 regmap_reg_range(0x0120, 0x0127), 874 regmap_reg_range(0x0201, 0x0201), 875 regmap_reg_range(0x0210, 0x0213), 876 regmap_reg_range(0x0300, 0x0300), 877 regmap_reg_range(0x0302, 0x030b), 878 regmap_reg_range(0x0310, 0x031b), 879 regmap_reg_range(0x0320, 0x032b), 880 regmap_reg_range(0x0330, 0x0336), 881 regmap_reg_range(0x0338, 0x033b), 882 regmap_reg_range(0x033e, 0x033e), 883 regmap_reg_range(0x0340, 0x035f), 884 regmap_reg_range(0x0370, 0x0370), 885 regmap_reg_range(0x0378, 0x0378), 886 regmap_reg_range(0x037c, 0x037d), 887 regmap_reg_range(0x0390, 0x0393), 888 regmap_reg_range(0x0400, 0x040e), 889 regmap_reg_range(0x0410, 0x042f), 890 891 /* port 1 */ 892 regmap_reg_range(0x1000, 0x1001), 893 regmap_reg_range(0x1013, 0x1013), 894 regmap_reg_range(0x1017, 0x1017), 895 regmap_reg_range(0x101b, 0x101b), 896 regmap_reg_range(0x101f, 0x1020), 897 regmap_reg_range(0x1030, 0x1030), 898 regmap_reg_range(0x1100, 0x1115), 899 regmap_reg_range(0x111a, 0x111f), 900 regmap_reg_range(0x1122, 0x1127), 901 regmap_reg_range(0x112a, 0x112b), 902 regmap_reg_range(0x1136, 0x1139), 903 regmap_reg_range(0x113e, 0x113f), 904 regmap_reg_range(0x1400, 0x1401), 905 regmap_reg_range(0x1403, 0x1403), 906 regmap_reg_range(0x1410, 0x1417), 907 regmap_reg_range(0x1420, 0x1423), 908 regmap_reg_range(0x1500, 0x1507), 909 regmap_reg_range(0x1600, 0x1612), 910 regmap_reg_range(0x1800, 0x180f), 911 regmap_reg_range(0x1820, 0x1827), 912 regmap_reg_range(0x1830, 0x1837), 913 regmap_reg_range(0x1840, 0x184b), 914 regmap_reg_range(0x1900, 0x1907), 915 regmap_reg_range(0x1914, 0x1915), 916 regmap_reg_range(0x1a00, 0x1a03), 917 regmap_reg_range(0x1a04, 0x1a07), 918 regmap_reg_range(0x1b00, 0x1b01), 919 regmap_reg_range(0x1b04, 0x1b04), 920 921 /* port 2 */ 922 regmap_reg_range(0x2000, 0x2001), 923 regmap_reg_range(0x2013, 0x2013), 924 regmap_reg_range(0x2017, 0x2017), 925 regmap_reg_range(0x201b, 0x201b), 926 regmap_reg_range(0x201f, 0x2020), 927 regmap_reg_range(0x2030, 0x2030), 928 regmap_reg_range(0x2100, 0x2115), 929 regmap_reg_range(0x211a, 0x211f), 930 regmap_reg_range(0x2122, 0x2127), 931 regmap_reg_range(0x212a, 0x212b), 932 regmap_reg_range(0x2136, 0x2139), 933 regmap_reg_range(0x213e, 0x213f), 934 regmap_reg_range(0x2400, 0x2401), 935 regmap_reg_range(0x2403, 0x2403), 936 regmap_reg_range(0x2410, 0x2417), 937 regmap_reg_range(0x2420, 0x2423), 938 regmap_reg_range(0x2500, 0x2507), 939 regmap_reg_range(0x2600, 0x2612), 940 regmap_reg_range(0x2800, 0x280f), 941 regmap_reg_range(0x2820, 0x2827), 942 regmap_reg_range(0x2830, 0x2837), 943 regmap_reg_range(0x2840, 0x284b), 944 regmap_reg_range(0x2900, 0x2907), 945 regmap_reg_range(0x2914, 0x2915), 946 regmap_reg_range(0x2a00, 0x2a03), 947 regmap_reg_range(0x2a04, 0x2a07), 948 regmap_reg_range(0x2b00, 0x2b01), 949 regmap_reg_range(0x2b04, 0x2b04), 950 951 /* port 3 */ 952 regmap_reg_range(0x3000, 0x3001), 953 regmap_reg_range(0x3013, 0x3013), 954 regmap_reg_range(0x3017, 0x3017), 955 regmap_reg_range(0x301b, 0x301b), 956 regmap_reg_range(0x301f, 0x3020), 957 regmap_reg_range(0x3030, 0x3030), 958 regmap_reg_range(0x3100, 0x3115), 959 regmap_reg_range(0x311a, 0x311f), 960 regmap_reg_range(0x3122, 0x3127), 961 regmap_reg_range(0x312a, 0x312b), 962 regmap_reg_range(0x3136, 0x3139), 963 regmap_reg_range(0x313e, 0x313f), 964 regmap_reg_range(0x3400, 0x3401), 965 regmap_reg_range(0x3403, 0x3403), 966 regmap_reg_range(0x3410, 0x3417), 967 regmap_reg_range(0x3420, 0x3423), 968 regmap_reg_range(0x3500, 0x3507), 969 regmap_reg_range(0x3600, 0x3612), 970 regmap_reg_range(0x3800, 0x380f), 971 regmap_reg_range(0x3820, 0x3827), 972 regmap_reg_range(0x3830, 0x3837), 973 regmap_reg_range(0x3840, 0x384b), 974 regmap_reg_range(0x3900, 0x3907), 975 regmap_reg_range(0x3914, 0x3915), 976 regmap_reg_range(0x3a00, 0x3a03), 977 regmap_reg_range(0x3a04, 0x3a07), 978 regmap_reg_range(0x3b00, 0x3b01), 979 regmap_reg_range(0x3b04, 0x3b04), 980 981 /* port 4 */ 982 regmap_reg_range(0x4000, 0x4001), 983 regmap_reg_range(0x4013, 0x4013), 984 regmap_reg_range(0x4017, 0x4017), 985 regmap_reg_range(0x401b, 0x401b), 986 regmap_reg_range(0x401f, 0x4020), 987 regmap_reg_range(0x4030, 0x4030), 988 regmap_reg_range(0x4100, 0x4115), 989 regmap_reg_range(0x411a, 0x411f), 990 regmap_reg_range(0x4122, 0x4127), 991 regmap_reg_range(0x412a, 0x412b), 992 regmap_reg_range(0x4136, 0x4139), 993 regmap_reg_range(0x413e, 0x413f), 994 regmap_reg_range(0x4400, 0x4401), 995 regmap_reg_range(0x4403, 0x4403), 996 regmap_reg_range(0x4410, 0x4417), 997 regmap_reg_range(0x4420, 0x4423), 998 regmap_reg_range(0x4500, 0x4507), 999 regmap_reg_range(0x4600, 0x4612), 1000 regmap_reg_range(0x4800, 0x480f), 1001 regmap_reg_range(0x4820, 0x4827), 1002 regmap_reg_range(0x4830, 0x4837), 1003 regmap_reg_range(0x4840, 0x484b), 1004 regmap_reg_range(0x4900, 0x4907), 1005 regmap_reg_range(0x4914, 0x4915), 1006 regmap_reg_range(0x4a00, 0x4a03), 1007 regmap_reg_range(0x4a04, 0x4a07), 1008 regmap_reg_range(0x4b00, 0x4b01), 1009 regmap_reg_range(0x4b04, 0x4b04), 1010 1011 /* port 5 */ 1012 regmap_reg_range(0x5000, 0x5001), 1013 regmap_reg_range(0x5013, 0x5013), 1014 regmap_reg_range(0x5017, 0x5017), 1015 regmap_reg_range(0x501b, 0x501b), 1016 regmap_reg_range(0x501f, 0x5020), 1017 regmap_reg_range(0x5030, 0x5030), 1018 regmap_reg_range(0x5100, 0x5115), 1019 regmap_reg_range(0x511a, 0x511f), 1020 regmap_reg_range(0x5122, 0x5127), 1021 regmap_reg_range(0x512a, 0x512b), 1022 regmap_reg_range(0x5136, 0x5139), 1023 regmap_reg_range(0x513e, 0x513f), 1024 regmap_reg_range(0x5400, 0x5401), 1025 regmap_reg_range(0x5403, 0x5403), 1026 regmap_reg_range(0x5410, 0x5417), 1027 regmap_reg_range(0x5420, 0x5423), 1028 regmap_reg_range(0x5500, 0x5507), 1029 regmap_reg_range(0x5600, 0x5612), 1030 regmap_reg_range(0x5800, 0x580f), 1031 regmap_reg_range(0x5820, 0x5827), 1032 regmap_reg_range(0x5830, 0x5837), 1033 regmap_reg_range(0x5840, 0x584b), 1034 regmap_reg_range(0x5900, 0x5907), 1035 regmap_reg_range(0x5914, 0x5915), 1036 regmap_reg_range(0x5a00, 0x5a03), 1037 regmap_reg_range(0x5a04, 0x5a07), 1038 regmap_reg_range(0x5b00, 0x5b01), 1039 regmap_reg_range(0x5b04, 0x5b04), 1040 1041 /* port 6 */ 1042 regmap_reg_range(0x6000, 0x6001), 1043 regmap_reg_range(0x6013, 0x6013), 1044 regmap_reg_range(0x6017, 0x6017), 1045 regmap_reg_range(0x601b, 0x601b), 1046 regmap_reg_range(0x601f, 0x6020), 1047 regmap_reg_range(0x6030, 0x6030), 1048 regmap_reg_range(0x6100, 0x6115), 1049 regmap_reg_range(0x611a, 0x611f), 1050 regmap_reg_range(0x6122, 0x6127), 1051 regmap_reg_range(0x612a, 0x612b), 1052 regmap_reg_range(0x6136, 0x6139), 1053 regmap_reg_range(0x613e, 0x613f), 1054 regmap_reg_range(0x6300, 0x6301), 1055 regmap_reg_range(0x6400, 0x6401), 1056 regmap_reg_range(0x6403, 0x6403), 1057 regmap_reg_range(0x6410, 0x6417), 1058 regmap_reg_range(0x6420, 0x6423), 1059 regmap_reg_range(0x6500, 0x6507), 1060 regmap_reg_range(0x6600, 0x6612), 1061 regmap_reg_range(0x6800, 0x680f), 1062 regmap_reg_range(0x6820, 0x6827), 1063 regmap_reg_range(0x6830, 0x6837), 1064 regmap_reg_range(0x6840, 0x684b), 1065 regmap_reg_range(0x6900, 0x6907), 1066 regmap_reg_range(0x6914, 0x6915), 1067 regmap_reg_range(0x6a00, 0x6a03), 1068 regmap_reg_range(0x6a04, 0x6a07), 1069 regmap_reg_range(0x6b00, 0x6b01), 1070 regmap_reg_range(0x6b04, 0x6b04), 1071 }; 1072 1073 static const struct regmap_access_table ksz9896_register_set = { 1074 .yes_ranges = ksz9896_valid_regs, 1075 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs), 1076 }; 1077 1078 const struct ksz_chip_data ksz_switch_chips[] = { 1079 [KSZ8563] = { 1080 .chip_id = KSZ8563_CHIP_ID, 1081 .dev_name = "KSZ8563", 1082 .num_vlans = 4096, 1083 .num_alus = 4096, 1084 .num_statics = 16, 1085 .cpu_ports = 0x07, /* can be configured as cpu port */ 1086 .port_cnt = 3, /* total port count */ 1087 .port_nirqs = 3, 1088 .num_tx_queues = 4, 1089 .tc_cbs_supported = true, 1090 .tc_ets_supported = true, 1091 .ops = &ksz9477_dev_ops, 1092 .mib_names = ksz9477_mib_names, 1093 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1094 .reg_mib_cnt = MIB_COUNTER_NUM, 1095 .regs = ksz9477_regs, 1096 .masks = ksz9477_masks, 1097 .shifts = ksz9477_shifts, 1098 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1099 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1100 .supports_mii = {false, false, true}, 1101 .supports_rmii = {false, false, true}, 1102 .supports_rgmii = {false, false, true}, 1103 .internal_phy = {true, true, false}, 1104 .gbit_capable = {false, false, true}, 1105 .wr_table = &ksz8563_register_set, 1106 .rd_table = &ksz8563_register_set, 1107 }, 1108 1109 [KSZ8795] = { 1110 .chip_id = KSZ8795_CHIP_ID, 1111 .dev_name = "KSZ8795", 1112 .num_vlans = 4096, 1113 .num_alus = 0, 1114 .num_statics = 8, 1115 .cpu_ports = 0x10, /* can be configured as cpu port */ 1116 .port_cnt = 5, /* total cpu and user ports */ 1117 .num_tx_queues = 4, 1118 .ops = &ksz8_dev_ops, 1119 .ksz87xx_eee_link_erratum = true, 1120 .mib_names = ksz9477_mib_names, 1121 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1122 .reg_mib_cnt = MIB_COUNTER_NUM, 1123 .regs = ksz8795_regs, 1124 .masks = ksz8795_masks, 1125 .shifts = ksz8795_shifts, 1126 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1127 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1128 .supports_mii = {false, false, false, false, true}, 1129 .supports_rmii = {false, false, false, false, true}, 1130 .supports_rgmii = {false, false, false, false, true}, 1131 .internal_phy = {true, true, true, true, false}, 1132 }, 1133 1134 [KSZ8794] = { 1135 /* WARNING 1136 * ======= 1137 * KSZ8794 is similar to KSZ8795, except the port map 1138 * contains a gap between external and CPU ports, the 1139 * port map is NOT continuous. The per-port register 1140 * map is shifted accordingly too, i.e. registers at 1141 * offset 0x40 are NOT used on KSZ8794 and they ARE 1142 * used on KSZ8795 for external port 3. 1143 * external cpu 1144 * KSZ8794 0,1,2 4 1145 * KSZ8795 0,1,2,3 4 1146 * KSZ8765 0,1,2,3 4 1147 * port_cnt is configured as 5, even though it is 4 1148 */ 1149 .chip_id = KSZ8794_CHIP_ID, 1150 .dev_name = "KSZ8794", 1151 .num_vlans = 4096, 1152 .num_alus = 0, 1153 .num_statics = 8, 1154 .cpu_ports = 0x10, /* can be configured as cpu port */ 1155 .port_cnt = 5, /* total cpu and user ports */ 1156 .num_tx_queues = 4, 1157 .ops = &ksz8_dev_ops, 1158 .ksz87xx_eee_link_erratum = true, 1159 .mib_names = ksz9477_mib_names, 1160 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1161 .reg_mib_cnt = MIB_COUNTER_NUM, 1162 .regs = ksz8795_regs, 1163 .masks = ksz8795_masks, 1164 .shifts = ksz8795_shifts, 1165 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1166 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1167 .supports_mii = {false, false, false, false, true}, 1168 .supports_rmii = {false, false, false, false, true}, 1169 .supports_rgmii = {false, false, false, false, true}, 1170 .internal_phy = {true, true, true, false, false}, 1171 }, 1172 1173 [KSZ8765] = { 1174 .chip_id = KSZ8765_CHIP_ID, 1175 .dev_name = "KSZ8765", 1176 .num_vlans = 4096, 1177 .num_alus = 0, 1178 .num_statics = 8, 1179 .cpu_ports = 0x10, /* can be configured as cpu port */ 1180 .port_cnt = 5, /* total cpu and user ports */ 1181 .num_tx_queues = 4, 1182 .ops = &ksz8_dev_ops, 1183 .ksz87xx_eee_link_erratum = true, 1184 .mib_names = ksz9477_mib_names, 1185 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1186 .reg_mib_cnt = MIB_COUNTER_NUM, 1187 .regs = ksz8795_regs, 1188 .masks = ksz8795_masks, 1189 .shifts = ksz8795_shifts, 1190 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1191 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1192 .supports_mii = {false, false, false, false, true}, 1193 .supports_rmii = {false, false, false, false, true}, 1194 .supports_rgmii = {false, false, false, false, true}, 1195 .internal_phy = {true, true, true, true, false}, 1196 }, 1197 1198 [KSZ8830] = { 1199 .chip_id = KSZ8830_CHIP_ID, 1200 .dev_name = "KSZ8863/KSZ8873", 1201 .num_vlans = 16, 1202 .num_alus = 0, 1203 .num_statics = 8, 1204 .cpu_ports = 0x4, /* can be configured as cpu port */ 1205 .port_cnt = 3, 1206 .num_tx_queues = 4, 1207 .ops = &ksz8_dev_ops, 1208 .mib_names = ksz88xx_mib_names, 1209 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1210 .reg_mib_cnt = MIB_COUNTER_NUM, 1211 .regs = ksz8863_regs, 1212 .masks = ksz8863_masks, 1213 .shifts = ksz8863_shifts, 1214 .supports_mii = {false, false, true}, 1215 .supports_rmii = {false, false, true}, 1216 .internal_phy = {true, true, false}, 1217 }, 1218 1219 [KSZ9477] = { 1220 .chip_id = KSZ9477_CHIP_ID, 1221 .dev_name = "KSZ9477", 1222 .num_vlans = 4096, 1223 .num_alus = 4096, 1224 .num_statics = 16, 1225 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1226 .port_cnt = 7, /* total physical port count */ 1227 .port_nirqs = 4, 1228 .num_tx_queues = 4, 1229 .tc_cbs_supported = true, 1230 .tc_ets_supported = true, 1231 .ops = &ksz9477_dev_ops, 1232 .phy_errata_9477 = true, 1233 .mib_names = ksz9477_mib_names, 1234 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1235 .reg_mib_cnt = MIB_COUNTER_NUM, 1236 .regs = ksz9477_regs, 1237 .masks = ksz9477_masks, 1238 .shifts = ksz9477_shifts, 1239 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1240 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1241 .supports_mii = {false, false, false, false, 1242 false, true, false}, 1243 .supports_rmii = {false, false, false, false, 1244 false, true, false}, 1245 .supports_rgmii = {false, false, false, false, 1246 false, true, false}, 1247 .internal_phy = {true, true, true, true, 1248 true, false, false}, 1249 .gbit_capable = {true, true, true, true, true, true, true}, 1250 .wr_table = &ksz9477_register_set, 1251 .rd_table = &ksz9477_register_set, 1252 }, 1253 1254 [KSZ9896] = { 1255 .chip_id = KSZ9896_CHIP_ID, 1256 .dev_name = "KSZ9896", 1257 .num_vlans = 4096, 1258 .num_alus = 4096, 1259 .num_statics = 16, 1260 .cpu_ports = 0x3F, /* can be configured as cpu port */ 1261 .port_cnt = 6, /* total physical port count */ 1262 .port_nirqs = 2, 1263 .num_tx_queues = 4, 1264 .ops = &ksz9477_dev_ops, 1265 .phy_errata_9477 = true, 1266 .mib_names = ksz9477_mib_names, 1267 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1268 .reg_mib_cnt = MIB_COUNTER_NUM, 1269 .regs = ksz9477_regs, 1270 .masks = ksz9477_masks, 1271 .shifts = ksz9477_shifts, 1272 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1273 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1274 .supports_mii = {false, false, false, false, 1275 false, true}, 1276 .supports_rmii = {false, false, false, false, 1277 false, true}, 1278 .supports_rgmii = {false, false, false, false, 1279 false, true}, 1280 .internal_phy = {true, true, true, true, 1281 true, false}, 1282 .gbit_capable = {true, true, true, true, true, true}, 1283 .wr_table = &ksz9896_register_set, 1284 .rd_table = &ksz9896_register_set, 1285 }, 1286 1287 [KSZ9897] = { 1288 .chip_id = KSZ9897_CHIP_ID, 1289 .dev_name = "KSZ9897", 1290 .num_vlans = 4096, 1291 .num_alus = 4096, 1292 .num_statics = 16, 1293 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1294 .port_cnt = 7, /* total physical port count */ 1295 .port_nirqs = 2, 1296 .num_tx_queues = 4, 1297 .ops = &ksz9477_dev_ops, 1298 .phy_errata_9477 = true, 1299 .mib_names = ksz9477_mib_names, 1300 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1301 .reg_mib_cnt = MIB_COUNTER_NUM, 1302 .regs = ksz9477_regs, 1303 .masks = ksz9477_masks, 1304 .shifts = ksz9477_shifts, 1305 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1306 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1307 .supports_mii = {false, false, false, false, 1308 false, true, true}, 1309 .supports_rmii = {false, false, false, false, 1310 false, true, true}, 1311 .supports_rgmii = {false, false, false, false, 1312 false, true, true}, 1313 .internal_phy = {true, true, true, true, 1314 true, false, false}, 1315 .gbit_capable = {true, true, true, true, true, true, true}, 1316 }, 1317 1318 [KSZ9893] = { 1319 .chip_id = KSZ9893_CHIP_ID, 1320 .dev_name = "KSZ9893", 1321 .num_vlans = 4096, 1322 .num_alus = 4096, 1323 .num_statics = 16, 1324 .cpu_ports = 0x07, /* can be configured as cpu port */ 1325 .port_cnt = 3, /* total port count */ 1326 .port_nirqs = 2, 1327 .num_tx_queues = 4, 1328 .ops = &ksz9477_dev_ops, 1329 .mib_names = ksz9477_mib_names, 1330 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1331 .reg_mib_cnt = MIB_COUNTER_NUM, 1332 .regs = ksz9477_regs, 1333 .masks = ksz9477_masks, 1334 .shifts = ksz9477_shifts, 1335 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1336 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1337 .supports_mii = {false, false, true}, 1338 .supports_rmii = {false, false, true}, 1339 .supports_rgmii = {false, false, true}, 1340 .internal_phy = {true, true, false}, 1341 .gbit_capable = {true, true, true}, 1342 }, 1343 1344 [KSZ9563] = { 1345 .chip_id = KSZ9563_CHIP_ID, 1346 .dev_name = "KSZ9563", 1347 .num_vlans = 4096, 1348 .num_alus = 4096, 1349 .num_statics = 16, 1350 .cpu_ports = 0x07, /* can be configured as cpu port */ 1351 .port_cnt = 3, /* total port count */ 1352 .port_nirqs = 3, 1353 .num_tx_queues = 4, 1354 .tc_cbs_supported = true, 1355 .tc_ets_supported = true, 1356 .ops = &ksz9477_dev_ops, 1357 .mib_names = ksz9477_mib_names, 1358 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1359 .reg_mib_cnt = MIB_COUNTER_NUM, 1360 .regs = ksz9477_regs, 1361 .masks = ksz9477_masks, 1362 .shifts = ksz9477_shifts, 1363 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1364 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1365 .supports_mii = {false, false, true}, 1366 .supports_rmii = {false, false, true}, 1367 .supports_rgmii = {false, false, true}, 1368 .internal_phy = {true, true, false}, 1369 .gbit_capable = {true, true, true}, 1370 }, 1371 1372 [KSZ9567] = { 1373 .chip_id = KSZ9567_CHIP_ID, 1374 .dev_name = "KSZ9567", 1375 .num_vlans = 4096, 1376 .num_alus = 4096, 1377 .num_statics = 16, 1378 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1379 .port_cnt = 7, /* total physical port count */ 1380 .port_nirqs = 3, 1381 .num_tx_queues = 4, 1382 .tc_cbs_supported = true, 1383 .tc_ets_supported = true, 1384 .ops = &ksz9477_dev_ops, 1385 .phy_errata_9477 = true, 1386 .mib_names = ksz9477_mib_names, 1387 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1388 .reg_mib_cnt = MIB_COUNTER_NUM, 1389 .regs = ksz9477_regs, 1390 .masks = ksz9477_masks, 1391 .shifts = ksz9477_shifts, 1392 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1393 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1394 .supports_mii = {false, false, false, false, 1395 false, true, true}, 1396 .supports_rmii = {false, false, false, false, 1397 false, true, true}, 1398 .supports_rgmii = {false, false, false, false, 1399 false, true, true}, 1400 .internal_phy = {true, true, true, true, 1401 true, false, false}, 1402 .gbit_capable = {true, true, true, true, true, true, true}, 1403 }, 1404 1405 [LAN9370] = { 1406 .chip_id = LAN9370_CHIP_ID, 1407 .dev_name = "LAN9370", 1408 .num_vlans = 4096, 1409 .num_alus = 1024, 1410 .num_statics = 256, 1411 .cpu_ports = 0x10, /* can be configured as cpu port */ 1412 .port_cnt = 5, /* total physical port count */ 1413 .port_nirqs = 6, 1414 .num_tx_queues = 8, 1415 .tc_cbs_supported = true, 1416 .tc_ets_supported = true, 1417 .ops = &lan937x_dev_ops, 1418 .mib_names = ksz9477_mib_names, 1419 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1420 .reg_mib_cnt = MIB_COUNTER_NUM, 1421 .regs = ksz9477_regs, 1422 .masks = lan937x_masks, 1423 .shifts = lan937x_shifts, 1424 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1425 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1426 .supports_mii = {false, false, false, false, true}, 1427 .supports_rmii = {false, false, false, false, true}, 1428 .supports_rgmii = {false, false, false, false, true}, 1429 .internal_phy = {true, true, true, true, false}, 1430 }, 1431 1432 [LAN9371] = { 1433 .chip_id = LAN9371_CHIP_ID, 1434 .dev_name = "LAN9371", 1435 .num_vlans = 4096, 1436 .num_alus = 1024, 1437 .num_statics = 256, 1438 .cpu_ports = 0x30, /* can be configured as cpu port */ 1439 .port_cnt = 6, /* total physical port count */ 1440 .port_nirqs = 6, 1441 .num_tx_queues = 8, 1442 .tc_cbs_supported = true, 1443 .tc_ets_supported = true, 1444 .ops = &lan937x_dev_ops, 1445 .mib_names = ksz9477_mib_names, 1446 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1447 .reg_mib_cnt = MIB_COUNTER_NUM, 1448 .regs = ksz9477_regs, 1449 .masks = lan937x_masks, 1450 .shifts = lan937x_shifts, 1451 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1452 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1453 .supports_mii = {false, false, false, false, true, true}, 1454 .supports_rmii = {false, false, false, false, true, true}, 1455 .supports_rgmii = {false, false, false, false, true, true}, 1456 .internal_phy = {true, true, true, true, false, false}, 1457 }, 1458 1459 [LAN9372] = { 1460 .chip_id = LAN9372_CHIP_ID, 1461 .dev_name = "LAN9372", 1462 .num_vlans = 4096, 1463 .num_alus = 1024, 1464 .num_statics = 256, 1465 .cpu_ports = 0x30, /* can be configured as cpu port */ 1466 .port_cnt = 8, /* total physical port count */ 1467 .port_nirqs = 6, 1468 .num_tx_queues = 8, 1469 .tc_cbs_supported = true, 1470 .tc_ets_supported = true, 1471 .ops = &lan937x_dev_ops, 1472 .mib_names = ksz9477_mib_names, 1473 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1474 .reg_mib_cnt = MIB_COUNTER_NUM, 1475 .regs = ksz9477_regs, 1476 .masks = lan937x_masks, 1477 .shifts = lan937x_shifts, 1478 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1479 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1480 .supports_mii = {false, false, false, false, 1481 true, true, false, false}, 1482 .supports_rmii = {false, false, false, false, 1483 true, true, false, false}, 1484 .supports_rgmii = {false, false, false, false, 1485 true, true, false, false}, 1486 .internal_phy = {true, true, true, true, 1487 false, false, true, true}, 1488 }, 1489 1490 [LAN9373] = { 1491 .chip_id = LAN9373_CHIP_ID, 1492 .dev_name = "LAN9373", 1493 .num_vlans = 4096, 1494 .num_alus = 1024, 1495 .num_statics = 256, 1496 .cpu_ports = 0x38, /* can be configured as cpu port */ 1497 .port_cnt = 5, /* total physical port count */ 1498 .port_nirqs = 6, 1499 .num_tx_queues = 8, 1500 .tc_cbs_supported = true, 1501 .tc_ets_supported = true, 1502 .ops = &lan937x_dev_ops, 1503 .mib_names = ksz9477_mib_names, 1504 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1505 .reg_mib_cnt = MIB_COUNTER_NUM, 1506 .regs = ksz9477_regs, 1507 .masks = lan937x_masks, 1508 .shifts = lan937x_shifts, 1509 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1510 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1511 .supports_mii = {false, false, false, false, 1512 true, true, false, false}, 1513 .supports_rmii = {false, false, false, false, 1514 true, true, false, false}, 1515 .supports_rgmii = {false, false, false, false, 1516 true, true, false, false}, 1517 .internal_phy = {true, true, true, false, 1518 false, false, true, true}, 1519 }, 1520 1521 [LAN9374] = { 1522 .chip_id = LAN9374_CHIP_ID, 1523 .dev_name = "LAN9374", 1524 .num_vlans = 4096, 1525 .num_alus = 1024, 1526 .num_statics = 256, 1527 .cpu_ports = 0x30, /* can be configured as cpu port */ 1528 .port_cnt = 8, /* total physical port count */ 1529 .port_nirqs = 6, 1530 .num_tx_queues = 8, 1531 .tc_cbs_supported = true, 1532 .tc_ets_supported = true, 1533 .ops = &lan937x_dev_ops, 1534 .mib_names = ksz9477_mib_names, 1535 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1536 .reg_mib_cnt = MIB_COUNTER_NUM, 1537 .regs = ksz9477_regs, 1538 .masks = lan937x_masks, 1539 .shifts = lan937x_shifts, 1540 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1541 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1542 .supports_mii = {false, false, false, false, 1543 true, true, false, false}, 1544 .supports_rmii = {false, false, false, false, 1545 true, true, false, false}, 1546 .supports_rgmii = {false, false, false, false, 1547 true, true, false, false}, 1548 .internal_phy = {true, true, true, true, 1549 false, false, true, true}, 1550 }, 1551 }; 1552 EXPORT_SYMBOL_GPL(ksz_switch_chips); 1553 1554 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 1555 { 1556 int i; 1557 1558 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 1559 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 1560 1561 if (chip->chip_id == prod_num) 1562 return chip; 1563 } 1564 1565 return NULL; 1566 } 1567 1568 static int ksz_check_device_id(struct ksz_device *dev) 1569 { 1570 const struct ksz_chip_data *dt_chip_data; 1571 1572 dt_chip_data = of_device_get_match_data(dev->dev); 1573 1574 /* Check for Device Tree and Chip ID */ 1575 if (dt_chip_data->chip_id != dev->chip_id) { 1576 dev_err(dev->dev, 1577 "Device tree specifies chip %s but found %s, please fix it!\n", 1578 dt_chip_data->dev_name, dev->info->dev_name); 1579 return -ENODEV; 1580 } 1581 1582 return 0; 1583 } 1584 1585 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 1586 struct phylink_config *config) 1587 { 1588 struct ksz_device *dev = ds->priv; 1589 1590 config->legacy_pre_march2020 = false; 1591 1592 if (dev->info->supports_mii[port]) 1593 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1594 1595 if (dev->info->supports_rmii[port]) 1596 __set_bit(PHY_INTERFACE_MODE_RMII, 1597 config->supported_interfaces); 1598 1599 if (dev->info->supports_rgmii[port]) 1600 phy_interface_set_rgmii(config->supported_interfaces); 1601 1602 if (dev->info->internal_phy[port]) { 1603 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1604 config->supported_interfaces); 1605 /* Compatibility for phylib's default interface type when the 1606 * phy-mode property is absent 1607 */ 1608 __set_bit(PHY_INTERFACE_MODE_GMII, 1609 config->supported_interfaces); 1610 } 1611 1612 if (dev->dev_ops->get_caps) 1613 dev->dev_ops->get_caps(dev, port, config); 1614 } 1615 1616 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 1617 { 1618 struct ethtool_pause_stats *pstats; 1619 struct rtnl_link_stats64 *stats; 1620 struct ksz_stats_raw *raw; 1621 struct ksz_port_mib *mib; 1622 1623 mib = &dev->ports[port].mib; 1624 stats = &mib->stats64; 1625 pstats = &mib->pause_stats; 1626 raw = (struct ksz_stats_raw *)mib->counters; 1627 1628 spin_lock(&mib->stats64_lock); 1629 1630 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1631 raw->rx_pause; 1632 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1633 raw->tx_pause; 1634 1635 /* HW counters are counting bytes + FCS which is not acceptable 1636 * for rtnl_link_stats64 interface 1637 */ 1638 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 1639 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 1640 1641 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 1642 raw->rx_oversize; 1643 1644 stats->rx_crc_errors = raw->rx_crc_err; 1645 stats->rx_frame_errors = raw->rx_align_err; 1646 stats->rx_dropped = raw->rx_discards; 1647 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 1648 stats->rx_frame_errors + stats->rx_dropped; 1649 1650 stats->tx_window_errors = raw->tx_late_col; 1651 stats->tx_fifo_errors = raw->tx_discards; 1652 stats->tx_aborted_errors = raw->tx_exc_col; 1653 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 1654 stats->tx_aborted_errors; 1655 1656 stats->multicast = raw->rx_mcast; 1657 stats->collisions = raw->tx_total_col; 1658 1659 pstats->tx_pause_frames = raw->tx_pause; 1660 pstats->rx_pause_frames = raw->rx_pause; 1661 1662 spin_unlock(&mib->stats64_lock); 1663 } 1664 1665 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port) 1666 { 1667 struct ethtool_pause_stats *pstats; 1668 struct rtnl_link_stats64 *stats; 1669 struct ksz88xx_stats_raw *raw; 1670 struct ksz_port_mib *mib; 1671 1672 mib = &dev->ports[port].mib; 1673 stats = &mib->stats64; 1674 pstats = &mib->pause_stats; 1675 raw = (struct ksz88xx_stats_raw *)mib->counters; 1676 1677 spin_lock(&mib->stats64_lock); 1678 1679 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1680 raw->rx_pause; 1681 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1682 raw->tx_pause; 1683 1684 /* HW counters are counting bytes + FCS which is not acceptable 1685 * for rtnl_link_stats64 interface 1686 */ 1687 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN; 1688 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN; 1689 1690 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 1691 raw->rx_oversize; 1692 1693 stats->rx_crc_errors = raw->rx_crc_err; 1694 stats->rx_frame_errors = raw->rx_align_err; 1695 stats->rx_dropped = raw->rx_discards; 1696 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 1697 stats->rx_frame_errors + stats->rx_dropped; 1698 1699 stats->tx_window_errors = raw->tx_late_col; 1700 stats->tx_fifo_errors = raw->tx_discards; 1701 stats->tx_aborted_errors = raw->tx_exc_col; 1702 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 1703 stats->tx_aborted_errors; 1704 1705 stats->multicast = raw->rx_mcast; 1706 stats->collisions = raw->tx_total_col; 1707 1708 pstats->tx_pause_frames = raw->tx_pause; 1709 pstats->rx_pause_frames = raw->rx_pause; 1710 1711 spin_unlock(&mib->stats64_lock); 1712 } 1713 1714 static void ksz_get_stats64(struct dsa_switch *ds, int port, 1715 struct rtnl_link_stats64 *s) 1716 { 1717 struct ksz_device *dev = ds->priv; 1718 struct ksz_port_mib *mib; 1719 1720 mib = &dev->ports[port].mib; 1721 1722 spin_lock(&mib->stats64_lock); 1723 memcpy(s, &mib->stats64, sizeof(*s)); 1724 spin_unlock(&mib->stats64_lock); 1725 } 1726 1727 static void ksz_get_pause_stats(struct dsa_switch *ds, int port, 1728 struct ethtool_pause_stats *pause_stats) 1729 { 1730 struct ksz_device *dev = ds->priv; 1731 struct ksz_port_mib *mib; 1732 1733 mib = &dev->ports[port].mib; 1734 1735 spin_lock(&mib->stats64_lock); 1736 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 1737 spin_unlock(&mib->stats64_lock); 1738 } 1739 1740 static void ksz_get_strings(struct dsa_switch *ds, int port, 1741 u32 stringset, uint8_t *buf) 1742 { 1743 struct ksz_device *dev = ds->priv; 1744 int i; 1745 1746 if (stringset != ETH_SS_STATS) 1747 return; 1748 1749 for (i = 0; i < dev->info->mib_cnt; i++) { 1750 memcpy(buf + i * ETH_GSTRING_LEN, 1751 dev->info->mib_names[i].string, ETH_GSTRING_LEN); 1752 } 1753 } 1754 1755 static void ksz_update_port_member(struct ksz_device *dev, int port) 1756 { 1757 struct ksz_port *p = &dev->ports[port]; 1758 struct dsa_switch *ds = dev->ds; 1759 u8 port_member = 0, cpu_port; 1760 const struct dsa_port *dp; 1761 int i, j; 1762 1763 if (!dsa_is_user_port(ds, port)) 1764 return; 1765 1766 dp = dsa_to_port(ds, port); 1767 cpu_port = BIT(dsa_upstream_port(ds, port)); 1768 1769 for (i = 0; i < ds->num_ports; i++) { 1770 const struct dsa_port *other_dp = dsa_to_port(ds, i); 1771 struct ksz_port *other_p = &dev->ports[i]; 1772 u8 val = 0; 1773 1774 if (!dsa_is_user_port(ds, i)) 1775 continue; 1776 if (port == i) 1777 continue; 1778 if (!dsa_port_bridge_same(dp, other_dp)) 1779 continue; 1780 if (other_p->stp_state != BR_STATE_FORWARDING) 1781 continue; 1782 1783 if (p->stp_state == BR_STATE_FORWARDING) { 1784 val |= BIT(port); 1785 port_member |= BIT(i); 1786 } 1787 1788 /* Retain port [i]'s relationship to other ports than [port] */ 1789 for (j = 0; j < ds->num_ports; j++) { 1790 const struct dsa_port *third_dp; 1791 struct ksz_port *third_p; 1792 1793 if (j == i) 1794 continue; 1795 if (j == port) 1796 continue; 1797 if (!dsa_is_user_port(ds, j)) 1798 continue; 1799 third_p = &dev->ports[j]; 1800 if (third_p->stp_state != BR_STATE_FORWARDING) 1801 continue; 1802 third_dp = dsa_to_port(ds, j); 1803 if (dsa_port_bridge_same(other_dp, third_dp)) 1804 val |= BIT(j); 1805 } 1806 1807 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 1808 } 1809 1810 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 1811 } 1812 1813 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 1814 { 1815 struct ksz_device *dev = bus->priv; 1816 u16 val; 1817 int ret; 1818 1819 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val); 1820 if (ret < 0) 1821 return ret; 1822 1823 return val; 1824 } 1825 1826 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 1827 u16 val) 1828 { 1829 struct ksz_device *dev = bus->priv; 1830 1831 return dev->dev_ops->w_phy(dev, addr, regnum, val); 1832 } 1833 1834 static int ksz_irq_phy_setup(struct ksz_device *dev) 1835 { 1836 struct dsa_switch *ds = dev->ds; 1837 int phy; 1838 int irq; 1839 int ret; 1840 1841 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) { 1842 if (BIT(phy) & ds->phys_mii_mask) { 1843 irq = irq_find_mapping(dev->ports[phy].pirq.domain, 1844 PORT_SRC_PHY_INT); 1845 if (irq < 0) { 1846 ret = irq; 1847 goto out; 1848 } 1849 ds->slave_mii_bus->irq[phy] = irq; 1850 } 1851 } 1852 return 0; 1853 out: 1854 while (phy--) 1855 if (BIT(phy) & ds->phys_mii_mask) 1856 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]); 1857 1858 return ret; 1859 } 1860 1861 static void ksz_irq_phy_free(struct ksz_device *dev) 1862 { 1863 struct dsa_switch *ds = dev->ds; 1864 int phy; 1865 1866 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) 1867 if (BIT(phy) & ds->phys_mii_mask) 1868 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]); 1869 } 1870 1871 static int ksz_mdio_register(struct ksz_device *dev) 1872 { 1873 struct dsa_switch *ds = dev->ds; 1874 struct device_node *mdio_np; 1875 struct mii_bus *bus; 1876 int ret; 1877 1878 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); 1879 if (!mdio_np) 1880 return 0; 1881 1882 bus = devm_mdiobus_alloc(ds->dev); 1883 if (!bus) { 1884 of_node_put(mdio_np); 1885 return -ENOMEM; 1886 } 1887 1888 bus->priv = dev; 1889 bus->read = ksz_sw_mdio_read; 1890 bus->write = ksz_sw_mdio_write; 1891 bus->name = "ksz slave smi"; 1892 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); 1893 bus->parent = ds->dev; 1894 bus->phy_mask = ~ds->phys_mii_mask; 1895 1896 ds->slave_mii_bus = bus; 1897 1898 if (dev->irq > 0) { 1899 ret = ksz_irq_phy_setup(dev); 1900 if (ret) { 1901 of_node_put(mdio_np); 1902 return ret; 1903 } 1904 } 1905 1906 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); 1907 if (ret) { 1908 dev_err(ds->dev, "unable to register MDIO bus %s\n", 1909 bus->id); 1910 if (dev->irq > 0) 1911 ksz_irq_phy_free(dev); 1912 } 1913 1914 of_node_put(mdio_np); 1915 1916 return ret; 1917 } 1918 1919 static void ksz_irq_mask(struct irq_data *d) 1920 { 1921 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1922 1923 kirq->masked |= BIT(d->hwirq); 1924 } 1925 1926 static void ksz_irq_unmask(struct irq_data *d) 1927 { 1928 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1929 1930 kirq->masked &= ~BIT(d->hwirq); 1931 } 1932 1933 static void ksz_irq_bus_lock(struct irq_data *d) 1934 { 1935 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1936 1937 mutex_lock(&kirq->dev->lock_irq); 1938 } 1939 1940 static void ksz_irq_bus_sync_unlock(struct irq_data *d) 1941 { 1942 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1943 struct ksz_device *dev = kirq->dev; 1944 int ret; 1945 1946 ret = ksz_write32(dev, kirq->reg_mask, kirq->masked); 1947 if (ret) 1948 dev_err(dev->dev, "failed to change IRQ mask\n"); 1949 1950 mutex_unlock(&dev->lock_irq); 1951 } 1952 1953 static const struct irq_chip ksz_irq_chip = { 1954 .name = "ksz-irq", 1955 .irq_mask = ksz_irq_mask, 1956 .irq_unmask = ksz_irq_unmask, 1957 .irq_bus_lock = ksz_irq_bus_lock, 1958 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock, 1959 }; 1960 1961 static int ksz_irq_domain_map(struct irq_domain *d, 1962 unsigned int irq, irq_hw_number_t hwirq) 1963 { 1964 irq_set_chip_data(irq, d->host_data); 1965 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq); 1966 irq_set_noprobe(irq); 1967 1968 return 0; 1969 } 1970 1971 static const struct irq_domain_ops ksz_irq_domain_ops = { 1972 .map = ksz_irq_domain_map, 1973 .xlate = irq_domain_xlate_twocell, 1974 }; 1975 1976 static void ksz_irq_free(struct ksz_irq *kirq) 1977 { 1978 int irq, virq; 1979 1980 free_irq(kirq->irq_num, kirq); 1981 1982 for (irq = 0; irq < kirq->nirqs; irq++) { 1983 virq = irq_find_mapping(kirq->domain, irq); 1984 irq_dispose_mapping(virq); 1985 } 1986 1987 irq_domain_remove(kirq->domain); 1988 } 1989 1990 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id) 1991 { 1992 struct ksz_irq *kirq = dev_id; 1993 unsigned int nhandled = 0; 1994 struct ksz_device *dev; 1995 unsigned int sub_irq; 1996 u8 data; 1997 int ret; 1998 u8 n; 1999 2000 dev = kirq->dev; 2001 2002 /* Read interrupt status register */ 2003 ret = ksz_read8(dev, kirq->reg_status, &data); 2004 if (ret) 2005 goto out; 2006 2007 for (n = 0; n < kirq->nirqs; ++n) { 2008 if (data & BIT(n)) { 2009 sub_irq = irq_find_mapping(kirq->domain, n); 2010 handle_nested_irq(sub_irq); 2011 ++nhandled; 2012 } 2013 } 2014 out: 2015 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 2016 } 2017 2018 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq) 2019 { 2020 int ret, n; 2021 2022 kirq->dev = dev; 2023 kirq->masked = ~0; 2024 2025 kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0, 2026 &ksz_irq_domain_ops, kirq); 2027 if (!kirq->domain) 2028 return -ENOMEM; 2029 2030 for (n = 0; n < kirq->nirqs; n++) 2031 irq_create_mapping(kirq->domain, n); 2032 2033 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn, 2034 IRQF_ONESHOT, kirq->name, kirq); 2035 if (ret) 2036 goto out; 2037 2038 return 0; 2039 2040 out: 2041 ksz_irq_free(kirq); 2042 2043 return ret; 2044 } 2045 2046 static int ksz_girq_setup(struct ksz_device *dev) 2047 { 2048 struct ksz_irq *girq = &dev->girq; 2049 2050 girq->nirqs = dev->info->port_cnt; 2051 girq->reg_mask = REG_SW_PORT_INT_MASK__1; 2052 girq->reg_status = REG_SW_PORT_INT_STATUS__1; 2053 snprintf(girq->name, sizeof(girq->name), "global_port_irq"); 2054 2055 girq->irq_num = dev->irq; 2056 2057 return ksz_irq_common_setup(dev, girq); 2058 } 2059 2060 static int ksz_pirq_setup(struct ksz_device *dev, u8 p) 2061 { 2062 struct ksz_irq *pirq = &dev->ports[p].pirq; 2063 2064 pirq->nirqs = dev->info->port_nirqs; 2065 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK); 2066 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS); 2067 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p); 2068 2069 pirq->irq_num = irq_find_mapping(dev->girq.domain, p); 2070 if (pirq->irq_num < 0) 2071 return pirq->irq_num; 2072 2073 return ksz_irq_common_setup(dev, pirq); 2074 } 2075 2076 static int ksz_setup(struct dsa_switch *ds) 2077 { 2078 struct ksz_device *dev = ds->priv; 2079 struct dsa_port *dp; 2080 struct ksz_port *p; 2081 const u16 *regs; 2082 int ret; 2083 2084 regs = dev->info->regs; 2085 2086 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 2087 dev->info->num_vlans, GFP_KERNEL); 2088 if (!dev->vlan_cache) 2089 return -ENOMEM; 2090 2091 ret = dev->dev_ops->reset(dev); 2092 if (ret) { 2093 dev_err(ds->dev, "failed to reset switch\n"); 2094 return ret; 2095 } 2096 2097 /* set broadcast storm protection 10% rate */ 2098 regmap_update_bits(dev->regmap[1], regs[S_BROADCAST_CTRL], 2099 BROADCAST_STORM_RATE, 2100 (BROADCAST_STORM_VALUE * 2101 BROADCAST_STORM_PROT_RATE) / 100); 2102 2103 dev->dev_ops->config_cpu_port(ds); 2104 2105 dev->dev_ops->enable_stp_addr(dev); 2106 2107 ds->num_tx_queues = dev->info->num_tx_queues; 2108 2109 regmap_update_bits(dev->regmap[0], regs[S_MULTICAST_CTRL], 2110 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 2111 2112 ksz_init_mib_timer(dev); 2113 2114 ds->configure_vlan_while_not_filtering = false; 2115 2116 if (dev->dev_ops->setup) { 2117 ret = dev->dev_ops->setup(ds); 2118 if (ret) 2119 return ret; 2120 } 2121 2122 /* Start with learning disabled on standalone user ports, and enabled 2123 * on the CPU port. In lack of other finer mechanisms, learning on the 2124 * CPU port will avoid flooding bridge local addresses on the network 2125 * in some cases. 2126 */ 2127 p = &dev->ports[dev->cpu_port]; 2128 p->learning = true; 2129 2130 if (dev->irq > 0) { 2131 ret = ksz_girq_setup(dev); 2132 if (ret) 2133 return ret; 2134 2135 dsa_switch_for_each_user_port(dp, dev->ds) { 2136 ret = ksz_pirq_setup(dev, dp->index); 2137 if (ret) 2138 goto out_girq; 2139 2140 ret = ksz_ptp_irq_setup(ds, dp->index); 2141 if (ret) 2142 goto out_pirq; 2143 } 2144 } 2145 2146 ret = ksz_ptp_clock_register(ds); 2147 if (ret) { 2148 dev_err(dev->dev, "Failed to register PTP clock: %d\n", ret); 2149 goto out_ptpirq; 2150 } 2151 2152 ret = ksz_mdio_register(dev); 2153 if (ret < 0) { 2154 dev_err(dev->dev, "failed to register the mdio"); 2155 goto out_ptp_clock_unregister; 2156 } 2157 2158 /* start switch */ 2159 regmap_update_bits(dev->regmap[0], regs[S_START_CTRL], 2160 SW_START, SW_START); 2161 2162 return 0; 2163 2164 out_ptp_clock_unregister: 2165 ksz_ptp_clock_unregister(ds); 2166 out_ptpirq: 2167 if (dev->irq > 0) 2168 dsa_switch_for_each_user_port(dp, dev->ds) 2169 ksz_ptp_irq_free(ds, dp->index); 2170 out_pirq: 2171 if (dev->irq > 0) 2172 dsa_switch_for_each_user_port(dp, dev->ds) 2173 ksz_irq_free(&dev->ports[dp->index].pirq); 2174 out_girq: 2175 if (dev->irq > 0) 2176 ksz_irq_free(&dev->girq); 2177 2178 return ret; 2179 } 2180 2181 static void ksz_teardown(struct dsa_switch *ds) 2182 { 2183 struct ksz_device *dev = ds->priv; 2184 struct dsa_port *dp; 2185 2186 ksz_ptp_clock_unregister(ds); 2187 2188 if (dev->irq > 0) { 2189 dsa_switch_for_each_user_port(dp, dev->ds) { 2190 ksz_ptp_irq_free(ds, dp->index); 2191 2192 ksz_irq_free(&dev->ports[dp->index].pirq); 2193 } 2194 2195 ksz_irq_free(&dev->girq); 2196 } 2197 2198 if (dev->dev_ops->teardown) 2199 dev->dev_ops->teardown(ds); 2200 } 2201 2202 static void port_r_cnt(struct ksz_device *dev, int port) 2203 { 2204 struct ksz_port_mib *mib = &dev->ports[port].mib; 2205 u64 *dropped; 2206 2207 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 2208 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 2209 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 2210 &mib->counters[mib->cnt_ptr]); 2211 ++mib->cnt_ptr; 2212 } 2213 2214 /* last one in storage */ 2215 dropped = &mib->counters[dev->info->mib_cnt]; 2216 2217 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 2218 while (mib->cnt_ptr < dev->info->mib_cnt) { 2219 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 2220 dropped, &mib->counters[mib->cnt_ptr]); 2221 ++mib->cnt_ptr; 2222 } 2223 mib->cnt_ptr = 0; 2224 } 2225 2226 static void ksz_mib_read_work(struct work_struct *work) 2227 { 2228 struct ksz_device *dev = container_of(work, struct ksz_device, 2229 mib_read.work); 2230 struct ksz_port_mib *mib; 2231 struct ksz_port *p; 2232 int i; 2233 2234 for (i = 0; i < dev->info->port_cnt; i++) { 2235 if (dsa_is_unused_port(dev->ds, i)) 2236 continue; 2237 2238 p = &dev->ports[i]; 2239 mib = &p->mib; 2240 mutex_lock(&mib->cnt_mutex); 2241 2242 /* Only read MIB counters when the port is told to do. 2243 * If not, read only dropped counters when link is not up. 2244 */ 2245 if (!p->read) { 2246 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 2247 2248 if (!netif_carrier_ok(dp->slave)) 2249 mib->cnt_ptr = dev->info->reg_mib_cnt; 2250 } 2251 port_r_cnt(dev, i); 2252 p->read = false; 2253 2254 if (dev->dev_ops->r_mib_stat64) 2255 dev->dev_ops->r_mib_stat64(dev, i); 2256 2257 mutex_unlock(&mib->cnt_mutex); 2258 } 2259 2260 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 2261 } 2262 2263 void ksz_init_mib_timer(struct ksz_device *dev) 2264 { 2265 int i; 2266 2267 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 2268 2269 for (i = 0; i < dev->info->port_cnt; i++) { 2270 struct ksz_port_mib *mib = &dev->ports[i].mib; 2271 2272 dev->dev_ops->port_init_cnt(dev, i); 2273 2274 mib->cnt_ptr = 0; 2275 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 2276 } 2277 } 2278 2279 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 2280 { 2281 struct ksz_device *dev = ds->priv; 2282 u16 val = 0xffff; 2283 int ret; 2284 2285 ret = dev->dev_ops->r_phy(dev, addr, reg, &val); 2286 if (ret) 2287 return ret; 2288 2289 return val; 2290 } 2291 2292 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 2293 { 2294 struct ksz_device *dev = ds->priv; 2295 int ret; 2296 2297 ret = dev->dev_ops->w_phy(dev, addr, reg, val); 2298 if (ret) 2299 return ret; 2300 2301 return 0; 2302 } 2303 2304 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 2305 { 2306 struct ksz_device *dev = ds->priv; 2307 2308 if (dev->chip_id == KSZ8830_CHIP_ID) { 2309 /* Silicon Errata Sheet (DS80000830A): 2310 * Port 1 does not work with LinkMD Cable-Testing. 2311 * Port 1 does not respond to received PAUSE control frames. 2312 */ 2313 if (!port) 2314 return MICREL_KSZ8_P1_ERRATA; 2315 } 2316 2317 return 0; 2318 } 2319 2320 static void ksz_mac_link_down(struct dsa_switch *ds, int port, 2321 unsigned int mode, phy_interface_t interface) 2322 { 2323 struct ksz_device *dev = ds->priv; 2324 struct ksz_port *p = &dev->ports[port]; 2325 2326 /* Read all MIB counters when the link is going down. */ 2327 p->read = true; 2328 /* timer started */ 2329 if (dev->mib_read_interval) 2330 schedule_delayed_work(&dev->mib_read, 0); 2331 } 2332 2333 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 2334 { 2335 struct ksz_device *dev = ds->priv; 2336 2337 if (sset != ETH_SS_STATS) 2338 return 0; 2339 2340 return dev->info->mib_cnt; 2341 } 2342 2343 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 2344 uint64_t *buf) 2345 { 2346 const struct dsa_port *dp = dsa_to_port(ds, port); 2347 struct ksz_device *dev = ds->priv; 2348 struct ksz_port_mib *mib; 2349 2350 mib = &dev->ports[port].mib; 2351 mutex_lock(&mib->cnt_mutex); 2352 2353 /* Only read dropped counters if no link. */ 2354 if (!netif_carrier_ok(dp->slave)) 2355 mib->cnt_ptr = dev->info->reg_mib_cnt; 2356 port_r_cnt(dev, port); 2357 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 2358 mutex_unlock(&mib->cnt_mutex); 2359 } 2360 2361 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 2362 struct dsa_bridge bridge, 2363 bool *tx_fwd_offload, 2364 struct netlink_ext_ack *extack) 2365 { 2366 /* port_stp_state_set() will be called after to put the port in 2367 * appropriate state so there is no need to do anything. 2368 */ 2369 2370 return 0; 2371 } 2372 2373 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 2374 struct dsa_bridge bridge) 2375 { 2376 /* port_stp_state_set() will be called after to put the port in 2377 * forwarding state so there is no need to do anything. 2378 */ 2379 } 2380 2381 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 2382 { 2383 struct ksz_device *dev = ds->priv; 2384 2385 dev->dev_ops->flush_dyn_mac_table(dev, port); 2386 } 2387 2388 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 2389 { 2390 struct ksz_device *dev = ds->priv; 2391 2392 if (!dev->dev_ops->set_ageing_time) 2393 return -EOPNOTSUPP; 2394 2395 return dev->dev_ops->set_ageing_time(dev, msecs); 2396 } 2397 2398 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 2399 const unsigned char *addr, u16 vid, 2400 struct dsa_db db) 2401 { 2402 struct ksz_device *dev = ds->priv; 2403 2404 if (!dev->dev_ops->fdb_add) 2405 return -EOPNOTSUPP; 2406 2407 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 2408 } 2409 2410 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 2411 const unsigned char *addr, 2412 u16 vid, struct dsa_db db) 2413 { 2414 struct ksz_device *dev = ds->priv; 2415 2416 if (!dev->dev_ops->fdb_del) 2417 return -EOPNOTSUPP; 2418 2419 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 2420 } 2421 2422 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 2423 dsa_fdb_dump_cb_t *cb, void *data) 2424 { 2425 struct ksz_device *dev = ds->priv; 2426 2427 if (!dev->dev_ops->fdb_dump) 2428 return -EOPNOTSUPP; 2429 2430 return dev->dev_ops->fdb_dump(dev, port, cb, data); 2431 } 2432 2433 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 2434 const struct switchdev_obj_port_mdb *mdb, 2435 struct dsa_db db) 2436 { 2437 struct ksz_device *dev = ds->priv; 2438 2439 if (!dev->dev_ops->mdb_add) 2440 return -EOPNOTSUPP; 2441 2442 return dev->dev_ops->mdb_add(dev, port, mdb, db); 2443 } 2444 2445 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 2446 const struct switchdev_obj_port_mdb *mdb, 2447 struct dsa_db db) 2448 { 2449 struct ksz_device *dev = ds->priv; 2450 2451 if (!dev->dev_ops->mdb_del) 2452 return -EOPNOTSUPP; 2453 2454 return dev->dev_ops->mdb_del(dev, port, mdb, db); 2455 } 2456 2457 static int ksz_enable_port(struct dsa_switch *ds, int port, 2458 struct phy_device *phy) 2459 { 2460 struct ksz_device *dev = ds->priv; 2461 2462 if (!dsa_is_user_port(ds, port)) 2463 return 0; 2464 2465 /* setup slave port */ 2466 dev->dev_ops->port_setup(dev, port, false); 2467 2468 /* port_stp_state_set() will be called after to enable the port so 2469 * there is no need to do anything. 2470 */ 2471 2472 return 0; 2473 } 2474 2475 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 2476 { 2477 struct ksz_device *dev = ds->priv; 2478 struct ksz_port *p; 2479 const u16 *regs; 2480 u8 data; 2481 2482 regs = dev->info->regs; 2483 2484 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 2485 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2486 2487 p = &dev->ports[port]; 2488 2489 switch (state) { 2490 case BR_STATE_DISABLED: 2491 data |= PORT_LEARN_DISABLE; 2492 break; 2493 case BR_STATE_LISTENING: 2494 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2495 break; 2496 case BR_STATE_LEARNING: 2497 data |= PORT_RX_ENABLE; 2498 if (!p->learning) 2499 data |= PORT_LEARN_DISABLE; 2500 break; 2501 case BR_STATE_FORWARDING: 2502 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 2503 if (!p->learning) 2504 data |= PORT_LEARN_DISABLE; 2505 break; 2506 case BR_STATE_BLOCKING: 2507 data |= PORT_LEARN_DISABLE; 2508 break; 2509 default: 2510 dev_err(ds->dev, "invalid STP state: %d\n", state); 2511 return; 2512 } 2513 2514 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 2515 2516 p->stp_state = state; 2517 2518 ksz_update_port_member(dev, port); 2519 } 2520 2521 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 2522 struct switchdev_brport_flags flags, 2523 struct netlink_ext_ack *extack) 2524 { 2525 if (flags.mask & ~BR_LEARNING) 2526 return -EINVAL; 2527 2528 return 0; 2529 } 2530 2531 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 2532 struct switchdev_brport_flags flags, 2533 struct netlink_ext_ack *extack) 2534 { 2535 struct ksz_device *dev = ds->priv; 2536 struct ksz_port *p = &dev->ports[port]; 2537 2538 if (flags.mask & BR_LEARNING) { 2539 p->learning = !!(flags.val & BR_LEARNING); 2540 2541 /* Make the change take effect immediately */ 2542 ksz_port_stp_state_set(ds, port, p->stp_state); 2543 } 2544 2545 return 0; 2546 } 2547 2548 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 2549 int port, 2550 enum dsa_tag_protocol mp) 2551 { 2552 struct ksz_device *dev = ds->priv; 2553 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 2554 2555 if (dev->chip_id == KSZ8795_CHIP_ID || 2556 dev->chip_id == KSZ8794_CHIP_ID || 2557 dev->chip_id == KSZ8765_CHIP_ID) 2558 proto = DSA_TAG_PROTO_KSZ8795; 2559 2560 if (dev->chip_id == KSZ8830_CHIP_ID || 2561 dev->chip_id == KSZ8563_CHIP_ID || 2562 dev->chip_id == KSZ9893_CHIP_ID || 2563 dev->chip_id == KSZ9563_CHIP_ID) 2564 proto = DSA_TAG_PROTO_KSZ9893; 2565 2566 if (dev->chip_id == KSZ9477_CHIP_ID || 2567 dev->chip_id == KSZ9896_CHIP_ID || 2568 dev->chip_id == KSZ9897_CHIP_ID || 2569 dev->chip_id == KSZ9567_CHIP_ID) 2570 proto = DSA_TAG_PROTO_KSZ9477; 2571 2572 if (is_lan937x(dev)) 2573 proto = DSA_TAG_PROTO_LAN937X_VALUE; 2574 2575 return proto; 2576 } 2577 2578 static int ksz_connect_tag_protocol(struct dsa_switch *ds, 2579 enum dsa_tag_protocol proto) 2580 { 2581 struct ksz_tagger_data *tagger_data; 2582 2583 tagger_data = ksz_tagger_data(ds); 2584 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 2585 2586 return 0; 2587 } 2588 2589 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 2590 bool flag, struct netlink_ext_ack *extack) 2591 { 2592 struct ksz_device *dev = ds->priv; 2593 2594 if (!dev->dev_ops->vlan_filtering) 2595 return -EOPNOTSUPP; 2596 2597 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 2598 } 2599 2600 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 2601 const struct switchdev_obj_port_vlan *vlan, 2602 struct netlink_ext_ack *extack) 2603 { 2604 struct ksz_device *dev = ds->priv; 2605 2606 if (!dev->dev_ops->vlan_add) 2607 return -EOPNOTSUPP; 2608 2609 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 2610 } 2611 2612 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 2613 const struct switchdev_obj_port_vlan *vlan) 2614 { 2615 struct ksz_device *dev = ds->priv; 2616 2617 if (!dev->dev_ops->vlan_del) 2618 return -EOPNOTSUPP; 2619 2620 return dev->dev_ops->vlan_del(dev, port, vlan); 2621 } 2622 2623 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 2624 struct dsa_mall_mirror_tc_entry *mirror, 2625 bool ingress, struct netlink_ext_ack *extack) 2626 { 2627 struct ksz_device *dev = ds->priv; 2628 2629 if (!dev->dev_ops->mirror_add) 2630 return -EOPNOTSUPP; 2631 2632 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 2633 } 2634 2635 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 2636 struct dsa_mall_mirror_tc_entry *mirror) 2637 { 2638 struct ksz_device *dev = ds->priv; 2639 2640 if (dev->dev_ops->mirror_del) 2641 dev->dev_ops->mirror_del(dev, port, mirror); 2642 } 2643 2644 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 2645 { 2646 struct ksz_device *dev = ds->priv; 2647 2648 if (!dev->dev_ops->change_mtu) 2649 return -EOPNOTSUPP; 2650 2651 return dev->dev_ops->change_mtu(dev, port, mtu); 2652 } 2653 2654 static int ksz_max_mtu(struct dsa_switch *ds, int port) 2655 { 2656 struct ksz_device *dev = ds->priv; 2657 2658 switch (dev->chip_id) { 2659 case KSZ8795_CHIP_ID: 2660 case KSZ8794_CHIP_ID: 2661 case KSZ8765_CHIP_ID: 2662 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2663 case KSZ8830_CHIP_ID: 2664 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2665 case KSZ8563_CHIP_ID: 2666 case KSZ9477_CHIP_ID: 2667 case KSZ9563_CHIP_ID: 2668 case KSZ9567_CHIP_ID: 2669 case KSZ9893_CHIP_ID: 2670 case KSZ9896_CHIP_ID: 2671 case KSZ9897_CHIP_ID: 2672 case LAN9370_CHIP_ID: 2673 case LAN9371_CHIP_ID: 2674 case LAN9372_CHIP_ID: 2675 case LAN9373_CHIP_ID: 2676 case LAN9374_CHIP_ID: 2677 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2678 } 2679 2680 return -EOPNOTSUPP; 2681 } 2682 2683 static int ksz_validate_eee(struct dsa_switch *ds, int port) 2684 { 2685 struct ksz_device *dev = ds->priv; 2686 2687 if (!dev->info->internal_phy[port]) 2688 return -EOPNOTSUPP; 2689 2690 switch (dev->chip_id) { 2691 case KSZ8563_CHIP_ID: 2692 case KSZ9477_CHIP_ID: 2693 case KSZ9563_CHIP_ID: 2694 case KSZ9567_CHIP_ID: 2695 case KSZ9893_CHIP_ID: 2696 case KSZ9896_CHIP_ID: 2697 case KSZ9897_CHIP_ID: 2698 return 0; 2699 } 2700 2701 return -EOPNOTSUPP; 2702 } 2703 2704 static int ksz_get_mac_eee(struct dsa_switch *ds, int port, 2705 struct ethtool_eee *e) 2706 { 2707 int ret; 2708 2709 ret = ksz_validate_eee(ds, port); 2710 if (ret) 2711 return ret; 2712 2713 /* There is no documented control of Tx LPI configuration. */ 2714 e->tx_lpi_enabled = true; 2715 2716 /* There is no documented control of Tx LPI timer. According to tests 2717 * Tx LPI timer seems to be set by default to minimal value. 2718 */ 2719 e->tx_lpi_timer = 0; 2720 2721 return 0; 2722 } 2723 2724 static int ksz_set_mac_eee(struct dsa_switch *ds, int port, 2725 struct ethtool_eee *e) 2726 { 2727 struct ksz_device *dev = ds->priv; 2728 int ret; 2729 2730 ret = ksz_validate_eee(ds, port); 2731 if (ret) 2732 return ret; 2733 2734 if (!e->tx_lpi_enabled) { 2735 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n"); 2736 return -EINVAL; 2737 } 2738 2739 if (e->tx_lpi_timer) { 2740 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n"); 2741 return -EINVAL; 2742 } 2743 2744 return 0; 2745 } 2746 2747 static void ksz_set_xmii(struct ksz_device *dev, int port, 2748 phy_interface_t interface) 2749 { 2750 const u8 *bitval = dev->info->xmii_ctrl1; 2751 struct ksz_port *p = &dev->ports[port]; 2752 const u16 *regs = dev->info->regs; 2753 u8 data8; 2754 2755 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2756 2757 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 2758 P_RGMII_ID_EG_ENABLE); 2759 2760 switch (interface) { 2761 case PHY_INTERFACE_MODE_MII: 2762 data8 |= bitval[P_MII_SEL]; 2763 break; 2764 case PHY_INTERFACE_MODE_RMII: 2765 data8 |= bitval[P_RMII_SEL]; 2766 break; 2767 case PHY_INTERFACE_MODE_GMII: 2768 data8 |= bitval[P_GMII_SEL]; 2769 break; 2770 case PHY_INTERFACE_MODE_RGMII: 2771 case PHY_INTERFACE_MODE_RGMII_ID: 2772 case PHY_INTERFACE_MODE_RGMII_TXID: 2773 case PHY_INTERFACE_MODE_RGMII_RXID: 2774 data8 |= bitval[P_RGMII_SEL]; 2775 /* On KSZ9893, disable RGMII in-band status support */ 2776 if (dev->chip_id == KSZ9893_CHIP_ID || 2777 dev->chip_id == KSZ8563_CHIP_ID || 2778 dev->chip_id == KSZ9563_CHIP_ID) 2779 data8 &= ~P_MII_MAC_MODE; 2780 break; 2781 default: 2782 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 2783 phy_modes(interface), port); 2784 return; 2785 } 2786 2787 if (p->rgmii_tx_val) 2788 data8 |= P_RGMII_ID_EG_ENABLE; 2789 2790 if (p->rgmii_rx_val) 2791 data8 |= P_RGMII_ID_IG_ENABLE; 2792 2793 /* Write the updated value */ 2794 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 2795 } 2796 2797 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 2798 { 2799 const u8 *bitval = dev->info->xmii_ctrl1; 2800 const u16 *regs = dev->info->regs; 2801 phy_interface_t interface; 2802 u8 data8; 2803 u8 val; 2804 2805 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2806 2807 val = FIELD_GET(P_MII_SEL_M, data8); 2808 2809 if (val == bitval[P_MII_SEL]) { 2810 if (gbit) 2811 interface = PHY_INTERFACE_MODE_GMII; 2812 else 2813 interface = PHY_INTERFACE_MODE_MII; 2814 } else if (val == bitval[P_RMII_SEL]) { 2815 interface = PHY_INTERFACE_MODE_RGMII; 2816 } else { 2817 interface = PHY_INTERFACE_MODE_RGMII; 2818 if (data8 & P_RGMII_ID_EG_ENABLE) 2819 interface = PHY_INTERFACE_MODE_RGMII_TXID; 2820 if (data8 & P_RGMII_ID_IG_ENABLE) { 2821 interface = PHY_INTERFACE_MODE_RGMII_RXID; 2822 if (data8 & P_RGMII_ID_EG_ENABLE) 2823 interface = PHY_INTERFACE_MODE_RGMII_ID; 2824 } 2825 } 2826 2827 return interface; 2828 } 2829 2830 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port, 2831 unsigned int mode, 2832 const struct phylink_link_state *state) 2833 { 2834 struct ksz_device *dev = ds->priv; 2835 2836 if (ksz_is_ksz88x3(dev)) 2837 return; 2838 2839 /* Internal PHYs */ 2840 if (dev->info->internal_phy[port]) 2841 return; 2842 2843 if (phylink_autoneg_inband(mode)) { 2844 dev_err(dev->dev, "In-band AN not supported!\n"); 2845 return; 2846 } 2847 2848 ksz_set_xmii(dev, port, state->interface); 2849 2850 if (dev->dev_ops->phylink_mac_config) 2851 dev->dev_ops->phylink_mac_config(dev, port, mode, state); 2852 2853 if (dev->dev_ops->setup_rgmii_delay) 2854 dev->dev_ops->setup_rgmii_delay(dev, port); 2855 } 2856 2857 bool ksz_get_gbit(struct ksz_device *dev, int port) 2858 { 2859 const u8 *bitval = dev->info->xmii_ctrl1; 2860 const u16 *regs = dev->info->regs; 2861 bool gbit = false; 2862 u8 data8; 2863 bool val; 2864 2865 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2866 2867 val = FIELD_GET(P_GMII_1GBIT_M, data8); 2868 2869 if (val == bitval[P_GMII_1GBIT]) 2870 gbit = true; 2871 2872 return gbit; 2873 } 2874 2875 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) 2876 { 2877 const u8 *bitval = dev->info->xmii_ctrl1; 2878 const u16 *regs = dev->info->regs; 2879 u8 data8; 2880 2881 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2882 2883 data8 &= ~P_GMII_1GBIT_M; 2884 2885 if (gbit) 2886 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 2887 else 2888 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 2889 2890 /* Write the updated value */ 2891 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 2892 } 2893 2894 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) 2895 { 2896 const u8 *bitval = dev->info->xmii_ctrl0; 2897 const u16 *regs = dev->info->regs; 2898 u8 data8; 2899 2900 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 2901 2902 data8 &= ~P_MII_100MBIT_M; 2903 2904 if (speed == SPEED_100) 2905 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 2906 else 2907 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 2908 2909 /* Write the updated value */ 2910 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 2911 } 2912 2913 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) 2914 { 2915 if (speed == SPEED_1000) 2916 ksz_set_gbit(dev, port, true); 2917 else 2918 ksz_set_gbit(dev, port, false); 2919 2920 if (speed == SPEED_100 || speed == SPEED_10) 2921 ksz_set_100_10mbit(dev, port, speed); 2922 } 2923 2924 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 2925 bool tx_pause, bool rx_pause) 2926 { 2927 const u8 *bitval = dev->info->xmii_ctrl0; 2928 const u32 *masks = dev->info->masks; 2929 const u16 *regs = dev->info->regs; 2930 u8 mask; 2931 u8 val; 2932 2933 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 2934 masks[P_MII_RX_FLOW_CTRL]; 2935 2936 if (duplex == DUPLEX_FULL) 2937 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 2938 else 2939 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 2940 2941 if (tx_pause) 2942 val |= masks[P_MII_TX_FLOW_CTRL]; 2943 2944 if (rx_pause) 2945 val |= masks[P_MII_RX_FLOW_CTRL]; 2946 2947 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 2948 } 2949 2950 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, 2951 unsigned int mode, 2952 phy_interface_t interface, 2953 struct phy_device *phydev, int speed, 2954 int duplex, bool tx_pause, 2955 bool rx_pause) 2956 { 2957 struct ksz_port *p; 2958 2959 p = &dev->ports[port]; 2960 2961 /* Internal PHYs */ 2962 if (dev->info->internal_phy[port]) 2963 return; 2964 2965 p->phydev.speed = speed; 2966 2967 ksz_port_set_xmii_speed(dev, port, speed); 2968 2969 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 2970 } 2971 2972 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port, 2973 unsigned int mode, 2974 phy_interface_t interface, 2975 struct phy_device *phydev, int speed, 2976 int duplex, bool tx_pause, bool rx_pause) 2977 { 2978 struct ksz_device *dev = ds->priv; 2979 2980 if (dev->dev_ops->phylink_mac_link_up) 2981 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface, 2982 phydev, speed, duplex, 2983 tx_pause, rx_pause); 2984 } 2985 2986 static int ksz_switch_detect(struct ksz_device *dev) 2987 { 2988 u8 id1, id2, id4; 2989 u16 id16; 2990 u32 id32; 2991 int ret; 2992 2993 /* read chip id */ 2994 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 2995 if (ret) 2996 return ret; 2997 2998 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 2999 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 3000 3001 switch (id1) { 3002 case KSZ87_FAMILY_ID: 3003 if (id2 == KSZ87_CHIP_ID_95) { 3004 u8 val; 3005 3006 dev->chip_id = KSZ8795_CHIP_ID; 3007 3008 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 3009 if (val & KSZ8_PORT_FIBER_MODE) 3010 dev->chip_id = KSZ8765_CHIP_ID; 3011 } else if (id2 == KSZ87_CHIP_ID_94) { 3012 dev->chip_id = KSZ8794_CHIP_ID; 3013 } else { 3014 return -ENODEV; 3015 } 3016 break; 3017 case KSZ88_FAMILY_ID: 3018 if (id2 == KSZ88_CHIP_ID_63) 3019 dev->chip_id = KSZ8830_CHIP_ID; 3020 else 3021 return -ENODEV; 3022 break; 3023 default: 3024 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 3025 if (ret) 3026 return ret; 3027 3028 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 3029 id32 &= ~0xFF; 3030 3031 switch (id32) { 3032 case KSZ9477_CHIP_ID: 3033 case KSZ9896_CHIP_ID: 3034 case KSZ9897_CHIP_ID: 3035 case KSZ9567_CHIP_ID: 3036 case LAN9370_CHIP_ID: 3037 case LAN9371_CHIP_ID: 3038 case LAN9372_CHIP_ID: 3039 case LAN9373_CHIP_ID: 3040 case LAN9374_CHIP_ID: 3041 dev->chip_id = id32; 3042 break; 3043 case KSZ9893_CHIP_ID: 3044 ret = ksz_read8(dev, REG_CHIP_ID4, 3045 &id4); 3046 if (ret) 3047 return ret; 3048 3049 if (id4 == SKU_ID_KSZ8563) 3050 dev->chip_id = KSZ8563_CHIP_ID; 3051 else if (id4 == SKU_ID_KSZ9563) 3052 dev->chip_id = KSZ9563_CHIP_ID; 3053 else 3054 dev->chip_id = KSZ9893_CHIP_ID; 3055 3056 break; 3057 default: 3058 dev_err(dev->dev, 3059 "unsupported switch detected %x)\n", id32); 3060 return -ENODEV; 3061 } 3062 } 3063 return 0; 3064 } 3065 3066 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth 3067 * is converted to Hex-decimal using the successive multiplication method. On 3068 * every step, integer part is taken and decimal part is carry forwarded. 3069 */ 3070 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw) 3071 { 3072 u32 cinc = 0; 3073 u32 txrate; 3074 u32 rate; 3075 u8 temp; 3076 u8 i; 3077 3078 txrate = idle_slope - send_slope; 3079 3080 if (!txrate) 3081 return -EINVAL; 3082 3083 rate = idle_slope; 3084 3085 /* 24 bit register */ 3086 for (i = 0; i < 6; i++) { 3087 rate = rate * 16; 3088 3089 temp = rate / txrate; 3090 3091 rate %= txrate; 3092 3093 cinc = ((cinc << 4) | temp); 3094 } 3095 3096 *bw = cinc; 3097 3098 return 0; 3099 } 3100 3101 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler, 3102 u8 shaper) 3103 { 3104 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0, 3105 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) | 3106 FIELD_PREP(MTI_SHAPING_M, shaper)); 3107 } 3108 3109 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port, 3110 struct tc_cbs_qopt_offload *qopt) 3111 { 3112 struct ksz_device *dev = ds->priv; 3113 int ret; 3114 u32 bw; 3115 3116 if (!dev->info->tc_cbs_supported) 3117 return -EOPNOTSUPP; 3118 3119 if (qopt->queue > dev->info->num_tx_queues) 3120 return -EINVAL; 3121 3122 /* Queue Selection */ 3123 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue); 3124 if (ret) 3125 return ret; 3126 3127 if (!qopt->enable) 3128 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3129 MTI_SHAPING_OFF); 3130 3131 /* High Credit */ 3132 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK, 3133 qopt->hicredit); 3134 if (ret) 3135 return ret; 3136 3137 /* Low Credit */ 3138 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK, 3139 qopt->locredit); 3140 if (ret) 3141 return ret; 3142 3143 /* Credit Increment Register */ 3144 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw); 3145 if (ret) 3146 return ret; 3147 3148 if (dev->dev_ops->tc_cbs_set_cinc) { 3149 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw); 3150 if (ret) 3151 return ret; 3152 } 3153 3154 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3155 MTI_SHAPING_SRP); 3156 } 3157 3158 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port) 3159 { 3160 int queue, ret; 3161 3162 /* Configuration will not take effect until the last Port Queue X 3163 * Egress Limit Control Register is written. 3164 */ 3165 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3166 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue, 3167 KSZ9477_OUT_RATE_NO_LIMIT); 3168 if (ret) 3169 return ret; 3170 } 3171 3172 return 0; 3173 } 3174 3175 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p, 3176 int band) 3177 { 3178 /* Compared to queues, bands prioritize packets differently. In strict 3179 * priority mode, the lowest priority is assigned to Queue 0 while the 3180 * highest priority is given to Band 0. 3181 */ 3182 return p->bands - 1 - band; 3183 } 3184 3185 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue) 3186 { 3187 int ret; 3188 3189 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3190 if (ret) 3191 return ret; 3192 3193 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3194 MTI_SHAPING_OFF); 3195 } 3196 3197 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue, 3198 int weight) 3199 { 3200 int ret; 3201 3202 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3203 if (ret) 3204 return ret; 3205 3206 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3207 MTI_SHAPING_OFF); 3208 if (ret) 3209 return ret; 3210 3211 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight); 3212 } 3213 3214 static int ksz_tc_ets_add(struct ksz_device *dev, int port, 3215 struct tc_ets_qopt_offload_replace_params *p) 3216 { 3217 int ret, band, tc_prio; 3218 u32 queue_map = 0; 3219 3220 /* In order to ensure proper prioritization, it is necessary to set the 3221 * rate limit for the related queue to zero. Otherwise strict priority 3222 * or WRR mode will not work. This is a hardware limitation. 3223 */ 3224 ret = ksz_disable_egress_rate_limit(dev, port); 3225 if (ret) 3226 return ret; 3227 3228 /* Configure queue scheduling mode for all bands. Currently only strict 3229 * prio mode is supported. 3230 */ 3231 for (band = 0; band < p->bands; band++) { 3232 int queue = ksz_ets_band_to_queue(p, band); 3233 3234 ret = ksz_queue_set_strict(dev, port, queue); 3235 if (ret) 3236 return ret; 3237 } 3238 3239 /* Configure the mapping between traffic classes and queues. Note: 3240 * priomap variable support 16 traffic classes, but the chip can handle 3241 * only 8 classes. 3242 */ 3243 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) { 3244 int queue; 3245 3246 if (tc_prio > KSZ9477_MAX_TC_PRIO) 3247 break; 3248 3249 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]); 3250 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 3251 } 3252 3253 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3254 } 3255 3256 static int ksz_tc_ets_del(struct ksz_device *dev, int port) 3257 { 3258 int ret, queue, tc_prio, s; 3259 u32 queue_map = 0; 3260 3261 /* To restore the default chip configuration, set all queues to use the 3262 * WRR scheduler with a weight of 1. 3263 */ 3264 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3265 ret = ksz_queue_set_wrr(dev, port, queue, 3266 KSZ9477_DEFAULT_WRR_WEIGHT); 3267 if (ret) 3268 return ret; 3269 } 3270 3271 switch (dev->info->num_tx_queues) { 3272 case 2: 3273 s = 2; 3274 break; 3275 case 4: 3276 s = 1; 3277 break; 3278 case 8: 3279 s = 0; 3280 break; 3281 default: 3282 return -EINVAL; 3283 } 3284 3285 /* Revert the queue mapping for TC-priority to its default setting on 3286 * the chip. 3287 */ 3288 for (tc_prio = 0; tc_prio <= KSZ9477_MAX_TC_PRIO; tc_prio++) { 3289 int queue; 3290 3291 queue = tc_prio >> s; 3292 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 3293 } 3294 3295 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3296 } 3297 3298 static int ksz_tc_ets_validate(struct ksz_device *dev, int port, 3299 struct tc_ets_qopt_offload_replace_params *p) 3300 { 3301 int band; 3302 3303 /* Since it is not feasible to share one port among multiple qdisc, 3304 * the user must configure all available queues appropriately. 3305 */ 3306 if (p->bands != dev->info->num_tx_queues) { 3307 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n", 3308 dev->info->num_tx_queues); 3309 return -EOPNOTSUPP; 3310 } 3311 3312 for (band = 0; band < p->bands; ++band) { 3313 /* The KSZ switches utilize a weighted round robin configuration 3314 * where a certain number of packets can be transmitted from a 3315 * queue before the next queue is serviced. For more information 3316 * on this, refer to section 5.2.8.4 of the KSZ8565R 3317 * documentation on the Port Transmit Queue Control 1 Register. 3318 * However, the current ETS Qdisc implementation (as of February 3319 * 2023) assigns a weight to each queue based on the number of 3320 * bytes or extrapolated bandwidth in percentages. Since this 3321 * differs from the KSZ switches' method and we don't want to 3322 * fake support by converting bytes to packets, it is better to 3323 * return an error instead. 3324 */ 3325 if (p->quanta[band]) { 3326 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n"); 3327 return -EOPNOTSUPP; 3328 } 3329 } 3330 3331 return 0; 3332 } 3333 3334 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port, 3335 struct tc_ets_qopt_offload *qopt) 3336 { 3337 struct ksz_device *dev = ds->priv; 3338 int ret; 3339 3340 if (!dev->info->tc_ets_supported) 3341 return -EOPNOTSUPP; 3342 3343 if (qopt->parent != TC_H_ROOT) { 3344 dev_err(dev->dev, "Parent should be \"root\"\n"); 3345 return -EOPNOTSUPP; 3346 } 3347 3348 switch (qopt->command) { 3349 case TC_ETS_REPLACE: 3350 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params); 3351 if (ret) 3352 return ret; 3353 3354 return ksz_tc_ets_add(dev, port, &qopt->replace_params); 3355 case TC_ETS_DESTROY: 3356 return ksz_tc_ets_del(dev, port); 3357 case TC_ETS_STATS: 3358 case TC_ETS_GRAFT: 3359 return -EOPNOTSUPP; 3360 } 3361 3362 return -EOPNOTSUPP; 3363 } 3364 3365 static int ksz_setup_tc(struct dsa_switch *ds, int port, 3366 enum tc_setup_type type, void *type_data) 3367 { 3368 switch (type) { 3369 case TC_SETUP_QDISC_CBS: 3370 return ksz_setup_tc_cbs(ds, port, type_data); 3371 case TC_SETUP_QDISC_ETS: 3372 return ksz_tc_setup_qdisc_ets(ds, port, type_data); 3373 default: 3374 return -EOPNOTSUPP; 3375 } 3376 } 3377 3378 static const struct dsa_switch_ops ksz_switch_ops = { 3379 .get_tag_protocol = ksz_get_tag_protocol, 3380 .connect_tag_protocol = ksz_connect_tag_protocol, 3381 .get_phy_flags = ksz_get_phy_flags, 3382 .setup = ksz_setup, 3383 .teardown = ksz_teardown, 3384 .phy_read = ksz_phy_read16, 3385 .phy_write = ksz_phy_write16, 3386 .phylink_get_caps = ksz_phylink_get_caps, 3387 .phylink_mac_config = ksz_phylink_mac_config, 3388 .phylink_mac_link_up = ksz_phylink_mac_link_up, 3389 .phylink_mac_link_down = ksz_mac_link_down, 3390 .port_enable = ksz_enable_port, 3391 .set_ageing_time = ksz_set_ageing_time, 3392 .get_strings = ksz_get_strings, 3393 .get_ethtool_stats = ksz_get_ethtool_stats, 3394 .get_sset_count = ksz_sset_count, 3395 .port_bridge_join = ksz_port_bridge_join, 3396 .port_bridge_leave = ksz_port_bridge_leave, 3397 .port_stp_state_set = ksz_port_stp_state_set, 3398 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 3399 .port_bridge_flags = ksz_port_bridge_flags, 3400 .port_fast_age = ksz_port_fast_age, 3401 .port_vlan_filtering = ksz_port_vlan_filtering, 3402 .port_vlan_add = ksz_port_vlan_add, 3403 .port_vlan_del = ksz_port_vlan_del, 3404 .port_fdb_dump = ksz_port_fdb_dump, 3405 .port_fdb_add = ksz_port_fdb_add, 3406 .port_fdb_del = ksz_port_fdb_del, 3407 .port_mdb_add = ksz_port_mdb_add, 3408 .port_mdb_del = ksz_port_mdb_del, 3409 .port_mirror_add = ksz_port_mirror_add, 3410 .port_mirror_del = ksz_port_mirror_del, 3411 .get_stats64 = ksz_get_stats64, 3412 .get_pause_stats = ksz_get_pause_stats, 3413 .port_change_mtu = ksz_change_mtu, 3414 .port_max_mtu = ksz_max_mtu, 3415 .get_ts_info = ksz_get_ts_info, 3416 .port_hwtstamp_get = ksz_hwtstamp_get, 3417 .port_hwtstamp_set = ksz_hwtstamp_set, 3418 .port_txtstamp = ksz_port_txtstamp, 3419 .port_rxtstamp = ksz_port_rxtstamp, 3420 .port_setup_tc = ksz_setup_tc, 3421 .get_mac_eee = ksz_get_mac_eee, 3422 .set_mac_eee = ksz_set_mac_eee, 3423 }; 3424 3425 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 3426 { 3427 struct dsa_switch *ds; 3428 struct ksz_device *swdev; 3429 3430 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 3431 if (!ds) 3432 return NULL; 3433 3434 ds->dev = base; 3435 ds->num_ports = DSA_MAX_PORTS; 3436 ds->ops = &ksz_switch_ops; 3437 3438 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 3439 if (!swdev) 3440 return NULL; 3441 3442 ds->priv = swdev; 3443 swdev->dev = base; 3444 3445 swdev->ds = ds; 3446 swdev->priv = priv; 3447 3448 return swdev; 3449 } 3450 EXPORT_SYMBOL(ksz_switch_alloc); 3451 3452 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 3453 struct device_node *port_dn) 3454 { 3455 phy_interface_t phy_mode = dev->ports[port_num].interface; 3456 int rx_delay = -1, tx_delay = -1; 3457 3458 if (!phy_interface_mode_is_rgmii(phy_mode)) 3459 return; 3460 3461 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 3462 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 3463 3464 if (rx_delay == -1 && tx_delay == -1) { 3465 dev_warn(dev->dev, 3466 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 3467 "please update device tree to specify \"rx-internal-delay-ps\" and " 3468 "\"tx-internal-delay-ps\"", 3469 port_num); 3470 3471 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 3472 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 3473 rx_delay = 2000; 3474 3475 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 3476 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 3477 tx_delay = 2000; 3478 } 3479 3480 if (rx_delay < 0) 3481 rx_delay = 0; 3482 if (tx_delay < 0) 3483 tx_delay = 0; 3484 3485 dev->ports[port_num].rgmii_rx_val = rx_delay; 3486 dev->ports[port_num].rgmii_tx_val = tx_delay; 3487 } 3488 3489 int ksz_switch_register(struct ksz_device *dev) 3490 { 3491 const struct ksz_chip_data *info; 3492 struct device_node *port, *ports; 3493 phy_interface_t interface; 3494 unsigned int port_num; 3495 int ret; 3496 int i; 3497 3498 if (dev->pdata) 3499 dev->chip_id = dev->pdata->chip_id; 3500 3501 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 3502 GPIOD_OUT_LOW); 3503 if (IS_ERR(dev->reset_gpio)) 3504 return PTR_ERR(dev->reset_gpio); 3505 3506 if (dev->reset_gpio) { 3507 gpiod_set_value_cansleep(dev->reset_gpio, 1); 3508 usleep_range(10000, 12000); 3509 gpiod_set_value_cansleep(dev->reset_gpio, 0); 3510 msleep(100); 3511 } 3512 3513 mutex_init(&dev->dev_mutex); 3514 mutex_init(&dev->regmap_mutex); 3515 mutex_init(&dev->alu_mutex); 3516 mutex_init(&dev->vlan_mutex); 3517 3518 ret = ksz_switch_detect(dev); 3519 if (ret) 3520 return ret; 3521 3522 info = ksz_lookup_info(dev->chip_id); 3523 if (!info) 3524 return -ENODEV; 3525 3526 /* Update the compatible info with the probed one */ 3527 dev->info = info; 3528 3529 dev_info(dev->dev, "found switch: %s, rev %i\n", 3530 dev->info->dev_name, dev->chip_rev); 3531 3532 ret = ksz_check_device_id(dev); 3533 if (ret) 3534 return ret; 3535 3536 dev->dev_ops = dev->info->ops; 3537 3538 ret = dev->dev_ops->init(dev); 3539 if (ret) 3540 return ret; 3541 3542 dev->ports = devm_kzalloc(dev->dev, 3543 dev->info->port_cnt * sizeof(struct ksz_port), 3544 GFP_KERNEL); 3545 if (!dev->ports) 3546 return -ENOMEM; 3547 3548 for (i = 0; i < dev->info->port_cnt; i++) { 3549 spin_lock_init(&dev->ports[i].mib.stats64_lock); 3550 mutex_init(&dev->ports[i].mib.cnt_mutex); 3551 dev->ports[i].mib.counters = 3552 devm_kzalloc(dev->dev, 3553 sizeof(u64) * (dev->info->mib_cnt + 1), 3554 GFP_KERNEL); 3555 if (!dev->ports[i].mib.counters) 3556 return -ENOMEM; 3557 3558 dev->ports[i].ksz_dev = dev; 3559 dev->ports[i].num = i; 3560 } 3561 3562 /* set the real number of ports */ 3563 dev->ds->num_ports = dev->info->port_cnt; 3564 3565 /* Host port interface will be self detected, or specifically set in 3566 * device tree. 3567 */ 3568 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 3569 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 3570 if (dev->dev->of_node) { 3571 ret = of_get_phy_mode(dev->dev->of_node, &interface); 3572 if (ret == 0) 3573 dev->compat_interface = interface; 3574 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 3575 if (!ports) 3576 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 3577 if (ports) { 3578 for_each_available_child_of_node(ports, port) { 3579 if (of_property_read_u32(port, "reg", 3580 &port_num)) 3581 continue; 3582 if (!(dev->port_mask & BIT(port_num))) { 3583 of_node_put(port); 3584 of_node_put(ports); 3585 return -EINVAL; 3586 } 3587 of_get_phy_mode(port, 3588 &dev->ports[port_num].interface); 3589 3590 ksz_parse_rgmii_delay(dev, port_num, port); 3591 } 3592 of_node_put(ports); 3593 } 3594 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 3595 "microchip,synclko-125"); 3596 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 3597 "microchip,synclko-disable"); 3598 if (dev->synclko_125 && dev->synclko_disable) { 3599 dev_err(dev->dev, "inconsistent synclko settings\n"); 3600 return -EINVAL; 3601 } 3602 } 3603 3604 ret = dsa_register_switch(dev->ds); 3605 if (ret) { 3606 dev->dev_ops->exit(dev); 3607 return ret; 3608 } 3609 3610 /* Read MIB counters every 30 seconds to avoid overflow. */ 3611 dev->mib_read_interval = msecs_to_jiffies(5000); 3612 3613 /* Start the MIB timer. */ 3614 schedule_delayed_work(&dev->mib_read, 0); 3615 3616 return ret; 3617 } 3618 EXPORT_SYMBOL(ksz_switch_register); 3619 3620 void ksz_switch_remove(struct ksz_device *dev) 3621 { 3622 /* timer started */ 3623 if (dev->mib_read_interval) { 3624 dev->mib_read_interval = 0; 3625 cancel_delayed_work_sync(&dev->mib_read); 3626 } 3627 3628 dev->dev_ops->exit(dev); 3629 dsa_unregister_switch(dev->ds); 3630 3631 if (dev->reset_gpio) 3632 gpiod_set_value_cansleep(dev->reset_gpio, 1); 3633 3634 } 3635 EXPORT_SYMBOL(ksz_switch_remove); 3636 3637 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 3638 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 3639 MODULE_LICENSE("GPL"); 3640