1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/dsa/ksz_common.h> 10 #include <linux/export.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/platform_data/microchip-ksz.h> 15 #include <linux/phy.h> 16 #include <linux/etherdevice.h> 17 #include <linux/if_bridge.h> 18 #include <linux/if_vlan.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/of_mdio.h> 22 #include <linux/of_device.h> 23 #include <linux/of_net.h> 24 #include <linux/micrel_phy.h> 25 #include <net/dsa.h> 26 #include <net/pkt_cls.h> 27 #include <net/switchdev.h> 28 29 #include "ksz_common.h" 30 #include "ksz_ptp.h" 31 #include "ksz8.h" 32 #include "ksz9477.h" 33 #include "lan937x.h" 34 35 #define MIB_COUNTER_NUM 0x20 36 37 struct ksz_stats_raw { 38 u64 rx_hi; 39 u64 rx_undersize; 40 u64 rx_fragments; 41 u64 rx_oversize; 42 u64 rx_jabbers; 43 u64 rx_symbol_err; 44 u64 rx_crc_err; 45 u64 rx_align_err; 46 u64 rx_mac_ctrl; 47 u64 rx_pause; 48 u64 rx_bcast; 49 u64 rx_mcast; 50 u64 rx_ucast; 51 u64 rx_64_or_less; 52 u64 rx_65_127; 53 u64 rx_128_255; 54 u64 rx_256_511; 55 u64 rx_512_1023; 56 u64 rx_1024_1522; 57 u64 rx_1523_2000; 58 u64 rx_2001; 59 u64 tx_hi; 60 u64 tx_late_col; 61 u64 tx_pause; 62 u64 tx_bcast; 63 u64 tx_mcast; 64 u64 tx_ucast; 65 u64 tx_deferred; 66 u64 tx_total_col; 67 u64 tx_exc_col; 68 u64 tx_single_col; 69 u64 tx_mult_col; 70 u64 rx_total; 71 u64 tx_total; 72 u64 rx_discards; 73 u64 tx_discards; 74 }; 75 76 struct ksz88xx_stats_raw { 77 u64 rx; 78 u64 rx_hi; 79 u64 rx_undersize; 80 u64 rx_fragments; 81 u64 rx_oversize; 82 u64 rx_jabbers; 83 u64 rx_symbol_err; 84 u64 rx_crc_err; 85 u64 rx_align_err; 86 u64 rx_mac_ctrl; 87 u64 rx_pause; 88 u64 rx_bcast; 89 u64 rx_mcast; 90 u64 rx_ucast; 91 u64 rx_64_or_less; 92 u64 rx_65_127; 93 u64 rx_128_255; 94 u64 rx_256_511; 95 u64 rx_512_1023; 96 u64 rx_1024_1522; 97 u64 tx; 98 u64 tx_hi; 99 u64 tx_late_col; 100 u64 tx_pause; 101 u64 tx_bcast; 102 u64 tx_mcast; 103 u64 tx_ucast; 104 u64 tx_deferred; 105 u64 tx_total_col; 106 u64 tx_exc_col; 107 u64 tx_single_col; 108 u64 tx_mult_col; 109 u64 rx_discards; 110 u64 tx_discards; 111 }; 112 113 static const struct ksz_mib_names ksz88xx_mib_names[] = { 114 { 0x00, "rx" }, 115 { 0x01, "rx_hi" }, 116 { 0x02, "rx_undersize" }, 117 { 0x03, "rx_fragments" }, 118 { 0x04, "rx_oversize" }, 119 { 0x05, "rx_jabbers" }, 120 { 0x06, "rx_symbol_err" }, 121 { 0x07, "rx_crc_err" }, 122 { 0x08, "rx_align_err" }, 123 { 0x09, "rx_mac_ctrl" }, 124 { 0x0a, "rx_pause" }, 125 { 0x0b, "rx_bcast" }, 126 { 0x0c, "rx_mcast" }, 127 { 0x0d, "rx_ucast" }, 128 { 0x0e, "rx_64_or_less" }, 129 { 0x0f, "rx_65_127" }, 130 { 0x10, "rx_128_255" }, 131 { 0x11, "rx_256_511" }, 132 { 0x12, "rx_512_1023" }, 133 { 0x13, "rx_1024_1522" }, 134 { 0x14, "tx" }, 135 { 0x15, "tx_hi" }, 136 { 0x16, "tx_late_col" }, 137 { 0x17, "tx_pause" }, 138 { 0x18, "tx_bcast" }, 139 { 0x19, "tx_mcast" }, 140 { 0x1a, "tx_ucast" }, 141 { 0x1b, "tx_deferred" }, 142 { 0x1c, "tx_total_col" }, 143 { 0x1d, "tx_exc_col" }, 144 { 0x1e, "tx_single_col" }, 145 { 0x1f, "tx_mult_col" }, 146 { 0x100, "rx_discards" }, 147 { 0x101, "tx_discards" }, 148 }; 149 150 static const struct ksz_mib_names ksz9477_mib_names[] = { 151 { 0x00, "rx_hi" }, 152 { 0x01, "rx_undersize" }, 153 { 0x02, "rx_fragments" }, 154 { 0x03, "rx_oversize" }, 155 { 0x04, "rx_jabbers" }, 156 { 0x05, "rx_symbol_err" }, 157 { 0x06, "rx_crc_err" }, 158 { 0x07, "rx_align_err" }, 159 { 0x08, "rx_mac_ctrl" }, 160 { 0x09, "rx_pause" }, 161 { 0x0A, "rx_bcast" }, 162 { 0x0B, "rx_mcast" }, 163 { 0x0C, "rx_ucast" }, 164 { 0x0D, "rx_64_or_less" }, 165 { 0x0E, "rx_65_127" }, 166 { 0x0F, "rx_128_255" }, 167 { 0x10, "rx_256_511" }, 168 { 0x11, "rx_512_1023" }, 169 { 0x12, "rx_1024_1522" }, 170 { 0x13, "rx_1523_2000" }, 171 { 0x14, "rx_2001" }, 172 { 0x15, "tx_hi" }, 173 { 0x16, "tx_late_col" }, 174 { 0x17, "tx_pause" }, 175 { 0x18, "tx_bcast" }, 176 { 0x19, "tx_mcast" }, 177 { 0x1A, "tx_ucast" }, 178 { 0x1B, "tx_deferred" }, 179 { 0x1C, "tx_total_col" }, 180 { 0x1D, "tx_exc_col" }, 181 { 0x1E, "tx_single_col" }, 182 { 0x1F, "tx_mult_col" }, 183 { 0x80, "rx_total" }, 184 { 0x81, "tx_total" }, 185 { 0x82, "rx_discards" }, 186 { 0x83, "tx_discards" }, 187 }; 188 189 static const struct ksz_dev_ops ksz8_dev_ops = { 190 .setup = ksz8_setup, 191 .get_port_addr = ksz8_get_port_addr, 192 .cfg_port_member = ksz8_cfg_port_member, 193 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 194 .port_setup = ksz8_port_setup, 195 .r_phy = ksz8_r_phy, 196 .w_phy = ksz8_w_phy, 197 .r_mib_cnt = ksz8_r_mib_cnt, 198 .r_mib_pkt = ksz8_r_mib_pkt, 199 .r_mib_stat64 = ksz88xx_r_mib_stats64, 200 .freeze_mib = ksz8_freeze_mib, 201 .port_init_cnt = ksz8_port_init_cnt, 202 .fdb_dump = ksz8_fdb_dump, 203 .fdb_add = ksz8_fdb_add, 204 .fdb_del = ksz8_fdb_del, 205 .mdb_add = ksz8_mdb_add, 206 .mdb_del = ksz8_mdb_del, 207 .vlan_filtering = ksz8_port_vlan_filtering, 208 .vlan_add = ksz8_port_vlan_add, 209 .vlan_del = ksz8_port_vlan_del, 210 .mirror_add = ksz8_port_mirror_add, 211 .mirror_del = ksz8_port_mirror_del, 212 .get_caps = ksz8_get_caps, 213 .config_cpu_port = ksz8_config_cpu_port, 214 .enable_stp_addr = ksz8_enable_stp_addr, 215 .reset = ksz8_reset_switch, 216 .init = ksz8_switch_init, 217 .exit = ksz8_switch_exit, 218 .change_mtu = ksz8_change_mtu, 219 }; 220 221 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, 222 unsigned int mode, 223 phy_interface_t interface, 224 struct phy_device *phydev, int speed, 225 int duplex, bool tx_pause, 226 bool rx_pause); 227 228 static const struct ksz_dev_ops ksz9477_dev_ops = { 229 .setup = ksz9477_setup, 230 .get_port_addr = ksz9477_get_port_addr, 231 .cfg_port_member = ksz9477_cfg_port_member, 232 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 233 .port_setup = ksz9477_port_setup, 234 .set_ageing_time = ksz9477_set_ageing_time, 235 .r_phy = ksz9477_r_phy, 236 .w_phy = ksz9477_w_phy, 237 .r_mib_cnt = ksz9477_r_mib_cnt, 238 .r_mib_pkt = ksz9477_r_mib_pkt, 239 .r_mib_stat64 = ksz_r_mib_stats64, 240 .freeze_mib = ksz9477_freeze_mib, 241 .port_init_cnt = ksz9477_port_init_cnt, 242 .vlan_filtering = ksz9477_port_vlan_filtering, 243 .vlan_add = ksz9477_port_vlan_add, 244 .vlan_del = ksz9477_port_vlan_del, 245 .mirror_add = ksz9477_port_mirror_add, 246 .mirror_del = ksz9477_port_mirror_del, 247 .get_caps = ksz9477_get_caps, 248 .fdb_dump = ksz9477_fdb_dump, 249 .fdb_add = ksz9477_fdb_add, 250 .fdb_del = ksz9477_fdb_del, 251 .mdb_add = ksz9477_mdb_add, 252 .mdb_del = ksz9477_mdb_del, 253 .change_mtu = ksz9477_change_mtu, 254 .phylink_mac_link_up = ksz9477_phylink_mac_link_up, 255 .config_cpu_port = ksz9477_config_cpu_port, 256 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc, 257 .enable_stp_addr = ksz9477_enable_stp_addr, 258 .reset = ksz9477_reset_switch, 259 .init = ksz9477_switch_init, 260 .exit = ksz9477_switch_exit, 261 }; 262 263 static const struct ksz_dev_ops lan937x_dev_ops = { 264 .setup = lan937x_setup, 265 .teardown = lan937x_teardown, 266 .get_port_addr = ksz9477_get_port_addr, 267 .cfg_port_member = ksz9477_cfg_port_member, 268 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 269 .port_setup = lan937x_port_setup, 270 .set_ageing_time = lan937x_set_ageing_time, 271 .r_phy = lan937x_r_phy, 272 .w_phy = lan937x_w_phy, 273 .r_mib_cnt = ksz9477_r_mib_cnt, 274 .r_mib_pkt = ksz9477_r_mib_pkt, 275 .r_mib_stat64 = ksz_r_mib_stats64, 276 .freeze_mib = ksz9477_freeze_mib, 277 .port_init_cnt = ksz9477_port_init_cnt, 278 .vlan_filtering = ksz9477_port_vlan_filtering, 279 .vlan_add = ksz9477_port_vlan_add, 280 .vlan_del = ksz9477_port_vlan_del, 281 .mirror_add = ksz9477_port_mirror_add, 282 .mirror_del = ksz9477_port_mirror_del, 283 .get_caps = lan937x_phylink_get_caps, 284 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 285 .fdb_dump = ksz9477_fdb_dump, 286 .fdb_add = ksz9477_fdb_add, 287 .fdb_del = ksz9477_fdb_del, 288 .mdb_add = ksz9477_mdb_add, 289 .mdb_del = ksz9477_mdb_del, 290 .change_mtu = lan937x_change_mtu, 291 .phylink_mac_link_up = ksz9477_phylink_mac_link_up, 292 .config_cpu_port = lan937x_config_cpu_port, 293 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc, 294 .enable_stp_addr = ksz9477_enable_stp_addr, 295 .reset = lan937x_reset_switch, 296 .init = lan937x_switch_init, 297 .exit = lan937x_switch_exit, 298 }; 299 300 static const u16 ksz8795_regs[] = { 301 [REG_IND_CTRL_0] = 0x6E, 302 [REG_IND_DATA_8] = 0x70, 303 [REG_IND_DATA_CHECK] = 0x72, 304 [REG_IND_DATA_HI] = 0x71, 305 [REG_IND_DATA_LO] = 0x75, 306 [REG_IND_MIB_CHECK] = 0x74, 307 [REG_IND_BYTE] = 0xA0, 308 [P_FORCE_CTRL] = 0x0C, 309 [P_LINK_STATUS] = 0x0E, 310 [P_LOCAL_CTRL] = 0x07, 311 [P_NEG_RESTART_CTRL] = 0x0D, 312 [P_REMOTE_STATUS] = 0x08, 313 [P_SPEED_STATUS] = 0x09, 314 [S_TAIL_TAG_CTRL] = 0x0C, 315 [P_STP_CTRL] = 0x02, 316 [S_START_CTRL] = 0x01, 317 [S_BROADCAST_CTRL] = 0x06, 318 [S_MULTICAST_CTRL] = 0x04, 319 [P_XMII_CTRL_0] = 0x06, 320 [P_XMII_CTRL_1] = 0x06, 321 }; 322 323 static const u32 ksz8795_masks[] = { 324 [PORT_802_1P_REMAPPING] = BIT(7), 325 [SW_TAIL_TAG_ENABLE] = BIT(1), 326 [MIB_COUNTER_OVERFLOW] = BIT(6), 327 [MIB_COUNTER_VALID] = BIT(5), 328 [VLAN_TABLE_FID] = GENMASK(6, 0), 329 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 330 [VLAN_TABLE_VALID] = BIT(12), 331 [STATIC_MAC_TABLE_VALID] = BIT(21), 332 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 333 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 334 [STATIC_MAC_TABLE_OVERRIDE] = BIT(26), 335 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(24, 20), 336 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 337 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(8), 338 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 339 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 340 [DYNAMIC_MAC_TABLE_FID] = GENMASK(26, 20), 341 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 342 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 343 [P_MII_TX_FLOW_CTRL] = BIT(5), 344 [P_MII_RX_FLOW_CTRL] = BIT(5), 345 }; 346 347 static const u8 ksz8795_xmii_ctrl0[] = { 348 [P_MII_100MBIT] = 0, 349 [P_MII_10MBIT] = 1, 350 [P_MII_FULL_DUPLEX] = 0, 351 [P_MII_HALF_DUPLEX] = 1, 352 }; 353 354 static const u8 ksz8795_xmii_ctrl1[] = { 355 [P_RGMII_SEL] = 3, 356 [P_GMII_SEL] = 2, 357 [P_RMII_SEL] = 1, 358 [P_MII_SEL] = 0, 359 [P_GMII_1GBIT] = 1, 360 [P_GMII_NOT_1GBIT] = 0, 361 }; 362 363 static const u8 ksz8795_shifts[] = { 364 [VLAN_TABLE_MEMBERSHIP_S] = 7, 365 [VLAN_TABLE] = 16, 366 [STATIC_MAC_FWD_PORTS] = 16, 367 [STATIC_MAC_FID] = 24, 368 [DYNAMIC_MAC_ENTRIES_H] = 3, 369 [DYNAMIC_MAC_ENTRIES] = 29, 370 [DYNAMIC_MAC_FID] = 16, 371 [DYNAMIC_MAC_TIMESTAMP] = 27, 372 [DYNAMIC_MAC_SRC_PORT] = 24, 373 }; 374 375 static const u16 ksz8863_regs[] = { 376 [REG_IND_CTRL_0] = 0x79, 377 [REG_IND_DATA_8] = 0x7B, 378 [REG_IND_DATA_CHECK] = 0x7B, 379 [REG_IND_DATA_HI] = 0x7C, 380 [REG_IND_DATA_LO] = 0x80, 381 [REG_IND_MIB_CHECK] = 0x80, 382 [P_FORCE_CTRL] = 0x0C, 383 [P_LINK_STATUS] = 0x0E, 384 [P_LOCAL_CTRL] = 0x0C, 385 [P_NEG_RESTART_CTRL] = 0x0D, 386 [P_REMOTE_STATUS] = 0x0E, 387 [P_SPEED_STATUS] = 0x0F, 388 [S_TAIL_TAG_CTRL] = 0x03, 389 [P_STP_CTRL] = 0x02, 390 [S_START_CTRL] = 0x01, 391 [S_BROADCAST_CTRL] = 0x06, 392 [S_MULTICAST_CTRL] = 0x04, 393 }; 394 395 static const u32 ksz8863_masks[] = { 396 [PORT_802_1P_REMAPPING] = BIT(3), 397 [SW_TAIL_TAG_ENABLE] = BIT(6), 398 [MIB_COUNTER_OVERFLOW] = BIT(7), 399 [MIB_COUNTER_VALID] = BIT(6), 400 [VLAN_TABLE_FID] = GENMASK(15, 12), 401 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 402 [VLAN_TABLE_VALID] = BIT(19), 403 [STATIC_MAC_TABLE_VALID] = BIT(19), 404 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 405 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), 406 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 407 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 408 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), 409 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), 410 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 411 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), 412 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 413 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 414 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 415 }; 416 417 static u8 ksz8863_shifts[] = { 418 [VLAN_TABLE_MEMBERSHIP_S] = 16, 419 [STATIC_MAC_FWD_PORTS] = 16, 420 [STATIC_MAC_FID] = 22, 421 [DYNAMIC_MAC_ENTRIES_H] = 8, 422 [DYNAMIC_MAC_ENTRIES] = 24, 423 [DYNAMIC_MAC_FID] = 16, 424 [DYNAMIC_MAC_TIMESTAMP] = 22, 425 [DYNAMIC_MAC_SRC_PORT] = 20, 426 }; 427 428 static const u16 ksz9477_regs[] = { 429 [P_STP_CTRL] = 0x0B04, 430 [S_START_CTRL] = 0x0300, 431 [S_BROADCAST_CTRL] = 0x0332, 432 [S_MULTICAST_CTRL] = 0x0331, 433 [P_XMII_CTRL_0] = 0x0300, 434 [P_XMII_CTRL_1] = 0x0301, 435 }; 436 437 static const u32 ksz9477_masks[] = { 438 [ALU_STAT_WRITE] = 0, 439 [ALU_STAT_READ] = 1, 440 [P_MII_TX_FLOW_CTRL] = BIT(5), 441 [P_MII_RX_FLOW_CTRL] = BIT(3), 442 }; 443 444 static const u8 ksz9477_shifts[] = { 445 [ALU_STAT_INDEX] = 16, 446 }; 447 448 static const u8 ksz9477_xmii_ctrl0[] = { 449 [P_MII_100MBIT] = 1, 450 [P_MII_10MBIT] = 0, 451 [P_MII_FULL_DUPLEX] = 1, 452 [P_MII_HALF_DUPLEX] = 0, 453 }; 454 455 static const u8 ksz9477_xmii_ctrl1[] = { 456 [P_RGMII_SEL] = 0, 457 [P_RMII_SEL] = 1, 458 [P_GMII_SEL] = 2, 459 [P_MII_SEL] = 3, 460 [P_GMII_1GBIT] = 0, 461 [P_GMII_NOT_1GBIT] = 1, 462 }; 463 464 static const u32 lan937x_masks[] = { 465 [ALU_STAT_WRITE] = 1, 466 [ALU_STAT_READ] = 2, 467 [P_MII_TX_FLOW_CTRL] = BIT(5), 468 [P_MII_RX_FLOW_CTRL] = BIT(3), 469 }; 470 471 static const u8 lan937x_shifts[] = { 472 [ALU_STAT_INDEX] = 8, 473 }; 474 475 static const struct regmap_range ksz8563_valid_regs[] = { 476 regmap_reg_range(0x0000, 0x0003), 477 regmap_reg_range(0x0006, 0x0006), 478 regmap_reg_range(0x000f, 0x001f), 479 regmap_reg_range(0x0100, 0x0100), 480 regmap_reg_range(0x0104, 0x0107), 481 regmap_reg_range(0x010d, 0x010d), 482 regmap_reg_range(0x0110, 0x0113), 483 regmap_reg_range(0x0120, 0x012b), 484 regmap_reg_range(0x0201, 0x0201), 485 regmap_reg_range(0x0210, 0x0213), 486 regmap_reg_range(0x0300, 0x0300), 487 regmap_reg_range(0x0302, 0x031b), 488 regmap_reg_range(0x0320, 0x032b), 489 regmap_reg_range(0x0330, 0x0336), 490 regmap_reg_range(0x0338, 0x033e), 491 regmap_reg_range(0x0340, 0x035f), 492 regmap_reg_range(0x0370, 0x0370), 493 regmap_reg_range(0x0378, 0x0378), 494 regmap_reg_range(0x037c, 0x037d), 495 regmap_reg_range(0x0390, 0x0393), 496 regmap_reg_range(0x0400, 0x040e), 497 regmap_reg_range(0x0410, 0x042f), 498 regmap_reg_range(0x0500, 0x0519), 499 regmap_reg_range(0x0520, 0x054b), 500 regmap_reg_range(0x0550, 0x05b3), 501 502 /* port 1 */ 503 regmap_reg_range(0x1000, 0x1001), 504 regmap_reg_range(0x1004, 0x100b), 505 regmap_reg_range(0x1013, 0x1013), 506 regmap_reg_range(0x1017, 0x1017), 507 regmap_reg_range(0x101b, 0x101b), 508 regmap_reg_range(0x101f, 0x1021), 509 regmap_reg_range(0x1030, 0x1030), 510 regmap_reg_range(0x1100, 0x1111), 511 regmap_reg_range(0x111a, 0x111d), 512 regmap_reg_range(0x1122, 0x1127), 513 regmap_reg_range(0x112a, 0x112b), 514 regmap_reg_range(0x1136, 0x1139), 515 regmap_reg_range(0x113e, 0x113f), 516 regmap_reg_range(0x1400, 0x1401), 517 regmap_reg_range(0x1403, 0x1403), 518 regmap_reg_range(0x1410, 0x1417), 519 regmap_reg_range(0x1420, 0x1423), 520 regmap_reg_range(0x1500, 0x1507), 521 regmap_reg_range(0x1600, 0x1612), 522 regmap_reg_range(0x1800, 0x180f), 523 regmap_reg_range(0x1900, 0x1907), 524 regmap_reg_range(0x1914, 0x191b), 525 regmap_reg_range(0x1a00, 0x1a03), 526 regmap_reg_range(0x1a04, 0x1a08), 527 regmap_reg_range(0x1b00, 0x1b01), 528 regmap_reg_range(0x1b04, 0x1b04), 529 regmap_reg_range(0x1c00, 0x1c05), 530 regmap_reg_range(0x1c08, 0x1c1b), 531 532 /* port 2 */ 533 regmap_reg_range(0x2000, 0x2001), 534 regmap_reg_range(0x2004, 0x200b), 535 regmap_reg_range(0x2013, 0x2013), 536 regmap_reg_range(0x2017, 0x2017), 537 regmap_reg_range(0x201b, 0x201b), 538 regmap_reg_range(0x201f, 0x2021), 539 regmap_reg_range(0x2030, 0x2030), 540 regmap_reg_range(0x2100, 0x2111), 541 regmap_reg_range(0x211a, 0x211d), 542 regmap_reg_range(0x2122, 0x2127), 543 regmap_reg_range(0x212a, 0x212b), 544 regmap_reg_range(0x2136, 0x2139), 545 regmap_reg_range(0x213e, 0x213f), 546 regmap_reg_range(0x2400, 0x2401), 547 regmap_reg_range(0x2403, 0x2403), 548 regmap_reg_range(0x2410, 0x2417), 549 regmap_reg_range(0x2420, 0x2423), 550 regmap_reg_range(0x2500, 0x2507), 551 regmap_reg_range(0x2600, 0x2612), 552 regmap_reg_range(0x2800, 0x280f), 553 regmap_reg_range(0x2900, 0x2907), 554 regmap_reg_range(0x2914, 0x291b), 555 regmap_reg_range(0x2a00, 0x2a03), 556 regmap_reg_range(0x2a04, 0x2a08), 557 regmap_reg_range(0x2b00, 0x2b01), 558 regmap_reg_range(0x2b04, 0x2b04), 559 regmap_reg_range(0x2c00, 0x2c05), 560 regmap_reg_range(0x2c08, 0x2c1b), 561 562 /* port 3 */ 563 regmap_reg_range(0x3000, 0x3001), 564 regmap_reg_range(0x3004, 0x300b), 565 regmap_reg_range(0x3013, 0x3013), 566 regmap_reg_range(0x3017, 0x3017), 567 regmap_reg_range(0x301b, 0x301b), 568 regmap_reg_range(0x301f, 0x3021), 569 regmap_reg_range(0x3030, 0x3030), 570 regmap_reg_range(0x3300, 0x3301), 571 regmap_reg_range(0x3303, 0x3303), 572 regmap_reg_range(0x3400, 0x3401), 573 regmap_reg_range(0x3403, 0x3403), 574 regmap_reg_range(0x3410, 0x3417), 575 regmap_reg_range(0x3420, 0x3423), 576 regmap_reg_range(0x3500, 0x3507), 577 regmap_reg_range(0x3600, 0x3612), 578 regmap_reg_range(0x3800, 0x380f), 579 regmap_reg_range(0x3900, 0x3907), 580 regmap_reg_range(0x3914, 0x391b), 581 regmap_reg_range(0x3a00, 0x3a03), 582 regmap_reg_range(0x3a04, 0x3a08), 583 regmap_reg_range(0x3b00, 0x3b01), 584 regmap_reg_range(0x3b04, 0x3b04), 585 regmap_reg_range(0x3c00, 0x3c05), 586 regmap_reg_range(0x3c08, 0x3c1b), 587 }; 588 589 static const struct regmap_access_table ksz8563_register_set = { 590 .yes_ranges = ksz8563_valid_regs, 591 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), 592 }; 593 594 static const struct regmap_range ksz9477_valid_regs[] = { 595 regmap_reg_range(0x0000, 0x0003), 596 regmap_reg_range(0x0006, 0x0006), 597 regmap_reg_range(0x0010, 0x001f), 598 regmap_reg_range(0x0100, 0x0100), 599 regmap_reg_range(0x0103, 0x0107), 600 regmap_reg_range(0x010d, 0x010d), 601 regmap_reg_range(0x0110, 0x0113), 602 regmap_reg_range(0x0120, 0x012b), 603 regmap_reg_range(0x0201, 0x0201), 604 regmap_reg_range(0x0210, 0x0213), 605 regmap_reg_range(0x0300, 0x0300), 606 regmap_reg_range(0x0302, 0x031b), 607 regmap_reg_range(0x0320, 0x032b), 608 regmap_reg_range(0x0330, 0x0336), 609 regmap_reg_range(0x0338, 0x033b), 610 regmap_reg_range(0x033e, 0x033e), 611 regmap_reg_range(0x0340, 0x035f), 612 regmap_reg_range(0x0370, 0x0370), 613 regmap_reg_range(0x0378, 0x0378), 614 regmap_reg_range(0x037c, 0x037d), 615 regmap_reg_range(0x0390, 0x0393), 616 regmap_reg_range(0x0400, 0x040e), 617 regmap_reg_range(0x0410, 0x042f), 618 regmap_reg_range(0x0444, 0x044b), 619 regmap_reg_range(0x0450, 0x046f), 620 regmap_reg_range(0x0500, 0x0519), 621 regmap_reg_range(0x0520, 0x054b), 622 regmap_reg_range(0x0550, 0x05b3), 623 regmap_reg_range(0x0604, 0x060b), 624 regmap_reg_range(0x0610, 0x0612), 625 regmap_reg_range(0x0614, 0x062c), 626 regmap_reg_range(0x0640, 0x0645), 627 regmap_reg_range(0x0648, 0x064d), 628 629 /* port 1 */ 630 regmap_reg_range(0x1000, 0x1001), 631 regmap_reg_range(0x1013, 0x1013), 632 regmap_reg_range(0x1017, 0x1017), 633 regmap_reg_range(0x101b, 0x101b), 634 regmap_reg_range(0x101f, 0x1020), 635 regmap_reg_range(0x1030, 0x1030), 636 regmap_reg_range(0x1100, 0x1115), 637 regmap_reg_range(0x111a, 0x111f), 638 regmap_reg_range(0x1122, 0x1127), 639 regmap_reg_range(0x112a, 0x112b), 640 regmap_reg_range(0x1136, 0x1139), 641 regmap_reg_range(0x113e, 0x113f), 642 regmap_reg_range(0x1400, 0x1401), 643 regmap_reg_range(0x1403, 0x1403), 644 regmap_reg_range(0x1410, 0x1417), 645 regmap_reg_range(0x1420, 0x1423), 646 regmap_reg_range(0x1500, 0x1507), 647 regmap_reg_range(0x1600, 0x1613), 648 regmap_reg_range(0x1800, 0x180f), 649 regmap_reg_range(0x1820, 0x1827), 650 regmap_reg_range(0x1830, 0x1837), 651 regmap_reg_range(0x1840, 0x184b), 652 regmap_reg_range(0x1900, 0x1907), 653 regmap_reg_range(0x1914, 0x191b), 654 regmap_reg_range(0x1920, 0x1920), 655 regmap_reg_range(0x1923, 0x1927), 656 regmap_reg_range(0x1a00, 0x1a03), 657 regmap_reg_range(0x1a04, 0x1a07), 658 regmap_reg_range(0x1b00, 0x1b01), 659 regmap_reg_range(0x1b04, 0x1b04), 660 regmap_reg_range(0x1c00, 0x1c05), 661 regmap_reg_range(0x1c08, 0x1c1b), 662 663 /* port 2 */ 664 regmap_reg_range(0x2000, 0x2001), 665 regmap_reg_range(0x2013, 0x2013), 666 regmap_reg_range(0x2017, 0x2017), 667 regmap_reg_range(0x201b, 0x201b), 668 regmap_reg_range(0x201f, 0x2020), 669 regmap_reg_range(0x2030, 0x2030), 670 regmap_reg_range(0x2100, 0x2115), 671 regmap_reg_range(0x211a, 0x211f), 672 regmap_reg_range(0x2122, 0x2127), 673 regmap_reg_range(0x212a, 0x212b), 674 regmap_reg_range(0x2136, 0x2139), 675 regmap_reg_range(0x213e, 0x213f), 676 regmap_reg_range(0x2400, 0x2401), 677 regmap_reg_range(0x2403, 0x2403), 678 regmap_reg_range(0x2410, 0x2417), 679 regmap_reg_range(0x2420, 0x2423), 680 regmap_reg_range(0x2500, 0x2507), 681 regmap_reg_range(0x2600, 0x2613), 682 regmap_reg_range(0x2800, 0x280f), 683 regmap_reg_range(0x2820, 0x2827), 684 regmap_reg_range(0x2830, 0x2837), 685 regmap_reg_range(0x2840, 0x284b), 686 regmap_reg_range(0x2900, 0x2907), 687 regmap_reg_range(0x2914, 0x291b), 688 regmap_reg_range(0x2920, 0x2920), 689 regmap_reg_range(0x2923, 0x2927), 690 regmap_reg_range(0x2a00, 0x2a03), 691 regmap_reg_range(0x2a04, 0x2a07), 692 regmap_reg_range(0x2b00, 0x2b01), 693 regmap_reg_range(0x2b04, 0x2b04), 694 regmap_reg_range(0x2c00, 0x2c05), 695 regmap_reg_range(0x2c08, 0x2c1b), 696 697 /* port 3 */ 698 regmap_reg_range(0x3000, 0x3001), 699 regmap_reg_range(0x3013, 0x3013), 700 regmap_reg_range(0x3017, 0x3017), 701 regmap_reg_range(0x301b, 0x301b), 702 regmap_reg_range(0x301f, 0x3020), 703 regmap_reg_range(0x3030, 0x3030), 704 regmap_reg_range(0x3100, 0x3115), 705 regmap_reg_range(0x311a, 0x311f), 706 regmap_reg_range(0x3122, 0x3127), 707 regmap_reg_range(0x312a, 0x312b), 708 regmap_reg_range(0x3136, 0x3139), 709 regmap_reg_range(0x313e, 0x313f), 710 regmap_reg_range(0x3400, 0x3401), 711 regmap_reg_range(0x3403, 0x3403), 712 regmap_reg_range(0x3410, 0x3417), 713 regmap_reg_range(0x3420, 0x3423), 714 regmap_reg_range(0x3500, 0x3507), 715 regmap_reg_range(0x3600, 0x3613), 716 regmap_reg_range(0x3800, 0x380f), 717 regmap_reg_range(0x3820, 0x3827), 718 regmap_reg_range(0x3830, 0x3837), 719 regmap_reg_range(0x3840, 0x384b), 720 regmap_reg_range(0x3900, 0x3907), 721 regmap_reg_range(0x3914, 0x391b), 722 regmap_reg_range(0x3920, 0x3920), 723 regmap_reg_range(0x3923, 0x3927), 724 regmap_reg_range(0x3a00, 0x3a03), 725 regmap_reg_range(0x3a04, 0x3a07), 726 regmap_reg_range(0x3b00, 0x3b01), 727 regmap_reg_range(0x3b04, 0x3b04), 728 regmap_reg_range(0x3c00, 0x3c05), 729 regmap_reg_range(0x3c08, 0x3c1b), 730 731 /* port 4 */ 732 regmap_reg_range(0x4000, 0x4001), 733 regmap_reg_range(0x4013, 0x4013), 734 regmap_reg_range(0x4017, 0x4017), 735 regmap_reg_range(0x401b, 0x401b), 736 regmap_reg_range(0x401f, 0x4020), 737 regmap_reg_range(0x4030, 0x4030), 738 regmap_reg_range(0x4100, 0x4115), 739 regmap_reg_range(0x411a, 0x411f), 740 regmap_reg_range(0x4122, 0x4127), 741 regmap_reg_range(0x412a, 0x412b), 742 regmap_reg_range(0x4136, 0x4139), 743 regmap_reg_range(0x413e, 0x413f), 744 regmap_reg_range(0x4400, 0x4401), 745 regmap_reg_range(0x4403, 0x4403), 746 regmap_reg_range(0x4410, 0x4417), 747 regmap_reg_range(0x4420, 0x4423), 748 regmap_reg_range(0x4500, 0x4507), 749 regmap_reg_range(0x4600, 0x4613), 750 regmap_reg_range(0x4800, 0x480f), 751 regmap_reg_range(0x4820, 0x4827), 752 regmap_reg_range(0x4830, 0x4837), 753 regmap_reg_range(0x4840, 0x484b), 754 regmap_reg_range(0x4900, 0x4907), 755 regmap_reg_range(0x4914, 0x491b), 756 regmap_reg_range(0x4920, 0x4920), 757 regmap_reg_range(0x4923, 0x4927), 758 regmap_reg_range(0x4a00, 0x4a03), 759 regmap_reg_range(0x4a04, 0x4a07), 760 regmap_reg_range(0x4b00, 0x4b01), 761 regmap_reg_range(0x4b04, 0x4b04), 762 regmap_reg_range(0x4c00, 0x4c05), 763 regmap_reg_range(0x4c08, 0x4c1b), 764 765 /* port 5 */ 766 regmap_reg_range(0x5000, 0x5001), 767 regmap_reg_range(0x5013, 0x5013), 768 regmap_reg_range(0x5017, 0x5017), 769 regmap_reg_range(0x501b, 0x501b), 770 regmap_reg_range(0x501f, 0x5020), 771 regmap_reg_range(0x5030, 0x5030), 772 regmap_reg_range(0x5100, 0x5115), 773 regmap_reg_range(0x511a, 0x511f), 774 regmap_reg_range(0x5122, 0x5127), 775 regmap_reg_range(0x512a, 0x512b), 776 regmap_reg_range(0x5136, 0x5139), 777 regmap_reg_range(0x513e, 0x513f), 778 regmap_reg_range(0x5400, 0x5401), 779 regmap_reg_range(0x5403, 0x5403), 780 regmap_reg_range(0x5410, 0x5417), 781 regmap_reg_range(0x5420, 0x5423), 782 regmap_reg_range(0x5500, 0x5507), 783 regmap_reg_range(0x5600, 0x5613), 784 regmap_reg_range(0x5800, 0x580f), 785 regmap_reg_range(0x5820, 0x5827), 786 regmap_reg_range(0x5830, 0x5837), 787 regmap_reg_range(0x5840, 0x584b), 788 regmap_reg_range(0x5900, 0x5907), 789 regmap_reg_range(0x5914, 0x591b), 790 regmap_reg_range(0x5920, 0x5920), 791 regmap_reg_range(0x5923, 0x5927), 792 regmap_reg_range(0x5a00, 0x5a03), 793 regmap_reg_range(0x5a04, 0x5a07), 794 regmap_reg_range(0x5b00, 0x5b01), 795 regmap_reg_range(0x5b04, 0x5b04), 796 regmap_reg_range(0x5c00, 0x5c05), 797 regmap_reg_range(0x5c08, 0x5c1b), 798 799 /* port 6 */ 800 regmap_reg_range(0x6000, 0x6001), 801 regmap_reg_range(0x6013, 0x6013), 802 regmap_reg_range(0x6017, 0x6017), 803 regmap_reg_range(0x601b, 0x601b), 804 regmap_reg_range(0x601f, 0x6020), 805 regmap_reg_range(0x6030, 0x6030), 806 regmap_reg_range(0x6300, 0x6301), 807 regmap_reg_range(0x6400, 0x6401), 808 regmap_reg_range(0x6403, 0x6403), 809 regmap_reg_range(0x6410, 0x6417), 810 regmap_reg_range(0x6420, 0x6423), 811 regmap_reg_range(0x6500, 0x6507), 812 regmap_reg_range(0x6600, 0x6613), 813 regmap_reg_range(0x6800, 0x680f), 814 regmap_reg_range(0x6820, 0x6827), 815 regmap_reg_range(0x6830, 0x6837), 816 regmap_reg_range(0x6840, 0x684b), 817 regmap_reg_range(0x6900, 0x6907), 818 regmap_reg_range(0x6914, 0x691b), 819 regmap_reg_range(0x6920, 0x6920), 820 regmap_reg_range(0x6923, 0x6927), 821 regmap_reg_range(0x6a00, 0x6a03), 822 regmap_reg_range(0x6a04, 0x6a07), 823 regmap_reg_range(0x6b00, 0x6b01), 824 regmap_reg_range(0x6b04, 0x6b04), 825 regmap_reg_range(0x6c00, 0x6c05), 826 regmap_reg_range(0x6c08, 0x6c1b), 827 828 /* port 7 */ 829 regmap_reg_range(0x7000, 0x7001), 830 regmap_reg_range(0x7013, 0x7013), 831 regmap_reg_range(0x7017, 0x7017), 832 regmap_reg_range(0x701b, 0x701b), 833 regmap_reg_range(0x701f, 0x7020), 834 regmap_reg_range(0x7030, 0x7030), 835 regmap_reg_range(0x7200, 0x7203), 836 regmap_reg_range(0x7206, 0x7207), 837 regmap_reg_range(0x7300, 0x7301), 838 regmap_reg_range(0x7400, 0x7401), 839 regmap_reg_range(0x7403, 0x7403), 840 regmap_reg_range(0x7410, 0x7417), 841 regmap_reg_range(0x7420, 0x7423), 842 regmap_reg_range(0x7500, 0x7507), 843 regmap_reg_range(0x7600, 0x7613), 844 regmap_reg_range(0x7800, 0x780f), 845 regmap_reg_range(0x7820, 0x7827), 846 regmap_reg_range(0x7830, 0x7837), 847 regmap_reg_range(0x7840, 0x784b), 848 regmap_reg_range(0x7900, 0x7907), 849 regmap_reg_range(0x7914, 0x791b), 850 regmap_reg_range(0x7920, 0x7920), 851 regmap_reg_range(0x7923, 0x7927), 852 regmap_reg_range(0x7a00, 0x7a03), 853 regmap_reg_range(0x7a04, 0x7a07), 854 regmap_reg_range(0x7b00, 0x7b01), 855 regmap_reg_range(0x7b04, 0x7b04), 856 regmap_reg_range(0x7c00, 0x7c05), 857 regmap_reg_range(0x7c08, 0x7c1b), 858 }; 859 860 static const struct regmap_access_table ksz9477_register_set = { 861 .yes_ranges = ksz9477_valid_regs, 862 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), 863 }; 864 865 static const struct regmap_range ksz9896_valid_regs[] = { 866 regmap_reg_range(0x0000, 0x0003), 867 regmap_reg_range(0x0006, 0x0006), 868 regmap_reg_range(0x0010, 0x001f), 869 regmap_reg_range(0x0100, 0x0100), 870 regmap_reg_range(0x0103, 0x0107), 871 regmap_reg_range(0x010d, 0x010d), 872 regmap_reg_range(0x0110, 0x0113), 873 regmap_reg_range(0x0120, 0x0127), 874 regmap_reg_range(0x0201, 0x0201), 875 regmap_reg_range(0x0210, 0x0213), 876 regmap_reg_range(0x0300, 0x0300), 877 regmap_reg_range(0x0302, 0x030b), 878 regmap_reg_range(0x0310, 0x031b), 879 regmap_reg_range(0x0320, 0x032b), 880 regmap_reg_range(0x0330, 0x0336), 881 regmap_reg_range(0x0338, 0x033b), 882 regmap_reg_range(0x033e, 0x033e), 883 regmap_reg_range(0x0340, 0x035f), 884 regmap_reg_range(0x0370, 0x0370), 885 regmap_reg_range(0x0378, 0x0378), 886 regmap_reg_range(0x037c, 0x037d), 887 regmap_reg_range(0x0390, 0x0393), 888 regmap_reg_range(0x0400, 0x040e), 889 regmap_reg_range(0x0410, 0x042f), 890 891 /* port 1 */ 892 regmap_reg_range(0x1000, 0x1001), 893 regmap_reg_range(0x1013, 0x1013), 894 regmap_reg_range(0x1017, 0x1017), 895 regmap_reg_range(0x101b, 0x101b), 896 regmap_reg_range(0x101f, 0x1020), 897 regmap_reg_range(0x1030, 0x1030), 898 regmap_reg_range(0x1100, 0x1115), 899 regmap_reg_range(0x111a, 0x111f), 900 regmap_reg_range(0x1122, 0x1127), 901 regmap_reg_range(0x112a, 0x112b), 902 regmap_reg_range(0x1136, 0x1139), 903 regmap_reg_range(0x113e, 0x113f), 904 regmap_reg_range(0x1400, 0x1401), 905 regmap_reg_range(0x1403, 0x1403), 906 regmap_reg_range(0x1410, 0x1417), 907 regmap_reg_range(0x1420, 0x1423), 908 regmap_reg_range(0x1500, 0x1507), 909 regmap_reg_range(0x1600, 0x1612), 910 regmap_reg_range(0x1800, 0x180f), 911 regmap_reg_range(0x1820, 0x1827), 912 regmap_reg_range(0x1830, 0x1837), 913 regmap_reg_range(0x1840, 0x184b), 914 regmap_reg_range(0x1900, 0x1907), 915 regmap_reg_range(0x1914, 0x1915), 916 regmap_reg_range(0x1a00, 0x1a03), 917 regmap_reg_range(0x1a04, 0x1a07), 918 regmap_reg_range(0x1b00, 0x1b01), 919 regmap_reg_range(0x1b04, 0x1b04), 920 921 /* port 2 */ 922 regmap_reg_range(0x2000, 0x2001), 923 regmap_reg_range(0x2013, 0x2013), 924 regmap_reg_range(0x2017, 0x2017), 925 regmap_reg_range(0x201b, 0x201b), 926 regmap_reg_range(0x201f, 0x2020), 927 regmap_reg_range(0x2030, 0x2030), 928 regmap_reg_range(0x2100, 0x2115), 929 regmap_reg_range(0x211a, 0x211f), 930 regmap_reg_range(0x2122, 0x2127), 931 regmap_reg_range(0x212a, 0x212b), 932 regmap_reg_range(0x2136, 0x2139), 933 regmap_reg_range(0x213e, 0x213f), 934 regmap_reg_range(0x2400, 0x2401), 935 regmap_reg_range(0x2403, 0x2403), 936 regmap_reg_range(0x2410, 0x2417), 937 regmap_reg_range(0x2420, 0x2423), 938 regmap_reg_range(0x2500, 0x2507), 939 regmap_reg_range(0x2600, 0x2612), 940 regmap_reg_range(0x2800, 0x280f), 941 regmap_reg_range(0x2820, 0x2827), 942 regmap_reg_range(0x2830, 0x2837), 943 regmap_reg_range(0x2840, 0x284b), 944 regmap_reg_range(0x2900, 0x2907), 945 regmap_reg_range(0x2914, 0x2915), 946 regmap_reg_range(0x2a00, 0x2a03), 947 regmap_reg_range(0x2a04, 0x2a07), 948 regmap_reg_range(0x2b00, 0x2b01), 949 regmap_reg_range(0x2b04, 0x2b04), 950 951 /* port 3 */ 952 regmap_reg_range(0x3000, 0x3001), 953 regmap_reg_range(0x3013, 0x3013), 954 regmap_reg_range(0x3017, 0x3017), 955 regmap_reg_range(0x301b, 0x301b), 956 regmap_reg_range(0x301f, 0x3020), 957 regmap_reg_range(0x3030, 0x3030), 958 regmap_reg_range(0x3100, 0x3115), 959 regmap_reg_range(0x311a, 0x311f), 960 regmap_reg_range(0x3122, 0x3127), 961 regmap_reg_range(0x312a, 0x312b), 962 regmap_reg_range(0x3136, 0x3139), 963 regmap_reg_range(0x313e, 0x313f), 964 regmap_reg_range(0x3400, 0x3401), 965 regmap_reg_range(0x3403, 0x3403), 966 regmap_reg_range(0x3410, 0x3417), 967 regmap_reg_range(0x3420, 0x3423), 968 regmap_reg_range(0x3500, 0x3507), 969 regmap_reg_range(0x3600, 0x3612), 970 regmap_reg_range(0x3800, 0x380f), 971 regmap_reg_range(0x3820, 0x3827), 972 regmap_reg_range(0x3830, 0x3837), 973 regmap_reg_range(0x3840, 0x384b), 974 regmap_reg_range(0x3900, 0x3907), 975 regmap_reg_range(0x3914, 0x3915), 976 regmap_reg_range(0x3a00, 0x3a03), 977 regmap_reg_range(0x3a04, 0x3a07), 978 regmap_reg_range(0x3b00, 0x3b01), 979 regmap_reg_range(0x3b04, 0x3b04), 980 981 /* port 4 */ 982 regmap_reg_range(0x4000, 0x4001), 983 regmap_reg_range(0x4013, 0x4013), 984 regmap_reg_range(0x4017, 0x4017), 985 regmap_reg_range(0x401b, 0x401b), 986 regmap_reg_range(0x401f, 0x4020), 987 regmap_reg_range(0x4030, 0x4030), 988 regmap_reg_range(0x4100, 0x4115), 989 regmap_reg_range(0x411a, 0x411f), 990 regmap_reg_range(0x4122, 0x4127), 991 regmap_reg_range(0x412a, 0x412b), 992 regmap_reg_range(0x4136, 0x4139), 993 regmap_reg_range(0x413e, 0x413f), 994 regmap_reg_range(0x4400, 0x4401), 995 regmap_reg_range(0x4403, 0x4403), 996 regmap_reg_range(0x4410, 0x4417), 997 regmap_reg_range(0x4420, 0x4423), 998 regmap_reg_range(0x4500, 0x4507), 999 regmap_reg_range(0x4600, 0x4612), 1000 regmap_reg_range(0x4800, 0x480f), 1001 regmap_reg_range(0x4820, 0x4827), 1002 regmap_reg_range(0x4830, 0x4837), 1003 regmap_reg_range(0x4840, 0x484b), 1004 regmap_reg_range(0x4900, 0x4907), 1005 regmap_reg_range(0x4914, 0x4915), 1006 regmap_reg_range(0x4a00, 0x4a03), 1007 regmap_reg_range(0x4a04, 0x4a07), 1008 regmap_reg_range(0x4b00, 0x4b01), 1009 regmap_reg_range(0x4b04, 0x4b04), 1010 1011 /* port 5 */ 1012 regmap_reg_range(0x5000, 0x5001), 1013 regmap_reg_range(0x5013, 0x5013), 1014 regmap_reg_range(0x5017, 0x5017), 1015 regmap_reg_range(0x501b, 0x501b), 1016 regmap_reg_range(0x501f, 0x5020), 1017 regmap_reg_range(0x5030, 0x5030), 1018 regmap_reg_range(0x5100, 0x5115), 1019 regmap_reg_range(0x511a, 0x511f), 1020 regmap_reg_range(0x5122, 0x5127), 1021 regmap_reg_range(0x512a, 0x512b), 1022 regmap_reg_range(0x5136, 0x5139), 1023 regmap_reg_range(0x513e, 0x513f), 1024 regmap_reg_range(0x5400, 0x5401), 1025 regmap_reg_range(0x5403, 0x5403), 1026 regmap_reg_range(0x5410, 0x5417), 1027 regmap_reg_range(0x5420, 0x5423), 1028 regmap_reg_range(0x5500, 0x5507), 1029 regmap_reg_range(0x5600, 0x5612), 1030 regmap_reg_range(0x5800, 0x580f), 1031 regmap_reg_range(0x5820, 0x5827), 1032 regmap_reg_range(0x5830, 0x5837), 1033 regmap_reg_range(0x5840, 0x584b), 1034 regmap_reg_range(0x5900, 0x5907), 1035 regmap_reg_range(0x5914, 0x5915), 1036 regmap_reg_range(0x5a00, 0x5a03), 1037 regmap_reg_range(0x5a04, 0x5a07), 1038 regmap_reg_range(0x5b00, 0x5b01), 1039 regmap_reg_range(0x5b04, 0x5b04), 1040 1041 /* port 6 */ 1042 regmap_reg_range(0x6000, 0x6001), 1043 regmap_reg_range(0x6013, 0x6013), 1044 regmap_reg_range(0x6017, 0x6017), 1045 regmap_reg_range(0x601b, 0x601b), 1046 regmap_reg_range(0x601f, 0x6020), 1047 regmap_reg_range(0x6030, 0x6030), 1048 regmap_reg_range(0x6100, 0x6115), 1049 regmap_reg_range(0x611a, 0x611f), 1050 regmap_reg_range(0x6122, 0x6127), 1051 regmap_reg_range(0x612a, 0x612b), 1052 regmap_reg_range(0x6136, 0x6139), 1053 regmap_reg_range(0x613e, 0x613f), 1054 regmap_reg_range(0x6300, 0x6301), 1055 regmap_reg_range(0x6400, 0x6401), 1056 regmap_reg_range(0x6403, 0x6403), 1057 regmap_reg_range(0x6410, 0x6417), 1058 regmap_reg_range(0x6420, 0x6423), 1059 regmap_reg_range(0x6500, 0x6507), 1060 regmap_reg_range(0x6600, 0x6612), 1061 regmap_reg_range(0x6800, 0x680f), 1062 regmap_reg_range(0x6820, 0x6827), 1063 regmap_reg_range(0x6830, 0x6837), 1064 regmap_reg_range(0x6840, 0x684b), 1065 regmap_reg_range(0x6900, 0x6907), 1066 regmap_reg_range(0x6914, 0x6915), 1067 regmap_reg_range(0x6a00, 0x6a03), 1068 regmap_reg_range(0x6a04, 0x6a07), 1069 regmap_reg_range(0x6b00, 0x6b01), 1070 regmap_reg_range(0x6b04, 0x6b04), 1071 }; 1072 1073 static const struct regmap_access_table ksz9896_register_set = { 1074 .yes_ranges = ksz9896_valid_regs, 1075 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs), 1076 }; 1077 1078 static const struct regmap_range ksz8873_valid_regs[] = { 1079 regmap_reg_range(0x00, 0x01), 1080 /* global control register */ 1081 regmap_reg_range(0x02, 0x0f), 1082 1083 /* port registers */ 1084 regmap_reg_range(0x10, 0x1d), 1085 regmap_reg_range(0x1e, 0x1f), 1086 regmap_reg_range(0x20, 0x2d), 1087 regmap_reg_range(0x2e, 0x2f), 1088 regmap_reg_range(0x30, 0x39), 1089 regmap_reg_range(0x3f, 0x3f), 1090 1091 /* advanced control registers */ 1092 regmap_reg_range(0x60, 0x6f), 1093 regmap_reg_range(0x70, 0x75), 1094 regmap_reg_range(0x76, 0x78), 1095 regmap_reg_range(0x79, 0x7a), 1096 regmap_reg_range(0x7b, 0x83), 1097 regmap_reg_range(0x8e, 0x99), 1098 regmap_reg_range(0x9a, 0xa5), 1099 regmap_reg_range(0xa6, 0xa6), 1100 regmap_reg_range(0xa7, 0xaa), 1101 regmap_reg_range(0xab, 0xae), 1102 regmap_reg_range(0xaf, 0xba), 1103 regmap_reg_range(0xbb, 0xbc), 1104 regmap_reg_range(0xbd, 0xbd), 1105 regmap_reg_range(0xc0, 0xc0), 1106 regmap_reg_range(0xc2, 0xc2), 1107 regmap_reg_range(0xc3, 0xc3), 1108 regmap_reg_range(0xc4, 0xc4), 1109 regmap_reg_range(0xc6, 0xc6), 1110 }; 1111 1112 static const struct regmap_access_table ksz8873_register_set = { 1113 .yes_ranges = ksz8873_valid_regs, 1114 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs), 1115 }; 1116 1117 const struct ksz_chip_data ksz_switch_chips[] = { 1118 [KSZ8563] = { 1119 .chip_id = KSZ8563_CHIP_ID, 1120 .dev_name = "KSZ8563", 1121 .num_vlans = 4096, 1122 .num_alus = 4096, 1123 .num_statics = 16, 1124 .cpu_ports = 0x07, /* can be configured as cpu port */ 1125 .port_cnt = 3, /* total port count */ 1126 .port_nirqs = 3, 1127 .num_tx_queues = 4, 1128 .tc_cbs_supported = true, 1129 .tc_ets_supported = true, 1130 .ops = &ksz9477_dev_ops, 1131 .mib_names = ksz9477_mib_names, 1132 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1133 .reg_mib_cnt = MIB_COUNTER_NUM, 1134 .regs = ksz9477_regs, 1135 .masks = ksz9477_masks, 1136 .shifts = ksz9477_shifts, 1137 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1138 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1139 .supports_mii = {false, false, true}, 1140 .supports_rmii = {false, false, true}, 1141 .supports_rgmii = {false, false, true}, 1142 .internal_phy = {true, true, false}, 1143 .gbit_capable = {false, false, true}, 1144 .wr_table = &ksz8563_register_set, 1145 .rd_table = &ksz8563_register_set, 1146 }, 1147 1148 [KSZ8795] = { 1149 .chip_id = KSZ8795_CHIP_ID, 1150 .dev_name = "KSZ8795", 1151 .num_vlans = 4096, 1152 .num_alus = 0, 1153 .num_statics = 8, 1154 .cpu_ports = 0x10, /* can be configured as cpu port */ 1155 .port_cnt = 5, /* total cpu and user ports */ 1156 .num_tx_queues = 4, 1157 .ops = &ksz8_dev_ops, 1158 .ksz87xx_eee_link_erratum = true, 1159 .mib_names = ksz9477_mib_names, 1160 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1161 .reg_mib_cnt = MIB_COUNTER_NUM, 1162 .regs = ksz8795_regs, 1163 .masks = ksz8795_masks, 1164 .shifts = ksz8795_shifts, 1165 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1166 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1167 .supports_mii = {false, false, false, false, true}, 1168 .supports_rmii = {false, false, false, false, true}, 1169 .supports_rgmii = {false, false, false, false, true}, 1170 .internal_phy = {true, true, true, true, false}, 1171 }, 1172 1173 [KSZ8794] = { 1174 /* WARNING 1175 * ======= 1176 * KSZ8794 is similar to KSZ8795, except the port map 1177 * contains a gap between external and CPU ports, the 1178 * port map is NOT continuous. The per-port register 1179 * map is shifted accordingly too, i.e. registers at 1180 * offset 0x40 are NOT used on KSZ8794 and they ARE 1181 * used on KSZ8795 for external port 3. 1182 * external cpu 1183 * KSZ8794 0,1,2 4 1184 * KSZ8795 0,1,2,3 4 1185 * KSZ8765 0,1,2,3 4 1186 * port_cnt is configured as 5, even though it is 4 1187 */ 1188 .chip_id = KSZ8794_CHIP_ID, 1189 .dev_name = "KSZ8794", 1190 .num_vlans = 4096, 1191 .num_alus = 0, 1192 .num_statics = 8, 1193 .cpu_ports = 0x10, /* can be configured as cpu port */ 1194 .port_cnt = 5, /* total cpu and user ports */ 1195 .num_tx_queues = 4, 1196 .ops = &ksz8_dev_ops, 1197 .ksz87xx_eee_link_erratum = true, 1198 .mib_names = ksz9477_mib_names, 1199 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1200 .reg_mib_cnt = MIB_COUNTER_NUM, 1201 .regs = ksz8795_regs, 1202 .masks = ksz8795_masks, 1203 .shifts = ksz8795_shifts, 1204 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1205 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1206 .supports_mii = {false, false, false, false, true}, 1207 .supports_rmii = {false, false, false, false, true}, 1208 .supports_rgmii = {false, false, false, false, true}, 1209 .internal_phy = {true, true, true, false, false}, 1210 }, 1211 1212 [KSZ8765] = { 1213 .chip_id = KSZ8765_CHIP_ID, 1214 .dev_name = "KSZ8765", 1215 .num_vlans = 4096, 1216 .num_alus = 0, 1217 .num_statics = 8, 1218 .cpu_ports = 0x10, /* can be configured as cpu port */ 1219 .port_cnt = 5, /* total cpu and user ports */ 1220 .num_tx_queues = 4, 1221 .ops = &ksz8_dev_ops, 1222 .ksz87xx_eee_link_erratum = true, 1223 .mib_names = ksz9477_mib_names, 1224 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1225 .reg_mib_cnt = MIB_COUNTER_NUM, 1226 .regs = ksz8795_regs, 1227 .masks = ksz8795_masks, 1228 .shifts = ksz8795_shifts, 1229 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1230 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1231 .supports_mii = {false, false, false, false, true}, 1232 .supports_rmii = {false, false, false, false, true}, 1233 .supports_rgmii = {false, false, false, false, true}, 1234 .internal_phy = {true, true, true, true, false}, 1235 }, 1236 1237 [KSZ8830] = { 1238 .chip_id = KSZ8830_CHIP_ID, 1239 .dev_name = "KSZ8863/KSZ8873", 1240 .num_vlans = 16, 1241 .num_alus = 0, 1242 .num_statics = 8, 1243 .cpu_ports = 0x4, /* can be configured as cpu port */ 1244 .port_cnt = 3, 1245 .num_tx_queues = 4, 1246 .ops = &ksz8_dev_ops, 1247 .mib_names = ksz88xx_mib_names, 1248 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1249 .reg_mib_cnt = MIB_COUNTER_NUM, 1250 .regs = ksz8863_regs, 1251 .masks = ksz8863_masks, 1252 .shifts = ksz8863_shifts, 1253 .supports_mii = {false, false, true}, 1254 .supports_rmii = {false, false, true}, 1255 .internal_phy = {true, true, false}, 1256 .wr_table = &ksz8873_register_set, 1257 .rd_table = &ksz8873_register_set, 1258 }, 1259 1260 [KSZ9477] = { 1261 .chip_id = KSZ9477_CHIP_ID, 1262 .dev_name = "KSZ9477", 1263 .num_vlans = 4096, 1264 .num_alus = 4096, 1265 .num_statics = 16, 1266 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1267 .port_cnt = 7, /* total physical port count */ 1268 .port_nirqs = 4, 1269 .num_tx_queues = 4, 1270 .tc_cbs_supported = true, 1271 .tc_ets_supported = true, 1272 .ops = &ksz9477_dev_ops, 1273 .phy_errata_9477 = true, 1274 .mib_names = ksz9477_mib_names, 1275 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1276 .reg_mib_cnt = MIB_COUNTER_NUM, 1277 .regs = ksz9477_regs, 1278 .masks = ksz9477_masks, 1279 .shifts = ksz9477_shifts, 1280 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1281 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1282 .supports_mii = {false, false, false, false, 1283 false, true, false}, 1284 .supports_rmii = {false, false, false, false, 1285 false, true, false}, 1286 .supports_rgmii = {false, false, false, false, 1287 false, true, false}, 1288 .internal_phy = {true, true, true, true, 1289 true, false, false}, 1290 .gbit_capable = {true, true, true, true, true, true, true}, 1291 .wr_table = &ksz9477_register_set, 1292 .rd_table = &ksz9477_register_set, 1293 }, 1294 1295 [KSZ9896] = { 1296 .chip_id = KSZ9896_CHIP_ID, 1297 .dev_name = "KSZ9896", 1298 .num_vlans = 4096, 1299 .num_alus = 4096, 1300 .num_statics = 16, 1301 .cpu_ports = 0x3F, /* can be configured as cpu port */ 1302 .port_cnt = 6, /* total physical port count */ 1303 .port_nirqs = 2, 1304 .num_tx_queues = 4, 1305 .ops = &ksz9477_dev_ops, 1306 .phy_errata_9477 = true, 1307 .mib_names = ksz9477_mib_names, 1308 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1309 .reg_mib_cnt = MIB_COUNTER_NUM, 1310 .regs = ksz9477_regs, 1311 .masks = ksz9477_masks, 1312 .shifts = ksz9477_shifts, 1313 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1314 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1315 .supports_mii = {false, false, false, false, 1316 false, true}, 1317 .supports_rmii = {false, false, false, false, 1318 false, true}, 1319 .supports_rgmii = {false, false, false, false, 1320 false, true}, 1321 .internal_phy = {true, true, true, true, 1322 true, false}, 1323 .gbit_capable = {true, true, true, true, true, true}, 1324 .wr_table = &ksz9896_register_set, 1325 .rd_table = &ksz9896_register_set, 1326 }, 1327 1328 [KSZ9897] = { 1329 .chip_id = KSZ9897_CHIP_ID, 1330 .dev_name = "KSZ9897", 1331 .num_vlans = 4096, 1332 .num_alus = 4096, 1333 .num_statics = 16, 1334 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1335 .port_cnt = 7, /* total physical port count */ 1336 .port_nirqs = 2, 1337 .num_tx_queues = 4, 1338 .ops = &ksz9477_dev_ops, 1339 .phy_errata_9477 = true, 1340 .mib_names = ksz9477_mib_names, 1341 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1342 .reg_mib_cnt = MIB_COUNTER_NUM, 1343 .regs = ksz9477_regs, 1344 .masks = ksz9477_masks, 1345 .shifts = ksz9477_shifts, 1346 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1347 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1348 .supports_mii = {false, false, false, false, 1349 false, true, true}, 1350 .supports_rmii = {false, false, false, false, 1351 false, true, true}, 1352 .supports_rgmii = {false, false, false, false, 1353 false, true, true}, 1354 .internal_phy = {true, true, true, true, 1355 true, false, false}, 1356 .gbit_capable = {true, true, true, true, true, true, true}, 1357 }, 1358 1359 [KSZ9893] = { 1360 .chip_id = KSZ9893_CHIP_ID, 1361 .dev_name = "KSZ9893", 1362 .num_vlans = 4096, 1363 .num_alus = 4096, 1364 .num_statics = 16, 1365 .cpu_ports = 0x07, /* can be configured as cpu port */ 1366 .port_cnt = 3, /* total port count */ 1367 .port_nirqs = 2, 1368 .num_tx_queues = 4, 1369 .ops = &ksz9477_dev_ops, 1370 .mib_names = ksz9477_mib_names, 1371 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1372 .reg_mib_cnt = MIB_COUNTER_NUM, 1373 .regs = ksz9477_regs, 1374 .masks = ksz9477_masks, 1375 .shifts = ksz9477_shifts, 1376 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1377 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1378 .supports_mii = {false, false, true}, 1379 .supports_rmii = {false, false, true}, 1380 .supports_rgmii = {false, false, true}, 1381 .internal_phy = {true, true, false}, 1382 .gbit_capable = {true, true, true}, 1383 }, 1384 1385 [KSZ9563] = { 1386 .chip_id = KSZ9563_CHIP_ID, 1387 .dev_name = "KSZ9563", 1388 .num_vlans = 4096, 1389 .num_alus = 4096, 1390 .num_statics = 16, 1391 .cpu_ports = 0x07, /* can be configured as cpu port */ 1392 .port_cnt = 3, /* total port count */ 1393 .port_nirqs = 3, 1394 .num_tx_queues = 4, 1395 .tc_cbs_supported = true, 1396 .tc_ets_supported = true, 1397 .ops = &ksz9477_dev_ops, 1398 .mib_names = ksz9477_mib_names, 1399 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1400 .reg_mib_cnt = MIB_COUNTER_NUM, 1401 .regs = ksz9477_regs, 1402 .masks = ksz9477_masks, 1403 .shifts = ksz9477_shifts, 1404 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1405 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1406 .supports_mii = {false, false, true}, 1407 .supports_rmii = {false, false, true}, 1408 .supports_rgmii = {false, false, true}, 1409 .internal_phy = {true, true, false}, 1410 .gbit_capable = {true, true, true}, 1411 }, 1412 1413 [KSZ9567] = { 1414 .chip_id = KSZ9567_CHIP_ID, 1415 .dev_name = "KSZ9567", 1416 .num_vlans = 4096, 1417 .num_alus = 4096, 1418 .num_statics = 16, 1419 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1420 .port_cnt = 7, /* total physical port count */ 1421 .port_nirqs = 3, 1422 .num_tx_queues = 4, 1423 .tc_cbs_supported = true, 1424 .tc_ets_supported = true, 1425 .ops = &ksz9477_dev_ops, 1426 .phy_errata_9477 = true, 1427 .mib_names = ksz9477_mib_names, 1428 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1429 .reg_mib_cnt = MIB_COUNTER_NUM, 1430 .regs = ksz9477_regs, 1431 .masks = ksz9477_masks, 1432 .shifts = ksz9477_shifts, 1433 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1434 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1435 .supports_mii = {false, false, false, false, 1436 false, true, true}, 1437 .supports_rmii = {false, false, false, false, 1438 false, true, true}, 1439 .supports_rgmii = {false, false, false, false, 1440 false, true, true}, 1441 .internal_phy = {true, true, true, true, 1442 true, false, false}, 1443 .gbit_capable = {true, true, true, true, true, true, true}, 1444 }, 1445 1446 [LAN9370] = { 1447 .chip_id = LAN9370_CHIP_ID, 1448 .dev_name = "LAN9370", 1449 .num_vlans = 4096, 1450 .num_alus = 1024, 1451 .num_statics = 256, 1452 .cpu_ports = 0x10, /* can be configured as cpu port */ 1453 .port_cnt = 5, /* total physical port count */ 1454 .port_nirqs = 6, 1455 .num_tx_queues = 8, 1456 .tc_cbs_supported = true, 1457 .tc_ets_supported = true, 1458 .ops = &lan937x_dev_ops, 1459 .mib_names = ksz9477_mib_names, 1460 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1461 .reg_mib_cnt = MIB_COUNTER_NUM, 1462 .regs = ksz9477_regs, 1463 .masks = lan937x_masks, 1464 .shifts = lan937x_shifts, 1465 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1466 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1467 .supports_mii = {false, false, false, false, true}, 1468 .supports_rmii = {false, false, false, false, true}, 1469 .supports_rgmii = {false, false, false, false, true}, 1470 .internal_phy = {true, true, true, true, false}, 1471 }, 1472 1473 [LAN9371] = { 1474 .chip_id = LAN9371_CHIP_ID, 1475 .dev_name = "LAN9371", 1476 .num_vlans = 4096, 1477 .num_alus = 1024, 1478 .num_statics = 256, 1479 .cpu_ports = 0x30, /* can be configured as cpu port */ 1480 .port_cnt = 6, /* total physical port count */ 1481 .port_nirqs = 6, 1482 .num_tx_queues = 8, 1483 .tc_cbs_supported = true, 1484 .tc_ets_supported = true, 1485 .ops = &lan937x_dev_ops, 1486 .mib_names = ksz9477_mib_names, 1487 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1488 .reg_mib_cnt = MIB_COUNTER_NUM, 1489 .regs = ksz9477_regs, 1490 .masks = lan937x_masks, 1491 .shifts = lan937x_shifts, 1492 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1493 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1494 .supports_mii = {false, false, false, false, true, true}, 1495 .supports_rmii = {false, false, false, false, true, true}, 1496 .supports_rgmii = {false, false, false, false, true, true}, 1497 .internal_phy = {true, true, true, true, false, false}, 1498 }, 1499 1500 [LAN9372] = { 1501 .chip_id = LAN9372_CHIP_ID, 1502 .dev_name = "LAN9372", 1503 .num_vlans = 4096, 1504 .num_alus = 1024, 1505 .num_statics = 256, 1506 .cpu_ports = 0x30, /* can be configured as cpu port */ 1507 .port_cnt = 8, /* total physical port count */ 1508 .port_nirqs = 6, 1509 .num_tx_queues = 8, 1510 .tc_cbs_supported = true, 1511 .tc_ets_supported = true, 1512 .ops = &lan937x_dev_ops, 1513 .mib_names = ksz9477_mib_names, 1514 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1515 .reg_mib_cnt = MIB_COUNTER_NUM, 1516 .regs = ksz9477_regs, 1517 .masks = lan937x_masks, 1518 .shifts = lan937x_shifts, 1519 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1520 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1521 .supports_mii = {false, false, false, false, 1522 true, true, false, false}, 1523 .supports_rmii = {false, false, false, false, 1524 true, true, false, false}, 1525 .supports_rgmii = {false, false, false, false, 1526 true, true, false, false}, 1527 .internal_phy = {true, true, true, true, 1528 false, false, true, true}, 1529 }, 1530 1531 [LAN9373] = { 1532 .chip_id = LAN9373_CHIP_ID, 1533 .dev_name = "LAN9373", 1534 .num_vlans = 4096, 1535 .num_alus = 1024, 1536 .num_statics = 256, 1537 .cpu_ports = 0x38, /* can be configured as cpu port */ 1538 .port_cnt = 5, /* total physical port count */ 1539 .port_nirqs = 6, 1540 .num_tx_queues = 8, 1541 .tc_cbs_supported = true, 1542 .tc_ets_supported = true, 1543 .ops = &lan937x_dev_ops, 1544 .mib_names = ksz9477_mib_names, 1545 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1546 .reg_mib_cnt = MIB_COUNTER_NUM, 1547 .regs = ksz9477_regs, 1548 .masks = lan937x_masks, 1549 .shifts = lan937x_shifts, 1550 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1551 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1552 .supports_mii = {false, false, false, false, 1553 true, true, false, false}, 1554 .supports_rmii = {false, false, false, false, 1555 true, true, false, false}, 1556 .supports_rgmii = {false, false, false, false, 1557 true, true, false, false}, 1558 .internal_phy = {true, true, true, false, 1559 false, false, true, true}, 1560 }, 1561 1562 [LAN9374] = { 1563 .chip_id = LAN9374_CHIP_ID, 1564 .dev_name = "LAN9374", 1565 .num_vlans = 4096, 1566 .num_alus = 1024, 1567 .num_statics = 256, 1568 .cpu_ports = 0x30, /* can be configured as cpu port */ 1569 .port_cnt = 8, /* total physical port count */ 1570 .port_nirqs = 6, 1571 .num_tx_queues = 8, 1572 .tc_cbs_supported = true, 1573 .tc_ets_supported = true, 1574 .ops = &lan937x_dev_ops, 1575 .mib_names = ksz9477_mib_names, 1576 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1577 .reg_mib_cnt = MIB_COUNTER_NUM, 1578 .regs = ksz9477_regs, 1579 .masks = lan937x_masks, 1580 .shifts = lan937x_shifts, 1581 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1582 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1583 .supports_mii = {false, false, false, false, 1584 true, true, false, false}, 1585 .supports_rmii = {false, false, false, false, 1586 true, true, false, false}, 1587 .supports_rgmii = {false, false, false, false, 1588 true, true, false, false}, 1589 .internal_phy = {true, true, true, true, 1590 false, false, true, true}, 1591 }, 1592 }; 1593 EXPORT_SYMBOL_GPL(ksz_switch_chips); 1594 1595 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 1596 { 1597 int i; 1598 1599 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 1600 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 1601 1602 if (chip->chip_id == prod_num) 1603 return chip; 1604 } 1605 1606 return NULL; 1607 } 1608 1609 static int ksz_check_device_id(struct ksz_device *dev) 1610 { 1611 const struct ksz_chip_data *dt_chip_data; 1612 1613 dt_chip_data = of_device_get_match_data(dev->dev); 1614 1615 /* Check for Device Tree and Chip ID */ 1616 if (dt_chip_data->chip_id != dev->chip_id) { 1617 dev_err(dev->dev, 1618 "Device tree specifies chip %s but found %s, please fix it!\n", 1619 dt_chip_data->dev_name, dev->info->dev_name); 1620 return -ENODEV; 1621 } 1622 1623 return 0; 1624 } 1625 1626 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 1627 struct phylink_config *config) 1628 { 1629 struct ksz_device *dev = ds->priv; 1630 1631 config->legacy_pre_march2020 = false; 1632 1633 if (dev->info->supports_mii[port]) 1634 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1635 1636 if (dev->info->supports_rmii[port]) 1637 __set_bit(PHY_INTERFACE_MODE_RMII, 1638 config->supported_interfaces); 1639 1640 if (dev->info->supports_rgmii[port]) 1641 phy_interface_set_rgmii(config->supported_interfaces); 1642 1643 if (dev->info->internal_phy[port]) { 1644 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1645 config->supported_interfaces); 1646 /* Compatibility for phylib's default interface type when the 1647 * phy-mode property is absent 1648 */ 1649 __set_bit(PHY_INTERFACE_MODE_GMII, 1650 config->supported_interfaces); 1651 } 1652 1653 if (dev->dev_ops->get_caps) 1654 dev->dev_ops->get_caps(dev, port, config); 1655 } 1656 1657 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 1658 { 1659 struct ethtool_pause_stats *pstats; 1660 struct rtnl_link_stats64 *stats; 1661 struct ksz_stats_raw *raw; 1662 struct ksz_port_mib *mib; 1663 1664 mib = &dev->ports[port].mib; 1665 stats = &mib->stats64; 1666 pstats = &mib->pause_stats; 1667 raw = (struct ksz_stats_raw *)mib->counters; 1668 1669 spin_lock(&mib->stats64_lock); 1670 1671 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1672 raw->rx_pause; 1673 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1674 raw->tx_pause; 1675 1676 /* HW counters are counting bytes + FCS which is not acceptable 1677 * for rtnl_link_stats64 interface 1678 */ 1679 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 1680 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 1681 1682 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 1683 raw->rx_oversize; 1684 1685 stats->rx_crc_errors = raw->rx_crc_err; 1686 stats->rx_frame_errors = raw->rx_align_err; 1687 stats->rx_dropped = raw->rx_discards; 1688 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 1689 stats->rx_frame_errors + stats->rx_dropped; 1690 1691 stats->tx_window_errors = raw->tx_late_col; 1692 stats->tx_fifo_errors = raw->tx_discards; 1693 stats->tx_aborted_errors = raw->tx_exc_col; 1694 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 1695 stats->tx_aborted_errors; 1696 1697 stats->multicast = raw->rx_mcast; 1698 stats->collisions = raw->tx_total_col; 1699 1700 pstats->tx_pause_frames = raw->tx_pause; 1701 pstats->rx_pause_frames = raw->rx_pause; 1702 1703 spin_unlock(&mib->stats64_lock); 1704 } 1705 1706 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port) 1707 { 1708 struct ethtool_pause_stats *pstats; 1709 struct rtnl_link_stats64 *stats; 1710 struct ksz88xx_stats_raw *raw; 1711 struct ksz_port_mib *mib; 1712 1713 mib = &dev->ports[port].mib; 1714 stats = &mib->stats64; 1715 pstats = &mib->pause_stats; 1716 raw = (struct ksz88xx_stats_raw *)mib->counters; 1717 1718 spin_lock(&mib->stats64_lock); 1719 1720 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1721 raw->rx_pause; 1722 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1723 raw->tx_pause; 1724 1725 /* HW counters are counting bytes + FCS which is not acceptable 1726 * for rtnl_link_stats64 interface 1727 */ 1728 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN; 1729 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN; 1730 1731 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 1732 raw->rx_oversize; 1733 1734 stats->rx_crc_errors = raw->rx_crc_err; 1735 stats->rx_frame_errors = raw->rx_align_err; 1736 stats->rx_dropped = raw->rx_discards; 1737 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 1738 stats->rx_frame_errors + stats->rx_dropped; 1739 1740 stats->tx_window_errors = raw->tx_late_col; 1741 stats->tx_fifo_errors = raw->tx_discards; 1742 stats->tx_aborted_errors = raw->tx_exc_col; 1743 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 1744 stats->tx_aborted_errors; 1745 1746 stats->multicast = raw->rx_mcast; 1747 stats->collisions = raw->tx_total_col; 1748 1749 pstats->tx_pause_frames = raw->tx_pause; 1750 pstats->rx_pause_frames = raw->rx_pause; 1751 1752 spin_unlock(&mib->stats64_lock); 1753 } 1754 1755 static void ksz_get_stats64(struct dsa_switch *ds, int port, 1756 struct rtnl_link_stats64 *s) 1757 { 1758 struct ksz_device *dev = ds->priv; 1759 struct ksz_port_mib *mib; 1760 1761 mib = &dev->ports[port].mib; 1762 1763 spin_lock(&mib->stats64_lock); 1764 memcpy(s, &mib->stats64, sizeof(*s)); 1765 spin_unlock(&mib->stats64_lock); 1766 } 1767 1768 static void ksz_get_pause_stats(struct dsa_switch *ds, int port, 1769 struct ethtool_pause_stats *pause_stats) 1770 { 1771 struct ksz_device *dev = ds->priv; 1772 struct ksz_port_mib *mib; 1773 1774 mib = &dev->ports[port].mib; 1775 1776 spin_lock(&mib->stats64_lock); 1777 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 1778 spin_unlock(&mib->stats64_lock); 1779 } 1780 1781 static void ksz_get_strings(struct dsa_switch *ds, int port, 1782 u32 stringset, uint8_t *buf) 1783 { 1784 struct ksz_device *dev = ds->priv; 1785 int i; 1786 1787 if (stringset != ETH_SS_STATS) 1788 return; 1789 1790 for (i = 0; i < dev->info->mib_cnt; i++) { 1791 memcpy(buf + i * ETH_GSTRING_LEN, 1792 dev->info->mib_names[i].string, ETH_GSTRING_LEN); 1793 } 1794 } 1795 1796 static void ksz_update_port_member(struct ksz_device *dev, int port) 1797 { 1798 struct ksz_port *p = &dev->ports[port]; 1799 struct dsa_switch *ds = dev->ds; 1800 u8 port_member = 0, cpu_port; 1801 const struct dsa_port *dp; 1802 int i, j; 1803 1804 if (!dsa_is_user_port(ds, port)) 1805 return; 1806 1807 dp = dsa_to_port(ds, port); 1808 cpu_port = BIT(dsa_upstream_port(ds, port)); 1809 1810 for (i = 0; i < ds->num_ports; i++) { 1811 const struct dsa_port *other_dp = dsa_to_port(ds, i); 1812 struct ksz_port *other_p = &dev->ports[i]; 1813 u8 val = 0; 1814 1815 if (!dsa_is_user_port(ds, i)) 1816 continue; 1817 if (port == i) 1818 continue; 1819 if (!dsa_port_bridge_same(dp, other_dp)) 1820 continue; 1821 if (other_p->stp_state != BR_STATE_FORWARDING) 1822 continue; 1823 1824 if (p->stp_state == BR_STATE_FORWARDING) { 1825 val |= BIT(port); 1826 port_member |= BIT(i); 1827 } 1828 1829 /* Retain port [i]'s relationship to other ports than [port] */ 1830 for (j = 0; j < ds->num_ports; j++) { 1831 const struct dsa_port *third_dp; 1832 struct ksz_port *third_p; 1833 1834 if (j == i) 1835 continue; 1836 if (j == port) 1837 continue; 1838 if (!dsa_is_user_port(ds, j)) 1839 continue; 1840 third_p = &dev->ports[j]; 1841 if (third_p->stp_state != BR_STATE_FORWARDING) 1842 continue; 1843 third_dp = dsa_to_port(ds, j); 1844 if (dsa_port_bridge_same(other_dp, third_dp)) 1845 val |= BIT(j); 1846 } 1847 1848 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 1849 } 1850 1851 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 1852 } 1853 1854 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 1855 { 1856 struct ksz_device *dev = bus->priv; 1857 u16 val; 1858 int ret; 1859 1860 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val); 1861 if (ret < 0) 1862 return ret; 1863 1864 return val; 1865 } 1866 1867 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 1868 u16 val) 1869 { 1870 struct ksz_device *dev = bus->priv; 1871 1872 return dev->dev_ops->w_phy(dev, addr, regnum, val); 1873 } 1874 1875 static int ksz_irq_phy_setup(struct ksz_device *dev) 1876 { 1877 struct dsa_switch *ds = dev->ds; 1878 int phy; 1879 int irq; 1880 int ret; 1881 1882 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) { 1883 if (BIT(phy) & ds->phys_mii_mask) { 1884 irq = irq_find_mapping(dev->ports[phy].pirq.domain, 1885 PORT_SRC_PHY_INT); 1886 if (irq < 0) { 1887 ret = irq; 1888 goto out; 1889 } 1890 ds->slave_mii_bus->irq[phy] = irq; 1891 } 1892 } 1893 return 0; 1894 out: 1895 while (phy--) 1896 if (BIT(phy) & ds->phys_mii_mask) 1897 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]); 1898 1899 return ret; 1900 } 1901 1902 static void ksz_irq_phy_free(struct ksz_device *dev) 1903 { 1904 struct dsa_switch *ds = dev->ds; 1905 int phy; 1906 1907 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) 1908 if (BIT(phy) & ds->phys_mii_mask) 1909 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]); 1910 } 1911 1912 static int ksz_mdio_register(struct ksz_device *dev) 1913 { 1914 struct dsa_switch *ds = dev->ds; 1915 struct device_node *mdio_np; 1916 struct mii_bus *bus; 1917 int ret; 1918 1919 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); 1920 if (!mdio_np) 1921 return 0; 1922 1923 bus = devm_mdiobus_alloc(ds->dev); 1924 if (!bus) { 1925 of_node_put(mdio_np); 1926 return -ENOMEM; 1927 } 1928 1929 bus->priv = dev; 1930 bus->read = ksz_sw_mdio_read; 1931 bus->write = ksz_sw_mdio_write; 1932 bus->name = "ksz slave smi"; 1933 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); 1934 bus->parent = ds->dev; 1935 bus->phy_mask = ~ds->phys_mii_mask; 1936 1937 ds->slave_mii_bus = bus; 1938 1939 if (dev->irq > 0) { 1940 ret = ksz_irq_phy_setup(dev); 1941 if (ret) { 1942 of_node_put(mdio_np); 1943 return ret; 1944 } 1945 } 1946 1947 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); 1948 if (ret) { 1949 dev_err(ds->dev, "unable to register MDIO bus %s\n", 1950 bus->id); 1951 if (dev->irq > 0) 1952 ksz_irq_phy_free(dev); 1953 } 1954 1955 of_node_put(mdio_np); 1956 1957 return ret; 1958 } 1959 1960 static void ksz_irq_mask(struct irq_data *d) 1961 { 1962 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1963 1964 kirq->masked |= BIT(d->hwirq); 1965 } 1966 1967 static void ksz_irq_unmask(struct irq_data *d) 1968 { 1969 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1970 1971 kirq->masked &= ~BIT(d->hwirq); 1972 } 1973 1974 static void ksz_irq_bus_lock(struct irq_data *d) 1975 { 1976 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1977 1978 mutex_lock(&kirq->dev->lock_irq); 1979 } 1980 1981 static void ksz_irq_bus_sync_unlock(struct irq_data *d) 1982 { 1983 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1984 struct ksz_device *dev = kirq->dev; 1985 int ret; 1986 1987 ret = ksz_write32(dev, kirq->reg_mask, kirq->masked); 1988 if (ret) 1989 dev_err(dev->dev, "failed to change IRQ mask\n"); 1990 1991 mutex_unlock(&dev->lock_irq); 1992 } 1993 1994 static const struct irq_chip ksz_irq_chip = { 1995 .name = "ksz-irq", 1996 .irq_mask = ksz_irq_mask, 1997 .irq_unmask = ksz_irq_unmask, 1998 .irq_bus_lock = ksz_irq_bus_lock, 1999 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock, 2000 }; 2001 2002 static int ksz_irq_domain_map(struct irq_domain *d, 2003 unsigned int irq, irq_hw_number_t hwirq) 2004 { 2005 irq_set_chip_data(irq, d->host_data); 2006 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq); 2007 irq_set_noprobe(irq); 2008 2009 return 0; 2010 } 2011 2012 static const struct irq_domain_ops ksz_irq_domain_ops = { 2013 .map = ksz_irq_domain_map, 2014 .xlate = irq_domain_xlate_twocell, 2015 }; 2016 2017 static void ksz_irq_free(struct ksz_irq *kirq) 2018 { 2019 int irq, virq; 2020 2021 free_irq(kirq->irq_num, kirq); 2022 2023 for (irq = 0; irq < kirq->nirqs; irq++) { 2024 virq = irq_find_mapping(kirq->domain, irq); 2025 irq_dispose_mapping(virq); 2026 } 2027 2028 irq_domain_remove(kirq->domain); 2029 } 2030 2031 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id) 2032 { 2033 struct ksz_irq *kirq = dev_id; 2034 unsigned int nhandled = 0; 2035 struct ksz_device *dev; 2036 unsigned int sub_irq; 2037 u8 data; 2038 int ret; 2039 u8 n; 2040 2041 dev = kirq->dev; 2042 2043 /* Read interrupt status register */ 2044 ret = ksz_read8(dev, kirq->reg_status, &data); 2045 if (ret) 2046 goto out; 2047 2048 for (n = 0; n < kirq->nirqs; ++n) { 2049 if (data & BIT(n)) { 2050 sub_irq = irq_find_mapping(kirq->domain, n); 2051 handle_nested_irq(sub_irq); 2052 ++nhandled; 2053 } 2054 } 2055 out: 2056 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 2057 } 2058 2059 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq) 2060 { 2061 int ret, n; 2062 2063 kirq->dev = dev; 2064 kirq->masked = ~0; 2065 2066 kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0, 2067 &ksz_irq_domain_ops, kirq); 2068 if (!kirq->domain) 2069 return -ENOMEM; 2070 2071 for (n = 0; n < kirq->nirqs; n++) 2072 irq_create_mapping(kirq->domain, n); 2073 2074 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn, 2075 IRQF_ONESHOT, kirq->name, kirq); 2076 if (ret) 2077 goto out; 2078 2079 return 0; 2080 2081 out: 2082 ksz_irq_free(kirq); 2083 2084 return ret; 2085 } 2086 2087 static int ksz_girq_setup(struct ksz_device *dev) 2088 { 2089 struct ksz_irq *girq = &dev->girq; 2090 2091 girq->nirqs = dev->info->port_cnt; 2092 girq->reg_mask = REG_SW_PORT_INT_MASK__1; 2093 girq->reg_status = REG_SW_PORT_INT_STATUS__1; 2094 snprintf(girq->name, sizeof(girq->name), "global_port_irq"); 2095 2096 girq->irq_num = dev->irq; 2097 2098 return ksz_irq_common_setup(dev, girq); 2099 } 2100 2101 static int ksz_pirq_setup(struct ksz_device *dev, u8 p) 2102 { 2103 struct ksz_irq *pirq = &dev->ports[p].pirq; 2104 2105 pirq->nirqs = dev->info->port_nirqs; 2106 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK); 2107 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS); 2108 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p); 2109 2110 pirq->irq_num = irq_find_mapping(dev->girq.domain, p); 2111 if (pirq->irq_num < 0) 2112 return pirq->irq_num; 2113 2114 return ksz_irq_common_setup(dev, pirq); 2115 } 2116 2117 static int ksz_setup(struct dsa_switch *ds) 2118 { 2119 struct ksz_device *dev = ds->priv; 2120 struct dsa_port *dp; 2121 struct ksz_port *p; 2122 const u16 *regs; 2123 int ret; 2124 2125 regs = dev->info->regs; 2126 2127 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 2128 dev->info->num_vlans, GFP_KERNEL); 2129 if (!dev->vlan_cache) 2130 return -ENOMEM; 2131 2132 ret = dev->dev_ops->reset(dev); 2133 if (ret) { 2134 dev_err(ds->dev, "failed to reset switch\n"); 2135 return ret; 2136 } 2137 2138 /* set broadcast storm protection 10% rate */ 2139 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL], 2140 BROADCAST_STORM_RATE, 2141 (BROADCAST_STORM_VALUE * 2142 BROADCAST_STORM_PROT_RATE) / 100); 2143 2144 dev->dev_ops->config_cpu_port(ds); 2145 2146 dev->dev_ops->enable_stp_addr(dev); 2147 2148 ds->num_tx_queues = dev->info->num_tx_queues; 2149 2150 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL], 2151 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 2152 2153 ksz_init_mib_timer(dev); 2154 2155 ds->configure_vlan_while_not_filtering = false; 2156 2157 if (dev->dev_ops->setup) { 2158 ret = dev->dev_ops->setup(ds); 2159 if (ret) 2160 return ret; 2161 } 2162 2163 /* Start with learning disabled on standalone user ports, and enabled 2164 * on the CPU port. In lack of other finer mechanisms, learning on the 2165 * CPU port will avoid flooding bridge local addresses on the network 2166 * in some cases. 2167 */ 2168 p = &dev->ports[dev->cpu_port]; 2169 p->learning = true; 2170 2171 if (dev->irq > 0) { 2172 ret = ksz_girq_setup(dev); 2173 if (ret) 2174 return ret; 2175 2176 dsa_switch_for_each_user_port(dp, dev->ds) { 2177 ret = ksz_pirq_setup(dev, dp->index); 2178 if (ret) 2179 goto out_girq; 2180 2181 ret = ksz_ptp_irq_setup(ds, dp->index); 2182 if (ret) 2183 goto out_pirq; 2184 } 2185 } 2186 2187 ret = ksz_ptp_clock_register(ds); 2188 if (ret) { 2189 dev_err(dev->dev, "Failed to register PTP clock: %d\n", ret); 2190 goto out_ptpirq; 2191 } 2192 2193 ret = ksz_mdio_register(dev); 2194 if (ret < 0) { 2195 dev_err(dev->dev, "failed to register the mdio"); 2196 goto out_ptp_clock_unregister; 2197 } 2198 2199 /* start switch */ 2200 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL], 2201 SW_START, SW_START); 2202 2203 return 0; 2204 2205 out_ptp_clock_unregister: 2206 ksz_ptp_clock_unregister(ds); 2207 out_ptpirq: 2208 if (dev->irq > 0) 2209 dsa_switch_for_each_user_port(dp, dev->ds) 2210 ksz_ptp_irq_free(ds, dp->index); 2211 out_pirq: 2212 if (dev->irq > 0) 2213 dsa_switch_for_each_user_port(dp, dev->ds) 2214 ksz_irq_free(&dev->ports[dp->index].pirq); 2215 out_girq: 2216 if (dev->irq > 0) 2217 ksz_irq_free(&dev->girq); 2218 2219 return ret; 2220 } 2221 2222 static void ksz_teardown(struct dsa_switch *ds) 2223 { 2224 struct ksz_device *dev = ds->priv; 2225 struct dsa_port *dp; 2226 2227 ksz_ptp_clock_unregister(ds); 2228 2229 if (dev->irq > 0) { 2230 dsa_switch_for_each_user_port(dp, dev->ds) { 2231 ksz_ptp_irq_free(ds, dp->index); 2232 2233 ksz_irq_free(&dev->ports[dp->index].pirq); 2234 } 2235 2236 ksz_irq_free(&dev->girq); 2237 } 2238 2239 if (dev->dev_ops->teardown) 2240 dev->dev_ops->teardown(ds); 2241 } 2242 2243 static void port_r_cnt(struct ksz_device *dev, int port) 2244 { 2245 struct ksz_port_mib *mib = &dev->ports[port].mib; 2246 u64 *dropped; 2247 2248 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 2249 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 2250 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 2251 &mib->counters[mib->cnt_ptr]); 2252 ++mib->cnt_ptr; 2253 } 2254 2255 /* last one in storage */ 2256 dropped = &mib->counters[dev->info->mib_cnt]; 2257 2258 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 2259 while (mib->cnt_ptr < dev->info->mib_cnt) { 2260 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 2261 dropped, &mib->counters[mib->cnt_ptr]); 2262 ++mib->cnt_ptr; 2263 } 2264 mib->cnt_ptr = 0; 2265 } 2266 2267 static void ksz_mib_read_work(struct work_struct *work) 2268 { 2269 struct ksz_device *dev = container_of(work, struct ksz_device, 2270 mib_read.work); 2271 struct ksz_port_mib *mib; 2272 struct ksz_port *p; 2273 int i; 2274 2275 for (i = 0; i < dev->info->port_cnt; i++) { 2276 if (dsa_is_unused_port(dev->ds, i)) 2277 continue; 2278 2279 p = &dev->ports[i]; 2280 mib = &p->mib; 2281 mutex_lock(&mib->cnt_mutex); 2282 2283 /* Only read MIB counters when the port is told to do. 2284 * If not, read only dropped counters when link is not up. 2285 */ 2286 if (!p->read) { 2287 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 2288 2289 if (!netif_carrier_ok(dp->slave)) 2290 mib->cnt_ptr = dev->info->reg_mib_cnt; 2291 } 2292 port_r_cnt(dev, i); 2293 p->read = false; 2294 2295 if (dev->dev_ops->r_mib_stat64) 2296 dev->dev_ops->r_mib_stat64(dev, i); 2297 2298 mutex_unlock(&mib->cnt_mutex); 2299 } 2300 2301 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 2302 } 2303 2304 void ksz_init_mib_timer(struct ksz_device *dev) 2305 { 2306 int i; 2307 2308 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 2309 2310 for (i = 0; i < dev->info->port_cnt; i++) { 2311 struct ksz_port_mib *mib = &dev->ports[i].mib; 2312 2313 dev->dev_ops->port_init_cnt(dev, i); 2314 2315 mib->cnt_ptr = 0; 2316 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 2317 } 2318 } 2319 2320 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 2321 { 2322 struct ksz_device *dev = ds->priv; 2323 u16 val = 0xffff; 2324 int ret; 2325 2326 ret = dev->dev_ops->r_phy(dev, addr, reg, &val); 2327 if (ret) 2328 return ret; 2329 2330 return val; 2331 } 2332 2333 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 2334 { 2335 struct ksz_device *dev = ds->priv; 2336 int ret; 2337 2338 ret = dev->dev_ops->w_phy(dev, addr, reg, val); 2339 if (ret) 2340 return ret; 2341 2342 return 0; 2343 } 2344 2345 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 2346 { 2347 struct ksz_device *dev = ds->priv; 2348 2349 if (dev->chip_id == KSZ8830_CHIP_ID) { 2350 /* Silicon Errata Sheet (DS80000830A): 2351 * Port 1 does not work with LinkMD Cable-Testing. 2352 * Port 1 does not respond to received PAUSE control frames. 2353 */ 2354 if (!port) 2355 return MICREL_KSZ8_P1_ERRATA; 2356 } 2357 2358 return 0; 2359 } 2360 2361 static void ksz_mac_link_down(struct dsa_switch *ds, int port, 2362 unsigned int mode, phy_interface_t interface) 2363 { 2364 struct ksz_device *dev = ds->priv; 2365 struct ksz_port *p = &dev->ports[port]; 2366 2367 /* Read all MIB counters when the link is going down. */ 2368 p->read = true; 2369 /* timer started */ 2370 if (dev->mib_read_interval) 2371 schedule_delayed_work(&dev->mib_read, 0); 2372 } 2373 2374 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 2375 { 2376 struct ksz_device *dev = ds->priv; 2377 2378 if (sset != ETH_SS_STATS) 2379 return 0; 2380 2381 return dev->info->mib_cnt; 2382 } 2383 2384 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 2385 uint64_t *buf) 2386 { 2387 const struct dsa_port *dp = dsa_to_port(ds, port); 2388 struct ksz_device *dev = ds->priv; 2389 struct ksz_port_mib *mib; 2390 2391 mib = &dev->ports[port].mib; 2392 mutex_lock(&mib->cnt_mutex); 2393 2394 /* Only read dropped counters if no link. */ 2395 if (!netif_carrier_ok(dp->slave)) 2396 mib->cnt_ptr = dev->info->reg_mib_cnt; 2397 port_r_cnt(dev, port); 2398 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 2399 mutex_unlock(&mib->cnt_mutex); 2400 } 2401 2402 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 2403 struct dsa_bridge bridge, 2404 bool *tx_fwd_offload, 2405 struct netlink_ext_ack *extack) 2406 { 2407 /* port_stp_state_set() will be called after to put the port in 2408 * appropriate state so there is no need to do anything. 2409 */ 2410 2411 return 0; 2412 } 2413 2414 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 2415 struct dsa_bridge bridge) 2416 { 2417 /* port_stp_state_set() will be called after to put the port in 2418 * forwarding state so there is no need to do anything. 2419 */ 2420 } 2421 2422 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 2423 { 2424 struct ksz_device *dev = ds->priv; 2425 2426 dev->dev_ops->flush_dyn_mac_table(dev, port); 2427 } 2428 2429 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 2430 { 2431 struct ksz_device *dev = ds->priv; 2432 2433 if (!dev->dev_ops->set_ageing_time) 2434 return -EOPNOTSUPP; 2435 2436 return dev->dev_ops->set_ageing_time(dev, msecs); 2437 } 2438 2439 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 2440 const unsigned char *addr, u16 vid, 2441 struct dsa_db db) 2442 { 2443 struct ksz_device *dev = ds->priv; 2444 2445 if (!dev->dev_ops->fdb_add) 2446 return -EOPNOTSUPP; 2447 2448 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 2449 } 2450 2451 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 2452 const unsigned char *addr, 2453 u16 vid, struct dsa_db db) 2454 { 2455 struct ksz_device *dev = ds->priv; 2456 2457 if (!dev->dev_ops->fdb_del) 2458 return -EOPNOTSUPP; 2459 2460 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 2461 } 2462 2463 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 2464 dsa_fdb_dump_cb_t *cb, void *data) 2465 { 2466 struct ksz_device *dev = ds->priv; 2467 2468 if (!dev->dev_ops->fdb_dump) 2469 return -EOPNOTSUPP; 2470 2471 return dev->dev_ops->fdb_dump(dev, port, cb, data); 2472 } 2473 2474 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 2475 const struct switchdev_obj_port_mdb *mdb, 2476 struct dsa_db db) 2477 { 2478 struct ksz_device *dev = ds->priv; 2479 2480 if (!dev->dev_ops->mdb_add) 2481 return -EOPNOTSUPP; 2482 2483 return dev->dev_ops->mdb_add(dev, port, mdb, db); 2484 } 2485 2486 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 2487 const struct switchdev_obj_port_mdb *mdb, 2488 struct dsa_db db) 2489 { 2490 struct ksz_device *dev = ds->priv; 2491 2492 if (!dev->dev_ops->mdb_del) 2493 return -EOPNOTSUPP; 2494 2495 return dev->dev_ops->mdb_del(dev, port, mdb, db); 2496 } 2497 2498 static int ksz_enable_port(struct dsa_switch *ds, int port, 2499 struct phy_device *phy) 2500 { 2501 struct ksz_device *dev = ds->priv; 2502 2503 if (!dsa_is_user_port(ds, port)) 2504 return 0; 2505 2506 /* setup slave port */ 2507 dev->dev_ops->port_setup(dev, port, false); 2508 2509 /* port_stp_state_set() will be called after to enable the port so 2510 * there is no need to do anything. 2511 */ 2512 2513 return 0; 2514 } 2515 2516 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 2517 { 2518 struct ksz_device *dev = ds->priv; 2519 struct ksz_port *p; 2520 const u16 *regs; 2521 u8 data; 2522 2523 regs = dev->info->regs; 2524 2525 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 2526 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2527 2528 p = &dev->ports[port]; 2529 2530 switch (state) { 2531 case BR_STATE_DISABLED: 2532 data |= PORT_LEARN_DISABLE; 2533 break; 2534 case BR_STATE_LISTENING: 2535 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2536 break; 2537 case BR_STATE_LEARNING: 2538 data |= PORT_RX_ENABLE; 2539 if (!p->learning) 2540 data |= PORT_LEARN_DISABLE; 2541 break; 2542 case BR_STATE_FORWARDING: 2543 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 2544 if (!p->learning) 2545 data |= PORT_LEARN_DISABLE; 2546 break; 2547 case BR_STATE_BLOCKING: 2548 data |= PORT_LEARN_DISABLE; 2549 break; 2550 default: 2551 dev_err(ds->dev, "invalid STP state: %d\n", state); 2552 return; 2553 } 2554 2555 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 2556 2557 p->stp_state = state; 2558 2559 ksz_update_port_member(dev, port); 2560 } 2561 2562 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 2563 struct switchdev_brport_flags flags, 2564 struct netlink_ext_ack *extack) 2565 { 2566 if (flags.mask & ~BR_LEARNING) 2567 return -EINVAL; 2568 2569 return 0; 2570 } 2571 2572 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 2573 struct switchdev_brport_flags flags, 2574 struct netlink_ext_ack *extack) 2575 { 2576 struct ksz_device *dev = ds->priv; 2577 struct ksz_port *p = &dev->ports[port]; 2578 2579 if (flags.mask & BR_LEARNING) { 2580 p->learning = !!(flags.val & BR_LEARNING); 2581 2582 /* Make the change take effect immediately */ 2583 ksz_port_stp_state_set(ds, port, p->stp_state); 2584 } 2585 2586 return 0; 2587 } 2588 2589 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 2590 int port, 2591 enum dsa_tag_protocol mp) 2592 { 2593 struct ksz_device *dev = ds->priv; 2594 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 2595 2596 if (dev->chip_id == KSZ8795_CHIP_ID || 2597 dev->chip_id == KSZ8794_CHIP_ID || 2598 dev->chip_id == KSZ8765_CHIP_ID) 2599 proto = DSA_TAG_PROTO_KSZ8795; 2600 2601 if (dev->chip_id == KSZ8830_CHIP_ID || 2602 dev->chip_id == KSZ8563_CHIP_ID || 2603 dev->chip_id == KSZ9893_CHIP_ID || 2604 dev->chip_id == KSZ9563_CHIP_ID) 2605 proto = DSA_TAG_PROTO_KSZ9893; 2606 2607 if (dev->chip_id == KSZ9477_CHIP_ID || 2608 dev->chip_id == KSZ9896_CHIP_ID || 2609 dev->chip_id == KSZ9897_CHIP_ID || 2610 dev->chip_id == KSZ9567_CHIP_ID) 2611 proto = DSA_TAG_PROTO_KSZ9477; 2612 2613 if (is_lan937x(dev)) 2614 proto = DSA_TAG_PROTO_LAN937X_VALUE; 2615 2616 return proto; 2617 } 2618 2619 static int ksz_connect_tag_protocol(struct dsa_switch *ds, 2620 enum dsa_tag_protocol proto) 2621 { 2622 struct ksz_tagger_data *tagger_data; 2623 2624 tagger_data = ksz_tagger_data(ds); 2625 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 2626 2627 return 0; 2628 } 2629 2630 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 2631 bool flag, struct netlink_ext_ack *extack) 2632 { 2633 struct ksz_device *dev = ds->priv; 2634 2635 if (!dev->dev_ops->vlan_filtering) 2636 return -EOPNOTSUPP; 2637 2638 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 2639 } 2640 2641 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 2642 const struct switchdev_obj_port_vlan *vlan, 2643 struct netlink_ext_ack *extack) 2644 { 2645 struct ksz_device *dev = ds->priv; 2646 2647 if (!dev->dev_ops->vlan_add) 2648 return -EOPNOTSUPP; 2649 2650 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 2651 } 2652 2653 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 2654 const struct switchdev_obj_port_vlan *vlan) 2655 { 2656 struct ksz_device *dev = ds->priv; 2657 2658 if (!dev->dev_ops->vlan_del) 2659 return -EOPNOTSUPP; 2660 2661 return dev->dev_ops->vlan_del(dev, port, vlan); 2662 } 2663 2664 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 2665 struct dsa_mall_mirror_tc_entry *mirror, 2666 bool ingress, struct netlink_ext_ack *extack) 2667 { 2668 struct ksz_device *dev = ds->priv; 2669 2670 if (!dev->dev_ops->mirror_add) 2671 return -EOPNOTSUPP; 2672 2673 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 2674 } 2675 2676 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 2677 struct dsa_mall_mirror_tc_entry *mirror) 2678 { 2679 struct ksz_device *dev = ds->priv; 2680 2681 if (dev->dev_ops->mirror_del) 2682 dev->dev_ops->mirror_del(dev, port, mirror); 2683 } 2684 2685 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 2686 { 2687 struct ksz_device *dev = ds->priv; 2688 2689 if (!dev->dev_ops->change_mtu) 2690 return -EOPNOTSUPP; 2691 2692 return dev->dev_ops->change_mtu(dev, port, mtu); 2693 } 2694 2695 static int ksz_max_mtu(struct dsa_switch *ds, int port) 2696 { 2697 struct ksz_device *dev = ds->priv; 2698 2699 switch (dev->chip_id) { 2700 case KSZ8795_CHIP_ID: 2701 case KSZ8794_CHIP_ID: 2702 case KSZ8765_CHIP_ID: 2703 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2704 case KSZ8830_CHIP_ID: 2705 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2706 case KSZ8563_CHIP_ID: 2707 case KSZ9477_CHIP_ID: 2708 case KSZ9563_CHIP_ID: 2709 case KSZ9567_CHIP_ID: 2710 case KSZ9893_CHIP_ID: 2711 case KSZ9896_CHIP_ID: 2712 case KSZ9897_CHIP_ID: 2713 case LAN9370_CHIP_ID: 2714 case LAN9371_CHIP_ID: 2715 case LAN9372_CHIP_ID: 2716 case LAN9373_CHIP_ID: 2717 case LAN9374_CHIP_ID: 2718 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2719 } 2720 2721 return -EOPNOTSUPP; 2722 } 2723 2724 static int ksz_validate_eee(struct dsa_switch *ds, int port) 2725 { 2726 struct ksz_device *dev = ds->priv; 2727 2728 if (!dev->info->internal_phy[port]) 2729 return -EOPNOTSUPP; 2730 2731 switch (dev->chip_id) { 2732 case KSZ8563_CHIP_ID: 2733 case KSZ9477_CHIP_ID: 2734 case KSZ9563_CHIP_ID: 2735 case KSZ9567_CHIP_ID: 2736 case KSZ9893_CHIP_ID: 2737 case KSZ9896_CHIP_ID: 2738 case KSZ9897_CHIP_ID: 2739 return 0; 2740 } 2741 2742 return -EOPNOTSUPP; 2743 } 2744 2745 static int ksz_get_mac_eee(struct dsa_switch *ds, int port, 2746 struct ethtool_eee *e) 2747 { 2748 int ret; 2749 2750 ret = ksz_validate_eee(ds, port); 2751 if (ret) 2752 return ret; 2753 2754 /* There is no documented control of Tx LPI configuration. */ 2755 e->tx_lpi_enabled = true; 2756 2757 /* There is no documented control of Tx LPI timer. According to tests 2758 * Tx LPI timer seems to be set by default to minimal value. 2759 */ 2760 e->tx_lpi_timer = 0; 2761 2762 return 0; 2763 } 2764 2765 static int ksz_set_mac_eee(struct dsa_switch *ds, int port, 2766 struct ethtool_eee *e) 2767 { 2768 struct ksz_device *dev = ds->priv; 2769 int ret; 2770 2771 ret = ksz_validate_eee(ds, port); 2772 if (ret) 2773 return ret; 2774 2775 if (!e->tx_lpi_enabled) { 2776 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n"); 2777 return -EINVAL; 2778 } 2779 2780 if (e->tx_lpi_timer) { 2781 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n"); 2782 return -EINVAL; 2783 } 2784 2785 return 0; 2786 } 2787 2788 static void ksz_set_xmii(struct ksz_device *dev, int port, 2789 phy_interface_t interface) 2790 { 2791 const u8 *bitval = dev->info->xmii_ctrl1; 2792 struct ksz_port *p = &dev->ports[port]; 2793 const u16 *regs = dev->info->regs; 2794 u8 data8; 2795 2796 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2797 2798 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 2799 P_RGMII_ID_EG_ENABLE); 2800 2801 switch (interface) { 2802 case PHY_INTERFACE_MODE_MII: 2803 data8 |= bitval[P_MII_SEL]; 2804 break; 2805 case PHY_INTERFACE_MODE_RMII: 2806 data8 |= bitval[P_RMII_SEL]; 2807 break; 2808 case PHY_INTERFACE_MODE_GMII: 2809 data8 |= bitval[P_GMII_SEL]; 2810 break; 2811 case PHY_INTERFACE_MODE_RGMII: 2812 case PHY_INTERFACE_MODE_RGMII_ID: 2813 case PHY_INTERFACE_MODE_RGMII_TXID: 2814 case PHY_INTERFACE_MODE_RGMII_RXID: 2815 data8 |= bitval[P_RGMII_SEL]; 2816 /* On KSZ9893, disable RGMII in-band status support */ 2817 if (dev->chip_id == KSZ9893_CHIP_ID || 2818 dev->chip_id == KSZ8563_CHIP_ID || 2819 dev->chip_id == KSZ9563_CHIP_ID) 2820 data8 &= ~P_MII_MAC_MODE; 2821 break; 2822 default: 2823 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 2824 phy_modes(interface), port); 2825 return; 2826 } 2827 2828 if (p->rgmii_tx_val) 2829 data8 |= P_RGMII_ID_EG_ENABLE; 2830 2831 if (p->rgmii_rx_val) 2832 data8 |= P_RGMII_ID_IG_ENABLE; 2833 2834 /* Write the updated value */ 2835 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 2836 } 2837 2838 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 2839 { 2840 const u8 *bitval = dev->info->xmii_ctrl1; 2841 const u16 *regs = dev->info->regs; 2842 phy_interface_t interface; 2843 u8 data8; 2844 u8 val; 2845 2846 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2847 2848 val = FIELD_GET(P_MII_SEL_M, data8); 2849 2850 if (val == bitval[P_MII_SEL]) { 2851 if (gbit) 2852 interface = PHY_INTERFACE_MODE_GMII; 2853 else 2854 interface = PHY_INTERFACE_MODE_MII; 2855 } else if (val == bitval[P_RMII_SEL]) { 2856 interface = PHY_INTERFACE_MODE_RGMII; 2857 } else { 2858 interface = PHY_INTERFACE_MODE_RGMII; 2859 if (data8 & P_RGMII_ID_EG_ENABLE) 2860 interface = PHY_INTERFACE_MODE_RGMII_TXID; 2861 if (data8 & P_RGMII_ID_IG_ENABLE) { 2862 interface = PHY_INTERFACE_MODE_RGMII_RXID; 2863 if (data8 & P_RGMII_ID_EG_ENABLE) 2864 interface = PHY_INTERFACE_MODE_RGMII_ID; 2865 } 2866 } 2867 2868 return interface; 2869 } 2870 2871 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port, 2872 unsigned int mode, 2873 const struct phylink_link_state *state) 2874 { 2875 struct ksz_device *dev = ds->priv; 2876 2877 if (ksz_is_ksz88x3(dev)) 2878 return; 2879 2880 /* Internal PHYs */ 2881 if (dev->info->internal_phy[port]) 2882 return; 2883 2884 if (phylink_autoneg_inband(mode)) { 2885 dev_err(dev->dev, "In-band AN not supported!\n"); 2886 return; 2887 } 2888 2889 ksz_set_xmii(dev, port, state->interface); 2890 2891 if (dev->dev_ops->phylink_mac_config) 2892 dev->dev_ops->phylink_mac_config(dev, port, mode, state); 2893 2894 if (dev->dev_ops->setup_rgmii_delay) 2895 dev->dev_ops->setup_rgmii_delay(dev, port); 2896 } 2897 2898 bool ksz_get_gbit(struct ksz_device *dev, int port) 2899 { 2900 const u8 *bitval = dev->info->xmii_ctrl1; 2901 const u16 *regs = dev->info->regs; 2902 bool gbit = false; 2903 u8 data8; 2904 bool val; 2905 2906 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2907 2908 val = FIELD_GET(P_GMII_1GBIT_M, data8); 2909 2910 if (val == bitval[P_GMII_1GBIT]) 2911 gbit = true; 2912 2913 return gbit; 2914 } 2915 2916 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) 2917 { 2918 const u8 *bitval = dev->info->xmii_ctrl1; 2919 const u16 *regs = dev->info->regs; 2920 u8 data8; 2921 2922 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2923 2924 data8 &= ~P_GMII_1GBIT_M; 2925 2926 if (gbit) 2927 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 2928 else 2929 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 2930 2931 /* Write the updated value */ 2932 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 2933 } 2934 2935 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) 2936 { 2937 const u8 *bitval = dev->info->xmii_ctrl0; 2938 const u16 *regs = dev->info->regs; 2939 u8 data8; 2940 2941 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 2942 2943 data8 &= ~P_MII_100MBIT_M; 2944 2945 if (speed == SPEED_100) 2946 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 2947 else 2948 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 2949 2950 /* Write the updated value */ 2951 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 2952 } 2953 2954 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) 2955 { 2956 if (speed == SPEED_1000) 2957 ksz_set_gbit(dev, port, true); 2958 else 2959 ksz_set_gbit(dev, port, false); 2960 2961 if (speed == SPEED_100 || speed == SPEED_10) 2962 ksz_set_100_10mbit(dev, port, speed); 2963 } 2964 2965 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 2966 bool tx_pause, bool rx_pause) 2967 { 2968 const u8 *bitval = dev->info->xmii_ctrl0; 2969 const u32 *masks = dev->info->masks; 2970 const u16 *regs = dev->info->regs; 2971 u8 mask; 2972 u8 val; 2973 2974 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 2975 masks[P_MII_RX_FLOW_CTRL]; 2976 2977 if (duplex == DUPLEX_FULL) 2978 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 2979 else 2980 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 2981 2982 if (tx_pause) 2983 val |= masks[P_MII_TX_FLOW_CTRL]; 2984 2985 if (rx_pause) 2986 val |= masks[P_MII_RX_FLOW_CTRL]; 2987 2988 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 2989 } 2990 2991 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, 2992 unsigned int mode, 2993 phy_interface_t interface, 2994 struct phy_device *phydev, int speed, 2995 int duplex, bool tx_pause, 2996 bool rx_pause) 2997 { 2998 struct ksz_port *p; 2999 3000 p = &dev->ports[port]; 3001 3002 /* Internal PHYs */ 3003 if (dev->info->internal_phy[port]) 3004 return; 3005 3006 p->phydev.speed = speed; 3007 3008 ksz_port_set_xmii_speed(dev, port, speed); 3009 3010 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 3011 } 3012 3013 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port, 3014 unsigned int mode, 3015 phy_interface_t interface, 3016 struct phy_device *phydev, int speed, 3017 int duplex, bool tx_pause, bool rx_pause) 3018 { 3019 struct ksz_device *dev = ds->priv; 3020 3021 if (dev->dev_ops->phylink_mac_link_up) 3022 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface, 3023 phydev, speed, duplex, 3024 tx_pause, rx_pause); 3025 } 3026 3027 static int ksz_switch_detect(struct ksz_device *dev) 3028 { 3029 u8 id1, id2, id4; 3030 u16 id16; 3031 u32 id32; 3032 int ret; 3033 3034 /* read chip id */ 3035 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 3036 if (ret) 3037 return ret; 3038 3039 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 3040 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 3041 3042 switch (id1) { 3043 case KSZ87_FAMILY_ID: 3044 if (id2 == KSZ87_CHIP_ID_95) { 3045 u8 val; 3046 3047 dev->chip_id = KSZ8795_CHIP_ID; 3048 3049 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 3050 if (val & KSZ8_PORT_FIBER_MODE) 3051 dev->chip_id = KSZ8765_CHIP_ID; 3052 } else if (id2 == KSZ87_CHIP_ID_94) { 3053 dev->chip_id = KSZ8794_CHIP_ID; 3054 } else { 3055 return -ENODEV; 3056 } 3057 break; 3058 case KSZ88_FAMILY_ID: 3059 if (id2 == KSZ88_CHIP_ID_63) 3060 dev->chip_id = KSZ8830_CHIP_ID; 3061 else 3062 return -ENODEV; 3063 break; 3064 default: 3065 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 3066 if (ret) 3067 return ret; 3068 3069 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 3070 id32 &= ~0xFF; 3071 3072 switch (id32) { 3073 case KSZ9477_CHIP_ID: 3074 case KSZ9896_CHIP_ID: 3075 case KSZ9897_CHIP_ID: 3076 case KSZ9567_CHIP_ID: 3077 case LAN9370_CHIP_ID: 3078 case LAN9371_CHIP_ID: 3079 case LAN9372_CHIP_ID: 3080 case LAN9373_CHIP_ID: 3081 case LAN9374_CHIP_ID: 3082 dev->chip_id = id32; 3083 break; 3084 case KSZ9893_CHIP_ID: 3085 ret = ksz_read8(dev, REG_CHIP_ID4, 3086 &id4); 3087 if (ret) 3088 return ret; 3089 3090 if (id4 == SKU_ID_KSZ8563) 3091 dev->chip_id = KSZ8563_CHIP_ID; 3092 else if (id4 == SKU_ID_KSZ9563) 3093 dev->chip_id = KSZ9563_CHIP_ID; 3094 else 3095 dev->chip_id = KSZ9893_CHIP_ID; 3096 3097 break; 3098 default: 3099 dev_err(dev->dev, 3100 "unsupported switch detected %x)\n", id32); 3101 return -ENODEV; 3102 } 3103 } 3104 return 0; 3105 } 3106 3107 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth 3108 * is converted to Hex-decimal using the successive multiplication method. On 3109 * every step, integer part is taken and decimal part is carry forwarded. 3110 */ 3111 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw) 3112 { 3113 u32 cinc = 0; 3114 u32 txrate; 3115 u32 rate; 3116 u8 temp; 3117 u8 i; 3118 3119 txrate = idle_slope - send_slope; 3120 3121 if (!txrate) 3122 return -EINVAL; 3123 3124 rate = idle_slope; 3125 3126 /* 24 bit register */ 3127 for (i = 0; i < 6; i++) { 3128 rate = rate * 16; 3129 3130 temp = rate / txrate; 3131 3132 rate %= txrate; 3133 3134 cinc = ((cinc << 4) | temp); 3135 } 3136 3137 *bw = cinc; 3138 3139 return 0; 3140 } 3141 3142 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler, 3143 u8 shaper) 3144 { 3145 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0, 3146 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) | 3147 FIELD_PREP(MTI_SHAPING_M, shaper)); 3148 } 3149 3150 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port, 3151 struct tc_cbs_qopt_offload *qopt) 3152 { 3153 struct ksz_device *dev = ds->priv; 3154 int ret; 3155 u32 bw; 3156 3157 if (!dev->info->tc_cbs_supported) 3158 return -EOPNOTSUPP; 3159 3160 if (qopt->queue > dev->info->num_tx_queues) 3161 return -EINVAL; 3162 3163 /* Queue Selection */ 3164 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue); 3165 if (ret) 3166 return ret; 3167 3168 if (!qopt->enable) 3169 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3170 MTI_SHAPING_OFF); 3171 3172 /* High Credit */ 3173 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK, 3174 qopt->hicredit); 3175 if (ret) 3176 return ret; 3177 3178 /* Low Credit */ 3179 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK, 3180 qopt->locredit); 3181 if (ret) 3182 return ret; 3183 3184 /* Credit Increment Register */ 3185 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw); 3186 if (ret) 3187 return ret; 3188 3189 if (dev->dev_ops->tc_cbs_set_cinc) { 3190 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw); 3191 if (ret) 3192 return ret; 3193 } 3194 3195 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3196 MTI_SHAPING_SRP); 3197 } 3198 3199 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port) 3200 { 3201 int queue, ret; 3202 3203 /* Configuration will not take effect until the last Port Queue X 3204 * Egress Limit Control Register is written. 3205 */ 3206 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3207 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue, 3208 KSZ9477_OUT_RATE_NO_LIMIT); 3209 if (ret) 3210 return ret; 3211 } 3212 3213 return 0; 3214 } 3215 3216 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p, 3217 int band) 3218 { 3219 /* Compared to queues, bands prioritize packets differently. In strict 3220 * priority mode, the lowest priority is assigned to Queue 0 while the 3221 * highest priority is given to Band 0. 3222 */ 3223 return p->bands - 1 - band; 3224 } 3225 3226 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue) 3227 { 3228 int ret; 3229 3230 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3231 if (ret) 3232 return ret; 3233 3234 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3235 MTI_SHAPING_OFF); 3236 } 3237 3238 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue, 3239 int weight) 3240 { 3241 int ret; 3242 3243 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3244 if (ret) 3245 return ret; 3246 3247 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3248 MTI_SHAPING_OFF); 3249 if (ret) 3250 return ret; 3251 3252 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight); 3253 } 3254 3255 static int ksz_tc_ets_add(struct ksz_device *dev, int port, 3256 struct tc_ets_qopt_offload_replace_params *p) 3257 { 3258 int ret, band, tc_prio; 3259 u32 queue_map = 0; 3260 3261 /* In order to ensure proper prioritization, it is necessary to set the 3262 * rate limit for the related queue to zero. Otherwise strict priority 3263 * or WRR mode will not work. This is a hardware limitation. 3264 */ 3265 ret = ksz_disable_egress_rate_limit(dev, port); 3266 if (ret) 3267 return ret; 3268 3269 /* Configure queue scheduling mode for all bands. Currently only strict 3270 * prio mode is supported. 3271 */ 3272 for (band = 0; band < p->bands; band++) { 3273 int queue = ksz_ets_band_to_queue(p, band); 3274 3275 ret = ksz_queue_set_strict(dev, port, queue); 3276 if (ret) 3277 return ret; 3278 } 3279 3280 /* Configure the mapping between traffic classes and queues. Note: 3281 * priomap variable support 16 traffic classes, but the chip can handle 3282 * only 8 classes. 3283 */ 3284 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) { 3285 int queue; 3286 3287 if (tc_prio > KSZ9477_MAX_TC_PRIO) 3288 break; 3289 3290 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]); 3291 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 3292 } 3293 3294 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3295 } 3296 3297 static int ksz_tc_ets_del(struct ksz_device *dev, int port) 3298 { 3299 int ret, queue, tc_prio, s; 3300 u32 queue_map = 0; 3301 3302 /* To restore the default chip configuration, set all queues to use the 3303 * WRR scheduler with a weight of 1. 3304 */ 3305 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3306 ret = ksz_queue_set_wrr(dev, port, queue, 3307 KSZ9477_DEFAULT_WRR_WEIGHT); 3308 if (ret) 3309 return ret; 3310 } 3311 3312 switch (dev->info->num_tx_queues) { 3313 case 2: 3314 s = 2; 3315 break; 3316 case 4: 3317 s = 1; 3318 break; 3319 case 8: 3320 s = 0; 3321 break; 3322 default: 3323 return -EINVAL; 3324 } 3325 3326 /* Revert the queue mapping for TC-priority to its default setting on 3327 * the chip. 3328 */ 3329 for (tc_prio = 0; tc_prio <= KSZ9477_MAX_TC_PRIO; tc_prio++) { 3330 int queue; 3331 3332 queue = tc_prio >> s; 3333 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 3334 } 3335 3336 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3337 } 3338 3339 static int ksz_tc_ets_validate(struct ksz_device *dev, int port, 3340 struct tc_ets_qopt_offload_replace_params *p) 3341 { 3342 int band; 3343 3344 /* Since it is not feasible to share one port among multiple qdisc, 3345 * the user must configure all available queues appropriately. 3346 */ 3347 if (p->bands != dev->info->num_tx_queues) { 3348 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n", 3349 dev->info->num_tx_queues); 3350 return -EOPNOTSUPP; 3351 } 3352 3353 for (band = 0; band < p->bands; ++band) { 3354 /* The KSZ switches utilize a weighted round robin configuration 3355 * where a certain number of packets can be transmitted from a 3356 * queue before the next queue is serviced. For more information 3357 * on this, refer to section 5.2.8.4 of the KSZ8565R 3358 * documentation on the Port Transmit Queue Control 1 Register. 3359 * However, the current ETS Qdisc implementation (as of February 3360 * 2023) assigns a weight to each queue based on the number of 3361 * bytes or extrapolated bandwidth in percentages. Since this 3362 * differs from the KSZ switches' method and we don't want to 3363 * fake support by converting bytes to packets, it is better to 3364 * return an error instead. 3365 */ 3366 if (p->quanta[band]) { 3367 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n"); 3368 return -EOPNOTSUPP; 3369 } 3370 } 3371 3372 return 0; 3373 } 3374 3375 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port, 3376 struct tc_ets_qopt_offload *qopt) 3377 { 3378 struct ksz_device *dev = ds->priv; 3379 int ret; 3380 3381 if (!dev->info->tc_ets_supported) 3382 return -EOPNOTSUPP; 3383 3384 if (qopt->parent != TC_H_ROOT) { 3385 dev_err(dev->dev, "Parent should be \"root\"\n"); 3386 return -EOPNOTSUPP; 3387 } 3388 3389 switch (qopt->command) { 3390 case TC_ETS_REPLACE: 3391 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params); 3392 if (ret) 3393 return ret; 3394 3395 return ksz_tc_ets_add(dev, port, &qopt->replace_params); 3396 case TC_ETS_DESTROY: 3397 return ksz_tc_ets_del(dev, port); 3398 case TC_ETS_STATS: 3399 case TC_ETS_GRAFT: 3400 return -EOPNOTSUPP; 3401 } 3402 3403 return -EOPNOTSUPP; 3404 } 3405 3406 static int ksz_setup_tc(struct dsa_switch *ds, int port, 3407 enum tc_setup_type type, void *type_data) 3408 { 3409 switch (type) { 3410 case TC_SETUP_QDISC_CBS: 3411 return ksz_setup_tc_cbs(ds, port, type_data); 3412 case TC_SETUP_QDISC_ETS: 3413 return ksz_tc_setup_qdisc_ets(ds, port, type_data); 3414 default: 3415 return -EOPNOTSUPP; 3416 } 3417 } 3418 3419 static const struct dsa_switch_ops ksz_switch_ops = { 3420 .get_tag_protocol = ksz_get_tag_protocol, 3421 .connect_tag_protocol = ksz_connect_tag_protocol, 3422 .get_phy_flags = ksz_get_phy_flags, 3423 .setup = ksz_setup, 3424 .teardown = ksz_teardown, 3425 .phy_read = ksz_phy_read16, 3426 .phy_write = ksz_phy_write16, 3427 .phylink_get_caps = ksz_phylink_get_caps, 3428 .phylink_mac_config = ksz_phylink_mac_config, 3429 .phylink_mac_link_up = ksz_phylink_mac_link_up, 3430 .phylink_mac_link_down = ksz_mac_link_down, 3431 .port_enable = ksz_enable_port, 3432 .set_ageing_time = ksz_set_ageing_time, 3433 .get_strings = ksz_get_strings, 3434 .get_ethtool_stats = ksz_get_ethtool_stats, 3435 .get_sset_count = ksz_sset_count, 3436 .port_bridge_join = ksz_port_bridge_join, 3437 .port_bridge_leave = ksz_port_bridge_leave, 3438 .port_stp_state_set = ksz_port_stp_state_set, 3439 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 3440 .port_bridge_flags = ksz_port_bridge_flags, 3441 .port_fast_age = ksz_port_fast_age, 3442 .port_vlan_filtering = ksz_port_vlan_filtering, 3443 .port_vlan_add = ksz_port_vlan_add, 3444 .port_vlan_del = ksz_port_vlan_del, 3445 .port_fdb_dump = ksz_port_fdb_dump, 3446 .port_fdb_add = ksz_port_fdb_add, 3447 .port_fdb_del = ksz_port_fdb_del, 3448 .port_mdb_add = ksz_port_mdb_add, 3449 .port_mdb_del = ksz_port_mdb_del, 3450 .port_mirror_add = ksz_port_mirror_add, 3451 .port_mirror_del = ksz_port_mirror_del, 3452 .get_stats64 = ksz_get_stats64, 3453 .get_pause_stats = ksz_get_pause_stats, 3454 .port_change_mtu = ksz_change_mtu, 3455 .port_max_mtu = ksz_max_mtu, 3456 .get_ts_info = ksz_get_ts_info, 3457 .port_hwtstamp_get = ksz_hwtstamp_get, 3458 .port_hwtstamp_set = ksz_hwtstamp_set, 3459 .port_txtstamp = ksz_port_txtstamp, 3460 .port_rxtstamp = ksz_port_rxtstamp, 3461 .port_setup_tc = ksz_setup_tc, 3462 .get_mac_eee = ksz_get_mac_eee, 3463 .set_mac_eee = ksz_set_mac_eee, 3464 }; 3465 3466 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 3467 { 3468 struct dsa_switch *ds; 3469 struct ksz_device *swdev; 3470 3471 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 3472 if (!ds) 3473 return NULL; 3474 3475 ds->dev = base; 3476 ds->num_ports = DSA_MAX_PORTS; 3477 ds->ops = &ksz_switch_ops; 3478 3479 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 3480 if (!swdev) 3481 return NULL; 3482 3483 ds->priv = swdev; 3484 swdev->dev = base; 3485 3486 swdev->ds = ds; 3487 swdev->priv = priv; 3488 3489 return swdev; 3490 } 3491 EXPORT_SYMBOL(ksz_switch_alloc); 3492 3493 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 3494 struct device_node *port_dn) 3495 { 3496 phy_interface_t phy_mode = dev->ports[port_num].interface; 3497 int rx_delay = -1, tx_delay = -1; 3498 3499 if (!phy_interface_mode_is_rgmii(phy_mode)) 3500 return; 3501 3502 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 3503 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 3504 3505 if (rx_delay == -1 && tx_delay == -1) { 3506 dev_warn(dev->dev, 3507 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 3508 "please update device tree to specify \"rx-internal-delay-ps\" and " 3509 "\"tx-internal-delay-ps\"", 3510 port_num); 3511 3512 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 3513 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 3514 rx_delay = 2000; 3515 3516 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 3517 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 3518 tx_delay = 2000; 3519 } 3520 3521 if (rx_delay < 0) 3522 rx_delay = 0; 3523 if (tx_delay < 0) 3524 tx_delay = 0; 3525 3526 dev->ports[port_num].rgmii_rx_val = rx_delay; 3527 dev->ports[port_num].rgmii_tx_val = tx_delay; 3528 } 3529 3530 int ksz_switch_register(struct ksz_device *dev) 3531 { 3532 const struct ksz_chip_data *info; 3533 struct device_node *port, *ports; 3534 phy_interface_t interface; 3535 unsigned int port_num; 3536 int ret; 3537 int i; 3538 3539 if (dev->pdata) 3540 dev->chip_id = dev->pdata->chip_id; 3541 3542 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 3543 GPIOD_OUT_LOW); 3544 if (IS_ERR(dev->reset_gpio)) 3545 return PTR_ERR(dev->reset_gpio); 3546 3547 if (dev->reset_gpio) { 3548 gpiod_set_value_cansleep(dev->reset_gpio, 1); 3549 usleep_range(10000, 12000); 3550 gpiod_set_value_cansleep(dev->reset_gpio, 0); 3551 msleep(100); 3552 } 3553 3554 mutex_init(&dev->dev_mutex); 3555 mutex_init(&dev->regmap_mutex); 3556 mutex_init(&dev->alu_mutex); 3557 mutex_init(&dev->vlan_mutex); 3558 3559 ret = ksz_switch_detect(dev); 3560 if (ret) 3561 return ret; 3562 3563 info = ksz_lookup_info(dev->chip_id); 3564 if (!info) 3565 return -ENODEV; 3566 3567 /* Update the compatible info with the probed one */ 3568 dev->info = info; 3569 3570 dev_info(dev->dev, "found switch: %s, rev %i\n", 3571 dev->info->dev_name, dev->chip_rev); 3572 3573 ret = ksz_check_device_id(dev); 3574 if (ret) 3575 return ret; 3576 3577 dev->dev_ops = dev->info->ops; 3578 3579 ret = dev->dev_ops->init(dev); 3580 if (ret) 3581 return ret; 3582 3583 dev->ports = devm_kzalloc(dev->dev, 3584 dev->info->port_cnt * sizeof(struct ksz_port), 3585 GFP_KERNEL); 3586 if (!dev->ports) 3587 return -ENOMEM; 3588 3589 for (i = 0; i < dev->info->port_cnt; i++) { 3590 spin_lock_init(&dev->ports[i].mib.stats64_lock); 3591 mutex_init(&dev->ports[i].mib.cnt_mutex); 3592 dev->ports[i].mib.counters = 3593 devm_kzalloc(dev->dev, 3594 sizeof(u64) * (dev->info->mib_cnt + 1), 3595 GFP_KERNEL); 3596 if (!dev->ports[i].mib.counters) 3597 return -ENOMEM; 3598 3599 dev->ports[i].ksz_dev = dev; 3600 dev->ports[i].num = i; 3601 } 3602 3603 /* set the real number of ports */ 3604 dev->ds->num_ports = dev->info->port_cnt; 3605 3606 /* Host port interface will be self detected, or specifically set in 3607 * device tree. 3608 */ 3609 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 3610 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 3611 if (dev->dev->of_node) { 3612 ret = of_get_phy_mode(dev->dev->of_node, &interface); 3613 if (ret == 0) 3614 dev->compat_interface = interface; 3615 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 3616 if (!ports) 3617 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 3618 if (ports) { 3619 for_each_available_child_of_node(ports, port) { 3620 if (of_property_read_u32(port, "reg", 3621 &port_num)) 3622 continue; 3623 if (!(dev->port_mask & BIT(port_num))) { 3624 of_node_put(port); 3625 of_node_put(ports); 3626 return -EINVAL; 3627 } 3628 of_get_phy_mode(port, 3629 &dev->ports[port_num].interface); 3630 3631 ksz_parse_rgmii_delay(dev, port_num, port); 3632 } 3633 of_node_put(ports); 3634 } 3635 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 3636 "microchip,synclko-125"); 3637 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 3638 "microchip,synclko-disable"); 3639 if (dev->synclko_125 && dev->synclko_disable) { 3640 dev_err(dev->dev, "inconsistent synclko settings\n"); 3641 return -EINVAL; 3642 } 3643 } 3644 3645 ret = dsa_register_switch(dev->ds); 3646 if (ret) { 3647 dev->dev_ops->exit(dev); 3648 return ret; 3649 } 3650 3651 /* Read MIB counters every 30 seconds to avoid overflow. */ 3652 dev->mib_read_interval = msecs_to_jiffies(5000); 3653 3654 /* Start the MIB timer. */ 3655 schedule_delayed_work(&dev->mib_read, 0); 3656 3657 return ret; 3658 } 3659 EXPORT_SYMBOL(ksz_switch_register); 3660 3661 void ksz_switch_remove(struct ksz_device *dev) 3662 { 3663 /* timer started */ 3664 if (dev->mib_read_interval) { 3665 dev->mib_read_interval = 0; 3666 cancel_delayed_work_sync(&dev->mib_read); 3667 } 3668 3669 dev->dev_ops->exit(dev); 3670 dsa_unregister_switch(dev->ds); 3671 3672 if (dev->reset_gpio) 3673 gpiod_set_value_cansleep(dev->reset_gpio, 1); 3674 3675 } 3676 EXPORT_SYMBOL(ksz_switch_remove); 3677 3678 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 3679 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 3680 MODULE_LICENSE("GPL"); 3681