1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/export.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/platform_data/microchip-ksz.h> 14 #include <linux/phy.h> 15 #include <linux/etherdevice.h> 16 #include <linux/if_bridge.h> 17 #include <linux/irq.h> 18 #include <linux/irqdomain.h> 19 #include <linux/of_mdio.h> 20 #include <linux/of_device.h> 21 #include <linux/of_net.h> 22 #include <linux/micrel_phy.h> 23 #include <net/dsa.h> 24 #include <net/switchdev.h> 25 26 #include "ksz_common.h" 27 #include "ksz8.h" 28 #include "ksz9477.h" 29 #include "lan937x.h" 30 31 #define MIB_COUNTER_NUM 0x20 32 33 struct ksz_stats_raw { 34 u64 rx_hi; 35 u64 rx_undersize; 36 u64 rx_fragments; 37 u64 rx_oversize; 38 u64 rx_jabbers; 39 u64 rx_symbol_err; 40 u64 rx_crc_err; 41 u64 rx_align_err; 42 u64 rx_mac_ctrl; 43 u64 rx_pause; 44 u64 rx_bcast; 45 u64 rx_mcast; 46 u64 rx_ucast; 47 u64 rx_64_or_less; 48 u64 rx_65_127; 49 u64 rx_128_255; 50 u64 rx_256_511; 51 u64 rx_512_1023; 52 u64 rx_1024_1522; 53 u64 rx_1523_2000; 54 u64 rx_2001; 55 u64 tx_hi; 56 u64 tx_late_col; 57 u64 tx_pause; 58 u64 tx_bcast; 59 u64 tx_mcast; 60 u64 tx_ucast; 61 u64 tx_deferred; 62 u64 tx_total_col; 63 u64 tx_exc_col; 64 u64 tx_single_col; 65 u64 tx_mult_col; 66 u64 rx_total; 67 u64 tx_total; 68 u64 rx_discards; 69 u64 tx_discards; 70 }; 71 72 static const struct ksz_mib_names ksz88xx_mib_names[] = { 73 { 0x00, "rx" }, 74 { 0x01, "rx_hi" }, 75 { 0x02, "rx_undersize" }, 76 { 0x03, "rx_fragments" }, 77 { 0x04, "rx_oversize" }, 78 { 0x05, "rx_jabbers" }, 79 { 0x06, "rx_symbol_err" }, 80 { 0x07, "rx_crc_err" }, 81 { 0x08, "rx_align_err" }, 82 { 0x09, "rx_mac_ctrl" }, 83 { 0x0a, "rx_pause" }, 84 { 0x0b, "rx_bcast" }, 85 { 0x0c, "rx_mcast" }, 86 { 0x0d, "rx_ucast" }, 87 { 0x0e, "rx_64_or_less" }, 88 { 0x0f, "rx_65_127" }, 89 { 0x10, "rx_128_255" }, 90 { 0x11, "rx_256_511" }, 91 { 0x12, "rx_512_1023" }, 92 { 0x13, "rx_1024_1522" }, 93 { 0x14, "tx" }, 94 { 0x15, "tx_hi" }, 95 { 0x16, "tx_late_col" }, 96 { 0x17, "tx_pause" }, 97 { 0x18, "tx_bcast" }, 98 { 0x19, "tx_mcast" }, 99 { 0x1a, "tx_ucast" }, 100 { 0x1b, "tx_deferred" }, 101 { 0x1c, "tx_total_col" }, 102 { 0x1d, "tx_exc_col" }, 103 { 0x1e, "tx_single_col" }, 104 { 0x1f, "tx_mult_col" }, 105 { 0x100, "rx_discards" }, 106 { 0x101, "tx_discards" }, 107 }; 108 109 static const struct ksz_mib_names ksz9477_mib_names[] = { 110 { 0x00, "rx_hi" }, 111 { 0x01, "rx_undersize" }, 112 { 0x02, "rx_fragments" }, 113 { 0x03, "rx_oversize" }, 114 { 0x04, "rx_jabbers" }, 115 { 0x05, "rx_symbol_err" }, 116 { 0x06, "rx_crc_err" }, 117 { 0x07, "rx_align_err" }, 118 { 0x08, "rx_mac_ctrl" }, 119 { 0x09, "rx_pause" }, 120 { 0x0A, "rx_bcast" }, 121 { 0x0B, "rx_mcast" }, 122 { 0x0C, "rx_ucast" }, 123 { 0x0D, "rx_64_or_less" }, 124 { 0x0E, "rx_65_127" }, 125 { 0x0F, "rx_128_255" }, 126 { 0x10, "rx_256_511" }, 127 { 0x11, "rx_512_1023" }, 128 { 0x12, "rx_1024_1522" }, 129 { 0x13, "rx_1523_2000" }, 130 { 0x14, "rx_2001" }, 131 { 0x15, "tx_hi" }, 132 { 0x16, "tx_late_col" }, 133 { 0x17, "tx_pause" }, 134 { 0x18, "tx_bcast" }, 135 { 0x19, "tx_mcast" }, 136 { 0x1A, "tx_ucast" }, 137 { 0x1B, "tx_deferred" }, 138 { 0x1C, "tx_total_col" }, 139 { 0x1D, "tx_exc_col" }, 140 { 0x1E, "tx_single_col" }, 141 { 0x1F, "tx_mult_col" }, 142 { 0x80, "rx_total" }, 143 { 0x81, "tx_total" }, 144 { 0x82, "rx_discards" }, 145 { 0x83, "tx_discards" }, 146 }; 147 148 static const struct ksz_dev_ops ksz8_dev_ops = { 149 .setup = ksz8_setup, 150 .get_port_addr = ksz8_get_port_addr, 151 .cfg_port_member = ksz8_cfg_port_member, 152 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 153 .port_setup = ksz8_port_setup, 154 .r_phy = ksz8_r_phy, 155 .w_phy = ksz8_w_phy, 156 .r_mib_cnt = ksz8_r_mib_cnt, 157 .r_mib_pkt = ksz8_r_mib_pkt, 158 .freeze_mib = ksz8_freeze_mib, 159 .port_init_cnt = ksz8_port_init_cnt, 160 .fdb_dump = ksz8_fdb_dump, 161 .mdb_add = ksz8_mdb_add, 162 .mdb_del = ksz8_mdb_del, 163 .vlan_filtering = ksz8_port_vlan_filtering, 164 .vlan_add = ksz8_port_vlan_add, 165 .vlan_del = ksz8_port_vlan_del, 166 .mirror_add = ksz8_port_mirror_add, 167 .mirror_del = ksz8_port_mirror_del, 168 .get_caps = ksz8_get_caps, 169 .config_cpu_port = ksz8_config_cpu_port, 170 .enable_stp_addr = ksz8_enable_stp_addr, 171 .reset = ksz8_reset_switch, 172 .init = ksz8_switch_init, 173 .exit = ksz8_switch_exit, 174 }; 175 176 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, 177 unsigned int mode, 178 phy_interface_t interface, 179 struct phy_device *phydev, int speed, 180 int duplex, bool tx_pause, 181 bool rx_pause); 182 183 static const struct ksz_dev_ops ksz9477_dev_ops = { 184 .setup = ksz9477_setup, 185 .get_port_addr = ksz9477_get_port_addr, 186 .cfg_port_member = ksz9477_cfg_port_member, 187 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 188 .port_setup = ksz9477_port_setup, 189 .set_ageing_time = ksz9477_set_ageing_time, 190 .r_phy = ksz9477_r_phy, 191 .w_phy = ksz9477_w_phy, 192 .r_mib_cnt = ksz9477_r_mib_cnt, 193 .r_mib_pkt = ksz9477_r_mib_pkt, 194 .r_mib_stat64 = ksz_r_mib_stats64, 195 .freeze_mib = ksz9477_freeze_mib, 196 .port_init_cnt = ksz9477_port_init_cnt, 197 .vlan_filtering = ksz9477_port_vlan_filtering, 198 .vlan_add = ksz9477_port_vlan_add, 199 .vlan_del = ksz9477_port_vlan_del, 200 .mirror_add = ksz9477_port_mirror_add, 201 .mirror_del = ksz9477_port_mirror_del, 202 .get_caps = ksz9477_get_caps, 203 .fdb_dump = ksz9477_fdb_dump, 204 .fdb_add = ksz9477_fdb_add, 205 .fdb_del = ksz9477_fdb_del, 206 .mdb_add = ksz9477_mdb_add, 207 .mdb_del = ksz9477_mdb_del, 208 .change_mtu = ksz9477_change_mtu, 209 .max_mtu = ksz9477_max_mtu, 210 .phylink_mac_link_up = ksz9477_phylink_mac_link_up, 211 .config_cpu_port = ksz9477_config_cpu_port, 212 .enable_stp_addr = ksz9477_enable_stp_addr, 213 .reset = ksz9477_reset_switch, 214 .init = ksz9477_switch_init, 215 .exit = ksz9477_switch_exit, 216 }; 217 218 static const struct ksz_dev_ops lan937x_dev_ops = { 219 .setup = lan937x_setup, 220 .teardown = lan937x_teardown, 221 .get_port_addr = ksz9477_get_port_addr, 222 .cfg_port_member = ksz9477_cfg_port_member, 223 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 224 .port_setup = lan937x_port_setup, 225 .set_ageing_time = lan937x_set_ageing_time, 226 .r_phy = lan937x_r_phy, 227 .w_phy = lan937x_w_phy, 228 .r_mib_cnt = ksz9477_r_mib_cnt, 229 .r_mib_pkt = ksz9477_r_mib_pkt, 230 .r_mib_stat64 = ksz_r_mib_stats64, 231 .freeze_mib = ksz9477_freeze_mib, 232 .port_init_cnt = ksz9477_port_init_cnt, 233 .vlan_filtering = ksz9477_port_vlan_filtering, 234 .vlan_add = ksz9477_port_vlan_add, 235 .vlan_del = ksz9477_port_vlan_del, 236 .mirror_add = ksz9477_port_mirror_add, 237 .mirror_del = ksz9477_port_mirror_del, 238 .get_caps = lan937x_phylink_get_caps, 239 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 240 .fdb_dump = ksz9477_fdb_dump, 241 .fdb_add = ksz9477_fdb_add, 242 .fdb_del = ksz9477_fdb_del, 243 .mdb_add = ksz9477_mdb_add, 244 .mdb_del = ksz9477_mdb_del, 245 .change_mtu = lan937x_change_mtu, 246 .max_mtu = ksz9477_max_mtu, 247 .phylink_mac_link_up = ksz9477_phylink_mac_link_up, 248 .config_cpu_port = lan937x_config_cpu_port, 249 .enable_stp_addr = ksz9477_enable_stp_addr, 250 .reset = lan937x_reset_switch, 251 .init = lan937x_switch_init, 252 .exit = lan937x_switch_exit, 253 }; 254 255 static const u16 ksz8795_regs[] = { 256 [REG_IND_CTRL_0] = 0x6E, 257 [REG_IND_DATA_8] = 0x70, 258 [REG_IND_DATA_CHECK] = 0x72, 259 [REG_IND_DATA_HI] = 0x71, 260 [REG_IND_DATA_LO] = 0x75, 261 [REG_IND_MIB_CHECK] = 0x74, 262 [REG_IND_BYTE] = 0xA0, 263 [P_FORCE_CTRL] = 0x0C, 264 [P_LINK_STATUS] = 0x0E, 265 [P_LOCAL_CTRL] = 0x07, 266 [P_NEG_RESTART_CTRL] = 0x0D, 267 [P_REMOTE_STATUS] = 0x08, 268 [P_SPEED_STATUS] = 0x09, 269 [S_TAIL_TAG_CTRL] = 0x0C, 270 [P_STP_CTRL] = 0x02, 271 [S_START_CTRL] = 0x01, 272 [S_BROADCAST_CTRL] = 0x06, 273 [S_MULTICAST_CTRL] = 0x04, 274 [P_XMII_CTRL_0] = 0x06, 275 [P_XMII_CTRL_1] = 0x56, 276 }; 277 278 static const u32 ksz8795_masks[] = { 279 [PORT_802_1P_REMAPPING] = BIT(7), 280 [SW_TAIL_TAG_ENABLE] = BIT(1), 281 [MIB_COUNTER_OVERFLOW] = BIT(6), 282 [MIB_COUNTER_VALID] = BIT(5), 283 [VLAN_TABLE_FID] = GENMASK(6, 0), 284 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 285 [VLAN_TABLE_VALID] = BIT(12), 286 [STATIC_MAC_TABLE_VALID] = BIT(21), 287 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 288 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 289 [STATIC_MAC_TABLE_OVERRIDE] = BIT(26), 290 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(24, 20), 291 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 292 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(8), 293 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 294 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 295 [DYNAMIC_MAC_TABLE_FID] = GENMASK(26, 20), 296 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 297 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 298 [P_MII_TX_FLOW_CTRL] = BIT(5), 299 [P_MII_RX_FLOW_CTRL] = BIT(5), 300 }; 301 302 static const u8 ksz8795_xmii_ctrl0[] = { 303 [P_MII_100MBIT] = 0, 304 [P_MII_10MBIT] = 1, 305 [P_MII_FULL_DUPLEX] = 0, 306 [P_MII_HALF_DUPLEX] = 1, 307 }; 308 309 static const u8 ksz8795_xmii_ctrl1[] = { 310 [P_RGMII_SEL] = 3, 311 [P_GMII_SEL] = 2, 312 [P_RMII_SEL] = 1, 313 [P_MII_SEL] = 0, 314 [P_GMII_1GBIT] = 1, 315 [P_GMII_NOT_1GBIT] = 0, 316 }; 317 318 static const u8 ksz8795_shifts[] = { 319 [VLAN_TABLE_MEMBERSHIP_S] = 7, 320 [VLAN_TABLE] = 16, 321 [STATIC_MAC_FWD_PORTS] = 16, 322 [STATIC_MAC_FID] = 24, 323 [DYNAMIC_MAC_ENTRIES_H] = 3, 324 [DYNAMIC_MAC_ENTRIES] = 29, 325 [DYNAMIC_MAC_FID] = 16, 326 [DYNAMIC_MAC_TIMESTAMP] = 27, 327 [DYNAMIC_MAC_SRC_PORT] = 24, 328 }; 329 330 static const u16 ksz8863_regs[] = { 331 [REG_IND_CTRL_0] = 0x79, 332 [REG_IND_DATA_8] = 0x7B, 333 [REG_IND_DATA_CHECK] = 0x7B, 334 [REG_IND_DATA_HI] = 0x7C, 335 [REG_IND_DATA_LO] = 0x80, 336 [REG_IND_MIB_CHECK] = 0x80, 337 [P_FORCE_CTRL] = 0x0C, 338 [P_LINK_STATUS] = 0x0E, 339 [P_LOCAL_CTRL] = 0x0C, 340 [P_NEG_RESTART_CTRL] = 0x0D, 341 [P_REMOTE_STATUS] = 0x0E, 342 [P_SPEED_STATUS] = 0x0F, 343 [S_TAIL_TAG_CTRL] = 0x03, 344 [P_STP_CTRL] = 0x02, 345 [S_START_CTRL] = 0x01, 346 [S_BROADCAST_CTRL] = 0x06, 347 [S_MULTICAST_CTRL] = 0x04, 348 }; 349 350 static const u32 ksz8863_masks[] = { 351 [PORT_802_1P_REMAPPING] = BIT(3), 352 [SW_TAIL_TAG_ENABLE] = BIT(6), 353 [MIB_COUNTER_OVERFLOW] = BIT(7), 354 [MIB_COUNTER_VALID] = BIT(6), 355 [VLAN_TABLE_FID] = GENMASK(15, 12), 356 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 357 [VLAN_TABLE_VALID] = BIT(19), 358 [STATIC_MAC_TABLE_VALID] = BIT(19), 359 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 360 [STATIC_MAC_TABLE_FID] = GENMASK(29, 26), 361 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 362 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 363 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(5, 0), 364 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 365 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 366 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 28), 367 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 368 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 369 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 370 }; 371 372 static u8 ksz8863_shifts[] = { 373 [VLAN_TABLE_MEMBERSHIP_S] = 16, 374 [STATIC_MAC_FWD_PORTS] = 16, 375 [STATIC_MAC_FID] = 22, 376 [DYNAMIC_MAC_ENTRIES_H] = 3, 377 [DYNAMIC_MAC_ENTRIES] = 24, 378 [DYNAMIC_MAC_FID] = 16, 379 [DYNAMIC_MAC_TIMESTAMP] = 24, 380 [DYNAMIC_MAC_SRC_PORT] = 20, 381 }; 382 383 static const u16 ksz9477_regs[] = { 384 [P_STP_CTRL] = 0x0B04, 385 [S_START_CTRL] = 0x0300, 386 [S_BROADCAST_CTRL] = 0x0332, 387 [S_MULTICAST_CTRL] = 0x0331, 388 [P_XMII_CTRL_0] = 0x0300, 389 [P_XMII_CTRL_1] = 0x0301, 390 }; 391 392 static const u32 ksz9477_masks[] = { 393 [ALU_STAT_WRITE] = 0, 394 [ALU_STAT_READ] = 1, 395 [P_MII_TX_FLOW_CTRL] = BIT(5), 396 [P_MII_RX_FLOW_CTRL] = BIT(3), 397 }; 398 399 static const u8 ksz9477_shifts[] = { 400 [ALU_STAT_INDEX] = 16, 401 }; 402 403 static const u8 ksz9477_xmii_ctrl0[] = { 404 [P_MII_100MBIT] = 1, 405 [P_MII_10MBIT] = 0, 406 [P_MII_FULL_DUPLEX] = 1, 407 [P_MII_HALF_DUPLEX] = 0, 408 }; 409 410 static const u8 ksz9477_xmii_ctrl1[] = { 411 [P_RGMII_SEL] = 0, 412 [P_RMII_SEL] = 1, 413 [P_GMII_SEL] = 2, 414 [P_MII_SEL] = 3, 415 [P_GMII_1GBIT] = 0, 416 [P_GMII_NOT_1GBIT] = 1, 417 }; 418 419 static const u32 lan937x_masks[] = { 420 [ALU_STAT_WRITE] = 1, 421 [ALU_STAT_READ] = 2, 422 [P_MII_TX_FLOW_CTRL] = BIT(5), 423 [P_MII_RX_FLOW_CTRL] = BIT(3), 424 }; 425 426 static const u8 lan937x_shifts[] = { 427 [ALU_STAT_INDEX] = 8, 428 }; 429 430 static const struct regmap_range ksz8563_valid_regs[] = { 431 regmap_reg_range(0x0000, 0x0003), 432 regmap_reg_range(0x0006, 0x0006), 433 regmap_reg_range(0x000f, 0x001f), 434 regmap_reg_range(0x0100, 0x0100), 435 regmap_reg_range(0x0104, 0x0107), 436 regmap_reg_range(0x010d, 0x010d), 437 regmap_reg_range(0x0110, 0x0113), 438 regmap_reg_range(0x0120, 0x012b), 439 regmap_reg_range(0x0201, 0x0201), 440 regmap_reg_range(0x0210, 0x0213), 441 regmap_reg_range(0x0300, 0x0300), 442 regmap_reg_range(0x0302, 0x031b), 443 regmap_reg_range(0x0320, 0x032b), 444 regmap_reg_range(0x0330, 0x0336), 445 regmap_reg_range(0x0338, 0x033e), 446 regmap_reg_range(0x0340, 0x035f), 447 regmap_reg_range(0x0370, 0x0370), 448 regmap_reg_range(0x0378, 0x0378), 449 regmap_reg_range(0x037c, 0x037d), 450 regmap_reg_range(0x0390, 0x0393), 451 regmap_reg_range(0x0400, 0x040e), 452 regmap_reg_range(0x0410, 0x042f), 453 regmap_reg_range(0x0500, 0x0519), 454 regmap_reg_range(0x0520, 0x054b), 455 regmap_reg_range(0x0550, 0x05b3), 456 457 /* port 1 */ 458 regmap_reg_range(0x1000, 0x1001), 459 regmap_reg_range(0x1004, 0x100b), 460 regmap_reg_range(0x1013, 0x1013), 461 regmap_reg_range(0x1017, 0x1017), 462 regmap_reg_range(0x101b, 0x101b), 463 regmap_reg_range(0x101f, 0x1021), 464 regmap_reg_range(0x1030, 0x1030), 465 regmap_reg_range(0x1100, 0x1111), 466 regmap_reg_range(0x111a, 0x111d), 467 regmap_reg_range(0x1122, 0x1127), 468 regmap_reg_range(0x112a, 0x112b), 469 regmap_reg_range(0x1136, 0x1139), 470 regmap_reg_range(0x113e, 0x113f), 471 regmap_reg_range(0x1400, 0x1401), 472 regmap_reg_range(0x1403, 0x1403), 473 regmap_reg_range(0x1410, 0x1417), 474 regmap_reg_range(0x1420, 0x1423), 475 regmap_reg_range(0x1500, 0x1507), 476 regmap_reg_range(0x1600, 0x1612), 477 regmap_reg_range(0x1800, 0x180f), 478 regmap_reg_range(0x1900, 0x1907), 479 regmap_reg_range(0x1914, 0x191b), 480 regmap_reg_range(0x1a00, 0x1a03), 481 regmap_reg_range(0x1a04, 0x1a08), 482 regmap_reg_range(0x1b00, 0x1b01), 483 regmap_reg_range(0x1b04, 0x1b04), 484 regmap_reg_range(0x1c00, 0x1c05), 485 regmap_reg_range(0x1c08, 0x1c1b), 486 487 /* port 2 */ 488 regmap_reg_range(0x2000, 0x2001), 489 regmap_reg_range(0x2004, 0x200b), 490 regmap_reg_range(0x2013, 0x2013), 491 regmap_reg_range(0x2017, 0x2017), 492 regmap_reg_range(0x201b, 0x201b), 493 regmap_reg_range(0x201f, 0x2021), 494 regmap_reg_range(0x2030, 0x2030), 495 regmap_reg_range(0x2100, 0x2111), 496 regmap_reg_range(0x211a, 0x211d), 497 regmap_reg_range(0x2122, 0x2127), 498 regmap_reg_range(0x212a, 0x212b), 499 regmap_reg_range(0x2136, 0x2139), 500 regmap_reg_range(0x213e, 0x213f), 501 regmap_reg_range(0x2400, 0x2401), 502 regmap_reg_range(0x2403, 0x2403), 503 regmap_reg_range(0x2410, 0x2417), 504 regmap_reg_range(0x2420, 0x2423), 505 regmap_reg_range(0x2500, 0x2507), 506 regmap_reg_range(0x2600, 0x2612), 507 regmap_reg_range(0x2800, 0x280f), 508 regmap_reg_range(0x2900, 0x2907), 509 regmap_reg_range(0x2914, 0x291b), 510 regmap_reg_range(0x2a00, 0x2a03), 511 regmap_reg_range(0x2a04, 0x2a08), 512 regmap_reg_range(0x2b00, 0x2b01), 513 regmap_reg_range(0x2b04, 0x2b04), 514 regmap_reg_range(0x2c00, 0x2c05), 515 regmap_reg_range(0x2c08, 0x2c1b), 516 517 /* port 3 */ 518 regmap_reg_range(0x3000, 0x3001), 519 regmap_reg_range(0x3004, 0x300b), 520 regmap_reg_range(0x3013, 0x3013), 521 regmap_reg_range(0x3017, 0x3017), 522 regmap_reg_range(0x301b, 0x301b), 523 regmap_reg_range(0x301f, 0x3021), 524 regmap_reg_range(0x3030, 0x3030), 525 regmap_reg_range(0x3300, 0x3301), 526 regmap_reg_range(0x3303, 0x3303), 527 regmap_reg_range(0x3400, 0x3401), 528 regmap_reg_range(0x3403, 0x3403), 529 regmap_reg_range(0x3410, 0x3417), 530 regmap_reg_range(0x3420, 0x3423), 531 regmap_reg_range(0x3500, 0x3507), 532 regmap_reg_range(0x3600, 0x3612), 533 regmap_reg_range(0x3800, 0x380f), 534 regmap_reg_range(0x3900, 0x3907), 535 regmap_reg_range(0x3914, 0x391b), 536 regmap_reg_range(0x3a00, 0x3a03), 537 regmap_reg_range(0x3a04, 0x3a08), 538 regmap_reg_range(0x3b00, 0x3b01), 539 regmap_reg_range(0x3b04, 0x3b04), 540 regmap_reg_range(0x3c00, 0x3c05), 541 regmap_reg_range(0x3c08, 0x3c1b), 542 }; 543 544 static const struct regmap_access_table ksz8563_register_set = { 545 .yes_ranges = ksz8563_valid_regs, 546 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), 547 }; 548 549 static const struct regmap_range ksz9477_valid_regs[] = { 550 regmap_reg_range(0x0000, 0x0003), 551 regmap_reg_range(0x0006, 0x0006), 552 regmap_reg_range(0x0010, 0x001f), 553 regmap_reg_range(0x0100, 0x0100), 554 regmap_reg_range(0x0103, 0x0107), 555 regmap_reg_range(0x010d, 0x010d), 556 regmap_reg_range(0x0110, 0x0113), 557 regmap_reg_range(0x0120, 0x012b), 558 regmap_reg_range(0x0201, 0x0201), 559 regmap_reg_range(0x0210, 0x0213), 560 regmap_reg_range(0x0300, 0x0300), 561 regmap_reg_range(0x0302, 0x031b), 562 regmap_reg_range(0x0320, 0x032b), 563 regmap_reg_range(0x0330, 0x0336), 564 regmap_reg_range(0x0338, 0x033b), 565 regmap_reg_range(0x033e, 0x033e), 566 regmap_reg_range(0x0340, 0x035f), 567 regmap_reg_range(0x0370, 0x0370), 568 regmap_reg_range(0x0378, 0x0378), 569 regmap_reg_range(0x037c, 0x037d), 570 regmap_reg_range(0x0390, 0x0393), 571 regmap_reg_range(0x0400, 0x040e), 572 regmap_reg_range(0x0410, 0x042f), 573 regmap_reg_range(0x0444, 0x044b), 574 regmap_reg_range(0x0450, 0x046f), 575 regmap_reg_range(0x0500, 0x0519), 576 regmap_reg_range(0x0520, 0x054b), 577 regmap_reg_range(0x0550, 0x05b3), 578 regmap_reg_range(0x0604, 0x060b), 579 regmap_reg_range(0x0610, 0x0612), 580 regmap_reg_range(0x0614, 0x062c), 581 regmap_reg_range(0x0640, 0x0645), 582 regmap_reg_range(0x0648, 0x064d), 583 584 /* port 1 */ 585 regmap_reg_range(0x1000, 0x1001), 586 regmap_reg_range(0x1013, 0x1013), 587 regmap_reg_range(0x1017, 0x1017), 588 regmap_reg_range(0x101b, 0x101b), 589 regmap_reg_range(0x101f, 0x1020), 590 regmap_reg_range(0x1030, 0x1030), 591 regmap_reg_range(0x1100, 0x1115), 592 regmap_reg_range(0x111a, 0x111f), 593 regmap_reg_range(0x1122, 0x1127), 594 regmap_reg_range(0x112a, 0x112b), 595 regmap_reg_range(0x1136, 0x1139), 596 regmap_reg_range(0x113e, 0x113f), 597 regmap_reg_range(0x1400, 0x1401), 598 regmap_reg_range(0x1403, 0x1403), 599 regmap_reg_range(0x1410, 0x1417), 600 regmap_reg_range(0x1420, 0x1423), 601 regmap_reg_range(0x1500, 0x1507), 602 regmap_reg_range(0x1600, 0x1613), 603 regmap_reg_range(0x1800, 0x180f), 604 regmap_reg_range(0x1820, 0x1827), 605 regmap_reg_range(0x1830, 0x1837), 606 regmap_reg_range(0x1840, 0x184b), 607 regmap_reg_range(0x1900, 0x1907), 608 regmap_reg_range(0x1914, 0x191b), 609 regmap_reg_range(0x1920, 0x1920), 610 regmap_reg_range(0x1923, 0x1927), 611 regmap_reg_range(0x1a00, 0x1a03), 612 regmap_reg_range(0x1a04, 0x1a07), 613 regmap_reg_range(0x1b00, 0x1b01), 614 regmap_reg_range(0x1b04, 0x1b04), 615 regmap_reg_range(0x1c00, 0x1c05), 616 regmap_reg_range(0x1c08, 0x1c1b), 617 618 /* port 2 */ 619 regmap_reg_range(0x2000, 0x2001), 620 regmap_reg_range(0x2013, 0x2013), 621 regmap_reg_range(0x2017, 0x2017), 622 regmap_reg_range(0x201b, 0x201b), 623 regmap_reg_range(0x201f, 0x2020), 624 regmap_reg_range(0x2030, 0x2030), 625 regmap_reg_range(0x2100, 0x2115), 626 regmap_reg_range(0x211a, 0x211f), 627 regmap_reg_range(0x2122, 0x2127), 628 regmap_reg_range(0x212a, 0x212b), 629 regmap_reg_range(0x2136, 0x2139), 630 regmap_reg_range(0x213e, 0x213f), 631 regmap_reg_range(0x2400, 0x2401), 632 regmap_reg_range(0x2403, 0x2403), 633 regmap_reg_range(0x2410, 0x2417), 634 regmap_reg_range(0x2420, 0x2423), 635 regmap_reg_range(0x2500, 0x2507), 636 regmap_reg_range(0x2600, 0x2613), 637 regmap_reg_range(0x2800, 0x280f), 638 regmap_reg_range(0x2820, 0x2827), 639 regmap_reg_range(0x2830, 0x2837), 640 regmap_reg_range(0x2840, 0x284b), 641 regmap_reg_range(0x2900, 0x2907), 642 regmap_reg_range(0x2914, 0x291b), 643 regmap_reg_range(0x2920, 0x2920), 644 regmap_reg_range(0x2923, 0x2927), 645 regmap_reg_range(0x2a00, 0x2a03), 646 regmap_reg_range(0x2a04, 0x2a07), 647 regmap_reg_range(0x2b00, 0x2b01), 648 regmap_reg_range(0x2b04, 0x2b04), 649 regmap_reg_range(0x2c00, 0x2c05), 650 regmap_reg_range(0x2c08, 0x2c1b), 651 652 /* port 3 */ 653 regmap_reg_range(0x3000, 0x3001), 654 regmap_reg_range(0x3013, 0x3013), 655 regmap_reg_range(0x3017, 0x3017), 656 regmap_reg_range(0x301b, 0x301b), 657 regmap_reg_range(0x301f, 0x3020), 658 regmap_reg_range(0x3030, 0x3030), 659 regmap_reg_range(0x3100, 0x3115), 660 regmap_reg_range(0x311a, 0x311f), 661 regmap_reg_range(0x3122, 0x3127), 662 regmap_reg_range(0x312a, 0x312b), 663 regmap_reg_range(0x3136, 0x3139), 664 regmap_reg_range(0x313e, 0x313f), 665 regmap_reg_range(0x3400, 0x3401), 666 regmap_reg_range(0x3403, 0x3403), 667 regmap_reg_range(0x3410, 0x3417), 668 regmap_reg_range(0x3420, 0x3423), 669 regmap_reg_range(0x3500, 0x3507), 670 regmap_reg_range(0x3600, 0x3613), 671 regmap_reg_range(0x3800, 0x380f), 672 regmap_reg_range(0x3820, 0x3827), 673 regmap_reg_range(0x3830, 0x3837), 674 regmap_reg_range(0x3840, 0x384b), 675 regmap_reg_range(0x3900, 0x3907), 676 regmap_reg_range(0x3914, 0x391b), 677 regmap_reg_range(0x3920, 0x3920), 678 regmap_reg_range(0x3923, 0x3927), 679 regmap_reg_range(0x3a00, 0x3a03), 680 regmap_reg_range(0x3a04, 0x3a07), 681 regmap_reg_range(0x3b00, 0x3b01), 682 regmap_reg_range(0x3b04, 0x3b04), 683 regmap_reg_range(0x3c00, 0x3c05), 684 regmap_reg_range(0x3c08, 0x3c1b), 685 686 /* port 4 */ 687 regmap_reg_range(0x4000, 0x4001), 688 regmap_reg_range(0x4013, 0x4013), 689 regmap_reg_range(0x4017, 0x4017), 690 regmap_reg_range(0x401b, 0x401b), 691 regmap_reg_range(0x401f, 0x4020), 692 regmap_reg_range(0x4030, 0x4030), 693 regmap_reg_range(0x4100, 0x4115), 694 regmap_reg_range(0x411a, 0x411f), 695 regmap_reg_range(0x4122, 0x4127), 696 regmap_reg_range(0x412a, 0x412b), 697 regmap_reg_range(0x4136, 0x4139), 698 regmap_reg_range(0x413e, 0x413f), 699 regmap_reg_range(0x4400, 0x4401), 700 regmap_reg_range(0x4403, 0x4403), 701 regmap_reg_range(0x4410, 0x4417), 702 regmap_reg_range(0x4420, 0x4423), 703 regmap_reg_range(0x4500, 0x4507), 704 regmap_reg_range(0x4600, 0x4613), 705 regmap_reg_range(0x4800, 0x480f), 706 regmap_reg_range(0x4820, 0x4827), 707 regmap_reg_range(0x4830, 0x4837), 708 regmap_reg_range(0x4840, 0x484b), 709 regmap_reg_range(0x4900, 0x4907), 710 regmap_reg_range(0x4914, 0x491b), 711 regmap_reg_range(0x4920, 0x4920), 712 regmap_reg_range(0x4923, 0x4927), 713 regmap_reg_range(0x4a00, 0x4a03), 714 regmap_reg_range(0x4a04, 0x4a07), 715 regmap_reg_range(0x4b00, 0x4b01), 716 regmap_reg_range(0x4b04, 0x4b04), 717 regmap_reg_range(0x4c00, 0x4c05), 718 regmap_reg_range(0x4c08, 0x4c1b), 719 720 /* port 5 */ 721 regmap_reg_range(0x5000, 0x5001), 722 regmap_reg_range(0x5013, 0x5013), 723 regmap_reg_range(0x5017, 0x5017), 724 regmap_reg_range(0x501b, 0x501b), 725 regmap_reg_range(0x501f, 0x5020), 726 regmap_reg_range(0x5030, 0x5030), 727 regmap_reg_range(0x5100, 0x5115), 728 regmap_reg_range(0x511a, 0x511f), 729 regmap_reg_range(0x5122, 0x5127), 730 regmap_reg_range(0x512a, 0x512b), 731 regmap_reg_range(0x5136, 0x5139), 732 regmap_reg_range(0x513e, 0x513f), 733 regmap_reg_range(0x5400, 0x5401), 734 regmap_reg_range(0x5403, 0x5403), 735 regmap_reg_range(0x5410, 0x5417), 736 regmap_reg_range(0x5420, 0x5423), 737 regmap_reg_range(0x5500, 0x5507), 738 regmap_reg_range(0x5600, 0x5613), 739 regmap_reg_range(0x5800, 0x580f), 740 regmap_reg_range(0x5820, 0x5827), 741 regmap_reg_range(0x5830, 0x5837), 742 regmap_reg_range(0x5840, 0x584b), 743 regmap_reg_range(0x5900, 0x5907), 744 regmap_reg_range(0x5914, 0x591b), 745 regmap_reg_range(0x5920, 0x5920), 746 regmap_reg_range(0x5923, 0x5927), 747 regmap_reg_range(0x5a00, 0x5a03), 748 regmap_reg_range(0x5a04, 0x5a07), 749 regmap_reg_range(0x5b00, 0x5b01), 750 regmap_reg_range(0x5b04, 0x5b04), 751 regmap_reg_range(0x5c00, 0x5c05), 752 regmap_reg_range(0x5c08, 0x5c1b), 753 754 /* port 6 */ 755 regmap_reg_range(0x6000, 0x6001), 756 regmap_reg_range(0x6013, 0x6013), 757 regmap_reg_range(0x6017, 0x6017), 758 regmap_reg_range(0x601b, 0x601b), 759 regmap_reg_range(0x601f, 0x6020), 760 regmap_reg_range(0x6030, 0x6030), 761 regmap_reg_range(0x6300, 0x6301), 762 regmap_reg_range(0x6400, 0x6401), 763 regmap_reg_range(0x6403, 0x6403), 764 regmap_reg_range(0x6410, 0x6417), 765 regmap_reg_range(0x6420, 0x6423), 766 regmap_reg_range(0x6500, 0x6507), 767 regmap_reg_range(0x6600, 0x6613), 768 regmap_reg_range(0x6800, 0x680f), 769 regmap_reg_range(0x6820, 0x6827), 770 regmap_reg_range(0x6830, 0x6837), 771 regmap_reg_range(0x6840, 0x684b), 772 regmap_reg_range(0x6900, 0x6907), 773 regmap_reg_range(0x6914, 0x691b), 774 regmap_reg_range(0x6920, 0x6920), 775 regmap_reg_range(0x6923, 0x6927), 776 regmap_reg_range(0x6a00, 0x6a03), 777 regmap_reg_range(0x6a04, 0x6a07), 778 regmap_reg_range(0x6b00, 0x6b01), 779 regmap_reg_range(0x6b04, 0x6b04), 780 regmap_reg_range(0x6c00, 0x6c05), 781 regmap_reg_range(0x6c08, 0x6c1b), 782 783 /* port 7 */ 784 regmap_reg_range(0x7000, 0x7001), 785 regmap_reg_range(0x7013, 0x7013), 786 regmap_reg_range(0x7017, 0x7017), 787 regmap_reg_range(0x701b, 0x701b), 788 regmap_reg_range(0x701f, 0x7020), 789 regmap_reg_range(0x7030, 0x7030), 790 regmap_reg_range(0x7200, 0x7203), 791 regmap_reg_range(0x7206, 0x7207), 792 regmap_reg_range(0x7300, 0x7301), 793 regmap_reg_range(0x7400, 0x7401), 794 regmap_reg_range(0x7403, 0x7403), 795 regmap_reg_range(0x7410, 0x7417), 796 regmap_reg_range(0x7420, 0x7423), 797 regmap_reg_range(0x7500, 0x7507), 798 regmap_reg_range(0x7600, 0x7613), 799 regmap_reg_range(0x7800, 0x780f), 800 regmap_reg_range(0x7820, 0x7827), 801 regmap_reg_range(0x7830, 0x7837), 802 regmap_reg_range(0x7840, 0x784b), 803 regmap_reg_range(0x7900, 0x7907), 804 regmap_reg_range(0x7914, 0x791b), 805 regmap_reg_range(0x7920, 0x7920), 806 regmap_reg_range(0x7923, 0x7927), 807 regmap_reg_range(0x7a00, 0x7a03), 808 regmap_reg_range(0x7a04, 0x7a07), 809 regmap_reg_range(0x7b00, 0x7b01), 810 regmap_reg_range(0x7b04, 0x7b04), 811 regmap_reg_range(0x7c00, 0x7c05), 812 regmap_reg_range(0x7c08, 0x7c1b), 813 }; 814 815 static const struct regmap_access_table ksz9477_register_set = { 816 .yes_ranges = ksz9477_valid_regs, 817 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), 818 }; 819 820 static const struct regmap_range ksz9896_valid_regs[] = { 821 regmap_reg_range(0x0000, 0x0003), 822 regmap_reg_range(0x0006, 0x0006), 823 regmap_reg_range(0x0010, 0x001f), 824 regmap_reg_range(0x0100, 0x0100), 825 regmap_reg_range(0x0103, 0x0107), 826 regmap_reg_range(0x010d, 0x010d), 827 regmap_reg_range(0x0110, 0x0113), 828 regmap_reg_range(0x0120, 0x0127), 829 regmap_reg_range(0x0201, 0x0201), 830 regmap_reg_range(0x0210, 0x0213), 831 regmap_reg_range(0x0300, 0x0300), 832 regmap_reg_range(0x0302, 0x030b), 833 regmap_reg_range(0x0310, 0x031b), 834 regmap_reg_range(0x0320, 0x032b), 835 regmap_reg_range(0x0330, 0x0336), 836 regmap_reg_range(0x0338, 0x033b), 837 regmap_reg_range(0x033e, 0x033e), 838 regmap_reg_range(0x0340, 0x035f), 839 regmap_reg_range(0x0370, 0x0370), 840 regmap_reg_range(0x0378, 0x0378), 841 regmap_reg_range(0x037c, 0x037d), 842 regmap_reg_range(0x0390, 0x0393), 843 regmap_reg_range(0x0400, 0x040e), 844 regmap_reg_range(0x0410, 0x042f), 845 846 /* port 1 */ 847 regmap_reg_range(0x1000, 0x1001), 848 regmap_reg_range(0x1013, 0x1013), 849 regmap_reg_range(0x1017, 0x1017), 850 regmap_reg_range(0x101b, 0x101b), 851 regmap_reg_range(0x101f, 0x1020), 852 regmap_reg_range(0x1030, 0x1030), 853 regmap_reg_range(0x1100, 0x1115), 854 regmap_reg_range(0x111a, 0x111f), 855 regmap_reg_range(0x1122, 0x1127), 856 regmap_reg_range(0x112a, 0x112b), 857 regmap_reg_range(0x1136, 0x1139), 858 regmap_reg_range(0x113e, 0x113f), 859 regmap_reg_range(0x1400, 0x1401), 860 regmap_reg_range(0x1403, 0x1403), 861 regmap_reg_range(0x1410, 0x1417), 862 regmap_reg_range(0x1420, 0x1423), 863 regmap_reg_range(0x1500, 0x1507), 864 regmap_reg_range(0x1600, 0x1612), 865 regmap_reg_range(0x1800, 0x180f), 866 regmap_reg_range(0x1820, 0x1827), 867 regmap_reg_range(0x1830, 0x1837), 868 regmap_reg_range(0x1840, 0x184b), 869 regmap_reg_range(0x1900, 0x1907), 870 regmap_reg_range(0x1914, 0x1915), 871 regmap_reg_range(0x1a00, 0x1a03), 872 regmap_reg_range(0x1a04, 0x1a07), 873 regmap_reg_range(0x1b00, 0x1b01), 874 regmap_reg_range(0x1b04, 0x1b04), 875 876 /* port 2 */ 877 regmap_reg_range(0x2000, 0x2001), 878 regmap_reg_range(0x2013, 0x2013), 879 regmap_reg_range(0x2017, 0x2017), 880 regmap_reg_range(0x201b, 0x201b), 881 regmap_reg_range(0x201f, 0x2020), 882 regmap_reg_range(0x2030, 0x2030), 883 regmap_reg_range(0x2100, 0x2115), 884 regmap_reg_range(0x211a, 0x211f), 885 regmap_reg_range(0x2122, 0x2127), 886 regmap_reg_range(0x212a, 0x212b), 887 regmap_reg_range(0x2136, 0x2139), 888 regmap_reg_range(0x213e, 0x213f), 889 regmap_reg_range(0x2400, 0x2401), 890 regmap_reg_range(0x2403, 0x2403), 891 regmap_reg_range(0x2410, 0x2417), 892 regmap_reg_range(0x2420, 0x2423), 893 regmap_reg_range(0x2500, 0x2507), 894 regmap_reg_range(0x2600, 0x2612), 895 regmap_reg_range(0x2800, 0x280f), 896 regmap_reg_range(0x2820, 0x2827), 897 regmap_reg_range(0x2830, 0x2837), 898 regmap_reg_range(0x2840, 0x284b), 899 regmap_reg_range(0x2900, 0x2907), 900 regmap_reg_range(0x2914, 0x2915), 901 regmap_reg_range(0x2a00, 0x2a03), 902 regmap_reg_range(0x2a04, 0x2a07), 903 regmap_reg_range(0x2b00, 0x2b01), 904 regmap_reg_range(0x2b04, 0x2b04), 905 906 /* port 3 */ 907 regmap_reg_range(0x3000, 0x3001), 908 regmap_reg_range(0x3013, 0x3013), 909 regmap_reg_range(0x3017, 0x3017), 910 regmap_reg_range(0x301b, 0x301b), 911 regmap_reg_range(0x301f, 0x3020), 912 regmap_reg_range(0x3030, 0x3030), 913 regmap_reg_range(0x3100, 0x3115), 914 regmap_reg_range(0x311a, 0x311f), 915 regmap_reg_range(0x3122, 0x3127), 916 regmap_reg_range(0x312a, 0x312b), 917 regmap_reg_range(0x3136, 0x3139), 918 regmap_reg_range(0x313e, 0x313f), 919 regmap_reg_range(0x3400, 0x3401), 920 regmap_reg_range(0x3403, 0x3403), 921 regmap_reg_range(0x3410, 0x3417), 922 regmap_reg_range(0x3420, 0x3423), 923 regmap_reg_range(0x3500, 0x3507), 924 regmap_reg_range(0x3600, 0x3612), 925 regmap_reg_range(0x3800, 0x380f), 926 regmap_reg_range(0x3820, 0x3827), 927 regmap_reg_range(0x3830, 0x3837), 928 regmap_reg_range(0x3840, 0x384b), 929 regmap_reg_range(0x3900, 0x3907), 930 regmap_reg_range(0x3914, 0x3915), 931 regmap_reg_range(0x3a00, 0x3a03), 932 regmap_reg_range(0x3a04, 0x3a07), 933 regmap_reg_range(0x3b00, 0x3b01), 934 regmap_reg_range(0x3b04, 0x3b04), 935 936 /* port 4 */ 937 regmap_reg_range(0x4000, 0x4001), 938 regmap_reg_range(0x4013, 0x4013), 939 regmap_reg_range(0x4017, 0x4017), 940 regmap_reg_range(0x401b, 0x401b), 941 regmap_reg_range(0x401f, 0x4020), 942 regmap_reg_range(0x4030, 0x4030), 943 regmap_reg_range(0x4100, 0x4115), 944 regmap_reg_range(0x411a, 0x411f), 945 regmap_reg_range(0x4122, 0x4127), 946 regmap_reg_range(0x412a, 0x412b), 947 regmap_reg_range(0x4136, 0x4139), 948 regmap_reg_range(0x413e, 0x413f), 949 regmap_reg_range(0x4400, 0x4401), 950 regmap_reg_range(0x4403, 0x4403), 951 regmap_reg_range(0x4410, 0x4417), 952 regmap_reg_range(0x4420, 0x4423), 953 regmap_reg_range(0x4500, 0x4507), 954 regmap_reg_range(0x4600, 0x4612), 955 regmap_reg_range(0x4800, 0x480f), 956 regmap_reg_range(0x4820, 0x4827), 957 regmap_reg_range(0x4830, 0x4837), 958 regmap_reg_range(0x4840, 0x484b), 959 regmap_reg_range(0x4900, 0x4907), 960 regmap_reg_range(0x4914, 0x4915), 961 regmap_reg_range(0x4a00, 0x4a03), 962 regmap_reg_range(0x4a04, 0x4a07), 963 regmap_reg_range(0x4b00, 0x4b01), 964 regmap_reg_range(0x4b04, 0x4b04), 965 966 /* port 5 */ 967 regmap_reg_range(0x5000, 0x5001), 968 regmap_reg_range(0x5013, 0x5013), 969 regmap_reg_range(0x5017, 0x5017), 970 regmap_reg_range(0x501b, 0x501b), 971 regmap_reg_range(0x501f, 0x5020), 972 regmap_reg_range(0x5030, 0x5030), 973 regmap_reg_range(0x5100, 0x5115), 974 regmap_reg_range(0x511a, 0x511f), 975 regmap_reg_range(0x5122, 0x5127), 976 regmap_reg_range(0x512a, 0x512b), 977 regmap_reg_range(0x5136, 0x5139), 978 regmap_reg_range(0x513e, 0x513f), 979 regmap_reg_range(0x5400, 0x5401), 980 regmap_reg_range(0x5403, 0x5403), 981 regmap_reg_range(0x5410, 0x5417), 982 regmap_reg_range(0x5420, 0x5423), 983 regmap_reg_range(0x5500, 0x5507), 984 regmap_reg_range(0x5600, 0x5612), 985 regmap_reg_range(0x5800, 0x580f), 986 regmap_reg_range(0x5820, 0x5827), 987 regmap_reg_range(0x5830, 0x5837), 988 regmap_reg_range(0x5840, 0x584b), 989 regmap_reg_range(0x5900, 0x5907), 990 regmap_reg_range(0x5914, 0x5915), 991 regmap_reg_range(0x5a00, 0x5a03), 992 regmap_reg_range(0x5a04, 0x5a07), 993 regmap_reg_range(0x5b00, 0x5b01), 994 regmap_reg_range(0x5b04, 0x5b04), 995 996 /* port 6 */ 997 regmap_reg_range(0x6000, 0x6001), 998 regmap_reg_range(0x6013, 0x6013), 999 regmap_reg_range(0x6017, 0x6017), 1000 regmap_reg_range(0x601b, 0x601b), 1001 regmap_reg_range(0x601f, 0x6020), 1002 regmap_reg_range(0x6030, 0x6030), 1003 regmap_reg_range(0x6100, 0x6115), 1004 regmap_reg_range(0x611a, 0x611f), 1005 regmap_reg_range(0x6122, 0x6127), 1006 regmap_reg_range(0x612a, 0x612b), 1007 regmap_reg_range(0x6136, 0x6139), 1008 regmap_reg_range(0x613e, 0x613f), 1009 regmap_reg_range(0x6300, 0x6301), 1010 regmap_reg_range(0x6400, 0x6401), 1011 regmap_reg_range(0x6403, 0x6403), 1012 regmap_reg_range(0x6410, 0x6417), 1013 regmap_reg_range(0x6420, 0x6423), 1014 regmap_reg_range(0x6500, 0x6507), 1015 regmap_reg_range(0x6600, 0x6612), 1016 regmap_reg_range(0x6800, 0x680f), 1017 regmap_reg_range(0x6820, 0x6827), 1018 regmap_reg_range(0x6830, 0x6837), 1019 regmap_reg_range(0x6840, 0x684b), 1020 regmap_reg_range(0x6900, 0x6907), 1021 regmap_reg_range(0x6914, 0x6915), 1022 regmap_reg_range(0x6a00, 0x6a03), 1023 regmap_reg_range(0x6a04, 0x6a07), 1024 regmap_reg_range(0x6b00, 0x6b01), 1025 regmap_reg_range(0x6b04, 0x6b04), 1026 }; 1027 1028 static const struct regmap_access_table ksz9896_register_set = { 1029 .yes_ranges = ksz9896_valid_regs, 1030 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs), 1031 }; 1032 1033 const struct ksz_chip_data ksz_switch_chips[] = { 1034 [KSZ8563] = { 1035 .chip_id = KSZ8563_CHIP_ID, 1036 .dev_name = "KSZ8563", 1037 .num_vlans = 4096, 1038 .num_alus = 4096, 1039 .num_statics = 16, 1040 .cpu_ports = 0x07, /* can be configured as cpu port */ 1041 .port_cnt = 3, /* total port count */ 1042 .port_nirqs = 3, 1043 .ops = &ksz9477_dev_ops, 1044 .mib_names = ksz9477_mib_names, 1045 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1046 .reg_mib_cnt = MIB_COUNTER_NUM, 1047 .regs = ksz9477_regs, 1048 .masks = ksz9477_masks, 1049 .shifts = ksz9477_shifts, 1050 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1051 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1052 .supports_mii = {false, false, true}, 1053 .supports_rmii = {false, false, true}, 1054 .supports_rgmii = {false, false, true}, 1055 .internal_phy = {true, true, false}, 1056 .gbit_capable = {false, false, true}, 1057 .wr_table = &ksz8563_register_set, 1058 .rd_table = &ksz8563_register_set, 1059 }, 1060 1061 [KSZ8795] = { 1062 .chip_id = KSZ8795_CHIP_ID, 1063 .dev_name = "KSZ8795", 1064 .num_vlans = 4096, 1065 .num_alus = 0, 1066 .num_statics = 8, 1067 .cpu_ports = 0x10, /* can be configured as cpu port */ 1068 .port_cnt = 5, /* total cpu and user ports */ 1069 .ops = &ksz8_dev_ops, 1070 .ksz87xx_eee_link_erratum = true, 1071 .mib_names = ksz9477_mib_names, 1072 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1073 .reg_mib_cnt = MIB_COUNTER_NUM, 1074 .regs = ksz8795_regs, 1075 .masks = ksz8795_masks, 1076 .shifts = ksz8795_shifts, 1077 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1078 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1079 .supports_mii = {false, false, false, false, true}, 1080 .supports_rmii = {false, false, false, false, true}, 1081 .supports_rgmii = {false, false, false, false, true}, 1082 .internal_phy = {true, true, true, true, false}, 1083 }, 1084 1085 [KSZ8794] = { 1086 /* WARNING 1087 * ======= 1088 * KSZ8794 is similar to KSZ8795, except the port map 1089 * contains a gap between external and CPU ports, the 1090 * port map is NOT continuous. The per-port register 1091 * map is shifted accordingly too, i.e. registers at 1092 * offset 0x40 are NOT used on KSZ8794 and they ARE 1093 * used on KSZ8795 for external port 3. 1094 * external cpu 1095 * KSZ8794 0,1,2 4 1096 * KSZ8795 0,1,2,3 4 1097 * KSZ8765 0,1,2,3 4 1098 * port_cnt is configured as 5, even though it is 4 1099 */ 1100 .chip_id = KSZ8794_CHIP_ID, 1101 .dev_name = "KSZ8794", 1102 .num_vlans = 4096, 1103 .num_alus = 0, 1104 .num_statics = 8, 1105 .cpu_ports = 0x10, /* can be configured as cpu port */ 1106 .port_cnt = 5, /* total cpu and user ports */ 1107 .ops = &ksz8_dev_ops, 1108 .ksz87xx_eee_link_erratum = true, 1109 .mib_names = ksz9477_mib_names, 1110 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1111 .reg_mib_cnt = MIB_COUNTER_NUM, 1112 .regs = ksz8795_regs, 1113 .masks = ksz8795_masks, 1114 .shifts = ksz8795_shifts, 1115 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1116 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1117 .supports_mii = {false, false, false, false, true}, 1118 .supports_rmii = {false, false, false, false, true}, 1119 .supports_rgmii = {false, false, false, false, true}, 1120 .internal_phy = {true, true, true, false, false}, 1121 }, 1122 1123 [KSZ8765] = { 1124 .chip_id = KSZ8765_CHIP_ID, 1125 .dev_name = "KSZ8765", 1126 .num_vlans = 4096, 1127 .num_alus = 0, 1128 .num_statics = 8, 1129 .cpu_ports = 0x10, /* can be configured as cpu port */ 1130 .port_cnt = 5, /* total cpu and user ports */ 1131 .ops = &ksz8_dev_ops, 1132 .ksz87xx_eee_link_erratum = true, 1133 .mib_names = ksz9477_mib_names, 1134 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1135 .reg_mib_cnt = MIB_COUNTER_NUM, 1136 .regs = ksz8795_regs, 1137 .masks = ksz8795_masks, 1138 .shifts = ksz8795_shifts, 1139 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1140 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1141 .supports_mii = {false, false, false, false, true}, 1142 .supports_rmii = {false, false, false, false, true}, 1143 .supports_rgmii = {false, false, false, false, true}, 1144 .internal_phy = {true, true, true, true, false}, 1145 }, 1146 1147 [KSZ8830] = { 1148 .chip_id = KSZ8830_CHIP_ID, 1149 .dev_name = "KSZ8863/KSZ8873", 1150 .num_vlans = 16, 1151 .num_alus = 0, 1152 .num_statics = 8, 1153 .cpu_ports = 0x4, /* can be configured as cpu port */ 1154 .port_cnt = 3, 1155 .ops = &ksz8_dev_ops, 1156 .mib_names = ksz88xx_mib_names, 1157 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1158 .reg_mib_cnt = MIB_COUNTER_NUM, 1159 .regs = ksz8863_regs, 1160 .masks = ksz8863_masks, 1161 .shifts = ksz8863_shifts, 1162 .supports_mii = {false, false, true}, 1163 .supports_rmii = {false, false, true}, 1164 .internal_phy = {true, true, false}, 1165 }, 1166 1167 [KSZ9477] = { 1168 .chip_id = KSZ9477_CHIP_ID, 1169 .dev_name = "KSZ9477", 1170 .num_vlans = 4096, 1171 .num_alus = 4096, 1172 .num_statics = 16, 1173 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1174 .port_cnt = 7, /* total physical port count */ 1175 .port_nirqs = 4, 1176 .ops = &ksz9477_dev_ops, 1177 .phy_errata_9477 = true, 1178 .mib_names = ksz9477_mib_names, 1179 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1180 .reg_mib_cnt = MIB_COUNTER_NUM, 1181 .regs = ksz9477_regs, 1182 .masks = ksz9477_masks, 1183 .shifts = ksz9477_shifts, 1184 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1185 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1186 .supports_mii = {false, false, false, false, 1187 false, true, false}, 1188 .supports_rmii = {false, false, false, false, 1189 false, true, false}, 1190 .supports_rgmii = {false, false, false, false, 1191 false, true, false}, 1192 .internal_phy = {true, true, true, true, 1193 true, false, false}, 1194 .gbit_capable = {true, true, true, true, true, true, true}, 1195 .wr_table = &ksz9477_register_set, 1196 .rd_table = &ksz9477_register_set, 1197 }, 1198 1199 [KSZ9896] = { 1200 .chip_id = KSZ9896_CHIP_ID, 1201 .dev_name = "KSZ9896", 1202 .num_vlans = 4096, 1203 .num_alus = 4096, 1204 .num_statics = 16, 1205 .cpu_ports = 0x3F, /* can be configured as cpu port */ 1206 .port_cnt = 6, /* total physical port count */ 1207 .port_nirqs = 2, 1208 .ops = &ksz9477_dev_ops, 1209 .phy_errata_9477 = true, 1210 .mib_names = ksz9477_mib_names, 1211 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1212 .reg_mib_cnt = MIB_COUNTER_NUM, 1213 .regs = ksz9477_regs, 1214 .masks = ksz9477_masks, 1215 .shifts = ksz9477_shifts, 1216 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1217 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1218 .supports_mii = {false, false, false, false, 1219 false, true}, 1220 .supports_rmii = {false, false, false, false, 1221 false, true}, 1222 .supports_rgmii = {false, false, false, false, 1223 false, true}, 1224 .internal_phy = {true, true, true, true, 1225 true, false}, 1226 .gbit_capable = {true, true, true, true, true, true}, 1227 .wr_table = &ksz9896_register_set, 1228 .rd_table = &ksz9896_register_set, 1229 }, 1230 1231 [KSZ9897] = { 1232 .chip_id = KSZ9897_CHIP_ID, 1233 .dev_name = "KSZ9897", 1234 .num_vlans = 4096, 1235 .num_alus = 4096, 1236 .num_statics = 16, 1237 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1238 .port_cnt = 7, /* total physical port count */ 1239 .port_nirqs = 2, 1240 .ops = &ksz9477_dev_ops, 1241 .phy_errata_9477 = true, 1242 .mib_names = ksz9477_mib_names, 1243 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1244 .reg_mib_cnt = MIB_COUNTER_NUM, 1245 .regs = ksz9477_regs, 1246 .masks = ksz9477_masks, 1247 .shifts = ksz9477_shifts, 1248 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1249 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1250 .supports_mii = {false, false, false, false, 1251 false, true, true}, 1252 .supports_rmii = {false, false, false, false, 1253 false, true, true}, 1254 .supports_rgmii = {false, false, false, false, 1255 false, true, true}, 1256 .internal_phy = {true, true, true, true, 1257 true, false, false}, 1258 .gbit_capable = {true, true, true, true, true, true, true}, 1259 }, 1260 1261 [KSZ9893] = { 1262 .chip_id = KSZ9893_CHIP_ID, 1263 .dev_name = "KSZ9893", 1264 .num_vlans = 4096, 1265 .num_alus = 4096, 1266 .num_statics = 16, 1267 .cpu_ports = 0x07, /* can be configured as cpu port */ 1268 .port_cnt = 3, /* total port count */ 1269 .port_nirqs = 2, 1270 .ops = &ksz9477_dev_ops, 1271 .mib_names = ksz9477_mib_names, 1272 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1273 .reg_mib_cnt = MIB_COUNTER_NUM, 1274 .regs = ksz9477_regs, 1275 .masks = ksz9477_masks, 1276 .shifts = ksz9477_shifts, 1277 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1278 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1279 .supports_mii = {false, false, true}, 1280 .supports_rmii = {false, false, true}, 1281 .supports_rgmii = {false, false, true}, 1282 .internal_phy = {true, true, false}, 1283 .gbit_capable = {true, true, true}, 1284 }, 1285 1286 [KSZ9563] = { 1287 .chip_id = KSZ9563_CHIP_ID, 1288 .dev_name = "KSZ9563", 1289 .num_vlans = 4096, 1290 .num_alus = 4096, 1291 .num_statics = 16, 1292 .cpu_ports = 0x07, /* can be configured as cpu port */ 1293 .port_cnt = 3, /* total port count */ 1294 .port_nirqs = 3, 1295 .ops = &ksz9477_dev_ops, 1296 .mib_names = ksz9477_mib_names, 1297 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1298 .reg_mib_cnt = MIB_COUNTER_NUM, 1299 .regs = ksz9477_regs, 1300 .masks = ksz9477_masks, 1301 .shifts = ksz9477_shifts, 1302 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1303 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1304 .supports_mii = {false, false, true}, 1305 .supports_rmii = {false, false, true}, 1306 .supports_rgmii = {false, false, true}, 1307 .internal_phy = {true, true, false}, 1308 .gbit_capable = {true, true, true}, 1309 }, 1310 1311 [KSZ9567] = { 1312 .chip_id = KSZ9567_CHIP_ID, 1313 .dev_name = "KSZ9567", 1314 .num_vlans = 4096, 1315 .num_alus = 4096, 1316 .num_statics = 16, 1317 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1318 .port_cnt = 7, /* total physical port count */ 1319 .port_nirqs = 3, 1320 .ops = &ksz9477_dev_ops, 1321 .phy_errata_9477 = true, 1322 .mib_names = ksz9477_mib_names, 1323 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1324 .reg_mib_cnt = MIB_COUNTER_NUM, 1325 .regs = ksz9477_regs, 1326 .masks = ksz9477_masks, 1327 .shifts = ksz9477_shifts, 1328 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1329 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1330 .supports_mii = {false, false, false, false, 1331 false, true, true}, 1332 .supports_rmii = {false, false, false, false, 1333 false, true, true}, 1334 .supports_rgmii = {false, false, false, false, 1335 false, true, true}, 1336 .internal_phy = {true, true, true, true, 1337 true, false, false}, 1338 .gbit_capable = {true, true, true, true, true, true, true}, 1339 }, 1340 1341 [LAN9370] = { 1342 .chip_id = LAN9370_CHIP_ID, 1343 .dev_name = "LAN9370", 1344 .num_vlans = 4096, 1345 .num_alus = 1024, 1346 .num_statics = 256, 1347 .cpu_ports = 0x10, /* can be configured as cpu port */ 1348 .port_cnt = 5, /* total physical port count */ 1349 .port_nirqs = 6, 1350 .ops = &lan937x_dev_ops, 1351 .mib_names = ksz9477_mib_names, 1352 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1353 .reg_mib_cnt = MIB_COUNTER_NUM, 1354 .regs = ksz9477_regs, 1355 .masks = lan937x_masks, 1356 .shifts = lan937x_shifts, 1357 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1358 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1359 .supports_mii = {false, false, false, false, true}, 1360 .supports_rmii = {false, false, false, false, true}, 1361 .supports_rgmii = {false, false, false, false, true}, 1362 .internal_phy = {true, true, true, true, false}, 1363 }, 1364 1365 [LAN9371] = { 1366 .chip_id = LAN9371_CHIP_ID, 1367 .dev_name = "LAN9371", 1368 .num_vlans = 4096, 1369 .num_alus = 1024, 1370 .num_statics = 256, 1371 .cpu_ports = 0x30, /* can be configured as cpu port */ 1372 .port_cnt = 6, /* total physical port count */ 1373 .port_nirqs = 6, 1374 .ops = &lan937x_dev_ops, 1375 .mib_names = ksz9477_mib_names, 1376 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1377 .reg_mib_cnt = MIB_COUNTER_NUM, 1378 .regs = ksz9477_regs, 1379 .masks = lan937x_masks, 1380 .shifts = lan937x_shifts, 1381 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1382 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1383 .supports_mii = {false, false, false, false, true, true}, 1384 .supports_rmii = {false, false, false, false, true, true}, 1385 .supports_rgmii = {false, false, false, false, true, true}, 1386 .internal_phy = {true, true, true, true, false, false}, 1387 }, 1388 1389 [LAN9372] = { 1390 .chip_id = LAN9372_CHIP_ID, 1391 .dev_name = "LAN9372", 1392 .num_vlans = 4096, 1393 .num_alus = 1024, 1394 .num_statics = 256, 1395 .cpu_ports = 0x30, /* can be configured as cpu port */ 1396 .port_cnt = 8, /* total physical port count */ 1397 .port_nirqs = 6, 1398 .ops = &lan937x_dev_ops, 1399 .mib_names = ksz9477_mib_names, 1400 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1401 .reg_mib_cnt = MIB_COUNTER_NUM, 1402 .regs = ksz9477_regs, 1403 .masks = lan937x_masks, 1404 .shifts = lan937x_shifts, 1405 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1406 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1407 .supports_mii = {false, false, false, false, 1408 true, true, false, false}, 1409 .supports_rmii = {false, false, false, false, 1410 true, true, false, false}, 1411 .supports_rgmii = {false, false, false, false, 1412 true, true, false, false}, 1413 .internal_phy = {true, true, true, true, 1414 false, false, true, true}, 1415 }, 1416 1417 [LAN9373] = { 1418 .chip_id = LAN9373_CHIP_ID, 1419 .dev_name = "LAN9373", 1420 .num_vlans = 4096, 1421 .num_alus = 1024, 1422 .num_statics = 256, 1423 .cpu_ports = 0x38, /* can be configured as cpu port */ 1424 .port_cnt = 5, /* total physical port count */ 1425 .port_nirqs = 6, 1426 .ops = &lan937x_dev_ops, 1427 .mib_names = ksz9477_mib_names, 1428 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1429 .reg_mib_cnt = MIB_COUNTER_NUM, 1430 .regs = ksz9477_regs, 1431 .masks = lan937x_masks, 1432 .shifts = lan937x_shifts, 1433 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1434 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1435 .supports_mii = {false, false, false, false, 1436 true, true, false, false}, 1437 .supports_rmii = {false, false, false, false, 1438 true, true, false, false}, 1439 .supports_rgmii = {false, false, false, false, 1440 true, true, false, false}, 1441 .internal_phy = {true, true, true, false, 1442 false, false, true, true}, 1443 }, 1444 1445 [LAN9374] = { 1446 .chip_id = LAN9374_CHIP_ID, 1447 .dev_name = "LAN9374", 1448 .num_vlans = 4096, 1449 .num_alus = 1024, 1450 .num_statics = 256, 1451 .cpu_ports = 0x30, /* can be configured as cpu port */ 1452 .port_cnt = 8, /* total physical port count */ 1453 .port_nirqs = 6, 1454 .ops = &lan937x_dev_ops, 1455 .mib_names = ksz9477_mib_names, 1456 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1457 .reg_mib_cnt = MIB_COUNTER_NUM, 1458 .regs = ksz9477_regs, 1459 .masks = lan937x_masks, 1460 .shifts = lan937x_shifts, 1461 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1462 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1463 .supports_mii = {false, false, false, false, 1464 true, true, false, false}, 1465 .supports_rmii = {false, false, false, false, 1466 true, true, false, false}, 1467 .supports_rgmii = {false, false, false, false, 1468 true, true, false, false}, 1469 .internal_phy = {true, true, true, true, 1470 false, false, true, true}, 1471 }, 1472 }; 1473 EXPORT_SYMBOL_GPL(ksz_switch_chips); 1474 1475 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 1476 { 1477 int i; 1478 1479 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 1480 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 1481 1482 if (chip->chip_id == prod_num) 1483 return chip; 1484 } 1485 1486 return NULL; 1487 } 1488 1489 static int ksz_check_device_id(struct ksz_device *dev) 1490 { 1491 const struct ksz_chip_data *dt_chip_data; 1492 1493 dt_chip_data = of_device_get_match_data(dev->dev); 1494 1495 /* Check for Device Tree and Chip ID */ 1496 if (dt_chip_data->chip_id != dev->chip_id) { 1497 dev_err(dev->dev, 1498 "Device tree specifies chip %s but found %s, please fix it!\n", 1499 dt_chip_data->dev_name, dev->info->dev_name); 1500 return -ENODEV; 1501 } 1502 1503 return 0; 1504 } 1505 1506 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 1507 struct phylink_config *config) 1508 { 1509 struct ksz_device *dev = ds->priv; 1510 1511 config->legacy_pre_march2020 = false; 1512 1513 if (dev->info->supports_mii[port]) 1514 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1515 1516 if (dev->info->supports_rmii[port]) 1517 __set_bit(PHY_INTERFACE_MODE_RMII, 1518 config->supported_interfaces); 1519 1520 if (dev->info->supports_rgmii[port]) 1521 phy_interface_set_rgmii(config->supported_interfaces); 1522 1523 if (dev->info->internal_phy[port]) { 1524 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1525 config->supported_interfaces); 1526 /* Compatibility for phylib's default interface type when the 1527 * phy-mode property is absent 1528 */ 1529 __set_bit(PHY_INTERFACE_MODE_GMII, 1530 config->supported_interfaces); 1531 } 1532 1533 if (dev->dev_ops->get_caps) 1534 dev->dev_ops->get_caps(dev, port, config); 1535 } 1536 1537 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 1538 { 1539 struct ethtool_pause_stats *pstats; 1540 struct rtnl_link_stats64 *stats; 1541 struct ksz_stats_raw *raw; 1542 struct ksz_port_mib *mib; 1543 1544 mib = &dev->ports[port].mib; 1545 stats = &mib->stats64; 1546 pstats = &mib->pause_stats; 1547 raw = (struct ksz_stats_raw *)mib->counters; 1548 1549 spin_lock(&mib->stats64_lock); 1550 1551 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1552 raw->rx_pause; 1553 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1554 raw->tx_pause; 1555 1556 /* HW counters are counting bytes + FCS which is not acceptable 1557 * for rtnl_link_stats64 interface 1558 */ 1559 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 1560 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 1561 1562 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 1563 raw->rx_oversize; 1564 1565 stats->rx_crc_errors = raw->rx_crc_err; 1566 stats->rx_frame_errors = raw->rx_align_err; 1567 stats->rx_dropped = raw->rx_discards; 1568 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 1569 stats->rx_frame_errors + stats->rx_dropped; 1570 1571 stats->tx_window_errors = raw->tx_late_col; 1572 stats->tx_fifo_errors = raw->tx_discards; 1573 stats->tx_aborted_errors = raw->tx_exc_col; 1574 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 1575 stats->tx_aborted_errors; 1576 1577 stats->multicast = raw->rx_mcast; 1578 stats->collisions = raw->tx_total_col; 1579 1580 pstats->tx_pause_frames = raw->tx_pause; 1581 pstats->rx_pause_frames = raw->rx_pause; 1582 1583 spin_unlock(&mib->stats64_lock); 1584 } 1585 1586 static void ksz_get_stats64(struct dsa_switch *ds, int port, 1587 struct rtnl_link_stats64 *s) 1588 { 1589 struct ksz_device *dev = ds->priv; 1590 struct ksz_port_mib *mib; 1591 1592 mib = &dev->ports[port].mib; 1593 1594 spin_lock(&mib->stats64_lock); 1595 memcpy(s, &mib->stats64, sizeof(*s)); 1596 spin_unlock(&mib->stats64_lock); 1597 } 1598 1599 static void ksz_get_pause_stats(struct dsa_switch *ds, int port, 1600 struct ethtool_pause_stats *pause_stats) 1601 { 1602 struct ksz_device *dev = ds->priv; 1603 struct ksz_port_mib *mib; 1604 1605 mib = &dev->ports[port].mib; 1606 1607 spin_lock(&mib->stats64_lock); 1608 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 1609 spin_unlock(&mib->stats64_lock); 1610 } 1611 1612 static void ksz_get_strings(struct dsa_switch *ds, int port, 1613 u32 stringset, uint8_t *buf) 1614 { 1615 struct ksz_device *dev = ds->priv; 1616 int i; 1617 1618 if (stringset != ETH_SS_STATS) 1619 return; 1620 1621 for (i = 0; i < dev->info->mib_cnt; i++) { 1622 memcpy(buf + i * ETH_GSTRING_LEN, 1623 dev->info->mib_names[i].string, ETH_GSTRING_LEN); 1624 } 1625 } 1626 1627 static void ksz_update_port_member(struct ksz_device *dev, int port) 1628 { 1629 struct ksz_port *p = &dev->ports[port]; 1630 struct dsa_switch *ds = dev->ds; 1631 u8 port_member = 0, cpu_port; 1632 const struct dsa_port *dp; 1633 int i, j; 1634 1635 if (!dsa_is_user_port(ds, port)) 1636 return; 1637 1638 dp = dsa_to_port(ds, port); 1639 cpu_port = BIT(dsa_upstream_port(ds, port)); 1640 1641 for (i = 0; i < ds->num_ports; i++) { 1642 const struct dsa_port *other_dp = dsa_to_port(ds, i); 1643 struct ksz_port *other_p = &dev->ports[i]; 1644 u8 val = 0; 1645 1646 if (!dsa_is_user_port(ds, i)) 1647 continue; 1648 if (port == i) 1649 continue; 1650 if (!dsa_port_bridge_same(dp, other_dp)) 1651 continue; 1652 if (other_p->stp_state != BR_STATE_FORWARDING) 1653 continue; 1654 1655 if (p->stp_state == BR_STATE_FORWARDING) { 1656 val |= BIT(port); 1657 port_member |= BIT(i); 1658 } 1659 1660 /* Retain port [i]'s relationship to other ports than [port] */ 1661 for (j = 0; j < ds->num_ports; j++) { 1662 const struct dsa_port *third_dp; 1663 struct ksz_port *third_p; 1664 1665 if (j == i) 1666 continue; 1667 if (j == port) 1668 continue; 1669 if (!dsa_is_user_port(ds, j)) 1670 continue; 1671 third_p = &dev->ports[j]; 1672 if (third_p->stp_state != BR_STATE_FORWARDING) 1673 continue; 1674 third_dp = dsa_to_port(ds, j); 1675 if (dsa_port_bridge_same(other_dp, third_dp)) 1676 val |= BIT(j); 1677 } 1678 1679 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 1680 } 1681 1682 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 1683 } 1684 1685 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 1686 { 1687 struct ksz_device *dev = bus->priv; 1688 u16 val; 1689 int ret; 1690 1691 if (regnum & MII_ADDR_C45) 1692 return -EOPNOTSUPP; 1693 1694 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val); 1695 if (ret < 0) 1696 return ret; 1697 1698 return val; 1699 } 1700 1701 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 1702 u16 val) 1703 { 1704 struct ksz_device *dev = bus->priv; 1705 1706 if (regnum & MII_ADDR_C45) 1707 return -EOPNOTSUPP; 1708 1709 return dev->dev_ops->w_phy(dev, addr, regnum, val); 1710 } 1711 1712 static int ksz_irq_phy_setup(struct ksz_device *dev) 1713 { 1714 struct dsa_switch *ds = dev->ds; 1715 int phy; 1716 int irq; 1717 int ret; 1718 1719 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) { 1720 if (BIT(phy) & ds->phys_mii_mask) { 1721 irq = irq_find_mapping(dev->ports[phy].pirq.domain, 1722 PORT_SRC_PHY_INT); 1723 if (irq < 0) { 1724 ret = irq; 1725 goto out; 1726 } 1727 ds->slave_mii_bus->irq[phy] = irq; 1728 } 1729 } 1730 return 0; 1731 out: 1732 while (phy--) 1733 if (BIT(phy) & ds->phys_mii_mask) 1734 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]); 1735 1736 return ret; 1737 } 1738 1739 static void ksz_irq_phy_free(struct ksz_device *dev) 1740 { 1741 struct dsa_switch *ds = dev->ds; 1742 int phy; 1743 1744 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) 1745 if (BIT(phy) & ds->phys_mii_mask) 1746 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]); 1747 } 1748 1749 static int ksz_mdio_register(struct ksz_device *dev) 1750 { 1751 struct dsa_switch *ds = dev->ds; 1752 struct device_node *mdio_np; 1753 struct mii_bus *bus; 1754 int ret; 1755 1756 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); 1757 if (!mdio_np) 1758 return 0; 1759 1760 bus = devm_mdiobus_alloc(ds->dev); 1761 if (!bus) { 1762 of_node_put(mdio_np); 1763 return -ENOMEM; 1764 } 1765 1766 bus->priv = dev; 1767 bus->read = ksz_sw_mdio_read; 1768 bus->write = ksz_sw_mdio_write; 1769 bus->name = "ksz slave smi"; 1770 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); 1771 bus->parent = ds->dev; 1772 bus->phy_mask = ~ds->phys_mii_mask; 1773 1774 ds->slave_mii_bus = bus; 1775 1776 if (dev->irq > 0) { 1777 ret = ksz_irq_phy_setup(dev); 1778 if (ret) { 1779 of_node_put(mdio_np); 1780 return ret; 1781 } 1782 } 1783 1784 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); 1785 if (ret) { 1786 dev_err(ds->dev, "unable to register MDIO bus %s\n", 1787 bus->id); 1788 if (dev->irq > 0) 1789 ksz_irq_phy_free(dev); 1790 } 1791 1792 of_node_put(mdio_np); 1793 1794 return ret; 1795 } 1796 1797 static void ksz_irq_mask(struct irq_data *d) 1798 { 1799 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1800 1801 kirq->masked |= BIT(d->hwirq); 1802 } 1803 1804 static void ksz_irq_unmask(struct irq_data *d) 1805 { 1806 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1807 1808 kirq->masked &= ~BIT(d->hwirq); 1809 } 1810 1811 static void ksz_irq_bus_lock(struct irq_data *d) 1812 { 1813 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1814 1815 mutex_lock(&kirq->dev->lock_irq); 1816 } 1817 1818 static void ksz_irq_bus_sync_unlock(struct irq_data *d) 1819 { 1820 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1821 struct ksz_device *dev = kirq->dev; 1822 int ret; 1823 1824 ret = ksz_write32(dev, kirq->reg_mask, kirq->masked); 1825 if (ret) 1826 dev_err(dev->dev, "failed to change IRQ mask\n"); 1827 1828 mutex_unlock(&dev->lock_irq); 1829 } 1830 1831 static const struct irq_chip ksz_irq_chip = { 1832 .name = "ksz-irq", 1833 .irq_mask = ksz_irq_mask, 1834 .irq_unmask = ksz_irq_unmask, 1835 .irq_bus_lock = ksz_irq_bus_lock, 1836 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock, 1837 }; 1838 1839 static int ksz_irq_domain_map(struct irq_domain *d, 1840 unsigned int irq, irq_hw_number_t hwirq) 1841 { 1842 irq_set_chip_data(irq, d->host_data); 1843 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq); 1844 irq_set_noprobe(irq); 1845 1846 return 0; 1847 } 1848 1849 static const struct irq_domain_ops ksz_irq_domain_ops = { 1850 .map = ksz_irq_domain_map, 1851 .xlate = irq_domain_xlate_twocell, 1852 }; 1853 1854 static void ksz_irq_free(struct ksz_irq *kirq) 1855 { 1856 int irq, virq; 1857 1858 free_irq(kirq->irq_num, kirq); 1859 1860 for (irq = 0; irq < kirq->nirqs; irq++) { 1861 virq = irq_find_mapping(kirq->domain, irq); 1862 irq_dispose_mapping(virq); 1863 } 1864 1865 irq_domain_remove(kirq->domain); 1866 } 1867 1868 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id) 1869 { 1870 struct ksz_irq *kirq = dev_id; 1871 unsigned int nhandled = 0; 1872 struct ksz_device *dev; 1873 unsigned int sub_irq; 1874 u8 data; 1875 int ret; 1876 u8 n; 1877 1878 dev = kirq->dev; 1879 1880 /* Read interrupt status register */ 1881 ret = ksz_read8(dev, kirq->reg_status, &data); 1882 if (ret) 1883 goto out; 1884 1885 for (n = 0; n < kirq->nirqs; ++n) { 1886 if (data & BIT(n)) { 1887 sub_irq = irq_find_mapping(kirq->domain, n); 1888 handle_nested_irq(sub_irq); 1889 ++nhandled; 1890 } 1891 } 1892 out: 1893 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 1894 } 1895 1896 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq) 1897 { 1898 int ret, n; 1899 1900 kirq->dev = dev; 1901 kirq->masked = ~0; 1902 1903 kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0, 1904 &ksz_irq_domain_ops, kirq); 1905 if (!kirq->domain) 1906 return -ENOMEM; 1907 1908 for (n = 0; n < kirq->nirqs; n++) 1909 irq_create_mapping(kirq->domain, n); 1910 1911 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn, 1912 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 1913 kirq->name, kirq); 1914 if (ret) 1915 goto out; 1916 1917 return 0; 1918 1919 out: 1920 ksz_irq_free(kirq); 1921 1922 return ret; 1923 } 1924 1925 static int ksz_girq_setup(struct ksz_device *dev) 1926 { 1927 struct ksz_irq *girq = &dev->girq; 1928 1929 girq->nirqs = dev->info->port_cnt; 1930 girq->reg_mask = REG_SW_PORT_INT_MASK__1; 1931 girq->reg_status = REG_SW_PORT_INT_STATUS__1; 1932 snprintf(girq->name, sizeof(girq->name), "global_port_irq"); 1933 1934 girq->irq_num = dev->irq; 1935 1936 return ksz_irq_common_setup(dev, girq); 1937 } 1938 1939 static int ksz_pirq_setup(struct ksz_device *dev, u8 p) 1940 { 1941 struct ksz_irq *pirq = &dev->ports[p].pirq; 1942 1943 pirq->nirqs = dev->info->port_nirqs; 1944 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK); 1945 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS); 1946 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p); 1947 1948 pirq->irq_num = irq_find_mapping(dev->girq.domain, p); 1949 if (pirq->irq_num < 0) 1950 return pirq->irq_num; 1951 1952 return ksz_irq_common_setup(dev, pirq); 1953 } 1954 1955 static int ksz_setup(struct dsa_switch *ds) 1956 { 1957 struct ksz_device *dev = ds->priv; 1958 struct dsa_port *dp; 1959 struct ksz_port *p; 1960 const u16 *regs; 1961 int ret; 1962 1963 regs = dev->info->regs; 1964 1965 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 1966 dev->info->num_vlans, GFP_KERNEL); 1967 if (!dev->vlan_cache) 1968 return -ENOMEM; 1969 1970 ret = dev->dev_ops->reset(dev); 1971 if (ret) { 1972 dev_err(ds->dev, "failed to reset switch\n"); 1973 return ret; 1974 } 1975 1976 /* set broadcast storm protection 10% rate */ 1977 regmap_update_bits(dev->regmap[1], regs[S_BROADCAST_CTRL], 1978 BROADCAST_STORM_RATE, 1979 (BROADCAST_STORM_VALUE * 1980 BROADCAST_STORM_PROT_RATE) / 100); 1981 1982 dev->dev_ops->config_cpu_port(ds); 1983 1984 dev->dev_ops->enable_stp_addr(dev); 1985 1986 regmap_update_bits(dev->regmap[0], regs[S_MULTICAST_CTRL], 1987 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 1988 1989 ksz_init_mib_timer(dev); 1990 1991 ds->configure_vlan_while_not_filtering = false; 1992 1993 if (dev->dev_ops->setup) { 1994 ret = dev->dev_ops->setup(ds); 1995 if (ret) 1996 return ret; 1997 } 1998 1999 /* Start with learning disabled on standalone user ports, and enabled 2000 * on the CPU port. In lack of other finer mechanisms, learning on the 2001 * CPU port will avoid flooding bridge local addresses on the network 2002 * in some cases. 2003 */ 2004 p = &dev->ports[dev->cpu_port]; 2005 p->learning = true; 2006 2007 if (dev->irq > 0) { 2008 ret = ksz_girq_setup(dev); 2009 if (ret) 2010 return ret; 2011 2012 dsa_switch_for_each_user_port(dp, dev->ds) { 2013 ret = ksz_pirq_setup(dev, dp->index); 2014 if (ret) 2015 goto out_girq; 2016 } 2017 } 2018 2019 ret = ksz_mdio_register(dev); 2020 if (ret < 0) { 2021 dev_err(dev->dev, "failed to register the mdio"); 2022 goto out_pirq; 2023 } 2024 2025 /* start switch */ 2026 regmap_update_bits(dev->regmap[0], regs[S_START_CTRL], 2027 SW_START, SW_START); 2028 2029 return 0; 2030 2031 out_pirq: 2032 if (dev->irq > 0) 2033 dsa_switch_for_each_user_port(dp, dev->ds) 2034 ksz_irq_free(&dev->ports[dp->index].pirq); 2035 out_girq: 2036 if (dev->irq > 0) 2037 ksz_irq_free(&dev->girq); 2038 2039 return ret; 2040 } 2041 2042 static void ksz_teardown(struct dsa_switch *ds) 2043 { 2044 struct ksz_device *dev = ds->priv; 2045 struct dsa_port *dp; 2046 2047 if (dev->irq > 0) { 2048 dsa_switch_for_each_user_port(dp, dev->ds) 2049 ksz_irq_free(&dev->ports[dp->index].pirq); 2050 2051 ksz_irq_free(&dev->girq); 2052 } 2053 2054 if (dev->dev_ops->teardown) 2055 dev->dev_ops->teardown(ds); 2056 } 2057 2058 static void port_r_cnt(struct ksz_device *dev, int port) 2059 { 2060 struct ksz_port_mib *mib = &dev->ports[port].mib; 2061 u64 *dropped; 2062 2063 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 2064 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 2065 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 2066 &mib->counters[mib->cnt_ptr]); 2067 ++mib->cnt_ptr; 2068 } 2069 2070 /* last one in storage */ 2071 dropped = &mib->counters[dev->info->mib_cnt]; 2072 2073 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 2074 while (mib->cnt_ptr < dev->info->mib_cnt) { 2075 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 2076 dropped, &mib->counters[mib->cnt_ptr]); 2077 ++mib->cnt_ptr; 2078 } 2079 mib->cnt_ptr = 0; 2080 } 2081 2082 static void ksz_mib_read_work(struct work_struct *work) 2083 { 2084 struct ksz_device *dev = container_of(work, struct ksz_device, 2085 mib_read.work); 2086 struct ksz_port_mib *mib; 2087 struct ksz_port *p; 2088 int i; 2089 2090 for (i = 0; i < dev->info->port_cnt; i++) { 2091 if (dsa_is_unused_port(dev->ds, i)) 2092 continue; 2093 2094 p = &dev->ports[i]; 2095 mib = &p->mib; 2096 mutex_lock(&mib->cnt_mutex); 2097 2098 /* Only read MIB counters when the port is told to do. 2099 * If not, read only dropped counters when link is not up. 2100 */ 2101 if (!p->read) { 2102 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 2103 2104 if (!netif_carrier_ok(dp->slave)) 2105 mib->cnt_ptr = dev->info->reg_mib_cnt; 2106 } 2107 port_r_cnt(dev, i); 2108 p->read = false; 2109 2110 if (dev->dev_ops->r_mib_stat64) 2111 dev->dev_ops->r_mib_stat64(dev, i); 2112 2113 mutex_unlock(&mib->cnt_mutex); 2114 } 2115 2116 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 2117 } 2118 2119 void ksz_init_mib_timer(struct ksz_device *dev) 2120 { 2121 int i; 2122 2123 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 2124 2125 for (i = 0; i < dev->info->port_cnt; i++) { 2126 struct ksz_port_mib *mib = &dev->ports[i].mib; 2127 2128 dev->dev_ops->port_init_cnt(dev, i); 2129 2130 mib->cnt_ptr = 0; 2131 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 2132 } 2133 } 2134 2135 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 2136 { 2137 struct ksz_device *dev = ds->priv; 2138 u16 val = 0xffff; 2139 int ret; 2140 2141 ret = dev->dev_ops->r_phy(dev, addr, reg, &val); 2142 if (ret) 2143 return ret; 2144 2145 return val; 2146 } 2147 2148 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 2149 { 2150 struct ksz_device *dev = ds->priv; 2151 int ret; 2152 2153 ret = dev->dev_ops->w_phy(dev, addr, reg, val); 2154 if (ret) 2155 return ret; 2156 2157 return 0; 2158 } 2159 2160 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 2161 { 2162 struct ksz_device *dev = ds->priv; 2163 2164 if (dev->chip_id == KSZ8830_CHIP_ID) { 2165 /* Silicon Errata Sheet (DS80000830A): 2166 * Port 1 does not work with LinkMD Cable-Testing. 2167 * Port 1 does not respond to received PAUSE control frames. 2168 */ 2169 if (!port) 2170 return MICREL_KSZ8_P1_ERRATA; 2171 } 2172 2173 return 0; 2174 } 2175 2176 static void ksz_mac_link_down(struct dsa_switch *ds, int port, 2177 unsigned int mode, phy_interface_t interface) 2178 { 2179 struct ksz_device *dev = ds->priv; 2180 struct ksz_port *p = &dev->ports[port]; 2181 2182 /* Read all MIB counters when the link is going down. */ 2183 p->read = true; 2184 /* timer started */ 2185 if (dev->mib_read_interval) 2186 schedule_delayed_work(&dev->mib_read, 0); 2187 } 2188 2189 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 2190 { 2191 struct ksz_device *dev = ds->priv; 2192 2193 if (sset != ETH_SS_STATS) 2194 return 0; 2195 2196 return dev->info->mib_cnt; 2197 } 2198 2199 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 2200 uint64_t *buf) 2201 { 2202 const struct dsa_port *dp = dsa_to_port(ds, port); 2203 struct ksz_device *dev = ds->priv; 2204 struct ksz_port_mib *mib; 2205 2206 mib = &dev->ports[port].mib; 2207 mutex_lock(&mib->cnt_mutex); 2208 2209 /* Only read dropped counters if no link. */ 2210 if (!netif_carrier_ok(dp->slave)) 2211 mib->cnt_ptr = dev->info->reg_mib_cnt; 2212 port_r_cnt(dev, port); 2213 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 2214 mutex_unlock(&mib->cnt_mutex); 2215 } 2216 2217 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 2218 struct dsa_bridge bridge, 2219 bool *tx_fwd_offload, 2220 struct netlink_ext_ack *extack) 2221 { 2222 /* port_stp_state_set() will be called after to put the port in 2223 * appropriate state so there is no need to do anything. 2224 */ 2225 2226 return 0; 2227 } 2228 2229 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 2230 struct dsa_bridge bridge) 2231 { 2232 /* port_stp_state_set() will be called after to put the port in 2233 * forwarding state so there is no need to do anything. 2234 */ 2235 } 2236 2237 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 2238 { 2239 struct ksz_device *dev = ds->priv; 2240 2241 dev->dev_ops->flush_dyn_mac_table(dev, port); 2242 } 2243 2244 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 2245 { 2246 struct ksz_device *dev = ds->priv; 2247 2248 if (!dev->dev_ops->set_ageing_time) 2249 return -EOPNOTSUPP; 2250 2251 return dev->dev_ops->set_ageing_time(dev, msecs); 2252 } 2253 2254 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 2255 const unsigned char *addr, u16 vid, 2256 struct dsa_db db) 2257 { 2258 struct ksz_device *dev = ds->priv; 2259 2260 if (!dev->dev_ops->fdb_add) 2261 return -EOPNOTSUPP; 2262 2263 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 2264 } 2265 2266 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 2267 const unsigned char *addr, 2268 u16 vid, struct dsa_db db) 2269 { 2270 struct ksz_device *dev = ds->priv; 2271 2272 if (!dev->dev_ops->fdb_del) 2273 return -EOPNOTSUPP; 2274 2275 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 2276 } 2277 2278 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 2279 dsa_fdb_dump_cb_t *cb, void *data) 2280 { 2281 struct ksz_device *dev = ds->priv; 2282 2283 if (!dev->dev_ops->fdb_dump) 2284 return -EOPNOTSUPP; 2285 2286 return dev->dev_ops->fdb_dump(dev, port, cb, data); 2287 } 2288 2289 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 2290 const struct switchdev_obj_port_mdb *mdb, 2291 struct dsa_db db) 2292 { 2293 struct ksz_device *dev = ds->priv; 2294 2295 if (!dev->dev_ops->mdb_add) 2296 return -EOPNOTSUPP; 2297 2298 return dev->dev_ops->mdb_add(dev, port, mdb, db); 2299 } 2300 2301 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 2302 const struct switchdev_obj_port_mdb *mdb, 2303 struct dsa_db db) 2304 { 2305 struct ksz_device *dev = ds->priv; 2306 2307 if (!dev->dev_ops->mdb_del) 2308 return -EOPNOTSUPP; 2309 2310 return dev->dev_ops->mdb_del(dev, port, mdb, db); 2311 } 2312 2313 static int ksz_enable_port(struct dsa_switch *ds, int port, 2314 struct phy_device *phy) 2315 { 2316 struct ksz_device *dev = ds->priv; 2317 2318 if (!dsa_is_user_port(ds, port)) 2319 return 0; 2320 2321 /* setup slave port */ 2322 dev->dev_ops->port_setup(dev, port, false); 2323 2324 /* port_stp_state_set() will be called after to enable the port so 2325 * there is no need to do anything. 2326 */ 2327 2328 return 0; 2329 } 2330 2331 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 2332 { 2333 struct ksz_device *dev = ds->priv; 2334 struct ksz_port *p; 2335 const u16 *regs; 2336 u8 data; 2337 2338 regs = dev->info->regs; 2339 2340 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 2341 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2342 2343 p = &dev->ports[port]; 2344 2345 switch (state) { 2346 case BR_STATE_DISABLED: 2347 data |= PORT_LEARN_DISABLE; 2348 break; 2349 case BR_STATE_LISTENING: 2350 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2351 break; 2352 case BR_STATE_LEARNING: 2353 data |= PORT_RX_ENABLE; 2354 if (!p->learning) 2355 data |= PORT_LEARN_DISABLE; 2356 break; 2357 case BR_STATE_FORWARDING: 2358 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 2359 if (!p->learning) 2360 data |= PORT_LEARN_DISABLE; 2361 break; 2362 case BR_STATE_BLOCKING: 2363 data |= PORT_LEARN_DISABLE; 2364 break; 2365 default: 2366 dev_err(ds->dev, "invalid STP state: %d\n", state); 2367 return; 2368 } 2369 2370 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 2371 2372 p->stp_state = state; 2373 2374 ksz_update_port_member(dev, port); 2375 } 2376 2377 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 2378 struct switchdev_brport_flags flags, 2379 struct netlink_ext_ack *extack) 2380 { 2381 if (flags.mask & ~BR_LEARNING) 2382 return -EINVAL; 2383 2384 return 0; 2385 } 2386 2387 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 2388 struct switchdev_brport_flags flags, 2389 struct netlink_ext_ack *extack) 2390 { 2391 struct ksz_device *dev = ds->priv; 2392 struct ksz_port *p = &dev->ports[port]; 2393 2394 if (flags.mask & BR_LEARNING) { 2395 p->learning = !!(flags.val & BR_LEARNING); 2396 2397 /* Make the change take effect immediately */ 2398 ksz_port_stp_state_set(ds, port, p->stp_state); 2399 } 2400 2401 return 0; 2402 } 2403 2404 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 2405 int port, 2406 enum dsa_tag_protocol mp) 2407 { 2408 struct ksz_device *dev = ds->priv; 2409 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 2410 2411 if (dev->chip_id == KSZ8795_CHIP_ID || 2412 dev->chip_id == KSZ8794_CHIP_ID || 2413 dev->chip_id == KSZ8765_CHIP_ID) 2414 proto = DSA_TAG_PROTO_KSZ8795; 2415 2416 if (dev->chip_id == KSZ8830_CHIP_ID || 2417 dev->chip_id == KSZ8563_CHIP_ID || 2418 dev->chip_id == KSZ9893_CHIP_ID || 2419 dev->chip_id == KSZ9563_CHIP_ID) 2420 proto = DSA_TAG_PROTO_KSZ9893; 2421 2422 if (dev->chip_id == KSZ9477_CHIP_ID || 2423 dev->chip_id == KSZ9896_CHIP_ID || 2424 dev->chip_id == KSZ9897_CHIP_ID || 2425 dev->chip_id == KSZ9567_CHIP_ID) 2426 proto = DSA_TAG_PROTO_KSZ9477; 2427 2428 if (is_lan937x(dev)) 2429 proto = DSA_TAG_PROTO_LAN937X_VALUE; 2430 2431 return proto; 2432 } 2433 2434 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 2435 bool flag, struct netlink_ext_ack *extack) 2436 { 2437 struct ksz_device *dev = ds->priv; 2438 2439 if (!dev->dev_ops->vlan_filtering) 2440 return -EOPNOTSUPP; 2441 2442 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 2443 } 2444 2445 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 2446 const struct switchdev_obj_port_vlan *vlan, 2447 struct netlink_ext_ack *extack) 2448 { 2449 struct ksz_device *dev = ds->priv; 2450 2451 if (!dev->dev_ops->vlan_add) 2452 return -EOPNOTSUPP; 2453 2454 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 2455 } 2456 2457 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 2458 const struct switchdev_obj_port_vlan *vlan) 2459 { 2460 struct ksz_device *dev = ds->priv; 2461 2462 if (!dev->dev_ops->vlan_del) 2463 return -EOPNOTSUPP; 2464 2465 return dev->dev_ops->vlan_del(dev, port, vlan); 2466 } 2467 2468 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 2469 struct dsa_mall_mirror_tc_entry *mirror, 2470 bool ingress, struct netlink_ext_ack *extack) 2471 { 2472 struct ksz_device *dev = ds->priv; 2473 2474 if (!dev->dev_ops->mirror_add) 2475 return -EOPNOTSUPP; 2476 2477 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 2478 } 2479 2480 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 2481 struct dsa_mall_mirror_tc_entry *mirror) 2482 { 2483 struct ksz_device *dev = ds->priv; 2484 2485 if (dev->dev_ops->mirror_del) 2486 dev->dev_ops->mirror_del(dev, port, mirror); 2487 } 2488 2489 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 2490 { 2491 struct ksz_device *dev = ds->priv; 2492 2493 if (!dev->dev_ops->change_mtu) 2494 return -EOPNOTSUPP; 2495 2496 return dev->dev_ops->change_mtu(dev, port, mtu); 2497 } 2498 2499 static int ksz_max_mtu(struct dsa_switch *ds, int port) 2500 { 2501 struct ksz_device *dev = ds->priv; 2502 2503 if (!dev->dev_ops->max_mtu) 2504 return -EOPNOTSUPP; 2505 2506 return dev->dev_ops->max_mtu(dev, port); 2507 } 2508 2509 static void ksz_set_xmii(struct ksz_device *dev, int port, 2510 phy_interface_t interface) 2511 { 2512 const u8 *bitval = dev->info->xmii_ctrl1; 2513 struct ksz_port *p = &dev->ports[port]; 2514 const u16 *regs = dev->info->regs; 2515 u8 data8; 2516 2517 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2518 2519 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 2520 P_RGMII_ID_EG_ENABLE); 2521 2522 switch (interface) { 2523 case PHY_INTERFACE_MODE_MII: 2524 data8 |= bitval[P_MII_SEL]; 2525 break; 2526 case PHY_INTERFACE_MODE_RMII: 2527 data8 |= bitval[P_RMII_SEL]; 2528 break; 2529 case PHY_INTERFACE_MODE_GMII: 2530 data8 |= bitval[P_GMII_SEL]; 2531 break; 2532 case PHY_INTERFACE_MODE_RGMII: 2533 case PHY_INTERFACE_MODE_RGMII_ID: 2534 case PHY_INTERFACE_MODE_RGMII_TXID: 2535 case PHY_INTERFACE_MODE_RGMII_RXID: 2536 data8 |= bitval[P_RGMII_SEL]; 2537 /* On KSZ9893, disable RGMII in-band status support */ 2538 if (dev->chip_id == KSZ9893_CHIP_ID || 2539 dev->chip_id == KSZ8563_CHIP_ID || 2540 dev->chip_id == KSZ9563_CHIP_ID) 2541 data8 &= ~P_MII_MAC_MODE; 2542 break; 2543 default: 2544 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 2545 phy_modes(interface), port); 2546 return; 2547 } 2548 2549 if (p->rgmii_tx_val) 2550 data8 |= P_RGMII_ID_EG_ENABLE; 2551 2552 if (p->rgmii_rx_val) 2553 data8 |= P_RGMII_ID_IG_ENABLE; 2554 2555 /* Write the updated value */ 2556 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 2557 } 2558 2559 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 2560 { 2561 const u8 *bitval = dev->info->xmii_ctrl1; 2562 const u16 *regs = dev->info->regs; 2563 phy_interface_t interface; 2564 u8 data8; 2565 u8 val; 2566 2567 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2568 2569 val = FIELD_GET(P_MII_SEL_M, data8); 2570 2571 if (val == bitval[P_MII_SEL]) { 2572 if (gbit) 2573 interface = PHY_INTERFACE_MODE_GMII; 2574 else 2575 interface = PHY_INTERFACE_MODE_MII; 2576 } else if (val == bitval[P_RMII_SEL]) { 2577 interface = PHY_INTERFACE_MODE_RGMII; 2578 } else { 2579 interface = PHY_INTERFACE_MODE_RGMII; 2580 if (data8 & P_RGMII_ID_EG_ENABLE) 2581 interface = PHY_INTERFACE_MODE_RGMII_TXID; 2582 if (data8 & P_RGMII_ID_IG_ENABLE) { 2583 interface = PHY_INTERFACE_MODE_RGMII_RXID; 2584 if (data8 & P_RGMII_ID_EG_ENABLE) 2585 interface = PHY_INTERFACE_MODE_RGMII_ID; 2586 } 2587 } 2588 2589 return interface; 2590 } 2591 2592 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port, 2593 unsigned int mode, 2594 const struct phylink_link_state *state) 2595 { 2596 struct ksz_device *dev = ds->priv; 2597 2598 if (ksz_is_ksz88x3(dev)) 2599 return; 2600 2601 /* Internal PHYs */ 2602 if (dev->info->internal_phy[port]) 2603 return; 2604 2605 if (phylink_autoneg_inband(mode)) { 2606 dev_err(dev->dev, "In-band AN not supported!\n"); 2607 return; 2608 } 2609 2610 ksz_set_xmii(dev, port, state->interface); 2611 2612 if (dev->dev_ops->phylink_mac_config) 2613 dev->dev_ops->phylink_mac_config(dev, port, mode, state); 2614 2615 if (dev->dev_ops->setup_rgmii_delay) 2616 dev->dev_ops->setup_rgmii_delay(dev, port); 2617 } 2618 2619 bool ksz_get_gbit(struct ksz_device *dev, int port) 2620 { 2621 const u8 *bitval = dev->info->xmii_ctrl1; 2622 const u16 *regs = dev->info->regs; 2623 bool gbit = false; 2624 u8 data8; 2625 bool val; 2626 2627 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2628 2629 val = FIELD_GET(P_GMII_1GBIT_M, data8); 2630 2631 if (val == bitval[P_GMII_1GBIT]) 2632 gbit = true; 2633 2634 return gbit; 2635 } 2636 2637 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) 2638 { 2639 const u8 *bitval = dev->info->xmii_ctrl1; 2640 const u16 *regs = dev->info->regs; 2641 u8 data8; 2642 2643 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2644 2645 data8 &= ~P_GMII_1GBIT_M; 2646 2647 if (gbit) 2648 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 2649 else 2650 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 2651 2652 /* Write the updated value */ 2653 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 2654 } 2655 2656 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) 2657 { 2658 const u8 *bitval = dev->info->xmii_ctrl0; 2659 const u16 *regs = dev->info->regs; 2660 u8 data8; 2661 2662 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 2663 2664 data8 &= ~P_MII_100MBIT_M; 2665 2666 if (speed == SPEED_100) 2667 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 2668 else 2669 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 2670 2671 /* Write the updated value */ 2672 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 2673 } 2674 2675 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) 2676 { 2677 if (speed == SPEED_1000) 2678 ksz_set_gbit(dev, port, true); 2679 else 2680 ksz_set_gbit(dev, port, false); 2681 2682 if (speed == SPEED_100 || speed == SPEED_10) 2683 ksz_set_100_10mbit(dev, port, speed); 2684 } 2685 2686 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 2687 bool tx_pause, bool rx_pause) 2688 { 2689 const u8 *bitval = dev->info->xmii_ctrl0; 2690 const u32 *masks = dev->info->masks; 2691 const u16 *regs = dev->info->regs; 2692 u8 mask; 2693 u8 val; 2694 2695 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 2696 masks[P_MII_RX_FLOW_CTRL]; 2697 2698 if (duplex == DUPLEX_FULL) 2699 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 2700 else 2701 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 2702 2703 if (tx_pause) 2704 val |= masks[P_MII_TX_FLOW_CTRL]; 2705 2706 if (rx_pause) 2707 val |= masks[P_MII_RX_FLOW_CTRL]; 2708 2709 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 2710 } 2711 2712 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, 2713 unsigned int mode, 2714 phy_interface_t interface, 2715 struct phy_device *phydev, int speed, 2716 int duplex, bool tx_pause, 2717 bool rx_pause) 2718 { 2719 struct ksz_port *p; 2720 2721 p = &dev->ports[port]; 2722 2723 /* Internal PHYs */ 2724 if (dev->info->internal_phy[port]) 2725 return; 2726 2727 p->phydev.speed = speed; 2728 2729 ksz_port_set_xmii_speed(dev, port, speed); 2730 2731 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 2732 } 2733 2734 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port, 2735 unsigned int mode, 2736 phy_interface_t interface, 2737 struct phy_device *phydev, int speed, 2738 int duplex, bool tx_pause, bool rx_pause) 2739 { 2740 struct ksz_device *dev = ds->priv; 2741 2742 if (dev->dev_ops->phylink_mac_link_up) 2743 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface, 2744 phydev, speed, duplex, 2745 tx_pause, rx_pause); 2746 } 2747 2748 static int ksz_switch_detect(struct ksz_device *dev) 2749 { 2750 u8 id1, id2, id4; 2751 u16 id16; 2752 u32 id32; 2753 int ret; 2754 2755 /* read chip id */ 2756 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 2757 if (ret) 2758 return ret; 2759 2760 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 2761 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 2762 2763 switch (id1) { 2764 case KSZ87_FAMILY_ID: 2765 if (id2 == KSZ87_CHIP_ID_95) { 2766 u8 val; 2767 2768 dev->chip_id = KSZ8795_CHIP_ID; 2769 2770 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 2771 if (val & KSZ8_PORT_FIBER_MODE) 2772 dev->chip_id = KSZ8765_CHIP_ID; 2773 } else if (id2 == KSZ87_CHIP_ID_94) { 2774 dev->chip_id = KSZ8794_CHIP_ID; 2775 } else { 2776 return -ENODEV; 2777 } 2778 break; 2779 case KSZ88_FAMILY_ID: 2780 if (id2 == KSZ88_CHIP_ID_63) 2781 dev->chip_id = KSZ8830_CHIP_ID; 2782 else 2783 return -ENODEV; 2784 break; 2785 default: 2786 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 2787 if (ret) 2788 return ret; 2789 2790 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 2791 id32 &= ~0xFF; 2792 2793 switch (id32) { 2794 case KSZ9477_CHIP_ID: 2795 case KSZ9896_CHIP_ID: 2796 case KSZ9897_CHIP_ID: 2797 case KSZ9567_CHIP_ID: 2798 case LAN9370_CHIP_ID: 2799 case LAN9371_CHIP_ID: 2800 case LAN9372_CHIP_ID: 2801 case LAN9373_CHIP_ID: 2802 case LAN9374_CHIP_ID: 2803 dev->chip_id = id32; 2804 break; 2805 case KSZ9893_CHIP_ID: 2806 ret = ksz_read8(dev, REG_CHIP_ID4, 2807 &id4); 2808 if (ret) 2809 return ret; 2810 2811 if (id4 == SKU_ID_KSZ8563) 2812 dev->chip_id = KSZ8563_CHIP_ID; 2813 else if (id4 == SKU_ID_KSZ9563) 2814 dev->chip_id = KSZ9563_CHIP_ID; 2815 else 2816 dev->chip_id = KSZ9893_CHIP_ID; 2817 2818 break; 2819 default: 2820 dev_err(dev->dev, 2821 "unsupported switch detected %x)\n", id32); 2822 return -ENODEV; 2823 } 2824 } 2825 return 0; 2826 } 2827 2828 static const struct dsa_switch_ops ksz_switch_ops = { 2829 .get_tag_protocol = ksz_get_tag_protocol, 2830 .get_phy_flags = ksz_get_phy_flags, 2831 .setup = ksz_setup, 2832 .teardown = ksz_teardown, 2833 .phy_read = ksz_phy_read16, 2834 .phy_write = ksz_phy_write16, 2835 .phylink_get_caps = ksz_phylink_get_caps, 2836 .phylink_mac_config = ksz_phylink_mac_config, 2837 .phylink_mac_link_up = ksz_phylink_mac_link_up, 2838 .phylink_mac_link_down = ksz_mac_link_down, 2839 .port_enable = ksz_enable_port, 2840 .set_ageing_time = ksz_set_ageing_time, 2841 .get_strings = ksz_get_strings, 2842 .get_ethtool_stats = ksz_get_ethtool_stats, 2843 .get_sset_count = ksz_sset_count, 2844 .port_bridge_join = ksz_port_bridge_join, 2845 .port_bridge_leave = ksz_port_bridge_leave, 2846 .port_stp_state_set = ksz_port_stp_state_set, 2847 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 2848 .port_bridge_flags = ksz_port_bridge_flags, 2849 .port_fast_age = ksz_port_fast_age, 2850 .port_vlan_filtering = ksz_port_vlan_filtering, 2851 .port_vlan_add = ksz_port_vlan_add, 2852 .port_vlan_del = ksz_port_vlan_del, 2853 .port_fdb_dump = ksz_port_fdb_dump, 2854 .port_fdb_add = ksz_port_fdb_add, 2855 .port_fdb_del = ksz_port_fdb_del, 2856 .port_mdb_add = ksz_port_mdb_add, 2857 .port_mdb_del = ksz_port_mdb_del, 2858 .port_mirror_add = ksz_port_mirror_add, 2859 .port_mirror_del = ksz_port_mirror_del, 2860 .get_stats64 = ksz_get_stats64, 2861 .get_pause_stats = ksz_get_pause_stats, 2862 .port_change_mtu = ksz_change_mtu, 2863 .port_max_mtu = ksz_max_mtu, 2864 }; 2865 2866 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 2867 { 2868 struct dsa_switch *ds; 2869 struct ksz_device *swdev; 2870 2871 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 2872 if (!ds) 2873 return NULL; 2874 2875 ds->dev = base; 2876 ds->num_ports = DSA_MAX_PORTS; 2877 ds->ops = &ksz_switch_ops; 2878 2879 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 2880 if (!swdev) 2881 return NULL; 2882 2883 ds->priv = swdev; 2884 swdev->dev = base; 2885 2886 swdev->ds = ds; 2887 swdev->priv = priv; 2888 2889 return swdev; 2890 } 2891 EXPORT_SYMBOL(ksz_switch_alloc); 2892 2893 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 2894 struct device_node *port_dn) 2895 { 2896 phy_interface_t phy_mode = dev->ports[port_num].interface; 2897 int rx_delay = -1, tx_delay = -1; 2898 2899 if (!phy_interface_mode_is_rgmii(phy_mode)) 2900 return; 2901 2902 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 2903 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 2904 2905 if (rx_delay == -1 && tx_delay == -1) { 2906 dev_warn(dev->dev, 2907 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 2908 "please update device tree to specify \"rx-internal-delay-ps\" and " 2909 "\"tx-internal-delay-ps\"", 2910 port_num); 2911 2912 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 2913 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 2914 rx_delay = 2000; 2915 2916 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 2917 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 2918 tx_delay = 2000; 2919 } 2920 2921 if (rx_delay < 0) 2922 rx_delay = 0; 2923 if (tx_delay < 0) 2924 tx_delay = 0; 2925 2926 dev->ports[port_num].rgmii_rx_val = rx_delay; 2927 dev->ports[port_num].rgmii_tx_val = tx_delay; 2928 } 2929 2930 int ksz_switch_register(struct ksz_device *dev) 2931 { 2932 const struct ksz_chip_data *info; 2933 struct device_node *port, *ports; 2934 phy_interface_t interface; 2935 unsigned int port_num; 2936 int ret; 2937 int i; 2938 2939 if (dev->pdata) 2940 dev->chip_id = dev->pdata->chip_id; 2941 2942 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 2943 GPIOD_OUT_LOW); 2944 if (IS_ERR(dev->reset_gpio)) 2945 return PTR_ERR(dev->reset_gpio); 2946 2947 if (dev->reset_gpio) { 2948 gpiod_set_value_cansleep(dev->reset_gpio, 1); 2949 usleep_range(10000, 12000); 2950 gpiod_set_value_cansleep(dev->reset_gpio, 0); 2951 msleep(100); 2952 } 2953 2954 mutex_init(&dev->dev_mutex); 2955 mutex_init(&dev->regmap_mutex); 2956 mutex_init(&dev->alu_mutex); 2957 mutex_init(&dev->vlan_mutex); 2958 2959 ret = ksz_switch_detect(dev); 2960 if (ret) 2961 return ret; 2962 2963 info = ksz_lookup_info(dev->chip_id); 2964 if (!info) 2965 return -ENODEV; 2966 2967 /* Update the compatible info with the probed one */ 2968 dev->info = info; 2969 2970 dev_info(dev->dev, "found switch: %s, rev %i\n", 2971 dev->info->dev_name, dev->chip_rev); 2972 2973 ret = ksz_check_device_id(dev); 2974 if (ret) 2975 return ret; 2976 2977 dev->dev_ops = dev->info->ops; 2978 2979 ret = dev->dev_ops->init(dev); 2980 if (ret) 2981 return ret; 2982 2983 dev->ports = devm_kzalloc(dev->dev, 2984 dev->info->port_cnt * sizeof(struct ksz_port), 2985 GFP_KERNEL); 2986 if (!dev->ports) 2987 return -ENOMEM; 2988 2989 for (i = 0; i < dev->info->port_cnt; i++) { 2990 spin_lock_init(&dev->ports[i].mib.stats64_lock); 2991 mutex_init(&dev->ports[i].mib.cnt_mutex); 2992 dev->ports[i].mib.counters = 2993 devm_kzalloc(dev->dev, 2994 sizeof(u64) * (dev->info->mib_cnt + 1), 2995 GFP_KERNEL); 2996 if (!dev->ports[i].mib.counters) 2997 return -ENOMEM; 2998 2999 dev->ports[i].ksz_dev = dev; 3000 dev->ports[i].num = i; 3001 } 3002 3003 /* set the real number of ports */ 3004 dev->ds->num_ports = dev->info->port_cnt; 3005 3006 /* Host port interface will be self detected, or specifically set in 3007 * device tree. 3008 */ 3009 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 3010 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 3011 if (dev->dev->of_node) { 3012 ret = of_get_phy_mode(dev->dev->of_node, &interface); 3013 if (ret == 0) 3014 dev->compat_interface = interface; 3015 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 3016 if (!ports) 3017 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 3018 if (ports) { 3019 for_each_available_child_of_node(ports, port) { 3020 if (of_property_read_u32(port, "reg", 3021 &port_num)) 3022 continue; 3023 if (!(dev->port_mask & BIT(port_num))) { 3024 of_node_put(port); 3025 of_node_put(ports); 3026 return -EINVAL; 3027 } 3028 of_get_phy_mode(port, 3029 &dev->ports[port_num].interface); 3030 3031 ksz_parse_rgmii_delay(dev, port_num, port); 3032 } 3033 of_node_put(ports); 3034 } 3035 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 3036 "microchip,synclko-125"); 3037 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 3038 "microchip,synclko-disable"); 3039 if (dev->synclko_125 && dev->synclko_disable) { 3040 dev_err(dev->dev, "inconsistent synclko settings\n"); 3041 return -EINVAL; 3042 } 3043 } 3044 3045 ret = dsa_register_switch(dev->ds); 3046 if (ret) { 3047 dev->dev_ops->exit(dev); 3048 return ret; 3049 } 3050 3051 /* Read MIB counters every 30 seconds to avoid overflow. */ 3052 dev->mib_read_interval = msecs_to_jiffies(5000); 3053 3054 /* Start the MIB timer. */ 3055 schedule_delayed_work(&dev->mib_read, 0); 3056 3057 return ret; 3058 } 3059 EXPORT_SYMBOL(ksz_switch_register); 3060 3061 void ksz_switch_remove(struct ksz_device *dev) 3062 { 3063 /* timer started */ 3064 if (dev->mib_read_interval) { 3065 dev->mib_read_interval = 0; 3066 cancel_delayed_work_sync(&dev->mib_read); 3067 } 3068 3069 dev->dev_ops->exit(dev); 3070 dsa_unregister_switch(dev->ds); 3071 3072 if (dev->reset_gpio) 3073 gpiod_set_value_cansleep(dev->reset_gpio, 1); 3074 3075 } 3076 EXPORT_SYMBOL(ksz_switch_remove); 3077 3078 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 3079 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 3080 MODULE_LICENSE("GPL"); 3081