1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/dsa/ksz_common.h> 10 #include <linux/export.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/platform_data/microchip-ksz.h> 15 #include <linux/phy.h> 16 #include <linux/etherdevice.h> 17 #include <linux/if_bridge.h> 18 #include <linux/if_vlan.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/of.h> 22 #include <linux/of_mdio.h> 23 #include <linux/of_net.h> 24 #include <linux/micrel_phy.h> 25 #include <net/dsa.h> 26 #include <net/pkt_cls.h> 27 #include <net/switchdev.h> 28 29 #include "ksz_common.h" 30 #include "ksz_ptp.h" 31 #include "ksz8.h" 32 #include "ksz9477.h" 33 #include "lan937x.h" 34 35 #define MIB_COUNTER_NUM 0x20 36 37 struct ksz_stats_raw { 38 u64 rx_hi; 39 u64 rx_undersize; 40 u64 rx_fragments; 41 u64 rx_oversize; 42 u64 rx_jabbers; 43 u64 rx_symbol_err; 44 u64 rx_crc_err; 45 u64 rx_align_err; 46 u64 rx_mac_ctrl; 47 u64 rx_pause; 48 u64 rx_bcast; 49 u64 rx_mcast; 50 u64 rx_ucast; 51 u64 rx_64_or_less; 52 u64 rx_65_127; 53 u64 rx_128_255; 54 u64 rx_256_511; 55 u64 rx_512_1023; 56 u64 rx_1024_1522; 57 u64 rx_1523_2000; 58 u64 rx_2001; 59 u64 tx_hi; 60 u64 tx_late_col; 61 u64 tx_pause; 62 u64 tx_bcast; 63 u64 tx_mcast; 64 u64 tx_ucast; 65 u64 tx_deferred; 66 u64 tx_total_col; 67 u64 tx_exc_col; 68 u64 tx_single_col; 69 u64 tx_mult_col; 70 u64 rx_total; 71 u64 tx_total; 72 u64 rx_discards; 73 u64 tx_discards; 74 }; 75 76 struct ksz88xx_stats_raw { 77 u64 rx; 78 u64 rx_hi; 79 u64 rx_undersize; 80 u64 rx_fragments; 81 u64 rx_oversize; 82 u64 rx_jabbers; 83 u64 rx_symbol_err; 84 u64 rx_crc_err; 85 u64 rx_align_err; 86 u64 rx_mac_ctrl; 87 u64 rx_pause; 88 u64 rx_bcast; 89 u64 rx_mcast; 90 u64 rx_ucast; 91 u64 rx_64_or_less; 92 u64 rx_65_127; 93 u64 rx_128_255; 94 u64 rx_256_511; 95 u64 rx_512_1023; 96 u64 rx_1024_1522; 97 u64 tx; 98 u64 tx_hi; 99 u64 tx_late_col; 100 u64 tx_pause; 101 u64 tx_bcast; 102 u64 tx_mcast; 103 u64 tx_ucast; 104 u64 tx_deferred; 105 u64 tx_total_col; 106 u64 tx_exc_col; 107 u64 tx_single_col; 108 u64 tx_mult_col; 109 u64 rx_discards; 110 u64 tx_discards; 111 }; 112 113 static const struct ksz_mib_names ksz88xx_mib_names[] = { 114 { 0x00, "rx" }, 115 { 0x01, "rx_hi" }, 116 { 0x02, "rx_undersize" }, 117 { 0x03, "rx_fragments" }, 118 { 0x04, "rx_oversize" }, 119 { 0x05, "rx_jabbers" }, 120 { 0x06, "rx_symbol_err" }, 121 { 0x07, "rx_crc_err" }, 122 { 0x08, "rx_align_err" }, 123 { 0x09, "rx_mac_ctrl" }, 124 { 0x0a, "rx_pause" }, 125 { 0x0b, "rx_bcast" }, 126 { 0x0c, "rx_mcast" }, 127 { 0x0d, "rx_ucast" }, 128 { 0x0e, "rx_64_or_less" }, 129 { 0x0f, "rx_65_127" }, 130 { 0x10, "rx_128_255" }, 131 { 0x11, "rx_256_511" }, 132 { 0x12, "rx_512_1023" }, 133 { 0x13, "rx_1024_1522" }, 134 { 0x14, "tx" }, 135 { 0x15, "tx_hi" }, 136 { 0x16, "tx_late_col" }, 137 { 0x17, "tx_pause" }, 138 { 0x18, "tx_bcast" }, 139 { 0x19, "tx_mcast" }, 140 { 0x1a, "tx_ucast" }, 141 { 0x1b, "tx_deferred" }, 142 { 0x1c, "tx_total_col" }, 143 { 0x1d, "tx_exc_col" }, 144 { 0x1e, "tx_single_col" }, 145 { 0x1f, "tx_mult_col" }, 146 { 0x100, "rx_discards" }, 147 { 0x101, "tx_discards" }, 148 }; 149 150 static const struct ksz_mib_names ksz9477_mib_names[] = { 151 { 0x00, "rx_hi" }, 152 { 0x01, "rx_undersize" }, 153 { 0x02, "rx_fragments" }, 154 { 0x03, "rx_oversize" }, 155 { 0x04, "rx_jabbers" }, 156 { 0x05, "rx_symbol_err" }, 157 { 0x06, "rx_crc_err" }, 158 { 0x07, "rx_align_err" }, 159 { 0x08, "rx_mac_ctrl" }, 160 { 0x09, "rx_pause" }, 161 { 0x0A, "rx_bcast" }, 162 { 0x0B, "rx_mcast" }, 163 { 0x0C, "rx_ucast" }, 164 { 0x0D, "rx_64_or_less" }, 165 { 0x0E, "rx_65_127" }, 166 { 0x0F, "rx_128_255" }, 167 { 0x10, "rx_256_511" }, 168 { 0x11, "rx_512_1023" }, 169 { 0x12, "rx_1024_1522" }, 170 { 0x13, "rx_1523_2000" }, 171 { 0x14, "rx_2001" }, 172 { 0x15, "tx_hi" }, 173 { 0x16, "tx_late_col" }, 174 { 0x17, "tx_pause" }, 175 { 0x18, "tx_bcast" }, 176 { 0x19, "tx_mcast" }, 177 { 0x1A, "tx_ucast" }, 178 { 0x1B, "tx_deferred" }, 179 { 0x1C, "tx_total_col" }, 180 { 0x1D, "tx_exc_col" }, 181 { 0x1E, "tx_single_col" }, 182 { 0x1F, "tx_mult_col" }, 183 { 0x80, "rx_total" }, 184 { 0x81, "tx_total" }, 185 { 0x82, "rx_discards" }, 186 { 0x83, "tx_discards" }, 187 }; 188 189 static const struct ksz_dev_ops ksz8_dev_ops = { 190 .setup = ksz8_setup, 191 .get_port_addr = ksz8_get_port_addr, 192 .cfg_port_member = ksz8_cfg_port_member, 193 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 194 .port_setup = ksz8_port_setup, 195 .r_phy = ksz8_r_phy, 196 .w_phy = ksz8_w_phy, 197 .r_mib_cnt = ksz8_r_mib_cnt, 198 .r_mib_pkt = ksz8_r_mib_pkt, 199 .r_mib_stat64 = ksz88xx_r_mib_stats64, 200 .freeze_mib = ksz8_freeze_mib, 201 .port_init_cnt = ksz8_port_init_cnt, 202 .fdb_dump = ksz8_fdb_dump, 203 .fdb_add = ksz8_fdb_add, 204 .fdb_del = ksz8_fdb_del, 205 .mdb_add = ksz8_mdb_add, 206 .mdb_del = ksz8_mdb_del, 207 .vlan_filtering = ksz8_port_vlan_filtering, 208 .vlan_add = ksz8_port_vlan_add, 209 .vlan_del = ksz8_port_vlan_del, 210 .mirror_add = ksz8_port_mirror_add, 211 .mirror_del = ksz8_port_mirror_del, 212 .get_caps = ksz8_get_caps, 213 .config_cpu_port = ksz8_config_cpu_port, 214 .enable_stp_addr = ksz8_enable_stp_addr, 215 .reset = ksz8_reset_switch, 216 .init = ksz8_switch_init, 217 .exit = ksz8_switch_exit, 218 .change_mtu = ksz8_change_mtu, 219 }; 220 221 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, 222 unsigned int mode, 223 phy_interface_t interface, 224 struct phy_device *phydev, int speed, 225 int duplex, bool tx_pause, 226 bool rx_pause); 227 228 static const struct ksz_dev_ops ksz9477_dev_ops = { 229 .setup = ksz9477_setup, 230 .get_port_addr = ksz9477_get_port_addr, 231 .cfg_port_member = ksz9477_cfg_port_member, 232 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 233 .port_setup = ksz9477_port_setup, 234 .set_ageing_time = ksz9477_set_ageing_time, 235 .r_phy = ksz9477_r_phy, 236 .w_phy = ksz9477_w_phy, 237 .r_mib_cnt = ksz9477_r_mib_cnt, 238 .r_mib_pkt = ksz9477_r_mib_pkt, 239 .r_mib_stat64 = ksz_r_mib_stats64, 240 .freeze_mib = ksz9477_freeze_mib, 241 .port_init_cnt = ksz9477_port_init_cnt, 242 .vlan_filtering = ksz9477_port_vlan_filtering, 243 .vlan_add = ksz9477_port_vlan_add, 244 .vlan_del = ksz9477_port_vlan_del, 245 .mirror_add = ksz9477_port_mirror_add, 246 .mirror_del = ksz9477_port_mirror_del, 247 .get_caps = ksz9477_get_caps, 248 .fdb_dump = ksz9477_fdb_dump, 249 .fdb_add = ksz9477_fdb_add, 250 .fdb_del = ksz9477_fdb_del, 251 .mdb_add = ksz9477_mdb_add, 252 .mdb_del = ksz9477_mdb_del, 253 .change_mtu = ksz9477_change_mtu, 254 .phylink_mac_link_up = ksz9477_phylink_mac_link_up, 255 .config_cpu_port = ksz9477_config_cpu_port, 256 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc, 257 .enable_stp_addr = ksz9477_enable_stp_addr, 258 .reset = ksz9477_reset_switch, 259 .init = ksz9477_switch_init, 260 .exit = ksz9477_switch_exit, 261 }; 262 263 static const struct ksz_dev_ops lan937x_dev_ops = { 264 .setup = lan937x_setup, 265 .teardown = lan937x_teardown, 266 .get_port_addr = ksz9477_get_port_addr, 267 .cfg_port_member = ksz9477_cfg_port_member, 268 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 269 .port_setup = lan937x_port_setup, 270 .set_ageing_time = lan937x_set_ageing_time, 271 .r_phy = lan937x_r_phy, 272 .w_phy = lan937x_w_phy, 273 .r_mib_cnt = ksz9477_r_mib_cnt, 274 .r_mib_pkt = ksz9477_r_mib_pkt, 275 .r_mib_stat64 = ksz_r_mib_stats64, 276 .freeze_mib = ksz9477_freeze_mib, 277 .port_init_cnt = ksz9477_port_init_cnt, 278 .vlan_filtering = ksz9477_port_vlan_filtering, 279 .vlan_add = ksz9477_port_vlan_add, 280 .vlan_del = ksz9477_port_vlan_del, 281 .mirror_add = ksz9477_port_mirror_add, 282 .mirror_del = ksz9477_port_mirror_del, 283 .get_caps = lan937x_phylink_get_caps, 284 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 285 .fdb_dump = ksz9477_fdb_dump, 286 .fdb_add = ksz9477_fdb_add, 287 .fdb_del = ksz9477_fdb_del, 288 .mdb_add = ksz9477_mdb_add, 289 .mdb_del = ksz9477_mdb_del, 290 .change_mtu = lan937x_change_mtu, 291 .phylink_mac_link_up = ksz9477_phylink_mac_link_up, 292 .config_cpu_port = lan937x_config_cpu_port, 293 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc, 294 .enable_stp_addr = ksz9477_enable_stp_addr, 295 .reset = lan937x_reset_switch, 296 .init = lan937x_switch_init, 297 .exit = lan937x_switch_exit, 298 }; 299 300 static const u16 ksz8795_regs[] = { 301 [REG_IND_CTRL_0] = 0x6E, 302 [REG_IND_DATA_8] = 0x70, 303 [REG_IND_DATA_CHECK] = 0x72, 304 [REG_IND_DATA_HI] = 0x71, 305 [REG_IND_DATA_LO] = 0x75, 306 [REG_IND_MIB_CHECK] = 0x74, 307 [REG_IND_BYTE] = 0xA0, 308 [P_FORCE_CTRL] = 0x0C, 309 [P_LINK_STATUS] = 0x0E, 310 [P_LOCAL_CTRL] = 0x07, 311 [P_NEG_RESTART_CTRL] = 0x0D, 312 [P_REMOTE_STATUS] = 0x08, 313 [P_SPEED_STATUS] = 0x09, 314 [S_TAIL_TAG_CTRL] = 0x0C, 315 [P_STP_CTRL] = 0x02, 316 [S_START_CTRL] = 0x01, 317 [S_BROADCAST_CTRL] = 0x06, 318 [S_MULTICAST_CTRL] = 0x04, 319 [P_XMII_CTRL_0] = 0x06, 320 [P_XMII_CTRL_1] = 0x06, 321 }; 322 323 static const u32 ksz8795_masks[] = { 324 [PORT_802_1P_REMAPPING] = BIT(7), 325 [SW_TAIL_TAG_ENABLE] = BIT(1), 326 [MIB_COUNTER_OVERFLOW] = BIT(6), 327 [MIB_COUNTER_VALID] = BIT(5), 328 [VLAN_TABLE_FID] = GENMASK(6, 0), 329 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 330 [VLAN_TABLE_VALID] = BIT(12), 331 [STATIC_MAC_TABLE_VALID] = BIT(21), 332 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 333 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 334 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 335 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 336 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 337 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 338 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 339 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 340 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 341 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 342 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 343 [P_MII_TX_FLOW_CTRL] = BIT(5), 344 [P_MII_RX_FLOW_CTRL] = BIT(5), 345 }; 346 347 static const u8 ksz8795_xmii_ctrl0[] = { 348 [P_MII_100MBIT] = 0, 349 [P_MII_10MBIT] = 1, 350 [P_MII_FULL_DUPLEX] = 0, 351 [P_MII_HALF_DUPLEX] = 1, 352 }; 353 354 static const u8 ksz8795_xmii_ctrl1[] = { 355 [P_RGMII_SEL] = 3, 356 [P_GMII_SEL] = 2, 357 [P_RMII_SEL] = 1, 358 [P_MII_SEL] = 0, 359 [P_GMII_1GBIT] = 1, 360 [P_GMII_NOT_1GBIT] = 0, 361 }; 362 363 static const u8 ksz8795_shifts[] = { 364 [VLAN_TABLE_MEMBERSHIP_S] = 7, 365 [VLAN_TABLE] = 16, 366 [STATIC_MAC_FWD_PORTS] = 16, 367 [STATIC_MAC_FID] = 24, 368 [DYNAMIC_MAC_ENTRIES_H] = 3, 369 [DYNAMIC_MAC_ENTRIES] = 29, 370 [DYNAMIC_MAC_FID] = 16, 371 [DYNAMIC_MAC_TIMESTAMP] = 27, 372 [DYNAMIC_MAC_SRC_PORT] = 24, 373 }; 374 375 static const u16 ksz8863_regs[] = { 376 [REG_IND_CTRL_0] = 0x79, 377 [REG_IND_DATA_8] = 0x7B, 378 [REG_IND_DATA_CHECK] = 0x7B, 379 [REG_IND_DATA_HI] = 0x7C, 380 [REG_IND_DATA_LO] = 0x80, 381 [REG_IND_MIB_CHECK] = 0x80, 382 [P_FORCE_CTRL] = 0x0C, 383 [P_LINK_STATUS] = 0x0E, 384 [P_LOCAL_CTRL] = 0x0C, 385 [P_NEG_RESTART_CTRL] = 0x0D, 386 [P_REMOTE_STATUS] = 0x0E, 387 [P_SPEED_STATUS] = 0x0F, 388 [S_TAIL_TAG_CTRL] = 0x03, 389 [P_STP_CTRL] = 0x02, 390 [S_START_CTRL] = 0x01, 391 [S_BROADCAST_CTRL] = 0x06, 392 [S_MULTICAST_CTRL] = 0x04, 393 }; 394 395 static const u32 ksz8863_masks[] = { 396 [PORT_802_1P_REMAPPING] = BIT(3), 397 [SW_TAIL_TAG_ENABLE] = BIT(6), 398 [MIB_COUNTER_OVERFLOW] = BIT(7), 399 [MIB_COUNTER_VALID] = BIT(6), 400 [VLAN_TABLE_FID] = GENMASK(15, 12), 401 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 402 [VLAN_TABLE_VALID] = BIT(19), 403 [STATIC_MAC_TABLE_VALID] = BIT(19), 404 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 405 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), 406 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 407 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 408 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), 409 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), 410 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 411 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), 412 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 413 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 414 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 415 }; 416 417 static u8 ksz8863_shifts[] = { 418 [VLAN_TABLE_MEMBERSHIP_S] = 16, 419 [STATIC_MAC_FWD_PORTS] = 16, 420 [STATIC_MAC_FID] = 22, 421 [DYNAMIC_MAC_ENTRIES_H] = 8, 422 [DYNAMIC_MAC_ENTRIES] = 24, 423 [DYNAMIC_MAC_FID] = 16, 424 [DYNAMIC_MAC_TIMESTAMP] = 22, 425 [DYNAMIC_MAC_SRC_PORT] = 20, 426 }; 427 428 static const u16 ksz9477_regs[] = { 429 [P_STP_CTRL] = 0x0B04, 430 [S_START_CTRL] = 0x0300, 431 [S_BROADCAST_CTRL] = 0x0332, 432 [S_MULTICAST_CTRL] = 0x0331, 433 [P_XMII_CTRL_0] = 0x0300, 434 [P_XMII_CTRL_1] = 0x0301, 435 }; 436 437 static const u32 ksz9477_masks[] = { 438 [ALU_STAT_WRITE] = 0, 439 [ALU_STAT_READ] = 1, 440 [P_MII_TX_FLOW_CTRL] = BIT(5), 441 [P_MII_RX_FLOW_CTRL] = BIT(3), 442 }; 443 444 static const u8 ksz9477_shifts[] = { 445 [ALU_STAT_INDEX] = 16, 446 }; 447 448 static const u8 ksz9477_xmii_ctrl0[] = { 449 [P_MII_100MBIT] = 1, 450 [P_MII_10MBIT] = 0, 451 [P_MII_FULL_DUPLEX] = 1, 452 [P_MII_HALF_DUPLEX] = 0, 453 }; 454 455 static const u8 ksz9477_xmii_ctrl1[] = { 456 [P_RGMII_SEL] = 0, 457 [P_RMII_SEL] = 1, 458 [P_GMII_SEL] = 2, 459 [P_MII_SEL] = 3, 460 [P_GMII_1GBIT] = 0, 461 [P_GMII_NOT_1GBIT] = 1, 462 }; 463 464 static const u32 lan937x_masks[] = { 465 [ALU_STAT_WRITE] = 1, 466 [ALU_STAT_READ] = 2, 467 [P_MII_TX_FLOW_CTRL] = BIT(5), 468 [P_MII_RX_FLOW_CTRL] = BIT(3), 469 }; 470 471 static const u8 lan937x_shifts[] = { 472 [ALU_STAT_INDEX] = 8, 473 }; 474 475 static const struct regmap_range ksz8563_valid_regs[] = { 476 regmap_reg_range(0x0000, 0x0003), 477 regmap_reg_range(0x0006, 0x0006), 478 regmap_reg_range(0x000f, 0x001f), 479 regmap_reg_range(0x0100, 0x0100), 480 regmap_reg_range(0x0104, 0x0107), 481 regmap_reg_range(0x010d, 0x010d), 482 regmap_reg_range(0x0110, 0x0113), 483 regmap_reg_range(0x0120, 0x012b), 484 regmap_reg_range(0x0201, 0x0201), 485 regmap_reg_range(0x0210, 0x0213), 486 regmap_reg_range(0x0300, 0x0300), 487 regmap_reg_range(0x0302, 0x031b), 488 regmap_reg_range(0x0320, 0x032b), 489 regmap_reg_range(0x0330, 0x0336), 490 regmap_reg_range(0x0338, 0x033e), 491 regmap_reg_range(0x0340, 0x035f), 492 regmap_reg_range(0x0370, 0x0370), 493 regmap_reg_range(0x0378, 0x0378), 494 regmap_reg_range(0x037c, 0x037d), 495 regmap_reg_range(0x0390, 0x0393), 496 regmap_reg_range(0x0400, 0x040e), 497 regmap_reg_range(0x0410, 0x042f), 498 regmap_reg_range(0x0500, 0x0519), 499 regmap_reg_range(0x0520, 0x054b), 500 regmap_reg_range(0x0550, 0x05b3), 501 502 /* port 1 */ 503 regmap_reg_range(0x1000, 0x1001), 504 regmap_reg_range(0x1004, 0x100b), 505 regmap_reg_range(0x1013, 0x1013), 506 regmap_reg_range(0x1017, 0x1017), 507 regmap_reg_range(0x101b, 0x101b), 508 regmap_reg_range(0x101f, 0x1021), 509 regmap_reg_range(0x1030, 0x1030), 510 regmap_reg_range(0x1100, 0x1111), 511 regmap_reg_range(0x111a, 0x111d), 512 regmap_reg_range(0x1122, 0x1127), 513 regmap_reg_range(0x112a, 0x112b), 514 regmap_reg_range(0x1136, 0x1139), 515 regmap_reg_range(0x113e, 0x113f), 516 regmap_reg_range(0x1400, 0x1401), 517 regmap_reg_range(0x1403, 0x1403), 518 regmap_reg_range(0x1410, 0x1417), 519 regmap_reg_range(0x1420, 0x1423), 520 regmap_reg_range(0x1500, 0x1507), 521 regmap_reg_range(0x1600, 0x1612), 522 regmap_reg_range(0x1800, 0x180f), 523 regmap_reg_range(0x1900, 0x1907), 524 regmap_reg_range(0x1914, 0x191b), 525 regmap_reg_range(0x1a00, 0x1a03), 526 regmap_reg_range(0x1a04, 0x1a08), 527 regmap_reg_range(0x1b00, 0x1b01), 528 regmap_reg_range(0x1b04, 0x1b04), 529 regmap_reg_range(0x1c00, 0x1c05), 530 regmap_reg_range(0x1c08, 0x1c1b), 531 532 /* port 2 */ 533 regmap_reg_range(0x2000, 0x2001), 534 regmap_reg_range(0x2004, 0x200b), 535 regmap_reg_range(0x2013, 0x2013), 536 regmap_reg_range(0x2017, 0x2017), 537 regmap_reg_range(0x201b, 0x201b), 538 regmap_reg_range(0x201f, 0x2021), 539 regmap_reg_range(0x2030, 0x2030), 540 regmap_reg_range(0x2100, 0x2111), 541 regmap_reg_range(0x211a, 0x211d), 542 regmap_reg_range(0x2122, 0x2127), 543 regmap_reg_range(0x212a, 0x212b), 544 regmap_reg_range(0x2136, 0x2139), 545 regmap_reg_range(0x213e, 0x213f), 546 regmap_reg_range(0x2400, 0x2401), 547 regmap_reg_range(0x2403, 0x2403), 548 regmap_reg_range(0x2410, 0x2417), 549 regmap_reg_range(0x2420, 0x2423), 550 regmap_reg_range(0x2500, 0x2507), 551 regmap_reg_range(0x2600, 0x2612), 552 regmap_reg_range(0x2800, 0x280f), 553 regmap_reg_range(0x2900, 0x2907), 554 regmap_reg_range(0x2914, 0x291b), 555 regmap_reg_range(0x2a00, 0x2a03), 556 regmap_reg_range(0x2a04, 0x2a08), 557 regmap_reg_range(0x2b00, 0x2b01), 558 regmap_reg_range(0x2b04, 0x2b04), 559 regmap_reg_range(0x2c00, 0x2c05), 560 regmap_reg_range(0x2c08, 0x2c1b), 561 562 /* port 3 */ 563 regmap_reg_range(0x3000, 0x3001), 564 regmap_reg_range(0x3004, 0x300b), 565 regmap_reg_range(0x3013, 0x3013), 566 regmap_reg_range(0x3017, 0x3017), 567 regmap_reg_range(0x301b, 0x301b), 568 regmap_reg_range(0x301f, 0x3021), 569 regmap_reg_range(0x3030, 0x3030), 570 regmap_reg_range(0x3300, 0x3301), 571 regmap_reg_range(0x3303, 0x3303), 572 regmap_reg_range(0x3400, 0x3401), 573 regmap_reg_range(0x3403, 0x3403), 574 regmap_reg_range(0x3410, 0x3417), 575 regmap_reg_range(0x3420, 0x3423), 576 regmap_reg_range(0x3500, 0x3507), 577 regmap_reg_range(0x3600, 0x3612), 578 regmap_reg_range(0x3800, 0x380f), 579 regmap_reg_range(0x3900, 0x3907), 580 regmap_reg_range(0x3914, 0x391b), 581 regmap_reg_range(0x3a00, 0x3a03), 582 regmap_reg_range(0x3a04, 0x3a08), 583 regmap_reg_range(0x3b00, 0x3b01), 584 regmap_reg_range(0x3b04, 0x3b04), 585 regmap_reg_range(0x3c00, 0x3c05), 586 regmap_reg_range(0x3c08, 0x3c1b), 587 }; 588 589 static const struct regmap_access_table ksz8563_register_set = { 590 .yes_ranges = ksz8563_valid_regs, 591 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), 592 }; 593 594 static const struct regmap_range ksz9477_valid_regs[] = { 595 regmap_reg_range(0x0000, 0x0003), 596 regmap_reg_range(0x0006, 0x0006), 597 regmap_reg_range(0x0010, 0x001f), 598 regmap_reg_range(0x0100, 0x0100), 599 regmap_reg_range(0x0103, 0x0107), 600 regmap_reg_range(0x010d, 0x010d), 601 regmap_reg_range(0x0110, 0x0113), 602 regmap_reg_range(0x0120, 0x012b), 603 regmap_reg_range(0x0201, 0x0201), 604 regmap_reg_range(0x0210, 0x0213), 605 regmap_reg_range(0x0300, 0x0300), 606 regmap_reg_range(0x0302, 0x031b), 607 regmap_reg_range(0x0320, 0x032b), 608 regmap_reg_range(0x0330, 0x0336), 609 regmap_reg_range(0x0338, 0x033b), 610 regmap_reg_range(0x033e, 0x033e), 611 regmap_reg_range(0x0340, 0x035f), 612 regmap_reg_range(0x0370, 0x0370), 613 regmap_reg_range(0x0378, 0x0378), 614 regmap_reg_range(0x037c, 0x037d), 615 regmap_reg_range(0x0390, 0x0393), 616 regmap_reg_range(0x0400, 0x040e), 617 regmap_reg_range(0x0410, 0x042f), 618 regmap_reg_range(0x0444, 0x044b), 619 regmap_reg_range(0x0450, 0x046f), 620 regmap_reg_range(0x0500, 0x0519), 621 regmap_reg_range(0x0520, 0x054b), 622 regmap_reg_range(0x0550, 0x05b3), 623 regmap_reg_range(0x0604, 0x060b), 624 regmap_reg_range(0x0610, 0x0612), 625 regmap_reg_range(0x0614, 0x062c), 626 regmap_reg_range(0x0640, 0x0645), 627 regmap_reg_range(0x0648, 0x064d), 628 629 /* port 1 */ 630 regmap_reg_range(0x1000, 0x1001), 631 regmap_reg_range(0x1013, 0x1013), 632 regmap_reg_range(0x1017, 0x1017), 633 regmap_reg_range(0x101b, 0x101b), 634 regmap_reg_range(0x101f, 0x1020), 635 regmap_reg_range(0x1030, 0x1030), 636 regmap_reg_range(0x1100, 0x1115), 637 regmap_reg_range(0x111a, 0x111f), 638 regmap_reg_range(0x1120, 0x112b), 639 regmap_reg_range(0x1134, 0x113b), 640 regmap_reg_range(0x113c, 0x113f), 641 regmap_reg_range(0x1400, 0x1401), 642 regmap_reg_range(0x1403, 0x1403), 643 regmap_reg_range(0x1410, 0x1417), 644 regmap_reg_range(0x1420, 0x1423), 645 regmap_reg_range(0x1500, 0x1507), 646 regmap_reg_range(0x1600, 0x1613), 647 regmap_reg_range(0x1800, 0x180f), 648 regmap_reg_range(0x1820, 0x1827), 649 regmap_reg_range(0x1830, 0x1837), 650 regmap_reg_range(0x1840, 0x184b), 651 regmap_reg_range(0x1900, 0x1907), 652 regmap_reg_range(0x1914, 0x191b), 653 regmap_reg_range(0x1920, 0x1920), 654 regmap_reg_range(0x1923, 0x1927), 655 regmap_reg_range(0x1a00, 0x1a03), 656 regmap_reg_range(0x1a04, 0x1a07), 657 regmap_reg_range(0x1b00, 0x1b01), 658 regmap_reg_range(0x1b04, 0x1b04), 659 regmap_reg_range(0x1c00, 0x1c05), 660 regmap_reg_range(0x1c08, 0x1c1b), 661 662 /* port 2 */ 663 regmap_reg_range(0x2000, 0x2001), 664 regmap_reg_range(0x2013, 0x2013), 665 regmap_reg_range(0x2017, 0x2017), 666 regmap_reg_range(0x201b, 0x201b), 667 regmap_reg_range(0x201f, 0x2020), 668 regmap_reg_range(0x2030, 0x2030), 669 regmap_reg_range(0x2100, 0x2115), 670 regmap_reg_range(0x211a, 0x211f), 671 regmap_reg_range(0x2120, 0x212b), 672 regmap_reg_range(0x2134, 0x213b), 673 regmap_reg_range(0x213c, 0x213f), 674 regmap_reg_range(0x2400, 0x2401), 675 regmap_reg_range(0x2403, 0x2403), 676 regmap_reg_range(0x2410, 0x2417), 677 regmap_reg_range(0x2420, 0x2423), 678 regmap_reg_range(0x2500, 0x2507), 679 regmap_reg_range(0x2600, 0x2613), 680 regmap_reg_range(0x2800, 0x280f), 681 regmap_reg_range(0x2820, 0x2827), 682 regmap_reg_range(0x2830, 0x2837), 683 regmap_reg_range(0x2840, 0x284b), 684 regmap_reg_range(0x2900, 0x2907), 685 regmap_reg_range(0x2914, 0x291b), 686 regmap_reg_range(0x2920, 0x2920), 687 regmap_reg_range(0x2923, 0x2927), 688 regmap_reg_range(0x2a00, 0x2a03), 689 regmap_reg_range(0x2a04, 0x2a07), 690 regmap_reg_range(0x2b00, 0x2b01), 691 regmap_reg_range(0x2b04, 0x2b04), 692 regmap_reg_range(0x2c00, 0x2c05), 693 regmap_reg_range(0x2c08, 0x2c1b), 694 695 /* port 3 */ 696 regmap_reg_range(0x3000, 0x3001), 697 regmap_reg_range(0x3013, 0x3013), 698 regmap_reg_range(0x3017, 0x3017), 699 regmap_reg_range(0x301b, 0x301b), 700 regmap_reg_range(0x301f, 0x3020), 701 regmap_reg_range(0x3030, 0x3030), 702 regmap_reg_range(0x3100, 0x3115), 703 regmap_reg_range(0x311a, 0x311f), 704 regmap_reg_range(0x3120, 0x312b), 705 regmap_reg_range(0x3134, 0x313b), 706 regmap_reg_range(0x313c, 0x313f), 707 regmap_reg_range(0x3400, 0x3401), 708 regmap_reg_range(0x3403, 0x3403), 709 regmap_reg_range(0x3410, 0x3417), 710 regmap_reg_range(0x3420, 0x3423), 711 regmap_reg_range(0x3500, 0x3507), 712 regmap_reg_range(0x3600, 0x3613), 713 regmap_reg_range(0x3800, 0x380f), 714 regmap_reg_range(0x3820, 0x3827), 715 regmap_reg_range(0x3830, 0x3837), 716 regmap_reg_range(0x3840, 0x384b), 717 regmap_reg_range(0x3900, 0x3907), 718 regmap_reg_range(0x3914, 0x391b), 719 regmap_reg_range(0x3920, 0x3920), 720 regmap_reg_range(0x3923, 0x3927), 721 regmap_reg_range(0x3a00, 0x3a03), 722 regmap_reg_range(0x3a04, 0x3a07), 723 regmap_reg_range(0x3b00, 0x3b01), 724 regmap_reg_range(0x3b04, 0x3b04), 725 regmap_reg_range(0x3c00, 0x3c05), 726 regmap_reg_range(0x3c08, 0x3c1b), 727 728 /* port 4 */ 729 regmap_reg_range(0x4000, 0x4001), 730 regmap_reg_range(0x4013, 0x4013), 731 regmap_reg_range(0x4017, 0x4017), 732 regmap_reg_range(0x401b, 0x401b), 733 regmap_reg_range(0x401f, 0x4020), 734 regmap_reg_range(0x4030, 0x4030), 735 regmap_reg_range(0x4100, 0x4115), 736 regmap_reg_range(0x411a, 0x411f), 737 regmap_reg_range(0x4120, 0x412b), 738 regmap_reg_range(0x4134, 0x413b), 739 regmap_reg_range(0x413c, 0x413f), 740 regmap_reg_range(0x4400, 0x4401), 741 regmap_reg_range(0x4403, 0x4403), 742 regmap_reg_range(0x4410, 0x4417), 743 regmap_reg_range(0x4420, 0x4423), 744 regmap_reg_range(0x4500, 0x4507), 745 regmap_reg_range(0x4600, 0x4613), 746 regmap_reg_range(0x4800, 0x480f), 747 regmap_reg_range(0x4820, 0x4827), 748 regmap_reg_range(0x4830, 0x4837), 749 regmap_reg_range(0x4840, 0x484b), 750 regmap_reg_range(0x4900, 0x4907), 751 regmap_reg_range(0x4914, 0x491b), 752 regmap_reg_range(0x4920, 0x4920), 753 regmap_reg_range(0x4923, 0x4927), 754 regmap_reg_range(0x4a00, 0x4a03), 755 regmap_reg_range(0x4a04, 0x4a07), 756 regmap_reg_range(0x4b00, 0x4b01), 757 regmap_reg_range(0x4b04, 0x4b04), 758 regmap_reg_range(0x4c00, 0x4c05), 759 regmap_reg_range(0x4c08, 0x4c1b), 760 761 /* port 5 */ 762 regmap_reg_range(0x5000, 0x5001), 763 regmap_reg_range(0x5013, 0x5013), 764 regmap_reg_range(0x5017, 0x5017), 765 regmap_reg_range(0x501b, 0x501b), 766 regmap_reg_range(0x501f, 0x5020), 767 regmap_reg_range(0x5030, 0x5030), 768 regmap_reg_range(0x5100, 0x5115), 769 regmap_reg_range(0x511a, 0x511f), 770 regmap_reg_range(0x5120, 0x512b), 771 regmap_reg_range(0x5134, 0x513b), 772 regmap_reg_range(0x513c, 0x513f), 773 regmap_reg_range(0x5400, 0x5401), 774 regmap_reg_range(0x5403, 0x5403), 775 regmap_reg_range(0x5410, 0x5417), 776 regmap_reg_range(0x5420, 0x5423), 777 regmap_reg_range(0x5500, 0x5507), 778 regmap_reg_range(0x5600, 0x5613), 779 regmap_reg_range(0x5800, 0x580f), 780 regmap_reg_range(0x5820, 0x5827), 781 regmap_reg_range(0x5830, 0x5837), 782 regmap_reg_range(0x5840, 0x584b), 783 regmap_reg_range(0x5900, 0x5907), 784 regmap_reg_range(0x5914, 0x591b), 785 regmap_reg_range(0x5920, 0x5920), 786 regmap_reg_range(0x5923, 0x5927), 787 regmap_reg_range(0x5a00, 0x5a03), 788 regmap_reg_range(0x5a04, 0x5a07), 789 regmap_reg_range(0x5b00, 0x5b01), 790 regmap_reg_range(0x5b04, 0x5b04), 791 regmap_reg_range(0x5c00, 0x5c05), 792 regmap_reg_range(0x5c08, 0x5c1b), 793 794 /* port 6 */ 795 regmap_reg_range(0x6000, 0x6001), 796 regmap_reg_range(0x6013, 0x6013), 797 regmap_reg_range(0x6017, 0x6017), 798 regmap_reg_range(0x601b, 0x601b), 799 regmap_reg_range(0x601f, 0x6020), 800 regmap_reg_range(0x6030, 0x6030), 801 regmap_reg_range(0x6300, 0x6301), 802 regmap_reg_range(0x6400, 0x6401), 803 regmap_reg_range(0x6403, 0x6403), 804 regmap_reg_range(0x6410, 0x6417), 805 regmap_reg_range(0x6420, 0x6423), 806 regmap_reg_range(0x6500, 0x6507), 807 regmap_reg_range(0x6600, 0x6613), 808 regmap_reg_range(0x6800, 0x680f), 809 regmap_reg_range(0x6820, 0x6827), 810 regmap_reg_range(0x6830, 0x6837), 811 regmap_reg_range(0x6840, 0x684b), 812 regmap_reg_range(0x6900, 0x6907), 813 regmap_reg_range(0x6914, 0x691b), 814 regmap_reg_range(0x6920, 0x6920), 815 regmap_reg_range(0x6923, 0x6927), 816 regmap_reg_range(0x6a00, 0x6a03), 817 regmap_reg_range(0x6a04, 0x6a07), 818 regmap_reg_range(0x6b00, 0x6b01), 819 regmap_reg_range(0x6b04, 0x6b04), 820 regmap_reg_range(0x6c00, 0x6c05), 821 regmap_reg_range(0x6c08, 0x6c1b), 822 823 /* port 7 */ 824 regmap_reg_range(0x7000, 0x7001), 825 regmap_reg_range(0x7013, 0x7013), 826 regmap_reg_range(0x7017, 0x7017), 827 regmap_reg_range(0x701b, 0x701b), 828 regmap_reg_range(0x701f, 0x7020), 829 regmap_reg_range(0x7030, 0x7030), 830 regmap_reg_range(0x7200, 0x7203), 831 regmap_reg_range(0x7206, 0x7207), 832 regmap_reg_range(0x7300, 0x7301), 833 regmap_reg_range(0x7400, 0x7401), 834 regmap_reg_range(0x7403, 0x7403), 835 regmap_reg_range(0x7410, 0x7417), 836 regmap_reg_range(0x7420, 0x7423), 837 regmap_reg_range(0x7500, 0x7507), 838 regmap_reg_range(0x7600, 0x7613), 839 regmap_reg_range(0x7800, 0x780f), 840 regmap_reg_range(0x7820, 0x7827), 841 regmap_reg_range(0x7830, 0x7837), 842 regmap_reg_range(0x7840, 0x784b), 843 regmap_reg_range(0x7900, 0x7907), 844 regmap_reg_range(0x7914, 0x791b), 845 regmap_reg_range(0x7920, 0x7920), 846 regmap_reg_range(0x7923, 0x7927), 847 regmap_reg_range(0x7a00, 0x7a03), 848 regmap_reg_range(0x7a04, 0x7a07), 849 regmap_reg_range(0x7b00, 0x7b01), 850 regmap_reg_range(0x7b04, 0x7b04), 851 regmap_reg_range(0x7c00, 0x7c05), 852 regmap_reg_range(0x7c08, 0x7c1b), 853 }; 854 855 static const struct regmap_access_table ksz9477_register_set = { 856 .yes_ranges = ksz9477_valid_regs, 857 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), 858 }; 859 860 static const struct regmap_range ksz9896_valid_regs[] = { 861 regmap_reg_range(0x0000, 0x0003), 862 regmap_reg_range(0x0006, 0x0006), 863 regmap_reg_range(0x0010, 0x001f), 864 regmap_reg_range(0x0100, 0x0100), 865 regmap_reg_range(0x0103, 0x0107), 866 regmap_reg_range(0x010d, 0x010d), 867 regmap_reg_range(0x0110, 0x0113), 868 regmap_reg_range(0x0120, 0x0127), 869 regmap_reg_range(0x0201, 0x0201), 870 regmap_reg_range(0x0210, 0x0213), 871 regmap_reg_range(0x0300, 0x0300), 872 regmap_reg_range(0x0302, 0x030b), 873 regmap_reg_range(0x0310, 0x031b), 874 regmap_reg_range(0x0320, 0x032b), 875 regmap_reg_range(0x0330, 0x0336), 876 regmap_reg_range(0x0338, 0x033b), 877 regmap_reg_range(0x033e, 0x033e), 878 regmap_reg_range(0x0340, 0x035f), 879 regmap_reg_range(0x0370, 0x0370), 880 regmap_reg_range(0x0378, 0x0378), 881 regmap_reg_range(0x037c, 0x037d), 882 regmap_reg_range(0x0390, 0x0393), 883 regmap_reg_range(0x0400, 0x040e), 884 regmap_reg_range(0x0410, 0x042f), 885 886 /* port 1 */ 887 regmap_reg_range(0x1000, 0x1001), 888 regmap_reg_range(0x1013, 0x1013), 889 regmap_reg_range(0x1017, 0x1017), 890 regmap_reg_range(0x101b, 0x101b), 891 regmap_reg_range(0x101f, 0x1020), 892 regmap_reg_range(0x1030, 0x1030), 893 regmap_reg_range(0x1100, 0x1115), 894 regmap_reg_range(0x111a, 0x111f), 895 regmap_reg_range(0x1122, 0x1127), 896 regmap_reg_range(0x112a, 0x112b), 897 regmap_reg_range(0x1136, 0x1139), 898 regmap_reg_range(0x113e, 0x113f), 899 regmap_reg_range(0x1400, 0x1401), 900 regmap_reg_range(0x1403, 0x1403), 901 regmap_reg_range(0x1410, 0x1417), 902 regmap_reg_range(0x1420, 0x1423), 903 regmap_reg_range(0x1500, 0x1507), 904 regmap_reg_range(0x1600, 0x1612), 905 regmap_reg_range(0x1800, 0x180f), 906 regmap_reg_range(0x1820, 0x1827), 907 regmap_reg_range(0x1830, 0x1837), 908 regmap_reg_range(0x1840, 0x184b), 909 regmap_reg_range(0x1900, 0x1907), 910 regmap_reg_range(0x1914, 0x1915), 911 regmap_reg_range(0x1a00, 0x1a03), 912 regmap_reg_range(0x1a04, 0x1a07), 913 regmap_reg_range(0x1b00, 0x1b01), 914 regmap_reg_range(0x1b04, 0x1b04), 915 916 /* port 2 */ 917 regmap_reg_range(0x2000, 0x2001), 918 regmap_reg_range(0x2013, 0x2013), 919 regmap_reg_range(0x2017, 0x2017), 920 regmap_reg_range(0x201b, 0x201b), 921 regmap_reg_range(0x201f, 0x2020), 922 regmap_reg_range(0x2030, 0x2030), 923 regmap_reg_range(0x2100, 0x2115), 924 regmap_reg_range(0x211a, 0x211f), 925 regmap_reg_range(0x2122, 0x2127), 926 regmap_reg_range(0x212a, 0x212b), 927 regmap_reg_range(0x2136, 0x2139), 928 regmap_reg_range(0x213e, 0x213f), 929 regmap_reg_range(0x2400, 0x2401), 930 regmap_reg_range(0x2403, 0x2403), 931 regmap_reg_range(0x2410, 0x2417), 932 regmap_reg_range(0x2420, 0x2423), 933 regmap_reg_range(0x2500, 0x2507), 934 regmap_reg_range(0x2600, 0x2612), 935 regmap_reg_range(0x2800, 0x280f), 936 regmap_reg_range(0x2820, 0x2827), 937 regmap_reg_range(0x2830, 0x2837), 938 regmap_reg_range(0x2840, 0x284b), 939 regmap_reg_range(0x2900, 0x2907), 940 regmap_reg_range(0x2914, 0x2915), 941 regmap_reg_range(0x2a00, 0x2a03), 942 regmap_reg_range(0x2a04, 0x2a07), 943 regmap_reg_range(0x2b00, 0x2b01), 944 regmap_reg_range(0x2b04, 0x2b04), 945 946 /* port 3 */ 947 regmap_reg_range(0x3000, 0x3001), 948 regmap_reg_range(0x3013, 0x3013), 949 regmap_reg_range(0x3017, 0x3017), 950 regmap_reg_range(0x301b, 0x301b), 951 regmap_reg_range(0x301f, 0x3020), 952 regmap_reg_range(0x3030, 0x3030), 953 regmap_reg_range(0x3100, 0x3115), 954 regmap_reg_range(0x311a, 0x311f), 955 regmap_reg_range(0x3122, 0x3127), 956 regmap_reg_range(0x312a, 0x312b), 957 regmap_reg_range(0x3136, 0x3139), 958 regmap_reg_range(0x313e, 0x313f), 959 regmap_reg_range(0x3400, 0x3401), 960 regmap_reg_range(0x3403, 0x3403), 961 regmap_reg_range(0x3410, 0x3417), 962 regmap_reg_range(0x3420, 0x3423), 963 regmap_reg_range(0x3500, 0x3507), 964 regmap_reg_range(0x3600, 0x3612), 965 regmap_reg_range(0x3800, 0x380f), 966 regmap_reg_range(0x3820, 0x3827), 967 regmap_reg_range(0x3830, 0x3837), 968 regmap_reg_range(0x3840, 0x384b), 969 regmap_reg_range(0x3900, 0x3907), 970 regmap_reg_range(0x3914, 0x3915), 971 regmap_reg_range(0x3a00, 0x3a03), 972 regmap_reg_range(0x3a04, 0x3a07), 973 regmap_reg_range(0x3b00, 0x3b01), 974 regmap_reg_range(0x3b04, 0x3b04), 975 976 /* port 4 */ 977 regmap_reg_range(0x4000, 0x4001), 978 regmap_reg_range(0x4013, 0x4013), 979 regmap_reg_range(0x4017, 0x4017), 980 regmap_reg_range(0x401b, 0x401b), 981 regmap_reg_range(0x401f, 0x4020), 982 regmap_reg_range(0x4030, 0x4030), 983 regmap_reg_range(0x4100, 0x4115), 984 regmap_reg_range(0x411a, 0x411f), 985 regmap_reg_range(0x4122, 0x4127), 986 regmap_reg_range(0x412a, 0x412b), 987 regmap_reg_range(0x4136, 0x4139), 988 regmap_reg_range(0x413e, 0x413f), 989 regmap_reg_range(0x4400, 0x4401), 990 regmap_reg_range(0x4403, 0x4403), 991 regmap_reg_range(0x4410, 0x4417), 992 regmap_reg_range(0x4420, 0x4423), 993 regmap_reg_range(0x4500, 0x4507), 994 regmap_reg_range(0x4600, 0x4612), 995 regmap_reg_range(0x4800, 0x480f), 996 regmap_reg_range(0x4820, 0x4827), 997 regmap_reg_range(0x4830, 0x4837), 998 regmap_reg_range(0x4840, 0x484b), 999 regmap_reg_range(0x4900, 0x4907), 1000 regmap_reg_range(0x4914, 0x4915), 1001 regmap_reg_range(0x4a00, 0x4a03), 1002 regmap_reg_range(0x4a04, 0x4a07), 1003 regmap_reg_range(0x4b00, 0x4b01), 1004 regmap_reg_range(0x4b04, 0x4b04), 1005 1006 /* port 5 */ 1007 regmap_reg_range(0x5000, 0x5001), 1008 regmap_reg_range(0x5013, 0x5013), 1009 regmap_reg_range(0x5017, 0x5017), 1010 regmap_reg_range(0x501b, 0x501b), 1011 regmap_reg_range(0x501f, 0x5020), 1012 regmap_reg_range(0x5030, 0x5030), 1013 regmap_reg_range(0x5100, 0x5115), 1014 regmap_reg_range(0x511a, 0x511f), 1015 regmap_reg_range(0x5122, 0x5127), 1016 regmap_reg_range(0x512a, 0x512b), 1017 regmap_reg_range(0x5136, 0x5139), 1018 regmap_reg_range(0x513e, 0x513f), 1019 regmap_reg_range(0x5400, 0x5401), 1020 regmap_reg_range(0x5403, 0x5403), 1021 regmap_reg_range(0x5410, 0x5417), 1022 regmap_reg_range(0x5420, 0x5423), 1023 regmap_reg_range(0x5500, 0x5507), 1024 regmap_reg_range(0x5600, 0x5612), 1025 regmap_reg_range(0x5800, 0x580f), 1026 regmap_reg_range(0x5820, 0x5827), 1027 regmap_reg_range(0x5830, 0x5837), 1028 regmap_reg_range(0x5840, 0x584b), 1029 regmap_reg_range(0x5900, 0x5907), 1030 regmap_reg_range(0x5914, 0x5915), 1031 regmap_reg_range(0x5a00, 0x5a03), 1032 regmap_reg_range(0x5a04, 0x5a07), 1033 regmap_reg_range(0x5b00, 0x5b01), 1034 regmap_reg_range(0x5b04, 0x5b04), 1035 1036 /* port 6 */ 1037 regmap_reg_range(0x6000, 0x6001), 1038 regmap_reg_range(0x6013, 0x6013), 1039 regmap_reg_range(0x6017, 0x6017), 1040 regmap_reg_range(0x601b, 0x601b), 1041 regmap_reg_range(0x601f, 0x6020), 1042 regmap_reg_range(0x6030, 0x6030), 1043 regmap_reg_range(0x6100, 0x6115), 1044 regmap_reg_range(0x611a, 0x611f), 1045 regmap_reg_range(0x6122, 0x6127), 1046 regmap_reg_range(0x612a, 0x612b), 1047 regmap_reg_range(0x6136, 0x6139), 1048 regmap_reg_range(0x613e, 0x613f), 1049 regmap_reg_range(0x6300, 0x6301), 1050 regmap_reg_range(0x6400, 0x6401), 1051 regmap_reg_range(0x6403, 0x6403), 1052 regmap_reg_range(0x6410, 0x6417), 1053 regmap_reg_range(0x6420, 0x6423), 1054 regmap_reg_range(0x6500, 0x6507), 1055 regmap_reg_range(0x6600, 0x6612), 1056 regmap_reg_range(0x6800, 0x680f), 1057 regmap_reg_range(0x6820, 0x6827), 1058 regmap_reg_range(0x6830, 0x6837), 1059 regmap_reg_range(0x6840, 0x684b), 1060 regmap_reg_range(0x6900, 0x6907), 1061 regmap_reg_range(0x6914, 0x6915), 1062 regmap_reg_range(0x6a00, 0x6a03), 1063 regmap_reg_range(0x6a04, 0x6a07), 1064 regmap_reg_range(0x6b00, 0x6b01), 1065 regmap_reg_range(0x6b04, 0x6b04), 1066 }; 1067 1068 static const struct regmap_access_table ksz9896_register_set = { 1069 .yes_ranges = ksz9896_valid_regs, 1070 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs), 1071 }; 1072 1073 static const struct regmap_range ksz8873_valid_regs[] = { 1074 regmap_reg_range(0x00, 0x01), 1075 /* global control register */ 1076 regmap_reg_range(0x02, 0x0f), 1077 1078 /* port registers */ 1079 regmap_reg_range(0x10, 0x1d), 1080 regmap_reg_range(0x1e, 0x1f), 1081 regmap_reg_range(0x20, 0x2d), 1082 regmap_reg_range(0x2e, 0x2f), 1083 regmap_reg_range(0x30, 0x39), 1084 regmap_reg_range(0x3f, 0x3f), 1085 1086 /* advanced control registers */ 1087 regmap_reg_range(0x60, 0x6f), 1088 regmap_reg_range(0x70, 0x75), 1089 regmap_reg_range(0x76, 0x78), 1090 regmap_reg_range(0x79, 0x7a), 1091 regmap_reg_range(0x7b, 0x83), 1092 regmap_reg_range(0x8e, 0x99), 1093 regmap_reg_range(0x9a, 0xa5), 1094 regmap_reg_range(0xa6, 0xa6), 1095 regmap_reg_range(0xa7, 0xaa), 1096 regmap_reg_range(0xab, 0xae), 1097 regmap_reg_range(0xaf, 0xba), 1098 regmap_reg_range(0xbb, 0xbc), 1099 regmap_reg_range(0xbd, 0xbd), 1100 regmap_reg_range(0xc0, 0xc0), 1101 regmap_reg_range(0xc2, 0xc2), 1102 regmap_reg_range(0xc3, 0xc3), 1103 regmap_reg_range(0xc4, 0xc4), 1104 regmap_reg_range(0xc6, 0xc6), 1105 }; 1106 1107 static const struct regmap_access_table ksz8873_register_set = { 1108 .yes_ranges = ksz8873_valid_regs, 1109 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs), 1110 }; 1111 1112 const struct ksz_chip_data ksz_switch_chips[] = { 1113 [KSZ8563] = { 1114 .chip_id = KSZ8563_CHIP_ID, 1115 .dev_name = "KSZ8563", 1116 .num_vlans = 4096, 1117 .num_alus = 4096, 1118 .num_statics = 16, 1119 .cpu_ports = 0x07, /* can be configured as cpu port */ 1120 .port_cnt = 3, /* total port count */ 1121 .port_nirqs = 3, 1122 .num_tx_queues = 4, 1123 .tc_cbs_supported = true, 1124 .tc_ets_supported = true, 1125 .ops = &ksz9477_dev_ops, 1126 .mib_names = ksz9477_mib_names, 1127 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1128 .reg_mib_cnt = MIB_COUNTER_NUM, 1129 .regs = ksz9477_regs, 1130 .masks = ksz9477_masks, 1131 .shifts = ksz9477_shifts, 1132 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1133 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1134 .supports_mii = {false, false, true}, 1135 .supports_rmii = {false, false, true}, 1136 .supports_rgmii = {false, false, true}, 1137 .internal_phy = {true, true, false}, 1138 .gbit_capable = {false, false, true}, 1139 .wr_table = &ksz8563_register_set, 1140 .rd_table = &ksz8563_register_set, 1141 }, 1142 1143 [KSZ8795] = { 1144 .chip_id = KSZ8795_CHIP_ID, 1145 .dev_name = "KSZ8795", 1146 .num_vlans = 4096, 1147 .num_alus = 0, 1148 .num_statics = 8, 1149 .cpu_ports = 0x10, /* can be configured as cpu port */ 1150 .port_cnt = 5, /* total cpu and user ports */ 1151 .num_tx_queues = 4, 1152 .ops = &ksz8_dev_ops, 1153 .ksz87xx_eee_link_erratum = true, 1154 .mib_names = ksz9477_mib_names, 1155 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1156 .reg_mib_cnt = MIB_COUNTER_NUM, 1157 .regs = ksz8795_regs, 1158 .masks = ksz8795_masks, 1159 .shifts = ksz8795_shifts, 1160 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1161 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1162 .supports_mii = {false, false, false, false, true}, 1163 .supports_rmii = {false, false, false, false, true}, 1164 .supports_rgmii = {false, false, false, false, true}, 1165 .internal_phy = {true, true, true, true, false}, 1166 }, 1167 1168 [KSZ8794] = { 1169 /* WARNING 1170 * ======= 1171 * KSZ8794 is similar to KSZ8795, except the port map 1172 * contains a gap between external and CPU ports, the 1173 * port map is NOT continuous. The per-port register 1174 * map is shifted accordingly too, i.e. registers at 1175 * offset 0x40 are NOT used on KSZ8794 and they ARE 1176 * used on KSZ8795 for external port 3. 1177 * external cpu 1178 * KSZ8794 0,1,2 4 1179 * KSZ8795 0,1,2,3 4 1180 * KSZ8765 0,1,2,3 4 1181 * port_cnt is configured as 5, even though it is 4 1182 */ 1183 .chip_id = KSZ8794_CHIP_ID, 1184 .dev_name = "KSZ8794", 1185 .num_vlans = 4096, 1186 .num_alus = 0, 1187 .num_statics = 8, 1188 .cpu_ports = 0x10, /* can be configured as cpu port */ 1189 .port_cnt = 5, /* total cpu and user ports */ 1190 .num_tx_queues = 4, 1191 .ops = &ksz8_dev_ops, 1192 .ksz87xx_eee_link_erratum = true, 1193 .mib_names = ksz9477_mib_names, 1194 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1195 .reg_mib_cnt = MIB_COUNTER_NUM, 1196 .regs = ksz8795_regs, 1197 .masks = ksz8795_masks, 1198 .shifts = ksz8795_shifts, 1199 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1200 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1201 .supports_mii = {false, false, false, false, true}, 1202 .supports_rmii = {false, false, false, false, true}, 1203 .supports_rgmii = {false, false, false, false, true}, 1204 .internal_phy = {true, true, true, false, false}, 1205 }, 1206 1207 [KSZ8765] = { 1208 .chip_id = KSZ8765_CHIP_ID, 1209 .dev_name = "KSZ8765", 1210 .num_vlans = 4096, 1211 .num_alus = 0, 1212 .num_statics = 8, 1213 .cpu_ports = 0x10, /* can be configured as cpu port */ 1214 .port_cnt = 5, /* total cpu and user ports */ 1215 .num_tx_queues = 4, 1216 .ops = &ksz8_dev_ops, 1217 .ksz87xx_eee_link_erratum = true, 1218 .mib_names = ksz9477_mib_names, 1219 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1220 .reg_mib_cnt = MIB_COUNTER_NUM, 1221 .regs = ksz8795_regs, 1222 .masks = ksz8795_masks, 1223 .shifts = ksz8795_shifts, 1224 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1225 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1226 .supports_mii = {false, false, false, false, true}, 1227 .supports_rmii = {false, false, false, false, true}, 1228 .supports_rgmii = {false, false, false, false, true}, 1229 .internal_phy = {true, true, true, true, false}, 1230 }, 1231 1232 [KSZ8830] = { 1233 .chip_id = KSZ8830_CHIP_ID, 1234 .dev_name = "KSZ8863/KSZ8873", 1235 .num_vlans = 16, 1236 .num_alus = 0, 1237 .num_statics = 8, 1238 .cpu_ports = 0x4, /* can be configured as cpu port */ 1239 .port_cnt = 3, 1240 .num_tx_queues = 4, 1241 .ops = &ksz8_dev_ops, 1242 .mib_names = ksz88xx_mib_names, 1243 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1244 .reg_mib_cnt = MIB_COUNTER_NUM, 1245 .regs = ksz8863_regs, 1246 .masks = ksz8863_masks, 1247 .shifts = ksz8863_shifts, 1248 .supports_mii = {false, false, true}, 1249 .supports_rmii = {false, false, true}, 1250 .internal_phy = {true, true, false}, 1251 .wr_table = &ksz8873_register_set, 1252 .rd_table = &ksz8873_register_set, 1253 }, 1254 1255 [KSZ9477] = { 1256 .chip_id = KSZ9477_CHIP_ID, 1257 .dev_name = "KSZ9477", 1258 .num_vlans = 4096, 1259 .num_alus = 4096, 1260 .num_statics = 16, 1261 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1262 .port_cnt = 7, /* total physical port count */ 1263 .port_nirqs = 4, 1264 .num_tx_queues = 4, 1265 .tc_cbs_supported = true, 1266 .tc_ets_supported = true, 1267 .ops = &ksz9477_dev_ops, 1268 .mib_names = ksz9477_mib_names, 1269 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1270 .reg_mib_cnt = MIB_COUNTER_NUM, 1271 .regs = ksz9477_regs, 1272 .masks = ksz9477_masks, 1273 .shifts = ksz9477_shifts, 1274 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1275 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1276 .supports_mii = {false, false, false, false, 1277 false, true, false}, 1278 .supports_rmii = {false, false, false, false, 1279 false, true, false}, 1280 .supports_rgmii = {false, false, false, false, 1281 false, true, false}, 1282 .internal_phy = {true, true, true, true, 1283 true, false, false}, 1284 .gbit_capable = {true, true, true, true, true, true, true}, 1285 .wr_table = &ksz9477_register_set, 1286 .rd_table = &ksz9477_register_set, 1287 }, 1288 1289 [KSZ9896] = { 1290 .chip_id = KSZ9896_CHIP_ID, 1291 .dev_name = "KSZ9896", 1292 .num_vlans = 4096, 1293 .num_alus = 4096, 1294 .num_statics = 16, 1295 .cpu_ports = 0x3F, /* can be configured as cpu port */ 1296 .port_cnt = 6, /* total physical port count */ 1297 .port_nirqs = 2, 1298 .num_tx_queues = 4, 1299 .ops = &ksz9477_dev_ops, 1300 .mib_names = ksz9477_mib_names, 1301 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1302 .reg_mib_cnt = MIB_COUNTER_NUM, 1303 .regs = ksz9477_regs, 1304 .masks = ksz9477_masks, 1305 .shifts = ksz9477_shifts, 1306 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1307 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1308 .supports_mii = {false, false, false, false, 1309 false, true}, 1310 .supports_rmii = {false, false, false, false, 1311 false, true}, 1312 .supports_rgmii = {false, false, false, false, 1313 false, true}, 1314 .internal_phy = {true, true, true, true, 1315 true, false}, 1316 .gbit_capable = {true, true, true, true, true, true}, 1317 .wr_table = &ksz9896_register_set, 1318 .rd_table = &ksz9896_register_set, 1319 }, 1320 1321 [KSZ9897] = { 1322 .chip_id = KSZ9897_CHIP_ID, 1323 .dev_name = "KSZ9897", 1324 .num_vlans = 4096, 1325 .num_alus = 4096, 1326 .num_statics = 16, 1327 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1328 .port_cnt = 7, /* total physical port count */ 1329 .port_nirqs = 2, 1330 .num_tx_queues = 4, 1331 .ops = &ksz9477_dev_ops, 1332 .mib_names = ksz9477_mib_names, 1333 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1334 .reg_mib_cnt = MIB_COUNTER_NUM, 1335 .regs = ksz9477_regs, 1336 .masks = ksz9477_masks, 1337 .shifts = ksz9477_shifts, 1338 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1339 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1340 .supports_mii = {false, false, false, false, 1341 false, true, true}, 1342 .supports_rmii = {false, false, false, false, 1343 false, true, true}, 1344 .supports_rgmii = {false, false, false, false, 1345 false, true, true}, 1346 .internal_phy = {true, true, true, true, 1347 true, false, false}, 1348 .gbit_capable = {true, true, true, true, true, true, true}, 1349 }, 1350 1351 [KSZ9893] = { 1352 .chip_id = KSZ9893_CHIP_ID, 1353 .dev_name = "KSZ9893", 1354 .num_vlans = 4096, 1355 .num_alus = 4096, 1356 .num_statics = 16, 1357 .cpu_ports = 0x07, /* can be configured as cpu port */ 1358 .port_cnt = 3, /* total port count */ 1359 .port_nirqs = 2, 1360 .num_tx_queues = 4, 1361 .ops = &ksz9477_dev_ops, 1362 .mib_names = ksz9477_mib_names, 1363 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1364 .reg_mib_cnt = MIB_COUNTER_NUM, 1365 .regs = ksz9477_regs, 1366 .masks = ksz9477_masks, 1367 .shifts = ksz9477_shifts, 1368 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1369 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1370 .supports_mii = {false, false, true}, 1371 .supports_rmii = {false, false, true}, 1372 .supports_rgmii = {false, false, true}, 1373 .internal_phy = {true, true, false}, 1374 .gbit_capable = {true, true, true}, 1375 }, 1376 1377 [KSZ9563] = { 1378 .chip_id = KSZ9563_CHIP_ID, 1379 .dev_name = "KSZ9563", 1380 .num_vlans = 4096, 1381 .num_alus = 4096, 1382 .num_statics = 16, 1383 .cpu_ports = 0x07, /* can be configured as cpu port */ 1384 .port_cnt = 3, /* total port count */ 1385 .port_nirqs = 3, 1386 .num_tx_queues = 4, 1387 .tc_cbs_supported = true, 1388 .tc_ets_supported = true, 1389 .ops = &ksz9477_dev_ops, 1390 .mib_names = ksz9477_mib_names, 1391 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1392 .reg_mib_cnt = MIB_COUNTER_NUM, 1393 .regs = ksz9477_regs, 1394 .masks = ksz9477_masks, 1395 .shifts = ksz9477_shifts, 1396 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1397 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1398 .supports_mii = {false, false, true}, 1399 .supports_rmii = {false, false, true}, 1400 .supports_rgmii = {false, false, true}, 1401 .internal_phy = {true, true, false}, 1402 .gbit_capable = {true, true, true}, 1403 }, 1404 1405 [KSZ9567] = { 1406 .chip_id = KSZ9567_CHIP_ID, 1407 .dev_name = "KSZ9567", 1408 .num_vlans = 4096, 1409 .num_alus = 4096, 1410 .num_statics = 16, 1411 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1412 .port_cnt = 7, /* total physical port count */ 1413 .port_nirqs = 3, 1414 .num_tx_queues = 4, 1415 .tc_cbs_supported = true, 1416 .tc_ets_supported = true, 1417 .ops = &ksz9477_dev_ops, 1418 .mib_names = ksz9477_mib_names, 1419 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1420 .reg_mib_cnt = MIB_COUNTER_NUM, 1421 .regs = ksz9477_regs, 1422 .masks = ksz9477_masks, 1423 .shifts = ksz9477_shifts, 1424 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1425 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1426 .supports_mii = {false, false, false, false, 1427 false, true, true}, 1428 .supports_rmii = {false, false, false, false, 1429 false, true, true}, 1430 .supports_rgmii = {false, false, false, false, 1431 false, true, true}, 1432 .internal_phy = {true, true, true, true, 1433 true, false, false}, 1434 .gbit_capable = {true, true, true, true, true, true, true}, 1435 }, 1436 1437 [LAN9370] = { 1438 .chip_id = LAN9370_CHIP_ID, 1439 .dev_name = "LAN9370", 1440 .num_vlans = 4096, 1441 .num_alus = 1024, 1442 .num_statics = 256, 1443 .cpu_ports = 0x10, /* can be configured as cpu port */ 1444 .port_cnt = 5, /* total physical port count */ 1445 .port_nirqs = 6, 1446 .num_tx_queues = 8, 1447 .tc_cbs_supported = true, 1448 .tc_ets_supported = true, 1449 .ops = &lan937x_dev_ops, 1450 .mib_names = ksz9477_mib_names, 1451 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1452 .reg_mib_cnt = MIB_COUNTER_NUM, 1453 .regs = ksz9477_regs, 1454 .masks = lan937x_masks, 1455 .shifts = lan937x_shifts, 1456 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1457 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1458 .supports_mii = {false, false, false, false, true}, 1459 .supports_rmii = {false, false, false, false, true}, 1460 .supports_rgmii = {false, false, false, false, true}, 1461 .internal_phy = {true, true, true, true, false}, 1462 }, 1463 1464 [LAN9371] = { 1465 .chip_id = LAN9371_CHIP_ID, 1466 .dev_name = "LAN9371", 1467 .num_vlans = 4096, 1468 .num_alus = 1024, 1469 .num_statics = 256, 1470 .cpu_ports = 0x30, /* can be configured as cpu port */ 1471 .port_cnt = 6, /* total physical port count */ 1472 .port_nirqs = 6, 1473 .num_tx_queues = 8, 1474 .tc_cbs_supported = true, 1475 .tc_ets_supported = true, 1476 .ops = &lan937x_dev_ops, 1477 .mib_names = ksz9477_mib_names, 1478 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1479 .reg_mib_cnt = MIB_COUNTER_NUM, 1480 .regs = ksz9477_regs, 1481 .masks = lan937x_masks, 1482 .shifts = lan937x_shifts, 1483 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1484 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1485 .supports_mii = {false, false, false, false, true, true}, 1486 .supports_rmii = {false, false, false, false, true, true}, 1487 .supports_rgmii = {false, false, false, false, true, true}, 1488 .internal_phy = {true, true, true, true, false, false}, 1489 }, 1490 1491 [LAN9372] = { 1492 .chip_id = LAN9372_CHIP_ID, 1493 .dev_name = "LAN9372", 1494 .num_vlans = 4096, 1495 .num_alus = 1024, 1496 .num_statics = 256, 1497 .cpu_ports = 0x30, /* can be configured as cpu port */ 1498 .port_cnt = 8, /* total physical port count */ 1499 .port_nirqs = 6, 1500 .num_tx_queues = 8, 1501 .tc_cbs_supported = true, 1502 .tc_ets_supported = true, 1503 .ops = &lan937x_dev_ops, 1504 .mib_names = ksz9477_mib_names, 1505 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1506 .reg_mib_cnt = MIB_COUNTER_NUM, 1507 .regs = ksz9477_regs, 1508 .masks = lan937x_masks, 1509 .shifts = lan937x_shifts, 1510 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1511 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1512 .supports_mii = {false, false, false, false, 1513 true, true, false, false}, 1514 .supports_rmii = {false, false, false, false, 1515 true, true, false, false}, 1516 .supports_rgmii = {false, false, false, false, 1517 true, true, false, false}, 1518 .internal_phy = {true, true, true, true, 1519 false, false, true, true}, 1520 }, 1521 1522 [LAN9373] = { 1523 .chip_id = LAN9373_CHIP_ID, 1524 .dev_name = "LAN9373", 1525 .num_vlans = 4096, 1526 .num_alus = 1024, 1527 .num_statics = 256, 1528 .cpu_ports = 0x38, /* can be configured as cpu port */ 1529 .port_cnt = 5, /* total physical port count */ 1530 .port_nirqs = 6, 1531 .num_tx_queues = 8, 1532 .tc_cbs_supported = true, 1533 .tc_ets_supported = true, 1534 .ops = &lan937x_dev_ops, 1535 .mib_names = ksz9477_mib_names, 1536 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1537 .reg_mib_cnt = MIB_COUNTER_NUM, 1538 .regs = ksz9477_regs, 1539 .masks = lan937x_masks, 1540 .shifts = lan937x_shifts, 1541 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1542 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1543 .supports_mii = {false, false, false, false, 1544 true, true, false, false}, 1545 .supports_rmii = {false, false, false, false, 1546 true, true, false, false}, 1547 .supports_rgmii = {false, false, false, false, 1548 true, true, false, false}, 1549 .internal_phy = {true, true, true, false, 1550 false, false, true, true}, 1551 }, 1552 1553 [LAN9374] = { 1554 .chip_id = LAN9374_CHIP_ID, 1555 .dev_name = "LAN9374", 1556 .num_vlans = 4096, 1557 .num_alus = 1024, 1558 .num_statics = 256, 1559 .cpu_ports = 0x30, /* can be configured as cpu port */ 1560 .port_cnt = 8, /* total physical port count */ 1561 .port_nirqs = 6, 1562 .num_tx_queues = 8, 1563 .tc_cbs_supported = true, 1564 .tc_ets_supported = true, 1565 .ops = &lan937x_dev_ops, 1566 .mib_names = ksz9477_mib_names, 1567 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1568 .reg_mib_cnt = MIB_COUNTER_NUM, 1569 .regs = ksz9477_regs, 1570 .masks = lan937x_masks, 1571 .shifts = lan937x_shifts, 1572 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1573 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1574 .supports_mii = {false, false, false, false, 1575 true, true, false, false}, 1576 .supports_rmii = {false, false, false, false, 1577 true, true, false, false}, 1578 .supports_rgmii = {false, false, false, false, 1579 true, true, false, false}, 1580 .internal_phy = {true, true, true, true, 1581 false, false, true, true}, 1582 }, 1583 }; 1584 EXPORT_SYMBOL_GPL(ksz_switch_chips); 1585 1586 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 1587 { 1588 int i; 1589 1590 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 1591 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 1592 1593 if (chip->chip_id == prod_num) 1594 return chip; 1595 } 1596 1597 return NULL; 1598 } 1599 1600 static int ksz_check_device_id(struct ksz_device *dev) 1601 { 1602 const struct ksz_chip_data *dt_chip_data; 1603 1604 dt_chip_data = of_device_get_match_data(dev->dev); 1605 1606 /* Check for Device Tree and Chip ID */ 1607 if (dt_chip_data->chip_id != dev->chip_id) { 1608 dev_err(dev->dev, 1609 "Device tree specifies chip %s but found %s, please fix it!\n", 1610 dt_chip_data->dev_name, dev->info->dev_name); 1611 return -ENODEV; 1612 } 1613 1614 return 0; 1615 } 1616 1617 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 1618 struct phylink_config *config) 1619 { 1620 struct ksz_device *dev = ds->priv; 1621 1622 if (dev->info->supports_mii[port]) 1623 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1624 1625 if (dev->info->supports_rmii[port]) 1626 __set_bit(PHY_INTERFACE_MODE_RMII, 1627 config->supported_interfaces); 1628 1629 if (dev->info->supports_rgmii[port]) 1630 phy_interface_set_rgmii(config->supported_interfaces); 1631 1632 if (dev->info->internal_phy[port]) { 1633 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1634 config->supported_interfaces); 1635 /* Compatibility for phylib's default interface type when the 1636 * phy-mode property is absent 1637 */ 1638 __set_bit(PHY_INTERFACE_MODE_GMII, 1639 config->supported_interfaces); 1640 } 1641 1642 if (dev->dev_ops->get_caps) 1643 dev->dev_ops->get_caps(dev, port, config); 1644 } 1645 1646 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 1647 { 1648 struct ethtool_pause_stats *pstats; 1649 struct rtnl_link_stats64 *stats; 1650 struct ksz_stats_raw *raw; 1651 struct ksz_port_mib *mib; 1652 1653 mib = &dev->ports[port].mib; 1654 stats = &mib->stats64; 1655 pstats = &mib->pause_stats; 1656 raw = (struct ksz_stats_raw *)mib->counters; 1657 1658 spin_lock(&mib->stats64_lock); 1659 1660 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1661 raw->rx_pause; 1662 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1663 raw->tx_pause; 1664 1665 /* HW counters are counting bytes + FCS which is not acceptable 1666 * for rtnl_link_stats64 interface 1667 */ 1668 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 1669 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 1670 1671 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 1672 raw->rx_oversize; 1673 1674 stats->rx_crc_errors = raw->rx_crc_err; 1675 stats->rx_frame_errors = raw->rx_align_err; 1676 stats->rx_dropped = raw->rx_discards; 1677 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 1678 stats->rx_frame_errors + stats->rx_dropped; 1679 1680 stats->tx_window_errors = raw->tx_late_col; 1681 stats->tx_fifo_errors = raw->tx_discards; 1682 stats->tx_aborted_errors = raw->tx_exc_col; 1683 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 1684 stats->tx_aborted_errors; 1685 1686 stats->multicast = raw->rx_mcast; 1687 stats->collisions = raw->tx_total_col; 1688 1689 pstats->tx_pause_frames = raw->tx_pause; 1690 pstats->rx_pause_frames = raw->rx_pause; 1691 1692 spin_unlock(&mib->stats64_lock); 1693 } 1694 1695 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port) 1696 { 1697 struct ethtool_pause_stats *pstats; 1698 struct rtnl_link_stats64 *stats; 1699 struct ksz88xx_stats_raw *raw; 1700 struct ksz_port_mib *mib; 1701 1702 mib = &dev->ports[port].mib; 1703 stats = &mib->stats64; 1704 pstats = &mib->pause_stats; 1705 raw = (struct ksz88xx_stats_raw *)mib->counters; 1706 1707 spin_lock(&mib->stats64_lock); 1708 1709 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1710 raw->rx_pause; 1711 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1712 raw->tx_pause; 1713 1714 /* HW counters are counting bytes + FCS which is not acceptable 1715 * for rtnl_link_stats64 interface 1716 */ 1717 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN; 1718 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN; 1719 1720 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 1721 raw->rx_oversize; 1722 1723 stats->rx_crc_errors = raw->rx_crc_err; 1724 stats->rx_frame_errors = raw->rx_align_err; 1725 stats->rx_dropped = raw->rx_discards; 1726 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 1727 stats->rx_frame_errors + stats->rx_dropped; 1728 1729 stats->tx_window_errors = raw->tx_late_col; 1730 stats->tx_fifo_errors = raw->tx_discards; 1731 stats->tx_aborted_errors = raw->tx_exc_col; 1732 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 1733 stats->tx_aborted_errors; 1734 1735 stats->multicast = raw->rx_mcast; 1736 stats->collisions = raw->tx_total_col; 1737 1738 pstats->tx_pause_frames = raw->tx_pause; 1739 pstats->rx_pause_frames = raw->rx_pause; 1740 1741 spin_unlock(&mib->stats64_lock); 1742 } 1743 1744 static void ksz_get_stats64(struct dsa_switch *ds, int port, 1745 struct rtnl_link_stats64 *s) 1746 { 1747 struct ksz_device *dev = ds->priv; 1748 struct ksz_port_mib *mib; 1749 1750 mib = &dev->ports[port].mib; 1751 1752 spin_lock(&mib->stats64_lock); 1753 memcpy(s, &mib->stats64, sizeof(*s)); 1754 spin_unlock(&mib->stats64_lock); 1755 } 1756 1757 static void ksz_get_pause_stats(struct dsa_switch *ds, int port, 1758 struct ethtool_pause_stats *pause_stats) 1759 { 1760 struct ksz_device *dev = ds->priv; 1761 struct ksz_port_mib *mib; 1762 1763 mib = &dev->ports[port].mib; 1764 1765 spin_lock(&mib->stats64_lock); 1766 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 1767 spin_unlock(&mib->stats64_lock); 1768 } 1769 1770 static void ksz_get_strings(struct dsa_switch *ds, int port, 1771 u32 stringset, uint8_t *buf) 1772 { 1773 struct ksz_device *dev = ds->priv; 1774 int i; 1775 1776 if (stringset != ETH_SS_STATS) 1777 return; 1778 1779 for (i = 0; i < dev->info->mib_cnt; i++) { 1780 memcpy(buf + i * ETH_GSTRING_LEN, 1781 dev->info->mib_names[i].string, ETH_GSTRING_LEN); 1782 } 1783 } 1784 1785 static void ksz_update_port_member(struct ksz_device *dev, int port) 1786 { 1787 struct ksz_port *p = &dev->ports[port]; 1788 struct dsa_switch *ds = dev->ds; 1789 u8 port_member = 0, cpu_port; 1790 const struct dsa_port *dp; 1791 int i, j; 1792 1793 if (!dsa_is_user_port(ds, port)) 1794 return; 1795 1796 dp = dsa_to_port(ds, port); 1797 cpu_port = BIT(dsa_upstream_port(ds, port)); 1798 1799 for (i = 0; i < ds->num_ports; i++) { 1800 const struct dsa_port *other_dp = dsa_to_port(ds, i); 1801 struct ksz_port *other_p = &dev->ports[i]; 1802 u8 val = 0; 1803 1804 if (!dsa_is_user_port(ds, i)) 1805 continue; 1806 if (port == i) 1807 continue; 1808 if (!dsa_port_bridge_same(dp, other_dp)) 1809 continue; 1810 if (other_p->stp_state != BR_STATE_FORWARDING) 1811 continue; 1812 1813 if (p->stp_state == BR_STATE_FORWARDING) { 1814 val |= BIT(port); 1815 port_member |= BIT(i); 1816 } 1817 1818 /* Retain port [i]'s relationship to other ports than [port] */ 1819 for (j = 0; j < ds->num_ports; j++) { 1820 const struct dsa_port *third_dp; 1821 struct ksz_port *third_p; 1822 1823 if (j == i) 1824 continue; 1825 if (j == port) 1826 continue; 1827 if (!dsa_is_user_port(ds, j)) 1828 continue; 1829 third_p = &dev->ports[j]; 1830 if (third_p->stp_state != BR_STATE_FORWARDING) 1831 continue; 1832 third_dp = dsa_to_port(ds, j); 1833 if (dsa_port_bridge_same(other_dp, third_dp)) 1834 val |= BIT(j); 1835 } 1836 1837 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 1838 } 1839 1840 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 1841 } 1842 1843 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 1844 { 1845 struct ksz_device *dev = bus->priv; 1846 u16 val; 1847 int ret; 1848 1849 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val); 1850 if (ret < 0) 1851 return ret; 1852 1853 return val; 1854 } 1855 1856 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 1857 u16 val) 1858 { 1859 struct ksz_device *dev = bus->priv; 1860 1861 return dev->dev_ops->w_phy(dev, addr, regnum, val); 1862 } 1863 1864 static int ksz_irq_phy_setup(struct ksz_device *dev) 1865 { 1866 struct dsa_switch *ds = dev->ds; 1867 int phy; 1868 int irq; 1869 int ret; 1870 1871 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) { 1872 if (BIT(phy) & ds->phys_mii_mask) { 1873 irq = irq_find_mapping(dev->ports[phy].pirq.domain, 1874 PORT_SRC_PHY_INT); 1875 if (irq < 0) { 1876 ret = irq; 1877 goto out; 1878 } 1879 ds->slave_mii_bus->irq[phy] = irq; 1880 } 1881 } 1882 return 0; 1883 out: 1884 while (phy--) 1885 if (BIT(phy) & ds->phys_mii_mask) 1886 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]); 1887 1888 return ret; 1889 } 1890 1891 static void ksz_irq_phy_free(struct ksz_device *dev) 1892 { 1893 struct dsa_switch *ds = dev->ds; 1894 int phy; 1895 1896 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) 1897 if (BIT(phy) & ds->phys_mii_mask) 1898 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]); 1899 } 1900 1901 static int ksz_mdio_register(struct ksz_device *dev) 1902 { 1903 struct dsa_switch *ds = dev->ds; 1904 struct device_node *mdio_np; 1905 struct mii_bus *bus; 1906 int ret; 1907 1908 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); 1909 if (!mdio_np) 1910 return 0; 1911 1912 bus = devm_mdiobus_alloc(ds->dev); 1913 if (!bus) { 1914 of_node_put(mdio_np); 1915 return -ENOMEM; 1916 } 1917 1918 bus->priv = dev; 1919 bus->read = ksz_sw_mdio_read; 1920 bus->write = ksz_sw_mdio_write; 1921 bus->name = "ksz slave smi"; 1922 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); 1923 bus->parent = ds->dev; 1924 bus->phy_mask = ~ds->phys_mii_mask; 1925 1926 ds->slave_mii_bus = bus; 1927 1928 if (dev->irq > 0) { 1929 ret = ksz_irq_phy_setup(dev); 1930 if (ret) { 1931 of_node_put(mdio_np); 1932 return ret; 1933 } 1934 } 1935 1936 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); 1937 if (ret) { 1938 dev_err(ds->dev, "unable to register MDIO bus %s\n", 1939 bus->id); 1940 if (dev->irq > 0) 1941 ksz_irq_phy_free(dev); 1942 } 1943 1944 of_node_put(mdio_np); 1945 1946 return ret; 1947 } 1948 1949 static void ksz_irq_mask(struct irq_data *d) 1950 { 1951 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1952 1953 kirq->masked |= BIT(d->hwirq); 1954 } 1955 1956 static void ksz_irq_unmask(struct irq_data *d) 1957 { 1958 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1959 1960 kirq->masked &= ~BIT(d->hwirq); 1961 } 1962 1963 static void ksz_irq_bus_lock(struct irq_data *d) 1964 { 1965 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1966 1967 mutex_lock(&kirq->dev->lock_irq); 1968 } 1969 1970 static void ksz_irq_bus_sync_unlock(struct irq_data *d) 1971 { 1972 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1973 struct ksz_device *dev = kirq->dev; 1974 int ret; 1975 1976 ret = ksz_write32(dev, kirq->reg_mask, kirq->masked); 1977 if (ret) 1978 dev_err(dev->dev, "failed to change IRQ mask\n"); 1979 1980 mutex_unlock(&dev->lock_irq); 1981 } 1982 1983 static const struct irq_chip ksz_irq_chip = { 1984 .name = "ksz-irq", 1985 .irq_mask = ksz_irq_mask, 1986 .irq_unmask = ksz_irq_unmask, 1987 .irq_bus_lock = ksz_irq_bus_lock, 1988 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock, 1989 }; 1990 1991 static int ksz_irq_domain_map(struct irq_domain *d, 1992 unsigned int irq, irq_hw_number_t hwirq) 1993 { 1994 irq_set_chip_data(irq, d->host_data); 1995 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq); 1996 irq_set_noprobe(irq); 1997 1998 return 0; 1999 } 2000 2001 static const struct irq_domain_ops ksz_irq_domain_ops = { 2002 .map = ksz_irq_domain_map, 2003 .xlate = irq_domain_xlate_twocell, 2004 }; 2005 2006 static void ksz_irq_free(struct ksz_irq *kirq) 2007 { 2008 int irq, virq; 2009 2010 free_irq(kirq->irq_num, kirq); 2011 2012 for (irq = 0; irq < kirq->nirqs; irq++) { 2013 virq = irq_find_mapping(kirq->domain, irq); 2014 irq_dispose_mapping(virq); 2015 } 2016 2017 irq_domain_remove(kirq->domain); 2018 } 2019 2020 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id) 2021 { 2022 struct ksz_irq *kirq = dev_id; 2023 unsigned int nhandled = 0; 2024 struct ksz_device *dev; 2025 unsigned int sub_irq; 2026 u8 data; 2027 int ret; 2028 u8 n; 2029 2030 dev = kirq->dev; 2031 2032 /* Read interrupt status register */ 2033 ret = ksz_read8(dev, kirq->reg_status, &data); 2034 if (ret) 2035 goto out; 2036 2037 for (n = 0; n < kirq->nirqs; ++n) { 2038 if (data & BIT(n)) { 2039 sub_irq = irq_find_mapping(kirq->domain, n); 2040 handle_nested_irq(sub_irq); 2041 ++nhandled; 2042 } 2043 } 2044 out: 2045 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 2046 } 2047 2048 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq) 2049 { 2050 int ret, n; 2051 2052 kirq->dev = dev; 2053 kirq->masked = ~0; 2054 2055 kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0, 2056 &ksz_irq_domain_ops, kirq); 2057 if (!kirq->domain) 2058 return -ENOMEM; 2059 2060 for (n = 0; n < kirq->nirqs; n++) 2061 irq_create_mapping(kirq->domain, n); 2062 2063 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn, 2064 IRQF_ONESHOT, kirq->name, kirq); 2065 if (ret) 2066 goto out; 2067 2068 return 0; 2069 2070 out: 2071 ksz_irq_free(kirq); 2072 2073 return ret; 2074 } 2075 2076 static int ksz_girq_setup(struct ksz_device *dev) 2077 { 2078 struct ksz_irq *girq = &dev->girq; 2079 2080 girq->nirqs = dev->info->port_cnt; 2081 girq->reg_mask = REG_SW_PORT_INT_MASK__1; 2082 girq->reg_status = REG_SW_PORT_INT_STATUS__1; 2083 snprintf(girq->name, sizeof(girq->name), "global_port_irq"); 2084 2085 girq->irq_num = dev->irq; 2086 2087 return ksz_irq_common_setup(dev, girq); 2088 } 2089 2090 static int ksz_pirq_setup(struct ksz_device *dev, u8 p) 2091 { 2092 struct ksz_irq *pirq = &dev->ports[p].pirq; 2093 2094 pirq->nirqs = dev->info->port_nirqs; 2095 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK); 2096 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS); 2097 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p); 2098 2099 pirq->irq_num = irq_find_mapping(dev->girq.domain, p); 2100 if (pirq->irq_num < 0) 2101 return pirq->irq_num; 2102 2103 return ksz_irq_common_setup(dev, pirq); 2104 } 2105 2106 static int ksz_setup(struct dsa_switch *ds) 2107 { 2108 struct ksz_device *dev = ds->priv; 2109 struct dsa_port *dp; 2110 struct ksz_port *p; 2111 const u16 *regs; 2112 int ret; 2113 2114 regs = dev->info->regs; 2115 2116 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 2117 dev->info->num_vlans, GFP_KERNEL); 2118 if (!dev->vlan_cache) 2119 return -ENOMEM; 2120 2121 ret = dev->dev_ops->reset(dev); 2122 if (ret) { 2123 dev_err(ds->dev, "failed to reset switch\n"); 2124 return ret; 2125 } 2126 2127 /* set broadcast storm protection 10% rate */ 2128 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL], 2129 BROADCAST_STORM_RATE, 2130 (BROADCAST_STORM_VALUE * 2131 BROADCAST_STORM_PROT_RATE) / 100); 2132 2133 dev->dev_ops->config_cpu_port(ds); 2134 2135 dev->dev_ops->enable_stp_addr(dev); 2136 2137 ds->num_tx_queues = dev->info->num_tx_queues; 2138 2139 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL], 2140 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 2141 2142 ksz_init_mib_timer(dev); 2143 2144 ds->configure_vlan_while_not_filtering = false; 2145 2146 if (dev->dev_ops->setup) { 2147 ret = dev->dev_ops->setup(ds); 2148 if (ret) 2149 return ret; 2150 } 2151 2152 /* Start with learning disabled on standalone user ports, and enabled 2153 * on the CPU port. In lack of other finer mechanisms, learning on the 2154 * CPU port will avoid flooding bridge local addresses on the network 2155 * in some cases. 2156 */ 2157 p = &dev->ports[dev->cpu_port]; 2158 p->learning = true; 2159 2160 if (dev->irq > 0) { 2161 ret = ksz_girq_setup(dev); 2162 if (ret) 2163 return ret; 2164 2165 dsa_switch_for_each_user_port(dp, dev->ds) { 2166 ret = ksz_pirq_setup(dev, dp->index); 2167 if (ret) 2168 goto out_girq; 2169 2170 ret = ksz_ptp_irq_setup(ds, dp->index); 2171 if (ret) 2172 goto out_pirq; 2173 } 2174 } 2175 2176 ret = ksz_ptp_clock_register(ds); 2177 if (ret) { 2178 dev_err(dev->dev, "Failed to register PTP clock: %d\n", ret); 2179 goto out_ptpirq; 2180 } 2181 2182 ret = ksz_mdio_register(dev); 2183 if (ret < 0) { 2184 dev_err(dev->dev, "failed to register the mdio"); 2185 goto out_ptp_clock_unregister; 2186 } 2187 2188 /* start switch */ 2189 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL], 2190 SW_START, SW_START); 2191 2192 return 0; 2193 2194 out_ptp_clock_unregister: 2195 ksz_ptp_clock_unregister(ds); 2196 out_ptpirq: 2197 if (dev->irq > 0) 2198 dsa_switch_for_each_user_port(dp, dev->ds) 2199 ksz_ptp_irq_free(ds, dp->index); 2200 out_pirq: 2201 if (dev->irq > 0) 2202 dsa_switch_for_each_user_port(dp, dev->ds) 2203 ksz_irq_free(&dev->ports[dp->index].pirq); 2204 out_girq: 2205 if (dev->irq > 0) 2206 ksz_irq_free(&dev->girq); 2207 2208 return ret; 2209 } 2210 2211 static void ksz_teardown(struct dsa_switch *ds) 2212 { 2213 struct ksz_device *dev = ds->priv; 2214 struct dsa_port *dp; 2215 2216 ksz_ptp_clock_unregister(ds); 2217 2218 if (dev->irq > 0) { 2219 dsa_switch_for_each_user_port(dp, dev->ds) { 2220 ksz_ptp_irq_free(ds, dp->index); 2221 2222 ksz_irq_free(&dev->ports[dp->index].pirq); 2223 } 2224 2225 ksz_irq_free(&dev->girq); 2226 } 2227 2228 if (dev->dev_ops->teardown) 2229 dev->dev_ops->teardown(ds); 2230 } 2231 2232 static void port_r_cnt(struct ksz_device *dev, int port) 2233 { 2234 struct ksz_port_mib *mib = &dev->ports[port].mib; 2235 u64 *dropped; 2236 2237 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 2238 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 2239 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 2240 &mib->counters[mib->cnt_ptr]); 2241 ++mib->cnt_ptr; 2242 } 2243 2244 /* last one in storage */ 2245 dropped = &mib->counters[dev->info->mib_cnt]; 2246 2247 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 2248 while (mib->cnt_ptr < dev->info->mib_cnt) { 2249 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 2250 dropped, &mib->counters[mib->cnt_ptr]); 2251 ++mib->cnt_ptr; 2252 } 2253 mib->cnt_ptr = 0; 2254 } 2255 2256 static void ksz_mib_read_work(struct work_struct *work) 2257 { 2258 struct ksz_device *dev = container_of(work, struct ksz_device, 2259 mib_read.work); 2260 struct ksz_port_mib *mib; 2261 struct ksz_port *p; 2262 int i; 2263 2264 for (i = 0; i < dev->info->port_cnt; i++) { 2265 if (dsa_is_unused_port(dev->ds, i)) 2266 continue; 2267 2268 p = &dev->ports[i]; 2269 mib = &p->mib; 2270 mutex_lock(&mib->cnt_mutex); 2271 2272 /* Only read MIB counters when the port is told to do. 2273 * If not, read only dropped counters when link is not up. 2274 */ 2275 if (!p->read) { 2276 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 2277 2278 if (!netif_carrier_ok(dp->slave)) 2279 mib->cnt_ptr = dev->info->reg_mib_cnt; 2280 } 2281 port_r_cnt(dev, i); 2282 p->read = false; 2283 2284 if (dev->dev_ops->r_mib_stat64) 2285 dev->dev_ops->r_mib_stat64(dev, i); 2286 2287 mutex_unlock(&mib->cnt_mutex); 2288 } 2289 2290 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 2291 } 2292 2293 void ksz_init_mib_timer(struct ksz_device *dev) 2294 { 2295 int i; 2296 2297 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 2298 2299 for (i = 0; i < dev->info->port_cnt; i++) { 2300 struct ksz_port_mib *mib = &dev->ports[i].mib; 2301 2302 dev->dev_ops->port_init_cnt(dev, i); 2303 2304 mib->cnt_ptr = 0; 2305 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 2306 } 2307 } 2308 2309 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 2310 { 2311 struct ksz_device *dev = ds->priv; 2312 u16 val = 0xffff; 2313 int ret; 2314 2315 ret = dev->dev_ops->r_phy(dev, addr, reg, &val); 2316 if (ret) 2317 return ret; 2318 2319 return val; 2320 } 2321 2322 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 2323 { 2324 struct ksz_device *dev = ds->priv; 2325 int ret; 2326 2327 ret = dev->dev_ops->w_phy(dev, addr, reg, val); 2328 if (ret) 2329 return ret; 2330 2331 return 0; 2332 } 2333 2334 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 2335 { 2336 struct ksz_device *dev = ds->priv; 2337 2338 switch (dev->chip_id) { 2339 case KSZ8830_CHIP_ID: 2340 /* Silicon Errata Sheet (DS80000830A): 2341 * Port 1 does not work with LinkMD Cable-Testing. 2342 * Port 1 does not respond to received PAUSE control frames. 2343 */ 2344 if (!port) 2345 return MICREL_KSZ8_P1_ERRATA; 2346 break; 2347 case KSZ9477_CHIP_ID: 2348 /* KSZ9477 Errata DS80000754C 2349 * 2350 * Module 4: Energy Efficient Ethernet (EEE) feature select must 2351 * be manually disabled 2352 * The EEE feature is enabled by default, but it is not fully 2353 * operational. It must be manually disabled through register 2354 * controls. If not disabled, the PHY ports can auto-negotiate 2355 * to enable EEE, and this feature can cause link drops when 2356 * linked to another device supporting EEE. 2357 */ 2358 return MICREL_NO_EEE; 2359 } 2360 2361 return 0; 2362 } 2363 2364 static void ksz_mac_link_down(struct dsa_switch *ds, int port, 2365 unsigned int mode, phy_interface_t interface) 2366 { 2367 struct ksz_device *dev = ds->priv; 2368 struct ksz_port *p = &dev->ports[port]; 2369 2370 /* Read all MIB counters when the link is going down. */ 2371 p->read = true; 2372 /* timer started */ 2373 if (dev->mib_read_interval) 2374 schedule_delayed_work(&dev->mib_read, 0); 2375 } 2376 2377 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 2378 { 2379 struct ksz_device *dev = ds->priv; 2380 2381 if (sset != ETH_SS_STATS) 2382 return 0; 2383 2384 return dev->info->mib_cnt; 2385 } 2386 2387 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 2388 uint64_t *buf) 2389 { 2390 const struct dsa_port *dp = dsa_to_port(ds, port); 2391 struct ksz_device *dev = ds->priv; 2392 struct ksz_port_mib *mib; 2393 2394 mib = &dev->ports[port].mib; 2395 mutex_lock(&mib->cnt_mutex); 2396 2397 /* Only read dropped counters if no link. */ 2398 if (!netif_carrier_ok(dp->slave)) 2399 mib->cnt_ptr = dev->info->reg_mib_cnt; 2400 port_r_cnt(dev, port); 2401 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 2402 mutex_unlock(&mib->cnt_mutex); 2403 } 2404 2405 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 2406 struct dsa_bridge bridge, 2407 bool *tx_fwd_offload, 2408 struct netlink_ext_ack *extack) 2409 { 2410 /* port_stp_state_set() will be called after to put the port in 2411 * appropriate state so there is no need to do anything. 2412 */ 2413 2414 return 0; 2415 } 2416 2417 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 2418 struct dsa_bridge bridge) 2419 { 2420 /* port_stp_state_set() will be called after to put the port in 2421 * forwarding state so there is no need to do anything. 2422 */ 2423 } 2424 2425 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 2426 { 2427 struct ksz_device *dev = ds->priv; 2428 2429 dev->dev_ops->flush_dyn_mac_table(dev, port); 2430 } 2431 2432 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 2433 { 2434 struct ksz_device *dev = ds->priv; 2435 2436 if (!dev->dev_ops->set_ageing_time) 2437 return -EOPNOTSUPP; 2438 2439 return dev->dev_ops->set_ageing_time(dev, msecs); 2440 } 2441 2442 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 2443 const unsigned char *addr, u16 vid, 2444 struct dsa_db db) 2445 { 2446 struct ksz_device *dev = ds->priv; 2447 2448 if (!dev->dev_ops->fdb_add) 2449 return -EOPNOTSUPP; 2450 2451 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 2452 } 2453 2454 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 2455 const unsigned char *addr, 2456 u16 vid, struct dsa_db db) 2457 { 2458 struct ksz_device *dev = ds->priv; 2459 2460 if (!dev->dev_ops->fdb_del) 2461 return -EOPNOTSUPP; 2462 2463 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 2464 } 2465 2466 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 2467 dsa_fdb_dump_cb_t *cb, void *data) 2468 { 2469 struct ksz_device *dev = ds->priv; 2470 2471 if (!dev->dev_ops->fdb_dump) 2472 return -EOPNOTSUPP; 2473 2474 return dev->dev_ops->fdb_dump(dev, port, cb, data); 2475 } 2476 2477 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 2478 const struct switchdev_obj_port_mdb *mdb, 2479 struct dsa_db db) 2480 { 2481 struct ksz_device *dev = ds->priv; 2482 2483 if (!dev->dev_ops->mdb_add) 2484 return -EOPNOTSUPP; 2485 2486 return dev->dev_ops->mdb_add(dev, port, mdb, db); 2487 } 2488 2489 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 2490 const struct switchdev_obj_port_mdb *mdb, 2491 struct dsa_db db) 2492 { 2493 struct ksz_device *dev = ds->priv; 2494 2495 if (!dev->dev_ops->mdb_del) 2496 return -EOPNOTSUPP; 2497 2498 return dev->dev_ops->mdb_del(dev, port, mdb, db); 2499 } 2500 2501 static int ksz_enable_port(struct dsa_switch *ds, int port, 2502 struct phy_device *phy) 2503 { 2504 struct ksz_device *dev = ds->priv; 2505 2506 if (!dsa_is_user_port(ds, port)) 2507 return 0; 2508 2509 /* setup slave port */ 2510 dev->dev_ops->port_setup(dev, port, false); 2511 2512 /* port_stp_state_set() will be called after to enable the port so 2513 * there is no need to do anything. 2514 */ 2515 2516 return 0; 2517 } 2518 2519 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 2520 { 2521 struct ksz_device *dev = ds->priv; 2522 struct ksz_port *p; 2523 const u16 *regs; 2524 u8 data; 2525 2526 regs = dev->info->regs; 2527 2528 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 2529 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2530 2531 p = &dev->ports[port]; 2532 2533 switch (state) { 2534 case BR_STATE_DISABLED: 2535 data |= PORT_LEARN_DISABLE; 2536 break; 2537 case BR_STATE_LISTENING: 2538 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2539 break; 2540 case BR_STATE_LEARNING: 2541 data |= PORT_RX_ENABLE; 2542 if (!p->learning) 2543 data |= PORT_LEARN_DISABLE; 2544 break; 2545 case BR_STATE_FORWARDING: 2546 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 2547 if (!p->learning) 2548 data |= PORT_LEARN_DISABLE; 2549 break; 2550 case BR_STATE_BLOCKING: 2551 data |= PORT_LEARN_DISABLE; 2552 break; 2553 default: 2554 dev_err(ds->dev, "invalid STP state: %d\n", state); 2555 return; 2556 } 2557 2558 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 2559 2560 p->stp_state = state; 2561 2562 ksz_update_port_member(dev, port); 2563 } 2564 2565 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 2566 struct switchdev_brport_flags flags, 2567 struct netlink_ext_ack *extack) 2568 { 2569 if (flags.mask & ~BR_LEARNING) 2570 return -EINVAL; 2571 2572 return 0; 2573 } 2574 2575 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 2576 struct switchdev_brport_flags flags, 2577 struct netlink_ext_ack *extack) 2578 { 2579 struct ksz_device *dev = ds->priv; 2580 struct ksz_port *p = &dev->ports[port]; 2581 2582 if (flags.mask & BR_LEARNING) { 2583 p->learning = !!(flags.val & BR_LEARNING); 2584 2585 /* Make the change take effect immediately */ 2586 ksz_port_stp_state_set(ds, port, p->stp_state); 2587 } 2588 2589 return 0; 2590 } 2591 2592 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 2593 int port, 2594 enum dsa_tag_protocol mp) 2595 { 2596 struct ksz_device *dev = ds->priv; 2597 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 2598 2599 if (dev->chip_id == KSZ8795_CHIP_ID || 2600 dev->chip_id == KSZ8794_CHIP_ID || 2601 dev->chip_id == KSZ8765_CHIP_ID) 2602 proto = DSA_TAG_PROTO_KSZ8795; 2603 2604 if (dev->chip_id == KSZ8830_CHIP_ID || 2605 dev->chip_id == KSZ8563_CHIP_ID || 2606 dev->chip_id == KSZ9893_CHIP_ID || 2607 dev->chip_id == KSZ9563_CHIP_ID) 2608 proto = DSA_TAG_PROTO_KSZ9893; 2609 2610 if (dev->chip_id == KSZ9477_CHIP_ID || 2611 dev->chip_id == KSZ9896_CHIP_ID || 2612 dev->chip_id == KSZ9897_CHIP_ID || 2613 dev->chip_id == KSZ9567_CHIP_ID) 2614 proto = DSA_TAG_PROTO_KSZ9477; 2615 2616 if (is_lan937x(dev)) 2617 proto = DSA_TAG_PROTO_LAN937X_VALUE; 2618 2619 return proto; 2620 } 2621 2622 static int ksz_connect_tag_protocol(struct dsa_switch *ds, 2623 enum dsa_tag_protocol proto) 2624 { 2625 struct ksz_tagger_data *tagger_data; 2626 2627 tagger_data = ksz_tagger_data(ds); 2628 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 2629 2630 return 0; 2631 } 2632 2633 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 2634 bool flag, struct netlink_ext_ack *extack) 2635 { 2636 struct ksz_device *dev = ds->priv; 2637 2638 if (!dev->dev_ops->vlan_filtering) 2639 return -EOPNOTSUPP; 2640 2641 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 2642 } 2643 2644 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 2645 const struct switchdev_obj_port_vlan *vlan, 2646 struct netlink_ext_ack *extack) 2647 { 2648 struct ksz_device *dev = ds->priv; 2649 2650 if (!dev->dev_ops->vlan_add) 2651 return -EOPNOTSUPP; 2652 2653 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 2654 } 2655 2656 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 2657 const struct switchdev_obj_port_vlan *vlan) 2658 { 2659 struct ksz_device *dev = ds->priv; 2660 2661 if (!dev->dev_ops->vlan_del) 2662 return -EOPNOTSUPP; 2663 2664 return dev->dev_ops->vlan_del(dev, port, vlan); 2665 } 2666 2667 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 2668 struct dsa_mall_mirror_tc_entry *mirror, 2669 bool ingress, struct netlink_ext_ack *extack) 2670 { 2671 struct ksz_device *dev = ds->priv; 2672 2673 if (!dev->dev_ops->mirror_add) 2674 return -EOPNOTSUPP; 2675 2676 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 2677 } 2678 2679 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 2680 struct dsa_mall_mirror_tc_entry *mirror) 2681 { 2682 struct ksz_device *dev = ds->priv; 2683 2684 if (dev->dev_ops->mirror_del) 2685 dev->dev_ops->mirror_del(dev, port, mirror); 2686 } 2687 2688 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 2689 { 2690 struct ksz_device *dev = ds->priv; 2691 2692 if (!dev->dev_ops->change_mtu) 2693 return -EOPNOTSUPP; 2694 2695 return dev->dev_ops->change_mtu(dev, port, mtu); 2696 } 2697 2698 static int ksz_max_mtu(struct dsa_switch *ds, int port) 2699 { 2700 struct ksz_device *dev = ds->priv; 2701 2702 switch (dev->chip_id) { 2703 case KSZ8795_CHIP_ID: 2704 case KSZ8794_CHIP_ID: 2705 case KSZ8765_CHIP_ID: 2706 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2707 case KSZ8830_CHIP_ID: 2708 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2709 case KSZ8563_CHIP_ID: 2710 case KSZ9477_CHIP_ID: 2711 case KSZ9563_CHIP_ID: 2712 case KSZ9567_CHIP_ID: 2713 case KSZ9893_CHIP_ID: 2714 case KSZ9896_CHIP_ID: 2715 case KSZ9897_CHIP_ID: 2716 case LAN9370_CHIP_ID: 2717 case LAN9371_CHIP_ID: 2718 case LAN9372_CHIP_ID: 2719 case LAN9373_CHIP_ID: 2720 case LAN9374_CHIP_ID: 2721 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2722 } 2723 2724 return -EOPNOTSUPP; 2725 } 2726 2727 static int ksz_validate_eee(struct dsa_switch *ds, int port) 2728 { 2729 struct ksz_device *dev = ds->priv; 2730 2731 if (!dev->info->internal_phy[port]) 2732 return -EOPNOTSUPP; 2733 2734 switch (dev->chip_id) { 2735 case KSZ8563_CHIP_ID: 2736 case KSZ9477_CHIP_ID: 2737 case KSZ9563_CHIP_ID: 2738 case KSZ9567_CHIP_ID: 2739 case KSZ9893_CHIP_ID: 2740 case KSZ9896_CHIP_ID: 2741 case KSZ9897_CHIP_ID: 2742 return 0; 2743 } 2744 2745 return -EOPNOTSUPP; 2746 } 2747 2748 static int ksz_get_mac_eee(struct dsa_switch *ds, int port, 2749 struct ethtool_eee *e) 2750 { 2751 int ret; 2752 2753 ret = ksz_validate_eee(ds, port); 2754 if (ret) 2755 return ret; 2756 2757 /* There is no documented control of Tx LPI configuration. */ 2758 e->tx_lpi_enabled = true; 2759 2760 /* There is no documented control of Tx LPI timer. According to tests 2761 * Tx LPI timer seems to be set by default to minimal value. 2762 */ 2763 e->tx_lpi_timer = 0; 2764 2765 return 0; 2766 } 2767 2768 static int ksz_set_mac_eee(struct dsa_switch *ds, int port, 2769 struct ethtool_eee *e) 2770 { 2771 struct ksz_device *dev = ds->priv; 2772 int ret; 2773 2774 ret = ksz_validate_eee(ds, port); 2775 if (ret) 2776 return ret; 2777 2778 if (!e->tx_lpi_enabled) { 2779 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n"); 2780 return -EINVAL; 2781 } 2782 2783 if (e->tx_lpi_timer) { 2784 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n"); 2785 return -EINVAL; 2786 } 2787 2788 return 0; 2789 } 2790 2791 static void ksz_set_xmii(struct ksz_device *dev, int port, 2792 phy_interface_t interface) 2793 { 2794 const u8 *bitval = dev->info->xmii_ctrl1; 2795 struct ksz_port *p = &dev->ports[port]; 2796 const u16 *regs = dev->info->regs; 2797 u8 data8; 2798 2799 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2800 2801 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 2802 P_RGMII_ID_EG_ENABLE); 2803 2804 switch (interface) { 2805 case PHY_INTERFACE_MODE_MII: 2806 data8 |= bitval[P_MII_SEL]; 2807 break; 2808 case PHY_INTERFACE_MODE_RMII: 2809 data8 |= bitval[P_RMII_SEL]; 2810 break; 2811 case PHY_INTERFACE_MODE_GMII: 2812 data8 |= bitval[P_GMII_SEL]; 2813 break; 2814 case PHY_INTERFACE_MODE_RGMII: 2815 case PHY_INTERFACE_MODE_RGMII_ID: 2816 case PHY_INTERFACE_MODE_RGMII_TXID: 2817 case PHY_INTERFACE_MODE_RGMII_RXID: 2818 data8 |= bitval[P_RGMII_SEL]; 2819 /* On KSZ9893, disable RGMII in-band status support */ 2820 if (dev->chip_id == KSZ9893_CHIP_ID || 2821 dev->chip_id == KSZ8563_CHIP_ID || 2822 dev->chip_id == KSZ9563_CHIP_ID) 2823 data8 &= ~P_MII_MAC_MODE; 2824 break; 2825 default: 2826 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 2827 phy_modes(interface), port); 2828 return; 2829 } 2830 2831 if (p->rgmii_tx_val) 2832 data8 |= P_RGMII_ID_EG_ENABLE; 2833 2834 if (p->rgmii_rx_val) 2835 data8 |= P_RGMII_ID_IG_ENABLE; 2836 2837 /* Write the updated value */ 2838 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 2839 } 2840 2841 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 2842 { 2843 const u8 *bitval = dev->info->xmii_ctrl1; 2844 const u16 *regs = dev->info->regs; 2845 phy_interface_t interface; 2846 u8 data8; 2847 u8 val; 2848 2849 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2850 2851 val = FIELD_GET(P_MII_SEL_M, data8); 2852 2853 if (val == bitval[P_MII_SEL]) { 2854 if (gbit) 2855 interface = PHY_INTERFACE_MODE_GMII; 2856 else 2857 interface = PHY_INTERFACE_MODE_MII; 2858 } else if (val == bitval[P_RMII_SEL]) { 2859 interface = PHY_INTERFACE_MODE_RGMII; 2860 } else { 2861 interface = PHY_INTERFACE_MODE_RGMII; 2862 if (data8 & P_RGMII_ID_EG_ENABLE) 2863 interface = PHY_INTERFACE_MODE_RGMII_TXID; 2864 if (data8 & P_RGMII_ID_IG_ENABLE) { 2865 interface = PHY_INTERFACE_MODE_RGMII_RXID; 2866 if (data8 & P_RGMII_ID_EG_ENABLE) 2867 interface = PHY_INTERFACE_MODE_RGMII_ID; 2868 } 2869 } 2870 2871 return interface; 2872 } 2873 2874 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port, 2875 unsigned int mode, 2876 const struct phylink_link_state *state) 2877 { 2878 struct ksz_device *dev = ds->priv; 2879 2880 if (ksz_is_ksz88x3(dev)) 2881 return; 2882 2883 /* Internal PHYs */ 2884 if (dev->info->internal_phy[port]) 2885 return; 2886 2887 if (phylink_autoneg_inband(mode)) { 2888 dev_err(dev->dev, "In-band AN not supported!\n"); 2889 return; 2890 } 2891 2892 ksz_set_xmii(dev, port, state->interface); 2893 2894 if (dev->dev_ops->phylink_mac_config) 2895 dev->dev_ops->phylink_mac_config(dev, port, mode, state); 2896 2897 if (dev->dev_ops->setup_rgmii_delay) 2898 dev->dev_ops->setup_rgmii_delay(dev, port); 2899 } 2900 2901 bool ksz_get_gbit(struct ksz_device *dev, int port) 2902 { 2903 const u8 *bitval = dev->info->xmii_ctrl1; 2904 const u16 *regs = dev->info->regs; 2905 bool gbit = false; 2906 u8 data8; 2907 bool val; 2908 2909 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2910 2911 val = FIELD_GET(P_GMII_1GBIT_M, data8); 2912 2913 if (val == bitval[P_GMII_1GBIT]) 2914 gbit = true; 2915 2916 return gbit; 2917 } 2918 2919 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) 2920 { 2921 const u8 *bitval = dev->info->xmii_ctrl1; 2922 const u16 *regs = dev->info->regs; 2923 u8 data8; 2924 2925 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2926 2927 data8 &= ~P_GMII_1GBIT_M; 2928 2929 if (gbit) 2930 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 2931 else 2932 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 2933 2934 /* Write the updated value */ 2935 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 2936 } 2937 2938 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) 2939 { 2940 const u8 *bitval = dev->info->xmii_ctrl0; 2941 const u16 *regs = dev->info->regs; 2942 u8 data8; 2943 2944 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 2945 2946 data8 &= ~P_MII_100MBIT_M; 2947 2948 if (speed == SPEED_100) 2949 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 2950 else 2951 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 2952 2953 /* Write the updated value */ 2954 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 2955 } 2956 2957 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) 2958 { 2959 if (speed == SPEED_1000) 2960 ksz_set_gbit(dev, port, true); 2961 else 2962 ksz_set_gbit(dev, port, false); 2963 2964 if (speed == SPEED_100 || speed == SPEED_10) 2965 ksz_set_100_10mbit(dev, port, speed); 2966 } 2967 2968 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 2969 bool tx_pause, bool rx_pause) 2970 { 2971 const u8 *bitval = dev->info->xmii_ctrl0; 2972 const u32 *masks = dev->info->masks; 2973 const u16 *regs = dev->info->regs; 2974 u8 mask; 2975 u8 val; 2976 2977 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 2978 masks[P_MII_RX_FLOW_CTRL]; 2979 2980 if (duplex == DUPLEX_FULL) 2981 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 2982 else 2983 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 2984 2985 if (tx_pause) 2986 val |= masks[P_MII_TX_FLOW_CTRL]; 2987 2988 if (rx_pause) 2989 val |= masks[P_MII_RX_FLOW_CTRL]; 2990 2991 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 2992 } 2993 2994 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, 2995 unsigned int mode, 2996 phy_interface_t interface, 2997 struct phy_device *phydev, int speed, 2998 int duplex, bool tx_pause, 2999 bool rx_pause) 3000 { 3001 struct ksz_port *p; 3002 3003 p = &dev->ports[port]; 3004 3005 /* Internal PHYs */ 3006 if (dev->info->internal_phy[port]) 3007 return; 3008 3009 p->phydev.speed = speed; 3010 3011 ksz_port_set_xmii_speed(dev, port, speed); 3012 3013 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 3014 } 3015 3016 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port, 3017 unsigned int mode, 3018 phy_interface_t interface, 3019 struct phy_device *phydev, int speed, 3020 int duplex, bool tx_pause, bool rx_pause) 3021 { 3022 struct ksz_device *dev = ds->priv; 3023 3024 if (dev->dev_ops->phylink_mac_link_up) 3025 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface, 3026 phydev, speed, duplex, 3027 tx_pause, rx_pause); 3028 } 3029 3030 static int ksz_switch_detect(struct ksz_device *dev) 3031 { 3032 u8 id1, id2, id4; 3033 u16 id16; 3034 u32 id32; 3035 int ret; 3036 3037 /* read chip id */ 3038 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 3039 if (ret) 3040 return ret; 3041 3042 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 3043 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 3044 3045 switch (id1) { 3046 case KSZ87_FAMILY_ID: 3047 if (id2 == KSZ87_CHIP_ID_95) { 3048 u8 val; 3049 3050 dev->chip_id = KSZ8795_CHIP_ID; 3051 3052 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 3053 if (val & KSZ8_PORT_FIBER_MODE) 3054 dev->chip_id = KSZ8765_CHIP_ID; 3055 } else if (id2 == KSZ87_CHIP_ID_94) { 3056 dev->chip_id = KSZ8794_CHIP_ID; 3057 } else { 3058 return -ENODEV; 3059 } 3060 break; 3061 case KSZ88_FAMILY_ID: 3062 if (id2 == KSZ88_CHIP_ID_63) 3063 dev->chip_id = KSZ8830_CHIP_ID; 3064 else 3065 return -ENODEV; 3066 break; 3067 default: 3068 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 3069 if (ret) 3070 return ret; 3071 3072 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 3073 id32 &= ~0xFF; 3074 3075 switch (id32) { 3076 case KSZ9477_CHIP_ID: 3077 case KSZ9896_CHIP_ID: 3078 case KSZ9897_CHIP_ID: 3079 case KSZ9567_CHIP_ID: 3080 case LAN9370_CHIP_ID: 3081 case LAN9371_CHIP_ID: 3082 case LAN9372_CHIP_ID: 3083 case LAN9373_CHIP_ID: 3084 case LAN9374_CHIP_ID: 3085 dev->chip_id = id32; 3086 break; 3087 case KSZ9893_CHIP_ID: 3088 ret = ksz_read8(dev, REG_CHIP_ID4, 3089 &id4); 3090 if (ret) 3091 return ret; 3092 3093 if (id4 == SKU_ID_KSZ8563) 3094 dev->chip_id = KSZ8563_CHIP_ID; 3095 else if (id4 == SKU_ID_KSZ9563) 3096 dev->chip_id = KSZ9563_CHIP_ID; 3097 else 3098 dev->chip_id = KSZ9893_CHIP_ID; 3099 3100 break; 3101 default: 3102 dev_err(dev->dev, 3103 "unsupported switch detected %x)\n", id32); 3104 return -ENODEV; 3105 } 3106 } 3107 return 0; 3108 } 3109 3110 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth 3111 * is converted to Hex-decimal using the successive multiplication method. On 3112 * every step, integer part is taken and decimal part is carry forwarded. 3113 */ 3114 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw) 3115 { 3116 u32 cinc = 0; 3117 u32 txrate; 3118 u32 rate; 3119 u8 temp; 3120 u8 i; 3121 3122 txrate = idle_slope - send_slope; 3123 3124 if (!txrate) 3125 return -EINVAL; 3126 3127 rate = idle_slope; 3128 3129 /* 24 bit register */ 3130 for (i = 0; i < 6; i++) { 3131 rate = rate * 16; 3132 3133 temp = rate / txrate; 3134 3135 rate %= txrate; 3136 3137 cinc = ((cinc << 4) | temp); 3138 } 3139 3140 *bw = cinc; 3141 3142 return 0; 3143 } 3144 3145 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler, 3146 u8 shaper) 3147 { 3148 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0, 3149 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) | 3150 FIELD_PREP(MTI_SHAPING_M, shaper)); 3151 } 3152 3153 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port, 3154 struct tc_cbs_qopt_offload *qopt) 3155 { 3156 struct ksz_device *dev = ds->priv; 3157 int ret; 3158 u32 bw; 3159 3160 if (!dev->info->tc_cbs_supported) 3161 return -EOPNOTSUPP; 3162 3163 if (qopt->queue > dev->info->num_tx_queues) 3164 return -EINVAL; 3165 3166 /* Queue Selection */ 3167 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue); 3168 if (ret) 3169 return ret; 3170 3171 if (!qopt->enable) 3172 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3173 MTI_SHAPING_OFF); 3174 3175 /* High Credit */ 3176 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK, 3177 qopt->hicredit); 3178 if (ret) 3179 return ret; 3180 3181 /* Low Credit */ 3182 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK, 3183 qopt->locredit); 3184 if (ret) 3185 return ret; 3186 3187 /* Credit Increment Register */ 3188 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw); 3189 if (ret) 3190 return ret; 3191 3192 if (dev->dev_ops->tc_cbs_set_cinc) { 3193 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw); 3194 if (ret) 3195 return ret; 3196 } 3197 3198 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3199 MTI_SHAPING_SRP); 3200 } 3201 3202 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port) 3203 { 3204 int queue, ret; 3205 3206 /* Configuration will not take effect until the last Port Queue X 3207 * Egress Limit Control Register is written. 3208 */ 3209 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3210 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue, 3211 KSZ9477_OUT_RATE_NO_LIMIT); 3212 if (ret) 3213 return ret; 3214 } 3215 3216 return 0; 3217 } 3218 3219 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p, 3220 int band) 3221 { 3222 /* Compared to queues, bands prioritize packets differently. In strict 3223 * priority mode, the lowest priority is assigned to Queue 0 while the 3224 * highest priority is given to Band 0. 3225 */ 3226 return p->bands - 1 - band; 3227 } 3228 3229 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue) 3230 { 3231 int ret; 3232 3233 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3234 if (ret) 3235 return ret; 3236 3237 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 3238 MTI_SHAPING_OFF); 3239 } 3240 3241 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue, 3242 int weight) 3243 { 3244 int ret; 3245 3246 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 3247 if (ret) 3248 return ret; 3249 3250 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 3251 MTI_SHAPING_OFF); 3252 if (ret) 3253 return ret; 3254 3255 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight); 3256 } 3257 3258 static int ksz_tc_ets_add(struct ksz_device *dev, int port, 3259 struct tc_ets_qopt_offload_replace_params *p) 3260 { 3261 int ret, band, tc_prio; 3262 u32 queue_map = 0; 3263 3264 /* In order to ensure proper prioritization, it is necessary to set the 3265 * rate limit for the related queue to zero. Otherwise strict priority 3266 * or WRR mode will not work. This is a hardware limitation. 3267 */ 3268 ret = ksz_disable_egress_rate_limit(dev, port); 3269 if (ret) 3270 return ret; 3271 3272 /* Configure queue scheduling mode for all bands. Currently only strict 3273 * prio mode is supported. 3274 */ 3275 for (band = 0; band < p->bands; band++) { 3276 int queue = ksz_ets_band_to_queue(p, band); 3277 3278 ret = ksz_queue_set_strict(dev, port, queue); 3279 if (ret) 3280 return ret; 3281 } 3282 3283 /* Configure the mapping between traffic classes and queues. Note: 3284 * priomap variable support 16 traffic classes, but the chip can handle 3285 * only 8 classes. 3286 */ 3287 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) { 3288 int queue; 3289 3290 if (tc_prio > KSZ9477_MAX_TC_PRIO) 3291 break; 3292 3293 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]); 3294 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 3295 } 3296 3297 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3298 } 3299 3300 static int ksz_tc_ets_del(struct ksz_device *dev, int port) 3301 { 3302 int ret, queue, tc_prio, s; 3303 u32 queue_map = 0; 3304 3305 /* To restore the default chip configuration, set all queues to use the 3306 * WRR scheduler with a weight of 1. 3307 */ 3308 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 3309 ret = ksz_queue_set_wrr(dev, port, queue, 3310 KSZ9477_DEFAULT_WRR_WEIGHT); 3311 if (ret) 3312 return ret; 3313 } 3314 3315 switch (dev->info->num_tx_queues) { 3316 case 2: 3317 s = 2; 3318 break; 3319 case 4: 3320 s = 1; 3321 break; 3322 case 8: 3323 s = 0; 3324 break; 3325 default: 3326 return -EINVAL; 3327 } 3328 3329 /* Revert the queue mapping for TC-priority to its default setting on 3330 * the chip. 3331 */ 3332 for (tc_prio = 0; tc_prio <= KSZ9477_MAX_TC_PRIO; tc_prio++) { 3333 int queue; 3334 3335 queue = tc_prio >> s; 3336 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 3337 } 3338 3339 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3340 } 3341 3342 static int ksz_tc_ets_validate(struct ksz_device *dev, int port, 3343 struct tc_ets_qopt_offload_replace_params *p) 3344 { 3345 int band; 3346 3347 /* Since it is not feasible to share one port among multiple qdisc, 3348 * the user must configure all available queues appropriately. 3349 */ 3350 if (p->bands != dev->info->num_tx_queues) { 3351 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n", 3352 dev->info->num_tx_queues); 3353 return -EOPNOTSUPP; 3354 } 3355 3356 for (band = 0; band < p->bands; ++band) { 3357 /* The KSZ switches utilize a weighted round robin configuration 3358 * where a certain number of packets can be transmitted from a 3359 * queue before the next queue is serviced. For more information 3360 * on this, refer to section 5.2.8.4 of the KSZ8565R 3361 * documentation on the Port Transmit Queue Control 1 Register. 3362 * However, the current ETS Qdisc implementation (as of February 3363 * 2023) assigns a weight to each queue based on the number of 3364 * bytes or extrapolated bandwidth in percentages. Since this 3365 * differs from the KSZ switches' method and we don't want to 3366 * fake support by converting bytes to packets, it is better to 3367 * return an error instead. 3368 */ 3369 if (p->quanta[band]) { 3370 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n"); 3371 return -EOPNOTSUPP; 3372 } 3373 } 3374 3375 return 0; 3376 } 3377 3378 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port, 3379 struct tc_ets_qopt_offload *qopt) 3380 { 3381 struct ksz_device *dev = ds->priv; 3382 int ret; 3383 3384 if (!dev->info->tc_ets_supported) 3385 return -EOPNOTSUPP; 3386 3387 if (qopt->parent != TC_H_ROOT) { 3388 dev_err(dev->dev, "Parent should be \"root\"\n"); 3389 return -EOPNOTSUPP; 3390 } 3391 3392 switch (qopt->command) { 3393 case TC_ETS_REPLACE: 3394 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params); 3395 if (ret) 3396 return ret; 3397 3398 return ksz_tc_ets_add(dev, port, &qopt->replace_params); 3399 case TC_ETS_DESTROY: 3400 return ksz_tc_ets_del(dev, port); 3401 case TC_ETS_STATS: 3402 case TC_ETS_GRAFT: 3403 return -EOPNOTSUPP; 3404 } 3405 3406 return -EOPNOTSUPP; 3407 } 3408 3409 static int ksz_setup_tc(struct dsa_switch *ds, int port, 3410 enum tc_setup_type type, void *type_data) 3411 { 3412 switch (type) { 3413 case TC_SETUP_QDISC_CBS: 3414 return ksz_setup_tc_cbs(ds, port, type_data); 3415 case TC_SETUP_QDISC_ETS: 3416 return ksz_tc_setup_qdisc_ets(ds, port, type_data); 3417 default: 3418 return -EOPNOTSUPP; 3419 } 3420 } 3421 3422 static const struct dsa_switch_ops ksz_switch_ops = { 3423 .get_tag_protocol = ksz_get_tag_protocol, 3424 .connect_tag_protocol = ksz_connect_tag_protocol, 3425 .get_phy_flags = ksz_get_phy_flags, 3426 .setup = ksz_setup, 3427 .teardown = ksz_teardown, 3428 .phy_read = ksz_phy_read16, 3429 .phy_write = ksz_phy_write16, 3430 .phylink_get_caps = ksz_phylink_get_caps, 3431 .phylink_mac_config = ksz_phylink_mac_config, 3432 .phylink_mac_link_up = ksz_phylink_mac_link_up, 3433 .phylink_mac_link_down = ksz_mac_link_down, 3434 .port_enable = ksz_enable_port, 3435 .set_ageing_time = ksz_set_ageing_time, 3436 .get_strings = ksz_get_strings, 3437 .get_ethtool_stats = ksz_get_ethtool_stats, 3438 .get_sset_count = ksz_sset_count, 3439 .port_bridge_join = ksz_port_bridge_join, 3440 .port_bridge_leave = ksz_port_bridge_leave, 3441 .port_stp_state_set = ksz_port_stp_state_set, 3442 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 3443 .port_bridge_flags = ksz_port_bridge_flags, 3444 .port_fast_age = ksz_port_fast_age, 3445 .port_vlan_filtering = ksz_port_vlan_filtering, 3446 .port_vlan_add = ksz_port_vlan_add, 3447 .port_vlan_del = ksz_port_vlan_del, 3448 .port_fdb_dump = ksz_port_fdb_dump, 3449 .port_fdb_add = ksz_port_fdb_add, 3450 .port_fdb_del = ksz_port_fdb_del, 3451 .port_mdb_add = ksz_port_mdb_add, 3452 .port_mdb_del = ksz_port_mdb_del, 3453 .port_mirror_add = ksz_port_mirror_add, 3454 .port_mirror_del = ksz_port_mirror_del, 3455 .get_stats64 = ksz_get_stats64, 3456 .get_pause_stats = ksz_get_pause_stats, 3457 .port_change_mtu = ksz_change_mtu, 3458 .port_max_mtu = ksz_max_mtu, 3459 .get_ts_info = ksz_get_ts_info, 3460 .port_hwtstamp_get = ksz_hwtstamp_get, 3461 .port_hwtstamp_set = ksz_hwtstamp_set, 3462 .port_txtstamp = ksz_port_txtstamp, 3463 .port_rxtstamp = ksz_port_rxtstamp, 3464 .port_setup_tc = ksz_setup_tc, 3465 .get_mac_eee = ksz_get_mac_eee, 3466 .set_mac_eee = ksz_set_mac_eee, 3467 }; 3468 3469 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 3470 { 3471 struct dsa_switch *ds; 3472 struct ksz_device *swdev; 3473 3474 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 3475 if (!ds) 3476 return NULL; 3477 3478 ds->dev = base; 3479 ds->num_ports = DSA_MAX_PORTS; 3480 ds->ops = &ksz_switch_ops; 3481 3482 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 3483 if (!swdev) 3484 return NULL; 3485 3486 ds->priv = swdev; 3487 swdev->dev = base; 3488 3489 swdev->ds = ds; 3490 swdev->priv = priv; 3491 3492 return swdev; 3493 } 3494 EXPORT_SYMBOL(ksz_switch_alloc); 3495 3496 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 3497 struct device_node *port_dn) 3498 { 3499 phy_interface_t phy_mode = dev->ports[port_num].interface; 3500 int rx_delay = -1, tx_delay = -1; 3501 3502 if (!phy_interface_mode_is_rgmii(phy_mode)) 3503 return; 3504 3505 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 3506 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 3507 3508 if (rx_delay == -1 && tx_delay == -1) { 3509 dev_warn(dev->dev, 3510 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 3511 "please update device tree to specify \"rx-internal-delay-ps\" and " 3512 "\"tx-internal-delay-ps\"", 3513 port_num); 3514 3515 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 3516 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 3517 rx_delay = 2000; 3518 3519 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 3520 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 3521 tx_delay = 2000; 3522 } 3523 3524 if (rx_delay < 0) 3525 rx_delay = 0; 3526 if (tx_delay < 0) 3527 tx_delay = 0; 3528 3529 dev->ports[port_num].rgmii_rx_val = rx_delay; 3530 dev->ports[port_num].rgmii_tx_val = tx_delay; 3531 } 3532 3533 int ksz_switch_register(struct ksz_device *dev) 3534 { 3535 const struct ksz_chip_data *info; 3536 struct device_node *port, *ports; 3537 phy_interface_t interface; 3538 unsigned int port_num; 3539 int ret; 3540 int i; 3541 3542 if (dev->pdata) 3543 dev->chip_id = dev->pdata->chip_id; 3544 3545 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 3546 GPIOD_OUT_LOW); 3547 if (IS_ERR(dev->reset_gpio)) 3548 return PTR_ERR(dev->reset_gpio); 3549 3550 if (dev->reset_gpio) { 3551 gpiod_set_value_cansleep(dev->reset_gpio, 1); 3552 usleep_range(10000, 12000); 3553 gpiod_set_value_cansleep(dev->reset_gpio, 0); 3554 msleep(100); 3555 } 3556 3557 mutex_init(&dev->dev_mutex); 3558 mutex_init(&dev->regmap_mutex); 3559 mutex_init(&dev->alu_mutex); 3560 mutex_init(&dev->vlan_mutex); 3561 3562 ret = ksz_switch_detect(dev); 3563 if (ret) 3564 return ret; 3565 3566 info = ksz_lookup_info(dev->chip_id); 3567 if (!info) 3568 return -ENODEV; 3569 3570 /* Update the compatible info with the probed one */ 3571 dev->info = info; 3572 3573 dev_info(dev->dev, "found switch: %s, rev %i\n", 3574 dev->info->dev_name, dev->chip_rev); 3575 3576 ret = ksz_check_device_id(dev); 3577 if (ret) 3578 return ret; 3579 3580 dev->dev_ops = dev->info->ops; 3581 3582 ret = dev->dev_ops->init(dev); 3583 if (ret) 3584 return ret; 3585 3586 dev->ports = devm_kzalloc(dev->dev, 3587 dev->info->port_cnt * sizeof(struct ksz_port), 3588 GFP_KERNEL); 3589 if (!dev->ports) 3590 return -ENOMEM; 3591 3592 for (i = 0; i < dev->info->port_cnt; i++) { 3593 spin_lock_init(&dev->ports[i].mib.stats64_lock); 3594 mutex_init(&dev->ports[i].mib.cnt_mutex); 3595 dev->ports[i].mib.counters = 3596 devm_kzalloc(dev->dev, 3597 sizeof(u64) * (dev->info->mib_cnt + 1), 3598 GFP_KERNEL); 3599 if (!dev->ports[i].mib.counters) 3600 return -ENOMEM; 3601 3602 dev->ports[i].ksz_dev = dev; 3603 dev->ports[i].num = i; 3604 } 3605 3606 /* set the real number of ports */ 3607 dev->ds->num_ports = dev->info->port_cnt; 3608 3609 /* Host port interface will be self detected, or specifically set in 3610 * device tree. 3611 */ 3612 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 3613 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 3614 if (dev->dev->of_node) { 3615 ret = of_get_phy_mode(dev->dev->of_node, &interface); 3616 if (ret == 0) 3617 dev->compat_interface = interface; 3618 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 3619 if (!ports) 3620 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 3621 if (ports) { 3622 for_each_available_child_of_node(ports, port) { 3623 if (of_property_read_u32(port, "reg", 3624 &port_num)) 3625 continue; 3626 if (!(dev->port_mask & BIT(port_num))) { 3627 of_node_put(port); 3628 of_node_put(ports); 3629 return -EINVAL; 3630 } 3631 of_get_phy_mode(port, 3632 &dev->ports[port_num].interface); 3633 3634 ksz_parse_rgmii_delay(dev, port_num, port); 3635 } 3636 of_node_put(ports); 3637 } 3638 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 3639 "microchip,synclko-125"); 3640 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 3641 "microchip,synclko-disable"); 3642 if (dev->synclko_125 && dev->synclko_disable) { 3643 dev_err(dev->dev, "inconsistent synclko settings\n"); 3644 return -EINVAL; 3645 } 3646 } 3647 3648 ret = dsa_register_switch(dev->ds); 3649 if (ret) { 3650 dev->dev_ops->exit(dev); 3651 return ret; 3652 } 3653 3654 /* Read MIB counters every 30 seconds to avoid overflow. */ 3655 dev->mib_read_interval = msecs_to_jiffies(5000); 3656 3657 /* Start the MIB timer. */ 3658 schedule_delayed_work(&dev->mib_read, 0); 3659 3660 return ret; 3661 } 3662 EXPORT_SYMBOL(ksz_switch_register); 3663 3664 void ksz_switch_remove(struct ksz_device *dev) 3665 { 3666 /* timer started */ 3667 if (dev->mib_read_interval) { 3668 dev->mib_read_interval = 0; 3669 cancel_delayed_work_sync(&dev->mib_read); 3670 } 3671 3672 dev->dev_ops->exit(dev); 3673 dsa_unregister_switch(dev->ds); 3674 3675 if (dev->reset_gpio) 3676 gpiod_set_value_cansleep(dev->reset_gpio, 1); 3677 3678 } 3679 EXPORT_SYMBOL(ksz_switch_remove); 3680 3681 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 3682 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 3683 MODULE_LICENSE("GPL"); 3684