1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/export.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/platform_data/microchip-ksz.h> 14 #include <linux/phy.h> 15 #include <linux/etherdevice.h> 16 #include <linux/if_bridge.h> 17 #include <linux/irq.h> 18 #include <linux/irqdomain.h> 19 #include <linux/of_mdio.h> 20 #include <linux/of_device.h> 21 #include <linux/of_net.h> 22 #include <linux/micrel_phy.h> 23 #include <net/dsa.h> 24 #include <net/switchdev.h> 25 26 #include "ksz_common.h" 27 #include "ksz8.h" 28 #include "ksz9477.h" 29 #include "lan937x.h" 30 31 #define MIB_COUNTER_NUM 0x20 32 33 struct ksz_stats_raw { 34 u64 rx_hi; 35 u64 rx_undersize; 36 u64 rx_fragments; 37 u64 rx_oversize; 38 u64 rx_jabbers; 39 u64 rx_symbol_err; 40 u64 rx_crc_err; 41 u64 rx_align_err; 42 u64 rx_mac_ctrl; 43 u64 rx_pause; 44 u64 rx_bcast; 45 u64 rx_mcast; 46 u64 rx_ucast; 47 u64 rx_64_or_less; 48 u64 rx_65_127; 49 u64 rx_128_255; 50 u64 rx_256_511; 51 u64 rx_512_1023; 52 u64 rx_1024_1522; 53 u64 rx_1523_2000; 54 u64 rx_2001; 55 u64 tx_hi; 56 u64 tx_late_col; 57 u64 tx_pause; 58 u64 tx_bcast; 59 u64 tx_mcast; 60 u64 tx_ucast; 61 u64 tx_deferred; 62 u64 tx_total_col; 63 u64 tx_exc_col; 64 u64 tx_single_col; 65 u64 tx_mult_col; 66 u64 rx_total; 67 u64 tx_total; 68 u64 rx_discards; 69 u64 tx_discards; 70 }; 71 72 static const struct ksz_mib_names ksz88xx_mib_names[] = { 73 { 0x00, "rx" }, 74 { 0x01, "rx_hi" }, 75 { 0x02, "rx_undersize" }, 76 { 0x03, "rx_fragments" }, 77 { 0x04, "rx_oversize" }, 78 { 0x05, "rx_jabbers" }, 79 { 0x06, "rx_symbol_err" }, 80 { 0x07, "rx_crc_err" }, 81 { 0x08, "rx_align_err" }, 82 { 0x09, "rx_mac_ctrl" }, 83 { 0x0a, "rx_pause" }, 84 { 0x0b, "rx_bcast" }, 85 { 0x0c, "rx_mcast" }, 86 { 0x0d, "rx_ucast" }, 87 { 0x0e, "rx_64_or_less" }, 88 { 0x0f, "rx_65_127" }, 89 { 0x10, "rx_128_255" }, 90 { 0x11, "rx_256_511" }, 91 { 0x12, "rx_512_1023" }, 92 { 0x13, "rx_1024_1522" }, 93 { 0x14, "tx" }, 94 { 0x15, "tx_hi" }, 95 { 0x16, "tx_late_col" }, 96 { 0x17, "tx_pause" }, 97 { 0x18, "tx_bcast" }, 98 { 0x19, "tx_mcast" }, 99 { 0x1a, "tx_ucast" }, 100 { 0x1b, "tx_deferred" }, 101 { 0x1c, "tx_total_col" }, 102 { 0x1d, "tx_exc_col" }, 103 { 0x1e, "tx_single_col" }, 104 { 0x1f, "tx_mult_col" }, 105 { 0x100, "rx_discards" }, 106 { 0x101, "tx_discards" }, 107 }; 108 109 static const struct ksz_mib_names ksz9477_mib_names[] = { 110 { 0x00, "rx_hi" }, 111 { 0x01, "rx_undersize" }, 112 { 0x02, "rx_fragments" }, 113 { 0x03, "rx_oversize" }, 114 { 0x04, "rx_jabbers" }, 115 { 0x05, "rx_symbol_err" }, 116 { 0x06, "rx_crc_err" }, 117 { 0x07, "rx_align_err" }, 118 { 0x08, "rx_mac_ctrl" }, 119 { 0x09, "rx_pause" }, 120 { 0x0A, "rx_bcast" }, 121 { 0x0B, "rx_mcast" }, 122 { 0x0C, "rx_ucast" }, 123 { 0x0D, "rx_64_or_less" }, 124 { 0x0E, "rx_65_127" }, 125 { 0x0F, "rx_128_255" }, 126 { 0x10, "rx_256_511" }, 127 { 0x11, "rx_512_1023" }, 128 { 0x12, "rx_1024_1522" }, 129 { 0x13, "rx_1523_2000" }, 130 { 0x14, "rx_2001" }, 131 { 0x15, "tx_hi" }, 132 { 0x16, "tx_late_col" }, 133 { 0x17, "tx_pause" }, 134 { 0x18, "tx_bcast" }, 135 { 0x19, "tx_mcast" }, 136 { 0x1A, "tx_ucast" }, 137 { 0x1B, "tx_deferred" }, 138 { 0x1C, "tx_total_col" }, 139 { 0x1D, "tx_exc_col" }, 140 { 0x1E, "tx_single_col" }, 141 { 0x1F, "tx_mult_col" }, 142 { 0x80, "rx_total" }, 143 { 0x81, "tx_total" }, 144 { 0x82, "rx_discards" }, 145 { 0x83, "tx_discards" }, 146 }; 147 148 static const struct ksz_dev_ops ksz8_dev_ops = { 149 .setup = ksz8_setup, 150 .get_port_addr = ksz8_get_port_addr, 151 .cfg_port_member = ksz8_cfg_port_member, 152 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 153 .port_setup = ksz8_port_setup, 154 .r_phy = ksz8_r_phy, 155 .w_phy = ksz8_w_phy, 156 .r_mib_cnt = ksz8_r_mib_cnt, 157 .r_mib_pkt = ksz8_r_mib_pkt, 158 .freeze_mib = ksz8_freeze_mib, 159 .port_init_cnt = ksz8_port_init_cnt, 160 .fdb_dump = ksz8_fdb_dump, 161 .mdb_add = ksz8_mdb_add, 162 .mdb_del = ksz8_mdb_del, 163 .vlan_filtering = ksz8_port_vlan_filtering, 164 .vlan_add = ksz8_port_vlan_add, 165 .vlan_del = ksz8_port_vlan_del, 166 .mirror_add = ksz8_port_mirror_add, 167 .mirror_del = ksz8_port_mirror_del, 168 .get_caps = ksz8_get_caps, 169 .config_cpu_port = ksz8_config_cpu_port, 170 .enable_stp_addr = ksz8_enable_stp_addr, 171 .reset = ksz8_reset_switch, 172 .init = ksz8_switch_init, 173 .exit = ksz8_switch_exit, 174 }; 175 176 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, 177 unsigned int mode, 178 phy_interface_t interface, 179 struct phy_device *phydev, int speed, 180 int duplex, bool tx_pause, 181 bool rx_pause); 182 183 static const struct ksz_dev_ops ksz9477_dev_ops = { 184 .setup = ksz9477_setup, 185 .get_port_addr = ksz9477_get_port_addr, 186 .cfg_port_member = ksz9477_cfg_port_member, 187 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 188 .port_setup = ksz9477_port_setup, 189 .set_ageing_time = ksz9477_set_ageing_time, 190 .r_phy = ksz9477_r_phy, 191 .w_phy = ksz9477_w_phy, 192 .r_mib_cnt = ksz9477_r_mib_cnt, 193 .r_mib_pkt = ksz9477_r_mib_pkt, 194 .r_mib_stat64 = ksz_r_mib_stats64, 195 .freeze_mib = ksz9477_freeze_mib, 196 .port_init_cnt = ksz9477_port_init_cnt, 197 .vlan_filtering = ksz9477_port_vlan_filtering, 198 .vlan_add = ksz9477_port_vlan_add, 199 .vlan_del = ksz9477_port_vlan_del, 200 .mirror_add = ksz9477_port_mirror_add, 201 .mirror_del = ksz9477_port_mirror_del, 202 .get_caps = ksz9477_get_caps, 203 .fdb_dump = ksz9477_fdb_dump, 204 .fdb_add = ksz9477_fdb_add, 205 .fdb_del = ksz9477_fdb_del, 206 .mdb_add = ksz9477_mdb_add, 207 .mdb_del = ksz9477_mdb_del, 208 .change_mtu = ksz9477_change_mtu, 209 .max_mtu = ksz9477_max_mtu, 210 .phylink_mac_link_up = ksz9477_phylink_mac_link_up, 211 .config_cpu_port = ksz9477_config_cpu_port, 212 .enable_stp_addr = ksz9477_enable_stp_addr, 213 .reset = ksz9477_reset_switch, 214 .init = ksz9477_switch_init, 215 .exit = ksz9477_switch_exit, 216 }; 217 218 static const struct ksz_dev_ops lan937x_dev_ops = { 219 .setup = lan937x_setup, 220 .teardown = lan937x_teardown, 221 .get_port_addr = ksz9477_get_port_addr, 222 .cfg_port_member = ksz9477_cfg_port_member, 223 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 224 .port_setup = lan937x_port_setup, 225 .set_ageing_time = lan937x_set_ageing_time, 226 .r_phy = lan937x_r_phy, 227 .w_phy = lan937x_w_phy, 228 .r_mib_cnt = ksz9477_r_mib_cnt, 229 .r_mib_pkt = ksz9477_r_mib_pkt, 230 .r_mib_stat64 = ksz_r_mib_stats64, 231 .freeze_mib = ksz9477_freeze_mib, 232 .port_init_cnt = ksz9477_port_init_cnt, 233 .vlan_filtering = ksz9477_port_vlan_filtering, 234 .vlan_add = ksz9477_port_vlan_add, 235 .vlan_del = ksz9477_port_vlan_del, 236 .mirror_add = ksz9477_port_mirror_add, 237 .mirror_del = ksz9477_port_mirror_del, 238 .get_caps = lan937x_phylink_get_caps, 239 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 240 .fdb_dump = ksz9477_fdb_dump, 241 .fdb_add = ksz9477_fdb_add, 242 .fdb_del = ksz9477_fdb_del, 243 .mdb_add = ksz9477_mdb_add, 244 .mdb_del = ksz9477_mdb_del, 245 .change_mtu = lan937x_change_mtu, 246 .max_mtu = ksz9477_max_mtu, 247 .phylink_mac_link_up = ksz9477_phylink_mac_link_up, 248 .config_cpu_port = lan937x_config_cpu_port, 249 .enable_stp_addr = ksz9477_enable_stp_addr, 250 .reset = lan937x_reset_switch, 251 .init = lan937x_switch_init, 252 .exit = lan937x_switch_exit, 253 }; 254 255 static const u16 ksz8795_regs[] = { 256 [REG_IND_CTRL_0] = 0x6E, 257 [REG_IND_DATA_8] = 0x70, 258 [REG_IND_DATA_CHECK] = 0x72, 259 [REG_IND_DATA_HI] = 0x71, 260 [REG_IND_DATA_LO] = 0x75, 261 [REG_IND_MIB_CHECK] = 0x74, 262 [REG_IND_BYTE] = 0xA0, 263 [P_FORCE_CTRL] = 0x0C, 264 [P_LINK_STATUS] = 0x0E, 265 [P_LOCAL_CTRL] = 0x07, 266 [P_NEG_RESTART_CTRL] = 0x0D, 267 [P_REMOTE_STATUS] = 0x08, 268 [P_SPEED_STATUS] = 0x09, 269 [S_TAIL_TAG_CTRL] = 0x0C, 270 [P_STP_CTRL] = 0x02, 271 [S_START_CTRL] = 0x01, 272 [S_BROADCAST_CTRL] = 0x06, 273 [S_MULTICAST_CTRL] = 0x04, 274 [P_XMII_CTRL_0] = 0x06, 275 [P_XMII_CTRL_1] = 0x56, 276 }; 277 278 static const u32 ksz8795_masks[] = { 279 [PORT_802_1P_REMAPPING] = BIT(7), 280 [SW_TAIL_TAG_ENABLE] = BIT(1), 281 [MIB_COUNTER_OVERFLOW] = BIT(6), 282 [MIB_COUNTER_VALID] = BIT(5), 283 [VLAN_TABLE_FID] = GENMASK(6, 0), 284 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 285 [VLAN_TABLE_VALID] = BIT(12), 286 [STATIC_MAC_TABLE_VALID] = BIT(21), 287 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 288 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 289 [STATIC_MAC_TABLE_OVERRIDE] = BIT(26), 290 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(24, 20), 291 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 292 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(8), 293 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 294 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 295 [DYNAMIC_MAC_TABLE_FID] = GENMASK(26, 20), 296 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 297 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 298 [P_MII_TX_FLOW_CTRL] = BIT(5), 299 [P_MII_RX_FLOW_CTRL] = BIT(5), 300 }; 301 302 static const u8 ksz8795_xmii_ctrl0[] = { 303 [P_MII_100MBIT] = 0, 304 [P_MII_10MBIT] = 1, 305 [P_MII_FULL_DUPLEX] = 0, 306 [P_MII_HALF_DUPLEX] = 1, 307 }; 308 309 static const u8 ksz8795_xmii_ctrl1[] = { 310 [P_RGMII_SEL] = 3, 311 [P_GMII_SEL] = 2, 312 [P_RMII_SEL] = 1, 313 [P_MII_SEL] = 0, 314 [P_GMII_1GBIT] = 1, 315 [P_GMII_NOT_1GBIT] = 0, 316 }; 317 318 static const u8 ksz8795_shifts[] = { 319 [VLAN_TABLE_MEMBERSHIP_S] = 7, 320 [VLAN_TABLE] = 16, 321 [STATIC_MAC_FWD_PORTS] = 16, 322 [STATIC_MAC_FID] = 24, 323 [DYNAMIC_MAC_ENTRIES_H] = 3, 324 [DYNAMIC_MAC_ENTRIES] = 29, 325 [DYNAMIC_MAC_FID] = 16, 326 [DYNAMIC_MAC_TIMESTAMP] = 27, 327 [DYNAMIC_MAC_SRC_PORT] = 24, 328 }; 329 330 static const u16 ksz8863_regs[] = { 331 [REG_IND_CTRL_0] = 0x79, 332 [REG_IND_DATA_8] = 0x7B, 333 [REG_IND_DATA_CHECK] = 0x7B, 334 [REG_IND_DATA_HI] = 0x7C, 335 [REG_IND_DATA_LO] = 0x80, 336 [REG_IND_MIB_CHECK] = 0x80, 337 [P_FORCE_CTRL] = 0x0C, 338 [P_LINK_STATUS] = 0x0E, 339 [P_LOCAL_CTRL] = 0x0C, 340 [P_NEG_RESTART_CTRL] = 0x0D, 341 [P_REMOTE_STATUS] = 0x0E, 342 [P_SPEED_STATUS] = 0x0F, 343 [S_TAIL_TAG_CTRL] = 0x03, 344 [P_STP_CTRL] = 0x02, 345 [S_START_CTRL] = 0x01, 346 [S_BROADCAST_CTRL] = 0x06, 347 [S_MULTICAST_CTRL] = 0x04, 348 }; 349 350 static const u32 ksz8863_masks[] = { 351 [PORT_802_1P_REMAPPING] = BIT(3), 352 [SW_TAIL_TAG_ENABLE] = BIT(6), 353 [MIB_COUNTER_OVERFLOW] = BIT(7), 354 [MIB_COUNTER_VALID] = BIT(6), 355 [VLAN_TABLE_FID] = GENMASK(15, 12), 356 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 357 [VLAN_TABLE_VALID] = BIT(19), 358 [STATIC_MAC_TABLE_VALID] = BIT(19), 359 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 360 [STATIC_MAC_TABLE_FID] = GENMASK(29, 26), 361 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 362 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 363 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(5, 0), 364 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 365 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 366 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 28), 367 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 368 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 369 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 370 }; 371 372 static u8 ksz8863_shifts[] = { 373 [VLAN_TABLE_MEMBERSHIP_S] = 16, 374 [STATIC_MAC_FWD_PORTS] = 16, 375 [STATIC_MAC_FID] = 22, 376 [DYNAMIC_MAC_ENTRIES_H] = 3, 377 [DYNAMIC_MAC_ENTRIES] = 24, 378 [DYNAMIC_MAC_FID] = 16, 379 [DYNAMIC_MAC_TIMESTAMP] = 24, 380 [DYNAMIC_MAC_SRC_PORT] = 20, 381 }; 382 383 static const u16 ksz9477_regs[] = { 384 [P_STP_CTRL] = 0x0B04, 385 [S_START_CTRL] = 0x0300, 386 [S_BROADCAST_CTRL] = 0x0332, 387 [S_MULTICAST_CTRL] = 0x0331, 388 [P_XMII_CTRL_0] = 0x0300, 389 [P_XMII_CTRL_1] = 0x0301, 390 }; 391 392 static const u32 ksz9477_masks[] = { 393 [ALU_STAT_WRITE] = 0, 394 [ALU_STAT_READ] = 1, 395 [P_MII_TX_FLOW_CTRL] = BIT(5), 396 [P_MII_RX_FLOW_CTRL] = BIT(3), 397 }; 398 399 static const u8 ksz9477_shifts[] = { 400 [ALU_STAT_INDEX] = 16, 401 }; 402 403 static const u8 ksz9477_xmii_ctrl0[] = { 404 [P_MII_100MBIT] = 1, 405 [P_MII_10MBIT] = 0, 406 [P_MII_FULL_DUPLEX] = 1, 407 [P_MII_HALF_DUPLEX] = 0, 408 }; 409 410 static const u8 ksz9477_xmii_ctrl1[] = { 411 [P_RGMII_SEL] = 0, 412 [P_RMII_SEL] = 1, 413 [P_GMII_SEL] = 2, 414 [P_MII_SEL] = 3, 415 [P_GMII_1GBIT] = 0, 416 [P_GMII_NOT_1GBIT] = 1, 417 }; 418 419 static const u32 lan937x_masks[] = { 420 [ALU_STAT_WRITE] = 1, 421 [ALU_STAT_READ] = 2, 422 [P_MII_TX_FLOW_CTRL] = BIT(5), 423 [P_MII_RX_FLOW_CTRL] = BIT(3), 424 }; 425 426 static const u8 lan937x_shifts[] = { 427 [ALU_STAT_INDEX] = 8, 428 }; 429 430 static const struct regmap_range ksz8563_valid_regs[] = { 431 regmap_reg_range(0x0000, 0x0003), 432 regmap_reg_range(0x0006, 0x0006), 433 regmap_reg_range(0x000f, 0x001f), 434 regmap_reg_range(0x0100, 0x0100), 435 regmap_reg_range(0x0104, 0x0107), 436 regmap_reg_range(0x010d, 0x010d), 437 regmap_reg_range(0x0110, 0x0113), 438 regmap_reg_range(0x0120, 0x012b), 439 regmap_reg_range(0x0201, 0x0201), 440 regmap_reg_range(0x0210, 0x0213), 441 regmap_reg_range(0x0300, 0x0300), 442 regmap_reg_range(0x0302, 0x031b), 443 regmap_reg_range(0x0320, 0x032b), 444 regmap_reg_range(0x0330, 0x0336), 445 regmap_reg_range(0x0338, 0x033e), 446 regmap_reg_range(0x0340, 0x035f), 447 regmap_reg_range(0x0370, 0x0370), 448 regmap_reg_range(0x0378, 0x0378), 449 regmap_reg_range(0x037c, 0x037d), 450 regmap_reg_range(0x0390, 0x0393), 451 regmap_reg_range(0x0400, 0x040e), 452 regmap_reg_range(0x0410, 0x042f), 453 regmap_reg_range(0x0500, 0x0519), 454 regmap_reg_range(0x0520, 0x054b), 455 regmap_reg_range(0x0550, 0x05b3), 456 457 /* port 1 */ 458 regmap_reg_range(0x1000, 0x1001), 459 regmap_reg_range(0x1004, 0x100b), 460 regmap_reg_range(0x1013, 0x1013), 461 regmap_reg_range(0x1017, 0x1017), 462 regmap_reg_range(0x101b, 0x101b), 463 regmap_reg_range(0x101f, 0x1021), 464 regmap_reg_range(0x1030, 0x1030), 465 regmap_reg_range(0x1100, 0x1111), 466 regmap_reg_range(0x111a, 0x111d), 467 regmap_reg_range(0x1122, 0x1127), 468 regmap_reg_range(0x112a, 0x112b), 469 regmap_reg_range(0x1136, 0x1139), 470 regmap_reg_range(0x113e, 0x113f), 471 regmap_reg_range(0x1400, 0x1401), 472 regmap_reg_range(0x1403, 0x1403), 473 regmap_reg_range(0x1410, 0x1417), 474 regmap_reg_range(0x1420, 0x1423), 475 regmap_reg_range(0x1500, 0x1507), 476 regmap_reg_range(0x1600, 0x1612), 477 regmap_reg_range(0x1800, 0x180f), 478 regmap_reg_range(0x1900, 0x1907), 479 regmap_reg_range(0x1914, 0x191b), 480 regmap_reg_range(0x1a00, 0x1a03), 481 regmap_reg_range(0x1a04, 0x1a08), 482 regmap_reg_range(0x1b00, 0x1b01), 483 regmap_reg_range(0x1b04, 0x1b04), 484 regmap_reg_range(0x1c00, 0x1c05), 485 regmap_reg_range(0x1c08, 0x1c1b), 486 487 /* port 2 */ 488 regmap_reg_range(0x2000, 0x2001), 489 regmap_reg_range(0x2004, 0x200b), 490 regmap_reg_range(0x2013, 0x2013), 491 regmap_reg_range(0x2017, 0x2017), 492 regmap_reg_range(0x201b, 0x201b), 493 regmap_reg_range(0x201f, 0x2021), 494 regmap_reg_range(0x2030, 0x2030), 495 regmap_reg_range(0x2100, 0x2111), 496 regmap_reg_range(0x211a, 0x211d), 497 regmap_reg_range(0x2122, 0x2127), 498 regmap_reg_range(0x212a, 0x212b), 499 regmap_reg_range(0x2136, 0x2139), 500 regmap_reg_range(0x213e, 0x213f), 501 regmap_reg_range(0x2400, 0x2401), 502 regmap_reg_range(0x2403, 0x2403), 503 regmap_reg_range(0x2410, 0x2417), 504 regmap_reg_range(0x2420, 0x2423), 505 regmap_reg_range(0x2500, 0x2507), 506 regmap_reg_range(0x2600, 0x2612), 507 regmap_reg_range(0x2800, 0x280f), 508 regmap_reg_range(0x2900, 0x2907), 509 regmap_reg_range(0x2914, 0x291b), 510 regmap_reg_range(0x2a00, 0x2a03), 511 regmap_reg_range(0x2a04, 0x2a08), 512 regmap_reg_range(0x2b00, 0x2b01), 513 regmap_reg_range(0x2b04, 0x2b04), 514 regmap_reg_range(0x2c00, 0x2c05), 515 regmap_reg_range(0x2c08, 0x2c1b), 516 517 /* port 3 */ 518 regmap_reg_range(0x3000, 0x3001), 519 regmap_reg_range(0x3004, 0x300b), 520 regmap_reg_range(0x3013, 0x3013), 521 regmap_reg_range(0x3017, 0x3017), 522 regmap_reg_range(0x301b, 0x301b), 523 regmap_reg_range(0x301f, 0x3021), 524 regmap_reg_range(0x3030, 0x3030), 525 regmap_reg_range(0x3300, 0x3301), 526 regmap_reg_range(0x3303, 0x3303), 527 regmap_reg_range(0x3400, 0x3401), 528 regmap_reg_range(0x3403, 0x3403), 529 regmap_reg_range(0x3410, 0x3417), 530 regmap_reg_range(0x3420, 0x3423), 531 regmap_reg_range(0x3500, 0x3507), 532 regmap_reg_range(0x3600, 0x3612), 533 regmap_reg_range(0x3800, 0x380f), 534 regmap_reg_range(0x3900, 0x3907), 535 regmap_reg_range(0x3914, 0x391b), 536 regmap_reg_range(0x3a00, 0x3a03), 537 regmap_reg_range(0x3a04, 0x3a08), 538 regmap_reg_range(0x3b00, 0x3b01), 539 regmap_reg_range(0x3b04, 0x3b04), 540 regmap_reg_range(0x3c00, 0x3c05), 541 regmap_reg_range(0x3c08, 0x3c1b), 542 }; 543 544 static const struct regmap_access_table ksz8563_register_set = { 545 .yes_ranges = ksz8563_valid_regs, 546 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), 547 }; 548 549 static const struct regmap_range ksz9477_valid_regs[] = { 550 regmap_reg_range(0x0000, 0x0003), 551 regmap_reg_range(0x0006, 0x0006), 552 regmap_reg_range(0x0010, 0x001f), 553 regmap_reg_range(0x0100, 0x0100), 554 regmap_reg_range(0x0103, 0x0107), 555 regmap_reg_range(0x010d, 0x010d), 556 regmap_reg_range(0x0110, 0x0113), 557 regmap_reg_range(0x0120, 0x012b), 558 regmap_reg_range(0x0201, 0x0201), 559 regmap_reg_range(0x0210, 0x0213), 560 regmap_reg_range(0x0300, 0x0300), 561 regmap_reg_range(0x0302, 0x031b), 562 regmap_reg_range(0x0320, 0x032b), 563 regmap_reg_range(0x0330, 0x0336), 564 regmap_reg_range(0x0338, 0x033b), 565 regmap_reg_range(0x033e, 0x033e), 566 regmap_reg_range(0x0340, 0x035f), 567 regmap_reg_range(0x0370, 0x0370), 568 regmap_reg_range(0x0378, 0x0378), 569 regmap_reg_range(0x037c, 0x037d), 570 regmap_reg_range(0x0390, 0x0393), 571 regmap_reg_range(0x0400, 0x040e), 572 regmap_reg_range(0x0410, 0x042f), 573 regmap_reg_range(0x0444, 0x044b), 574 regmap_reg_range(0x0450, 0x046f), 575 regmap_reg_range(0x0500, 0x0519), 576 regmap_reg_range(0x0520, 0x054b), 577 regmap_reg_range(0x0550, 0x05b3), 578 regmap_reg_range(0x0604, 0x060b), 579 regmap_reg_range(0x0610, 0x0612), 580 regmap_reg_range(0x0614, 0x062c), 581 regmap_reg_range(0x0640, 0x0645), 582 regmap_reg_range(0x0648, 0x064d), 583 584 /* port 1 */ 585 regmap_reg_range(0x1000, 0x1001), 586 regmap_reg_range(0x1013, 0x1013), 587 regmap_reg_range(0x1017, 0x1017), 588 regmap_reg_range(0x101b, 0x101b), 589 regmap_reg_range(0x101f, 0x1020), 590 regmap_reg_range(0x1030, 0x1030), 591 regmap_reg_range(0x1100, 0x1115), 592 regmap_reg_range(0x111a, 0x111f), 593 regmap_reg_range(0x1122, 0x1127), 594 regmap_reg_range(0x112a, 0x112b), 595 regmap_reg_range(0x1136, 0x1139), 596 regmap_reg_range(0x113e, 0x113f), 597 regmap_reg_range(0x1400, 0x1401), 598 regmap_reg_range(0x1403, 0x1403), 599 regmap_reg_range(0x1410, 0x1417), 600 regmap_reg_range(0x1420, 0x1423), 601 regmap_reg_range(0x1500, 0x1507), 602 regmap_reg_range(0x1600, 0x1613), 603 regmap_reg_range(0x1800, 0x180f), 604 regmap_reg_range(0x1820, 0x1827), 605 regmap_reg_range(0x1830, 0x1837), 606 regmap_reg_range(0x1840, 0x184b), 607 regmap_reg_range(0x1900, 0x1907), 608 regmap_reg_range(0x1914, 0x191b), 609 regmap_reg_range(0x1920, 0x1920), 610 regmap_reg_range(0x1923, 0x1927), 611 regmap_reg_range(0x1a00, 0x1a03), 612 regmap_reg_range(0x1a04, 0x1a07), 613 regmap_reg_range(0x1b00, 0x1b01), 614 regmap_reg_range(0x1b04, 0x1b04), 615 regmap_reg_range(0x1c00, 0x1c05), 616 regmap_reg_range(0x1c08, 0x1c1b), 617 618 /* port 2 */ 619 regmap_reg_range(0x2000, 0x2001), 620 regmap_reg_range(0x2013, 0x2013), 621 regmap_reg_range(0x2017, 0x2017), 622 regmap_reg_range(0x201b, 0x201b), 623 regmap_reg_range(0x201f, 0x2020), 624 regmap_reg_range(0x2030, 0x2030), 625 regmap_reg_range(0x2100, 0x2115), 626 regmap_reg_range(0x211a, 0x211f), 627 regmap_reg_range(0x2122, 0x2127), 628 regmap_reg_range(0x212a, 0x212b), 629 regmap_reg_range(0x2136, 0x2139), 630 regmap_reg_range(0x213e, 0x213f), 631 regmap_reg_range(0x2400, 0x2401), 632 regmap_reg_range(0x2403, 0x2403), 633 regmap_reg_range(0x2410, 0x2417), 634 regmap_reg_range(0x2420, 0x2423), 635 regmap_reg_range(0x2500, 0x2507), 636 regmap_reg_range(0x2600, 0x2613), 637 regmap_reg_range(0x2800, 0x280f), 638 regmap_reg_range(0x2820, 0x2827), 639 regmap_reg_range(0x2830, 0x2837), 640 regmap_reg_range(0x2840, 0x284b), 641 regmap_reg_range(0x2900, 0x2907), 642 regmap_reg_range(0x2914, 0x291b), 643 regmap_reg_range(0x2920, 0x2920), 644 regmap_reg_range(0x2923, 0x2927), 645 regmap_reg_range(0x2a00, 0x2a03), 646 regmap_reg_range(0x2a04, 0x2a07), 647 regmap_reg_range(0x2b00, 0x2b01), 648 regmap_reg_range(0x2b04, 0x2b04), 649 regmap_reg_range(0x2c00, 0x2c05), 650 regmap_reg_range(0x2c08, 0x2c1b), 651 652 /* port 3 */ 653 regmap_reg_range(0x3000, 0x3001), 654 regmap_reg_range(0x3013, 0x3013), 655 regmap_reg_range(0x3017, 0x3017), 656 regmap_reg_range(0x301b, 0x301b), 657 regmap_reg_range(0x301f, 0x3020), 658 regmap_reg_range(0x3030, 0x3030), 659 regmap_reg_range(0x3100, 0x3115), 660 regmap_reg_range(0x311a, 0x311f), 661 regmap_reg_range(0x3122, 0x3127), 662 regmap_reg_range(0x312a, 0x312b), 663 regmap_reg_range(0x3136, 0x3139), 664 regmap_reg_range(0x313e, 0x313f), 665 regmap_reg_range(0x3400, 0x3401), 666 regmap_reg_range(0x3403, 0x3403), 667 regmap_reg_range(0x3410, 0x3417), 668 regmap_reg_range(0x3420, 0x3423), 669 regmap_reg_range(0x3500, 0x3507), 670 regmap_reg_range(0x3600, 0x3613), 671 regmap_reg_range(0x3800, 0x380f), 672 regmap_reg_range(0x3820, 0x3827), 673 regmap_reg_range(0x3830, 0x3837), 674 regmap_reg_range(0x3840, 0x384b), 675 regmap_reg_range(0x3900, 0x3907), 676 regmap_reg_range(0x3914, 0x391b), 677 regmap_reg_range(0x3920, 0x3920), 678 regmap_reg_range(0x3923, 0x3927), 679 regmap_reg_range(0x3a00, 0x3a03), 680 regmap_reg_range(0x3a04, 0x3a07), 681 regmap_reg_range(0x3b00, 0x3b01), 682 regmap_reg_range(0x3b04, 0x3b04), 683 regmap_reg_range(0x3c00, 0x3c05), 684 regmap_reg_range(0x3c08, 0x3c1b), 685 686 /* port 4 */ 687 regmap_reg_range(0x4000, 0x4001), 688 regmap_reg_range(0x4013, 0x4013), 689 regmap_reg_range(0x4017, 0x4017), 690 regmap_reg_range(0x401b, 0x401b), 691 regmap_reg_range(0x401f, 0x4020), 692 regmap_reg_range(0x4030, 0x4030), 693 regmap_reg_range(0x4100, 0x4115), 694 regmap_reg_range(0x411a, 0x411f), 695 regmap_reg_range(0x4122, 0x4127), 696 regmap_reg_range(0x412a, 0x412b), 697 regmap_reg_range(0x4136, 0x4139), 698 regmap_reg_range(0x413e, 0x413f), 699 regmap_reg_range(0x4400, 0x4401), 700 regmap_reg_range(0x4403, 0x4403), 701 regmap_reg_range(0x4410, 0x4417), 702 regmap_reg_range(0x4420, 0x4423), 703 regmap_reg_range(0x4500, 0x4507), 704 regmap_reg_range(0x4600, 0x4613), 705 regmap_reg_range(0x4800, 0x480f), 706 regmap_reg_range(0x4820, 0x4827), 707 regmap_reg_range(0x4830, 0x4837), 708 regmap_reg_range(0x4840, 0x484b), 709 regmap_reg_range(0x4900, 0x4907), 710 regmap_reg_range(0x4914, 0x491b), 711 regmap_reg_range(0x4920, 0x4920), 712 regmap_reg_range(0x4923, 0x4927), 713 regmap_reg_range(0x4a00, 0x4a03), 714 regmap_reg_range(0x4a04, 0x4a07), 715 regmap_reg_range(0x4b00, 0x4b01), 716 regmap_reg_range(0x4b04, 0x4b04), 717 regmap_reg_range(0x4c00, 0x4c05), 718 regmap_reg_range(0x4c08, 0x4c1b), 719 720 /* port 5 */ 721 regmap_reg_range(0x5000, 0x5001), 722 regmap_reg_range(0x5013, 0x5013), 723 regmap_reg_range(0x5017, 0x5017), 724 regmap_reg_range(0x501b, 0x501b), 725 regmap_reg_range(0x501f, 0x5020), 726 regmap_reg_range(0x5030, 0x5030), 727 regmap_reg_range(0x5100, 0x5115), 728 regmap_reg_range(0x511a, 0x511f), 729 regmap_reg_range(0x5122, 0x5127), 730 regmap_reg_range(0x512a, 0x512b), 731 regmap_reg_range(0x5136, 0x5139), 732 regmap_reg_range(0x513e, 0x513f), 733 regmap_reg_range(0x5400, 0x5401), 734 regmap_reg_range(0x5403, 0x5403), 735 regmap_reg_range(0x5410, 0x5417), 736 regmap_reg_range(0x5420, 0x5423), 737 regmap_reg_range(0x5500, 0x5507), 738 regmap_reg_range(0x5600, 0x5613), 739 regmap_reg_range(0x5800, 0x580f), 740 regmap_reg_range(0x5820, 0x5827), 741 regmap_reg_range(0x5830, 0x5837), 742 regmap_reg_range(0x5840, 0x584b), 743 regmap_reg_range(0x5900, 0x5907), 744 regmap_reg_range(0x5914, 0x591b), 745 regmap_reg_range(0x5920, 0x5920), 746 regmap_reg_range(0x5923, 0x5927), 747 regmap_reg_range(0x5a00, 0x5a03), 748 regmap_reg_range(0x5a04, 0x5a07), 749 regmap_reg_range(0x5b00, 0x5b01), 750 regmap_reg_range(0x5b04, 0x5b04), 751 regmap_reg_range(0x5c00, 0x5c05), 752 regmap_reg_range(0x5c08, 0x5c1b), 753 754 /* port 6 */ 755 regmap_reg_range(0x6000, 0x6001), 756 regmap_reg_range(0x6013, 0x6013), 757 regmap_reg_range(0x6017, 0x6017), 758 regmap_reg_range(0x601b, 0x601b), 759 regmap_reg_range(0x601f, 0x6020), 760 regmap_reg_range(0x6030, 0x6030), 761 regmap_reg_range(0x6300, 0x6301), 762 regmap_reg_range(0x6400, 0x6401), 763 regmap_reg_range(0x6403, 0x6403), 764 regmap_reg_range(0x6410, 0x6417), 765 regmap_reg_range(0x6420, 0x6423), 766 regmap_reg_range(0x6500, 0x6507), 767 regmap_reg_range(0x6600, 0x6613), 768 regmap_reg_range(0x6800, 0x680f), 769 regmap_reg_range(0x6820, 0x6827), 770 regmap_reg_range(0x6830, 0x6837), 771 regmap_reg_range(0x6840, 0x684b), 772 regmap_reg_range(0x6900, 0x6907), 773 regmap_reg_range(0x6914, 0x691b), 774 regmap_reg_range(0x6920, 0x6920), 775 regmap_reg_range(0x6923, 0x6927), 776 regmap_reg_range(0x6a00, 0x6a03), 777 regmap_reg_range(0x6a04, 0x6a07), 778 regmap_reg_range(0x6b00, 0x6b01), 779 regmap_reg_range(0x6b04, 0x6b04), 780 regmap_reg_range(0x6c00, 0x6c05), 781 regmap_reg_range(0x6c08, 0x6c1b), 782 783 /* port 7 */ 784 regmap_reg_range(0x7000, 0x7001), 785 regmap_reg_range(0x7013, 0x7013), 786 regmap_reg_range(0x7017, 0x7017), 787 regmap_reg_range(0x701b, 0x701b), 788 regmap_reg_range(0x701f, 0x7020), 789 regmap_reg_range(0x7030, 0x7030), 790 regmap_reg_range(0x7200, 0x7203), 791 regmap_reg_range(0x7206, 0x7207), 792 regmap_reg_range(0x7300, 0x7301), 793 regmap_reg_range(0x7400, 0x7401), 794 regmap_reg_range(0x7403, 0x7403), 795 regmap_reg_range(0x7410, 0x7417), 796 regmap_reg_range(0x7420, 0x7423), 797 regmap_reg_range(0x7500, 0x7507), 798 regmap_reg_range(0x7600, 0x7613), 799 regmap_reg_range(0x7800, 0x780f), 800 regmap_reg_range(0x7820, 0x7827), 801 regmap_reg_range(0x7830, 0x7837), 802 regmap_reg_range(0x7840, 0x784b), 803 regmap_reg_range(0x7900, 0x7907), 804 regmap_reg_range(0x7914, 0x791b), 805 regmap_reg_range(0x7920, 0x7920), 806 regmap_reg_range(0x7923, 0x7927), 807 regmap_reg_range(0x7a00, 0x7a03), 808 regmap_reg_range(0x7a04, 0x7a07), 809 regmap_reg_range(0x7b00, 0x7b01), 810 regmap_reg_range(0x7b04, 0x7b04), 811 regmap_reg_range(0x7c00, 0x7c05), 812 regmap_reg_range(0x7c08, 0x7c1b), 813 }; 814 815 static const struct regmap_access_table ksz9477_register_set = { 816 .yes_ranges = ksz9477_valid_regs, 817 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), 818 }; 819 820 static const struct regmap_range ksz9896_valid_regs[] = { 821 regmap_reg_range(0x0000, 0x0003), 822 regmap_reg_range(0x0006, 0x0006), 823 regmap_reg_range(0x0010, 0x001f), 824 regmap_reg_range(0x0100, 0x0100), 825 regmap_reg_range(0x0103, 0x0107), 826 regmap_reg_range(0x010d, 0x010d), 827 regmap_reg_range(0x0110, 0x0113), 828 regmap_reg_range(0x0120, 0x0127), 829 regmap_reg_range(0x0201, 0x0201), 830 regmap_reg_range(0x0210, 0x0213), 831 regmap_reg_range(0x0300, 0x0300), 832 regmap_reg_range(0x0302, 0x030b), 833 regmap_reg_range(0x0310, 0x031b), 834 regmap_reg_range(0x0320, 0x032b), 835 regmap_reg_range(0x0330, 0x0336), 836 regmap_reg_range(0x0338, 0x033b), 837 regmap_reg_range(0x033e, 0x033e), 838 regmap_reg_range(0x0340, 0x035f), 839 regmap_reg_range(0x0370, 0x0370), 840 regmap_reg_range(0x0378, 0x0378), 841 regmap_reg_range(0x037c, 0x037d), 842 regmap_reg_range(0x0390, 0x0393), 843 regmap_reg_range(0x0400, 0x040e), 844 regmap_reg_range(0x0410, 0x042f), 845 846 /* port 1 */ 847 regmap_reg_range(0x1000, 0x1001), 848 regmap_reg_range(0x1013, 0x1013), 849 regmap_reg_range(0x1017, 0x1017), 850 regmap_reg_range(0x101b, 0x101b), 851 regmap_reg_range(0x101f, 0x1020), 852 regmap_reg_range(0x1030, 0x1030), 853 regmap_reg_range(0x1100, 0x1115), 854 regmap_reg_range(0x111a, 0x111f), 855 regmap_reg_range(0x1122, 0x1127), 856 regmap_reg_range(0x112a, 0x112b), 857 regmap_reg_range(0x1136, 0x1139), 858 regmap_reg_range(0x113e, 0x113f), 859 regmap_reg_range(0x1400, 0x1401), 860 regmap_reg_range(0x1403, 0x1403), 861 regmap_reg_range(0x1410, 0x1417), 862 regmap_reg_range(0x1420, 0x1423), 863 regmap_reg_range(0x1500, 0x1507), 864 regmap_reg_range(0x1600, 0x1612), 865 regmap_reg_range(0x1800, 0x180f), 866 regmap_reg_range(0x1820, 0x1827), 867 regmap_reg_range(0x1830, 0x1837), 868 regmap_reg_range(0x1840, 0x184b), 869 regmap_reg_range(0x1900, 0x1907), 870 regmap_reg_range(0x1914, 0x1915), 871 regmap_reg_range(0x1a00, 0x1a03), 872 regmap_reg_range(0x1a04, 0x1a07), 873 regmap_reg_range(0x1b00, 0x1b01), 874 regmap_reg_range(0x1b04, 0x1b04), 875 876 /* port 2 */ 877 regmap_reg_range(0x2000, 0x2001), 878 regmap_reg_range(0x2013, 0x2013), 879 regmap_reg_range(0x2017, 0x2017), 880 regmap_reg_range(0x201b, 0x201b), 881 regmap_reg_range(0x201f, 0x2020), 882 regmap_reg_range(0x2030, 0x2030), 883 regmap_reg_range(0x2100, 0x2115), 884 regmap_reg_range(0x211a, 0x211f), 885 regmap_reg_range(0x2122, 0x2127), 886 regmap_reg_range(0x212a, 0x212b), 887 regmap_reg_range(0x2136, 0x2139), 888 regmap_reg_range(0x213e, 0x213f), 889 regmap_reg_range(0x2400, 0x2401), 890 regmap_reg_range(0x2403, 0x2403), 891 regmap_reg_range(0x2410, 0x2417), 892 regmap_reg_range(0x2420, 0x2423), 893 regmap_reg_range(0x2500, 0x2507), 894 regmap_reg_range(0x2600, 0x2612), 895 regmap_reg_range(0x2800, 0x280f), 896 regmap_reg_range(0x2820, 0x2827), 897 regmap_reg_range(0x2830, 0x2837), 898 regmap_reg_range(0x2840, 0x284b), 899 regmap_reg_range(0x2900, 0x2907), 900 regmap_reg_range(0x2914, 0x2915), 901 regmap_reg_range(0x2a00, 0x2a03), 902 regmap_reg_range(0x2a04, 0x2a07), 903 regmap_reg_range(0x2b00, 0x2b01), 904 regmap_reg_range(0x2b04, 0x2b04), 905 906 /* port 3 */ 907 regmap_reg_range(0x3000, 0x3001), 908 regmap_reg_range(0x3013, 0x3013), 909 regmap_reg_range(0x3017, 0x3017), 910 regmap_reg_range(0x301b, 0x301b), 911 regmap_reg_range(0x301f, 0x3020), 912 regmap_reg_range(0x3030, 0x3030), 913 regmap_reg_range(0x3100, 0x3115), 914 regmap_reg_range(0x311a, 0x311f), 915 regmap_reg_range(0x3122, 0x3127), 916 regmap_reg_range(0x312a, 0x312b), 917 regmap_reg_range(0x3136, 0x3139), 918 regmap_reg_range(0x313e, 0x313f), 919 regmap_reg_range(0x3400, 0x3401), 920 regmap_reg_range(0x3403, 0x3403), 921 regmap_reg_range(0x3410, 0x3417), 922 regmap_reg_range(0x3420, 0x3423), 923 regmap_reg_range(0x3500, 0x3507), 924 regmap_reg_range(0x3600, 0x3612), 925 regmap_reg_range(0x3800, 0x380f), 926 regmap_reg_range(0x3820, 0x3827), 927 regmap_reg_range(0x3830, 0x3837), 928 regmap_reg_range(0x3840, 0x384b), 929 regmap_reg_range(0x3900, 0x3907), 930 regmap_reg_range(0x3914, 0x3915), 931 regmap_reg_range(0x3a00, 0x3a03), 932 regmap_reg_range(0x3a04, 0x3a07), 933 regmap_reg_range(0x3b00, 0x3b01), 934 regmap_reg_range(0x3b04, 0x3b04), 935 936 /* port 4 */ 937 regmap_reg_range(0x4000, 0x4001), 938 regmap_reg_range(0x4013, 0x4013), 939 regmap_reg_range(0x4017, 0x4017), 940 regmap_reg_range(0x401b, 0x401b), 941 regmap_reg_range(0x401f, 0x4020), 942 regmap_reg_range(0x4030, 0x4030), 943 regmap_reg_range(0x4100, 0x4115), 944 regmap_reg_range(0x411a, 0x411f), 945 regmap_reg_range(0x4122, 0x4127), 946 regmap_reg_range(0x412a, 0x412b), 947 regmap_reg_range(0x4136, 0x4139), 948 regmap_reg_range(0x413e, 0x413f), 949 regmap_reg_range(0x4400, 0x4401), 950 regmap_reg_range(0x4403, 0x4403), 951 regmap_reg_range(0x4410, 0x4417), 952 regmap_reg_range(0x4420, 0x4423), 953 regmap_reg_range(0x4500, 0x4507), 954 regmap_reg_range(0x4600, 0x4612), 955 regmap_reg_range(0x4800, 0x480f), 956 regmap_reg_range(0x4820, 0x4827), 957 regmap_reg_range(0x4830, 0x4837), 958 regmap_reg_range(0x4840, 0x484b), 959 regmap_reg_range(0x4900, 0x4907), 960 regmap_reg_range(0x4914, 0x4915), 961 regmap_reg_range(0x4a00, 0x4a03), 962 regmap_reg_range(0x4a04, 0x4a07), 963 regmap_reg_range(0x4b00, 0x4b01), 964 regmap_reg_range(0x4b04, 0x4b04), 965 966 /* port 5 */ 967 regmap_reg_range(0x5000, 0x5001), 968 regmap_reg_range(0x5013, 0x5013), 969 regmap_reg_range(0x5017, 0x5017), 970 regmap_reg_range(0x501b, 0x501b), 971 regmap_reg_range(0x501f, 0x5020), 972 regmap_reg_range(0x5030, 0x5030), 973 regmap_reg_range(0x5100, 0x5115), 974 regmap_reg_range(0x511a, 0x511f), 975 regmap_reg_range(0x5122, 0x5127), 976 regmap_reg_range(0x512a, 0x512b), 977 regmap_reg_range(0x5136, 0x5139), 978 regmap_reg_range(0x513e, 0x513f), 979 regmap_reg_range(0x5400, 0x5401), 980 regmap_reg_range(0x5403, 0x5403), 981 regmap_reg_range(0x5410, 0x5417), 982 regmap_reg_range(0x5420, 0x5423), 983 regmap_reg_range(0x5500, 0x5507), 984 regmap_reg_range(0x5600, 0x5612), 985 regmap_reg_range(0x5800, 0x580f), 986 regmap_reg_range(0x5820, 0x5827), 987 regmap_reg_range(0x5830, 0x5837), 988 regmap_reg_range(0x5840, 0x584b), 989 regmap_reg_range(0x5900, 0x5907), 990 regmap_reg_range(0x5914, 0x5915), 991 regmap_reg_range(0x5a00, 0x5a03), 992 regmap_reg_range(0x5a04, 0x5a07), 993 regmap_reg_range(0x5b00, 0x5b01), 994 regmap_reg_range(0x5b04, 0x5b04), 995 996 /* port 6 */ 997 regmap_reg_range(0x6000, 0x6001), 998 regmap_reg_range(0x6013, 0x6013), 999 regmap_reg_range(0x6017, 0x6017), 1000 regmap_reg_range(0x601b, 0x601b), 1001 regmap_reg_range(0x601f, 0x6020), 1002 regmap_reg_range(0x6030, 0x6030), 1003 regmap_reg_range(0x6100, 0x6115), 1004 regmap_reg_range(0x611a, 0x611f), 1005 regmap_reg_range(0x6122, 0x6127), 1006 regmap_reg_range(0x612a, 0x612b), 1007 regmap_reg_range(0x6136, 0x6139), 1008 regmap_reg_range(0x613e, 0x613f), 1009 regmap_reg_range(0x6300, 0x6301), 1010 regmap_reg_range(0x6400, 0x6401), 1011 regmap_reg_range(0x6403, 0x6403), 1012 regmap_reg_range(0x6410, 0x6417), 1013 regmap_reg_range(0x6420, 0x6423), 1014 regmap_reg_range(0x6500, 0x6507), 1015 regmap_reg_range(0x6600, 0x6612), 1016 regmap_reg_range(0x6800, 0x680f), 1017 regmap_reg_range(0x6820, 0x6827), 1018 regmap_reg_range(0x6830, 0x6837), 1019 regmap_reg_range(0x6840, 0x684b), 1020 regmap_reg_range(0x6900, 0x6907), 1021 regmap_reg_range(0x6914, 0x6915), 1022 regmap_reg_range(0x6a00, 0x6a03), 1023 regmap_reg_range(0x6a04, 0x6a07), 1024 regmap_reg_range(0x6b00, 0x6b01), 1025 regmap_reg_range(0x6b04, 0x6b04), 1026 }; 1027 1028 static const struct regmap_access_table ksz9896_register_set = { 1029 .yes_ranges = ksz9896_valid_regs, 1030 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs), 1031 }; 1032 1033 const struct ksz_chip_data ksz_switch_chips[] = { 1034 [KSZ8563] = { 1035 .chip_id = KSZ8563_CHIP_ID, 1036 .dev_name = "KSZ8563", 1037 .num_vlans = 4096, 1038 .num_alus = 4096, 1039 .num_statics = 16, 1040 .cpu_ports = 0x07, /* can be configured as cpu port */ 1041 .port_cnt = 3, /* total port count */ 1042 .ops = &ksz9477_dev_ops, 1043 .mib_names = ksz9477_mib_names, 1044 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1045 .reg_mib_cnt = MIB_COUNTER_NUM, 1046 .regs = ksz9477_regs, 1047 .masks = ksz9477_masks, 1048 .shifts = ksz9477_shifts, 1049 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1050 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1051 .supports_mii = {false, false, true}, 1052 .supports_rmii = {false, false, true}, 1053 .supports_rgmii = {false, false, true}, 1054 .internal_phy = {true, true, false}, 1055 .gbit_capable = {false, false, true}, 1056 .wr_table = &ksz8563_register_set, 1057 .rd_table = &ksz8563_register_set, 1058 }, 1059 1060 [KSZ8795] = { 1061 .chip_id = KSZ8795_CHIP_ID, 1062 .dev_name = "KSZ8795", 1063 .num_vlans = 4096, 1064 .num_alus = 0, 1065 .num_statics = 8, 1066 .cpu_ports = 0x10, /* can be configured as cpu port */ 1067 .port_cnt = 5, /* total cpu and user ports */ 1068 .ops = &ksz8_dev_ops, 1069 .ksz87xx_eee_link_erratum = true, 1070 .mib_names = ksz9477_mib_names, 1071 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1072 .reg_mib_cnt = MIB_COUNTER_NUM, 1073 .regs = ksz8795_regs, 1074 .masks = ksz8795_masks, 1075 .shifts = ksz8795_shifts, 1076 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1077 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1078 .supports_mii = {false, false, false, false, true}, 1079 .supports_rmii = {false, false, false, false, true}, 1080 .supports_rgmii = {false, false, false, false, true}, 1081 .internal_phy = {true, true, true, true, false}, 1082 }, 1083 1084 [KSZ8794] = { 1085 /* WARNING 1086 * ======= 1087 * KSZ8794 is similar to KSZ8795, except the port map 1088 * contains a gap between external and CPU ports, the 1089 * port map is NOT continuous. The per-port register 1090 * map is shifted accordingly too, i.e. registers at 1091 * offset 0x40 are NOT used on KSZ8794 and they ARE 1092 * used on KSZ8795 for external port 3. 1093 * external cpu 1094 * KSZ8794 0,1,2 4 1095 * KSZ8795 0,1,2,3 4 1096 * KSZ8765 0,1,2,3 4 1097 * port_cnt is configured as 5, even though it is 4 1098 */ 1099 .chip_id = KSZ8794_CHIP_ID, 1100 .dev_name = "KSZ8794", 1101 .num_vlans = 4096, 1102 .num_alus = 0, 1103 .num_statics = 8, 1104 .cpu_ports = 0x10, /* can be configured as cpu port */ 1105 .port_cnt = 5, /* total cpu and user ports */ 1106 .ops = &ksz8_dev_ops, 1107 .ksz87xx_eee_link_erratum = true, 1108 .mib_names = ksz9477_mib_names, 1109 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1110 .reg_mib_cnt = MIB_COUNTER_NUM, 1111 .regs = ksz8795_regs, 1112 .masks = ksz8795_masks, 1113 .shifts = ksz8795_shifts, 1114 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1115 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1116 .supports_mii = {false, false, false, false, true}, 1117 .supports_rmii = {false, false, false, false, true}, 1118 .supports_rgmii = {false, false, false, false, true}, 1119 .internal_phy = {true, true, true, false, false}, 1120 }, 1121 1122 [KSZ8765] = { 1123 .chip_id = KSZ8765_CHIP_ID, 1124 .dev_name = "KSZ8765", 1125 .num_vlans = 4096, 1126 .num_alus = 0, 1127 .num_statics = 8, 1128 .cpu_ports = 0x10, /* can be configured as cpu port */ 1129 .port_cnt = 5, /* total cpu and user ports */ 1130 .ops = &ksz8_dev_ops, 1131 .ksz87xx_eee_link_erratum = true, 1132 .mib_names = ksz9477_mib_names, 1133 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1134 .reg_mib_cnt = MIB_COUNTER_NUM, 1135 .regs = ksz8795_regs, 1136 .masks = ksz8795_masks, 1137 .shifts = ksz8795_shifts, 1138 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1139 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1140 .supports_mii = {false, false, false, false, true}, 1141 .supports_rmii = {false, false, false, false, true}, 1142 .supports_rgmii = {false, false, false, false, true}, 1143 .internal_phy = {true, true, true, true, false}, 1144 }, 1145 1146 [KSZ8830] = { 1147 .chip_id = KSZ8830_CHIP_ID, 1148 .dev_name = "KSZ8863/KSZ8873", 1149 .num_vlans = 16, 1150 .num_alus = 0, 1151 .num_statics = 8, 1152 .cpu_ports = 0x4, /* can be configured as cpu port */ 1153 .port_cnt = 3, 1154 .ops = &ksz8_dev_ops, 1155 .mib_names = ksz88xx_mib_names, 1156 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1157 .reg_mib_cnt = MIB_COUNTER_NUM, 1158 .regs = ksz8863_regs, 1159 .masks = ksz8863_masks, 1160 .shifts = ksz8863_shifts, 1161 .supports_mii = {false, false, true}, 1162 .supports_rmii = {false, false, true}, 1163 .internal_phy = {true, true, false}, 1164 }, 1165 1166 [KSZ9477] = { 1167 .chip_id = KSZ9477_CHIP_ID, 1168 .dev_name = "KSZ9477", 1169 .num_vlans = 4096, 1170 .num_alus = 4096, 1171 .num_statics = 16, 1172 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1173 .port_cnt = 7, /* total physical port count */ 1174 .port_nirqs = 4, 1175 .ops = &ksz9477_dev_ops, 1176 .phy_errata_9477 = true, 1177 .mib_names = ksz9477_mib_names, 1178 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1179 .reg_mib_cnt = MIB_COUNTER_NUM, 1180 .regs = ksz9477_regs, 1181 .masks = ksz9477_masks, 1182 .shifts = ksz9477_shifts, 1183 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1184 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1185 .supports_mii = {false, false, false, false, 1186 false, true, false}, 1187 .supports_rmii = {false, false, false, false, 1188 false, true, false}, 1189 .supports_rgmii = {false, false, false, false, 1190 false, true, false}, 1191 .internal_phy = {true, true, true, true, 1192 true, false, false}, 1193 .gbit_capable = {true, true, true, true, true, true, true}, 1194 .wr_table = &ksz9477_register_set, 1195 .rd_table = &ksz9477_register_set, 1196 }, 1197 1198 [KSZ9896] = { 1199 .chip_id = KSZ9896_CHIP_ID, 1200 .dev_name = "KSZ9896", 1201 .num_vlans = 4096, 1202 .num_alus = 4096, 1203 .num_statics = 16, 1204 .cpu_ports = 0x3F, /* can be configured as cpu port */ 1205 .port_cnt = 6, /* total physical port count */ 1206 .port_nirqs = 2, 1207 .ops = &ksz9477_dev_ops, 1208 .phy_errata_9477 = true, 1209 .mib_names = ksz9477_mib_names, 1210 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1211 .reg_mib_cnt = MIB_COUNTER_NUM, 1212 .regs = ksz9477_regs, 1213 .masks = ksz9477_masks, 1214 .shifts = ksz9477_shifts, 1215 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1216 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1217 .supports_mii = {false, false, false, false, 1218 false, true}, 1219 .supports_rmii = {false, false, false, false, 1220 false, true}, 1221 .supports_rgmii = {false, false, false, false, 1222 false, true}, 1223 .internal_phy = {true, true, true, true, 1224 true, false}, 1225 .gbit_capable = {true, true, true, true, true, true}, 1226 .wr_table = &ksz9896_register_set, 1227 .rd_table = &ksz9896_register_set, 1228 }, 1229 1230 [KSZ9897] = { 1231 .chip_id = KSZ9897_CHIP_ID, 1232 .dev_name = "KSZ9897", 1233 .num_vlans = 4096, 1234 .num_alus = 4096, 1235 .num_statics = 16, 1236 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1237 .port_cnt = 7, /* total physical port count */ 1238 .port_nirqs = 2, 1239 .ops = &ksz9477_dev_ops, 1240 .phy_errata_9477 = true, 1241 .mib_names = ksz9477_mib_names, 1242 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1243 .reg_mib_cnt = MIB_COUNTER_NUM, 1244 .regs = ksz9477_regs, 1245 .masks = ksz9477_masks, 1246 .shifts = ksz9477_shifts, 1247 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1248 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1249 .supports_mii = {false, false, false, false, 1250 false, true, true}, 1251 .supports_rmii = {false, false, false, false, 1252 false, true, true}, 1253 .supports_rgmii = {false, false, false, false, 1254 false, true, true}, 1255 .internal_phy = {true, true, true, true, 1256 true, false, false}, 1257 .gbit_capable = {true, true, true, true, true, true, true}, 1258 }, 1259 1260 [KSZ9893] = { 1261 .chip_id = KSZ9893_CHIP_ID, 1262 .dev_name = "KSZ9893", 1263 .num_vlans = 4096, 1264 .num_alus = 4096, 1265 .num_statics = 16, 1266 .cpu_ports = 0x07, /* can be configured as cpu port */ 1267 .port_cnt = 3, /* total port count */ 1268 .port_nirqs = 2, 1269 .ops = &ksz9477_dev_ops, 1270 .mib_names = ksz9477_mib_names, 1271 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1272 .reg_mib_cnt = MIB_COUNTER_NUM, 1273 .regs = ksz9477_regs, 1274 .masks = ksz9477_masks, 1275 .shifts = ksz9477_shifts, 1276 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1277 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1278 .supports_mii = {false, false, true}, 1279 .supports_rmii = {false, false, true}, 1280 .supports_rgmii = {false, false, true}, 1281 .internal_phy = {true, true, false}, 1282 .gbit_capable = {true, true, true}, 1283 }, 1284 1285 [KSZ9567] = { 1286 .chip_id = KSZ9567_CHIP_ID, 1287 .dev_name = "KSZ9567", 1288 .num_vlans = 4096, 1289 .num_alus = 4096, 1290 .num_statics = 16, 1291 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1292 .port_cnt = 7, /* total physical port count */ 1293 .port_nirqs = 3, 1294 .ops = &ksz9477_dev_ops, 1295 .phy_errata_9477 = true, 1296 .mib_names = ksz9477_mib_names, 1297 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1298 .reg_mib_cnt = MIB_COUNTER_NUM, 1299 .regs = ksz9477_regs, 1300 .masks = ksz9477_masks, 1301 .shifts = ksz9477_shifts, 1302 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1303 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1304 .supports_mii = {false, false, false, false, 1305 false, true, true}, 1306 .supports_rmii = {false, false, false, false, 1307 false, true, true}, 1308 .supports_rgmii = {false, false, false, false, 1309 false, true, true}, 1310 .internal_phy = {true, true, true, true, 1311 true, false, false}, 1312 .gbit_capable = {true, true, true, true, true, true, true}, 1313 }, 1314 1315 [LAN9370] = { 1316 .chip_id = LAN9370_CHIP_ID, 1317 .dev_name = "LAN9370", 1318 .num_vlans = 4096, 1319 .num_alus = 1024, 1320 .num_statics = 256, 1321 .cpu_ports = 0x10, /* can be configured as cpu port */ 1322 .port_cnt = 5, /* total physical port count */ 1323 .port_nirqs = 6, 1324 .ops = &lan937x_dev_ops, 1325 .mib_names = ksz9477_mib_names, 1326 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1327 .reg_mib_cnt = MIB_COUNTER_NUM, 1328 .regs = ksz9477_regs, 1329 .masks = lan937x_masks, 1330 .shifts = lan937x_shifts, 1331 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1332 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1333 .supports_mii = {false, false, false, false, true}, 1334 .supports_rmii = {false, false, false, false, true}, 1335 .supports_rgmii = {false, false, false, false, true}, 1336 .internal_phy = {true, true, true, true, false}, 1337 }, 1338 1339 [LAN9371] = { 1340 .chip_id = LAN9371_CHIP_ID, 1341 .dev_name = "LAN9371", 1342 .num_vlans = 4096, 1343 .num_alus = 1024, 1344 .num_statics = 256, 1345 .cpu_ports = 0x30, /* can be configured as cpu port */ 1346 .port_cnt = 6, /* total physical port count */ 1347 .port_nirqs = 6, 1348 .ops = &lan937x_dev_ops, 1349 .mib_names = ksz9477_mib_names, 1350 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1351 .reg_mib_cnt = MIB_COUNTER_NUM, 1352 .regs = ksz9477_regs, 1353 .masks = lan937x_masks, 1354 .shifts = lan937x_shifts, 1355 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1356 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1357 .supports_mii = {false, false, false, false, true, true}, 1358 .supports_rmii = {false, false, false, false, true, true}, 1359 .supports_rgmii = {false, false, false, false, true, true}, 1360 .internal_phy = {true, true, true, true, false, false}, 1361 }, 1362 1363 [LAN9372] = { 1364 .chip_id = LAN9372_CHIP_ID, 1365 .dev_name = "LAN9372", 1366 .num_vlans = 4096, 1367 .num_alus = 1024, 1368 .num_statics = 256, 1369 .cpu_ports = 0x30, /* can be configured as cpu port */ 1370 .port_cnt = 8, /* total physical port count */ 1371 .port_nirqs = 6, 1372 .ops = &lan937x_dev_ops, 1373 .mib_names = ksz9477_mib_names, 1374 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1375 .reg_mib_cnt = MIB_COUNTER_NUM, 1376 .regs = ksz9477_regs, 1377 .masks = lan937x_masks, 1378 .shifts = lan937x_shifts, 1379 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1380 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1381 .supports_mii = {false, false, false, false, 1382 true, true, false, false}, 1383 .supports_rmii = {false, false, false, false, 1384 true, true, false, false}, 1385 .supports_rgmii = {false, false, false, false, 1386 true, true, false, false}, 1387 .internal_phy = {true, true, true, true, 1388 false, false, true, true}, 1389 }, 1390 1391 [LAN9373] = { 1392 .chip_id = LAN9373_CHIP_ID, 1393 .dev_name = "LAN9373", 1394 .num_vlans = 4096, 1395 .num_alus = 1024, 1396 .num_statics = 256, 1397 .cpu_ports = 0x38, /* can be configured as cpu port */ 1398 .port_cnt = 5, /* total physical port count */ 1399 .port_nirqs = 6, 1400 .ops = &lan937x_dev_ops, 1401 .mib_names = ksz9477_mib_names, 1402 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1403 .reg_mib_cnt = MIB_COUNTER_NUM, 1404 .regs = ksz9477_regs, 1405 .masks = lan937x_masks, 1406 .shifts = lan937x_shifts, 1407 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1408 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1409 .supports_mii = {false, false, false, false, 1410 true, true, false, false}, 1411 .supports_rmii = {false, false, false, false, 1412 true, true, false, false}, 1413 .supports_rgmii = {false, false, false, false, 1414 true, true, false, false}, 1415 .internal_phy = {true, true, true, false, 1416 false, false, true, true}, 1417 }, 1418 1419 [LAN9374] = { 1420 .chip_id = LAN9374_CHIP_ID, 1421 .dev_name = "LAN9374", 1422 .num_vlans = 4096, 1423 .num_alus = 1024, 1424 .num_statics = 256, 1425 .cpu_ports = 0x30, /* can be configured as cpu port */ 1426 .port_cnt = 8, /* total physical port count */ 1427 .port_nirqs = 6, 1428 .ops = &lan937x_dev_ops, 1429 .mib_names = ksz9477_mib_names, 1430 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1431 .reg_mib_cnt = MIB_COUNTER_NUM, 1432 .regs = ksz9477_regs, 1433 .masks = lan937x_masks, 1434 .shifts = lan937x_shifts, 1435 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1436 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1437 .supports_mii = {false, false, false, false, 1438 true, true, false, false}, 1439 .supports_rmii = {false, false, false, false, 1440 true, true, false, false}, 1441 .supports_rgmii = {false, false, false, false, 1442 true, true, false, false}, 1443 .internal_phy = {true, true, true, true, 1444 false, false, true, true}, 1445 }, 1446 }; 1447 EXPORT_SYMBOL_GPL(ksz_switch_chips); 1448 1449 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 1450 { 1451 int i; 1452 1453 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 1454 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 1455 1456 if (chip->chip_id == prod_num) 1457 return chip; 1458 } 1459 1460 return NULL; 1461 } 1462 1463 static int ksz_check_device_id(struct ksz_device *dev) 1464 { 1465 const struct ksz_chip_data *dt_chip_data; 1466 1467 dt_chip_data = of_device_get_match_data(dev->dev); 1468 1469 /* Check for Device Tree and Chip ID */ 1470 if (dt_chip_data->chip_id != dev->chip_id) { 1471 dev_err(dev->dev, 1472 "Device tree specifies chip %s but found %s, please fix it!\n", 1473 dt_chip_data->dev_name, dev->info->dev_name); 1474 return -ENODEV; 1475 } 1476 1477 return 0; 1478 } 1479 1480 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 1481 struct phylink_config *config) 1482 { 1483 struct ksz_device *dev = ds->priv; 1484 1485 config->legacy_pre_march2020 = false; 1486 1487 if (dev->info->supports_mii[port]) 1488 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1489 1490 if (dev->info->supports_rmii[port]) 1491 __set_bit(PHY_INTERFACE_MODE_RMII, 1492 config->supported_interfaces); 1493 1494 if (dev->info->supports_rgmii[port]) 1495 phy_interface_set_rgmii(config->supported_interfaces); 1496 1497 if (dev->info->internal_phy[port]) { 1498 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1499 config->supported_interfaces); 1500 /* Compatibility for phylib's default interface type when the 1501 * phy-mode property is absent 1502 */ 1503 __set_bit(PHY_INTERFACE_MODE_GMII, 1504 config->supported_interfaces); 1505 } 1506 1507 if (dev->dev_ops->get_caps) 1508 dev->dev_ops->get_caps(dev, port, config); 1509 } 1510 1511 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 1512 { 1513 struct ethtool_pause_stats *pstats; 1514 struct rtnl_link_stats64 *stats; 1515 struct ksz_stats_raw *raw; 1516 struct ksz_port_mib *mib; 1517 1518 mib = &dev->ports[port].mib; 1519 stats = &mib->stats64; 1520 pstats = &mib->pause_stats; 1521 raw = (struct ksz_stats_raw *)mib->counters; 1522 1523 spin_lock(&mib->stats64_lock); 1524 1525 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1526 raw->rx_pause; 1527 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1528 raw->tx_pause; 1529 1530 /* HW counters are counting bytes + FCS which is not acceptable 1531 * for rtnl_link_stats64 interface 1532 */ 1533 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 1534 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 1535 1536 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 1537 raw->rx_oversize; 1538 1539 stats->rx_crc_errors = raw->rx_crc_err; 1540 stats->rx_frame_errors = raw->rx_align_err; 1541 stats->rx_dropped = raw->rx_discards; 1542 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 1543 stats->rx_frame_errors + stats->rx_dropped; 1544 1545 stats->tx_window_errors = raw->tx_late_col; 1546 stats->tx_fifo_errors = raw->tx_discards; 1547 stats->tx_aborted_errors = raw->tx_exc_col; 1548 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 1549 stats->tx_aborted_errors; 1550 1551 stats->multicast = raw->rx_mcast; 1552 stats->collisions = raw->tx_total_col; 1553 1554 pstats->tx_pause_frames = raw->tx_pause; 1555 pstats->rx_pause_frames = raw->rx_pause; 1556 1557 spin_unlock(&mib->stats64_lock); 1558 } 1559 1560 static void ksz_get_stats64(struct dsa_switch *ds, int port, 1561 struct rtnl_link_stats64 *s) 1562 { 1563 struct ksz_device *dev = ds->priv; 1564 struct ksz_port_mib *mib; 1565 1566 mib = &dev->ports[port].mib; 1567 1568 spin_lock(&mib->stats64_lock); 1569 memcpy(s, &mib->stats64, sizeof(*s)); 1570 spin_unlock(&mib->stats64_lock); 1571 } 1572 1573 static void ksz_get_pause_stats(struct dsa_switch *ds, int port, 1574 struct ethtool_pause_stats *pause_stats) 1575 { 1576 struct ksz_device *dev = ds->priv; 1577 struct ksz_port_mib *mib; 1578 1579 mib = &dev->ports[port].mib; 1580 1581 spin_lock(&mib->stats64_lock); 1582 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 1583 spin_unlock(&mib->stats64_lock); 1584 } 1585 1586 static void ksz_get_strings(struct dsa_switch *ds, int port, 1587 u32 stringset, uint8_t *buf) 1588 { 1589 struct ksz_device *dev = ds->priv; 1590 int i; 1591 1592 if (stringset != ETH_SS_STATS) 1593 return; 1594 1595 for (i = 0; i < dev->info->mib_cnt; i++) { 1596 memcpy(buf + i * ETH_GSTRING_LEN, 1597 dev->info->mib_names[i].string, ETH_GSTRING_LEN); 1598 } 1599 } 1600 1601 static void ksz_update_port_member(struct ksz_device *dev, int port) 1602 { 1603 struct ksz_port *p = &dev->ports[port]; 1604 struct dsa_switch *ds = dev->ds; 1605 u8 port_member = 0, cpu_port; 1606 const struct dsa_port *dp; 1607 int i, j; 1608 1609 if (!dsa_is_user_port(ds, port)) 1610 return; 1611 1612 dp = dsa_to_port(ds, port); 1613 cpu_port = BIT(dsa_upstream_port(ds, port)); 1614 1615 for (i = 0; i < ds->num_ports; i++) { 1616 const struct dsa_port *other_dp = dsa_to_port(ds, i); 1617 struct ksz_port *other_p = &dev->ports[i]; 1618 u8 val = 0; 1619 1620 if (!dsa_is_user_port(ds, i)) 1621 continue; 1622 if (port == i) 1623 continue; 1624 if (!dsa_port_bridge_same(dp, other_dp)) 1625 continue; 1626 if (other_p->stp_state != BR_STATE_FORWARDING) 1627 continue; 1628 1629 if (p->stp_state == BR_STATE_FORWARDING) { 1630 val |= BIT(port); 1631 port_member |= BIT(i); 1632 } 1633 1634 /* Retain port [i]'s relationship to other ports than [port] */ 1635 for (j = 0; j < ds->num_ports; j++) { 1636 const struct dsa_port *third_dp; 1637 struct ksz_port *third_p; 1638 1639 if (j == i) 1640 continue; 1641 if (j == port) 1642 continue; 1643 if (!dsa_is_user_port(ds, j)) 1644 continue; 1645 third_p = &dev->ports[j]; 1646 if (third_p->stp_state != BR_STATE_FORWARDING) 1647 continue; 1648 third_dp = dsa_to_port(ds, j); 1649 if (dsa_port_bridge_same(other_dp, third_dp)) 1650 val |= BIT(j); 1651 } 1652 1653 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 1654 } 1655 1656 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 1657 } 1658 1659 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 1660 { 1661 struct ksz_device *dev = bus->priv; 1662 u16 val; 1663 int ret; 1664 1665 if (regnum & MII_ADDR_C45) 1666 return -EOPNOTSUPP; 1667 1668 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val); 1669 if (ret < 0) 1670 return ret; 1671 1672 return val; 1673 } 1674 1675 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 1676 u16 val) 1677 { 1678 struct ksz_device *dev = bus->priv; 1679 1680 if (regnum & MII_ADDR_C45) 1681 return -EOPNOTSUPP; 1682 1683 return dev->dev_ops->w_phy(dev, addr, regnum, val); 1684 } 1685 1686 static int ksz_irq_phy_setup(struct ksz_device *dev) 1687 { 1688 struct dsa_switch *ds = dev->ds; 1689 int phy; 1690 int irq; 1691 int ret; 1692 1693 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) { 1694 if (BIT(phy) & ds->phys_mii_mask) { 1695 irq = irq_find_mapping(dev->ports[phy].pirq.domain, 1696 PORT_SRC_PHY_INT); 1697 if (irq < 0) { 1698 ret = irq; 1699 goto out; 1700 } 1701 ds->slave_mii_bus->irq[phy] = irq; 1702 } 1703 } 1704 return 0; 1705 out: 1706 while (phy--) 1707 if (BIT(phy) & ds->phys_mii_mask) 1708 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]); 1709 1710 return ret; 1711 } 1712 1713 static void ksz_irq_phy_free(struct ksz_device *dev) 1714 { 1715 struct dsa_switch *ds = dev->ds; 1716 int phy; 1717 1718 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) 1719 if (BIT(phy) & ds->phys_mii_mask) 1720 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]); 1721 } 1722 1723 static int ksz_mdio_register(struct ksz_device *dev) 1724 { 1725 struct dsa_switch *ds = dev->ds; 1726 struct device_node *mdio_np; 1727 struct mii_bus *bus; 1728 int ret; 1729 1730 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); 1731 if (!mdio_np) 1732 return 0; 1733 1734 bus = devm_mdiobus_alloc(ds->dev); 1735 if (!bus) { 1736 of_node_put(mdio_np); 1737 return -ENOMEM; 1738 } 1739 1740 bus->priv = dev; 1741 bus->read = ksz_sw_mdio_read; 1742 bus->write = ksz_sw_mdio_write; 1743 bus->name = "ksz slave smi"; 1744 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); 1745 bus->parent = ds->dev; 1746 bus->phy_mask = ~ds->phys_mii_mask; 1747 1748 ds->slave_mii_bus = bus; 1749 1750 if (dev->irq > 0) { 1751 ret = ksz_irq_phy_setup(dev); 1752 if (ret) { 1753 of_node_put(mdio_np); 1754 return ret; 1755 } 1756 } 1757 1758 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); 1759 if (ret) { 1760 dev_err(ds->dev, "unable to register MDIO bus %s\n", 1761 bus->id); 1762 if (dev->irq > 0) 1763 ksz_irq_phy_free(dev); 1764 } 1765 1766 of_node_put(mdio_np); 1767 1768 return ret; 1769 } 1770 1771 static void ksz_irq_mask(struct irq_data *d) 1772 { 1773 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1774 1775 kirq->masked |= BIT(d->hwirq); 1776 } 1777 1778 static void ksz_irq_unmask(struct irq_data *d) 1779 { 1780 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1781 1782 kirq->masked &= ~BIT(d->hwirq); 1783 } 1784 1785 static void ksz_irq_bus_lock(struct irq_data *d) 1786 { 1787 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1788 1789 mutex_lock(&kirq->dev->lock_irq); 1790 } 1791 1792 static void ksz_irq_bus_sync_unlock(struct irq_data *d) 1793 { 1794 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1795 struct ksz_device *dev = kirq->dev; 1796 int ret; 1797 1798 ret = ksz_write32(dev, kirq->reg_mask, kirq->masked); 1799 if (ret) 1800 dev_err(dev->dev, "failed to change IRQ mask\n"); 1801 1802 mutex_unlock(&dev->lock_irq); 1803 } 1804 1805 static const struct irq_chip ksz_irq_chip = { 1806 .name = "ksz-irq", 1807 .irq_mask = ksz_irq_mask, 1808 .irq_unmask = ksz_irq_unmask, 1809 .irq_bus_lock = ksz_irq_bus_lock, 1810 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock, 1811 }; 1812 1813 static int ksz_irq_domain_map(struct irq_domain *d, 1814 unsigned int irq, irq_hw_number_t hwirq) 1815 { 1816 irq_set_chip_data(irq, d->host_data); 1817 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq); 1818 irq_set_noprobe(irq); 1819 1820 return 0; 1821 } 1822 1823 static const struct irq_domain_ops ksz_irq_domain_ops = { 1824 .map = ksz_irq_domain_map, 1825 .xlate = irq_domain_xlate_twocell, 1826 }; 1827 1828 static void ksz_irq_free(struct ksz_irq *kirq) 1829 { 1830 int irq, virq; 1831 1832 free_irq(kirq->irq_num, kirq); 1833 1834 for (irq = 0; irq < kirq->nirqs; irq++) { 1835 virq = irq_find_mapping(kirq->domain, irq); 1836 irq_dispose_mapping(virq); 1837 } 1838 1839 irq_domain_remove(kirq->domain); 1840 } 1841 1842 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id) 1843 { 1844 struct ksz_irq *kirq = dev_id; 1845 unsigned int nhandled = 0; 1846 struct ksz_device *dev; 1847 unsigned int sub_irq; 1848 u8 data; 1849 int ret; 1850 u8 n; 1851 1852 dev = kirq->dev; 1853 1854 /* Read interrupt status register */ 1855 ret = ksz_read8(dev, kirq->reg_status, &data); 1856 if (ret) 1857 goto out; 1858 1859 for (n = 0; n < kirq->nirqs; ++n) { 1860 if (data & BIT(n)) { 1861 sub_irq = irq_find_mapping(kirq->domain, n); 1862 handle_nested_irq(sub_irq); 1863 ++nhandled; 1864 } 1865 } 1866 out: 1867 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 1868 } 1869 1870 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq) 1871 { 1872 int ret, n; 1873 1874 kirq->dev = dev; 1875 kirq->masked = ~0; 1876 1877 kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0, 1878 &ksz_irq_domain_ops, kirq); 1879 if (!kirq->domain) 1880 return -ENOMEM; 1881 1882 for (n = 0; n < kirq->nirqs; n++) 1883 irq_create_mapping(kirq->domain, n); 1884 1885 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn, 1886 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 1887 kirq->name, kirq); 1888 if (ret) 1889 goto out; 1890 1891 return 0; 1892 1893 out: 1894 ksz_irq_free(kirq); 1895 1896 return ret; 1897 } 1898 1899 static int ksz_girq_setup(struct ksz_device *dev) 1900 { 1901 struct ksz_irq *girq = &dev->girq; 1902 1903 girq->nirqs = dev->info->port_cnt; 1904 girq->reg_mask = REG_SW_PORT_INT_MASK__1; 1905 girq->reg_status = REG_SW_PORT_INT_STATUS__1; 1906 snprintf(girq->name, sizeof(girq->name), "global_port_irq"); 1907 1908 girq->irq_num = dev->irq; 1909 1910 return ksz_irq_common_setup(dev, girq); 1911 } 1912 1913 static int ksz_pirq_setup(struct ksz_device *dev, u8 p) 1914 { 1915 struct ksz_irq *pirq = &dev->ports[p].pirq; 1916 1917 pirq->nirqs = dev->info->port_nirqs; 1918 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK); 1919 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS); 1920 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p); 1921 1922 pirq->irq_num = irq_find_mapping(dev->girq.domain, p); 1923 if (pirq->irq_num < 0) 1924 return pirq->irq_num; 1925 1926 return ksz_irq_common_setup(dev, pirq); 1927 } 1928 1929 static int ksz_setup(struct dsa_switch *ds) 1930 { 1931 struct ksz_device *dev = ds->priv; 1932 struct dsa_port *dp; 1933 struct ksz_port *p; 1934 const u16 *regs; 1935 int ret; 1936 1937 regs = dev->info->regs; 1938 1939 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 1940 dev->info->num_vlans, GFP_KERNEL); 1941 if (!dev->vlan_cache) 1942 return -ENOMEM; 1943 1944 ret = dev->dev_ops->reset(dev); 1945 if (ret) { 1946 dev_err(ds->dev, "failed to reset switch\n"); 1947 return ret; 1948 } 1949 1950 /* set broadcast storm protection 10% rate */ 1951 regmap_update_bits(dev->regmap[1], regs[S_BROADCAST_CTRL], 1952 BROADCAST_STORM_RATE, 1953 (BROADCAST_STORM_VALUE * 1954 BROADCAST_STORM_PROT_RATE) / 100); 1955 1956 dev->dev_ops->config_cpu_port(ds); 1957 1958 dev->dev_ops->enable_stp_addr(dev); 1959 1960 regmap_update_bits(dev->regmap[0], regs[S_MULTICAST_CTRL], 1961 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 1962 1963 ksz_init_mib_timer(dev); 1964 1965 ds->configure_vlan_while_not_filtering = false; 1966 1967 if (dev->dev_ops->setup) { 1968 ret = dev->dev_ops->setup(ds); 1969 if (ret) 1970 return ret; 1971 } 1972 1973 /* Start with learning disabled on standalone user ports, and enabled 1974 * on the CPU port. In lack of other finer mechanisms, learning on the 1975 * CPU port will avoid flooding bridge local addresses on the network 1976 * in some cases. 1977 */ 1978 p = &dev->ports[dev->cpu_port]; 1979 p->learning = true; 1980 1981 if (dev->irq > 0) { 1982 ret = ksz_girq_setup(dev); 1983 if (ret) 1984 return ret; 1985 1986 dsa_switch_for_each_user_port(dp, dev->ds) { 1987 ret = ksz_pirq_setup(dev, dp->index); 1988 if (ret) 1989 goto out_girq; 1990 } 1991 } 1992 1993 ret = ksz_mdio_register(dev); 1994 if (ret < 0) { 1995 dev_err(dev->dev, "failed to register the mdio"); 1996 goto out_pirq; 1997 } 1998 1999 /* start switch */ 2000 regmap_update_bits(dev->regmap[0], regs[S_START_CTRL], 2001 SW_START, SW_START); 2002 2003 return 0; 2004 2005 out_pirq: 2006 if (dev->irq > 0) 2007 dsa_switch_for_each_user_port(dp, dev->ds) 2008 ksz_irq_free(&dev->ports[dp->index].pirq); 2009 out_girq: 2010 if (dev->irq > 0) 2011 ksz_irq_free(&dev->girq); 2012 2013 return ret; 2014 } 2015 2016 static void ksz_teardown(struct dsa_switch *ds) 2017 { 2018 struct ksz_device *dev = ds->priv; 2019 struct dsa_port *dp; 2020 2021 if (dev->irq > 0) { 2022 dsa_switch_for_each_user_port(dp, dev->ds) 2023 ksz_irq_free(&dev->ports[dp->index].pirq); 2024 2025 ksz_irq_free(&dev->girq); 2026 } 2027 2028 if (dev->dev_ops->teardown) 2029 dev->dev_ops->teardown(ds); 2030 } 2031 2032 static void port_r_cnt(struct ksz_device *dev, int port) 2033 { 2034 struct ksz_port_mib *mib = &dev->ports[port].mib; 2035 u64 *dropped; 2036 2037 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 2038 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 2039 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 2040 &mib->counters[mib->cnt_ptr]); 2041 ++mib->cnt_ptr; 2042 } 2043 2044 /* last one in storage */ 2045 dropped = &mib->counters[dev->info->mib_cnt]; 2046 2047 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 2048 while (mib->cnt_ptr < dev->info->mib_cnt) { 2049 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 2050 dropped, &mib->counters[mib->cnt_ptr]); 2051 ++mib->cnt_ptr; 2052 } 2053 mib->cnt_ptr = 0; 2054 } 2055 2056 static void ksz_mib_read_work(struct work_struct *work) 2057 { 2058 struct ksz_device *dev = container_of(work, struct ksz_device, 2059 mib_read.work); 2060 struct ksz_port_mib *mib; 2061 struct ksz_port *p; 2062 int i; 2063 2064 for (i = 0; i < dev->info->port_cnt; i++) { 2065 if (dsa_is_unused_port(dev->ds, i)) 2066 continue; 2067 2068 p = &dev->ports[i]; 2069 mib = &p->mib; 2070 mutex_lock(&mib->cnt_mutex); 2071 2072 /* Only read MIB counters when the port is told to do. 2073 * If not, read only dropped counters when link is not up. 2074 */ 2075 if (!p->read) { 2076 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 2077 2078 if (!netif_carrier_ok(dp->slave)) 2079 mib->cnt_ptr = dev->info->reg_mib_cnt; 2080 } 2081 port_r_cnt(dev, i); 2082 p->read = false; 2083 2084 if (dev->dev_ops->r_mib_stat64) 2085 dev->dev_ops->r_mib_stat64(dev, i); 2086 2087 mutex_unlock(&mib->cnt_mutex); 2088 } 2089 2090 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 2091 } 2092 2093 void ksz_init_mib_timer(struct ksz_device *dev) 2094 { 2095 int i; 2096 2097 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 2098 2099 for (i = 0; i < dev->info->port_cnt; i++) { 2100 struct ksz_port_mib *mib = &dev->ports[i].mib; 2101 2102 dev->dev_ops->port_init_cnt(dev, i); 2103 2104 mib->cnt_ptr = 0; 2105 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 2106 } 2107 } 2108 2109 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 2110 { 2111 struct ksz_device *dev = ds->priv; 2112 u16 val = 0xffff; 2113 int ret; 2114 2115 ret = dev->dev_ops->r_phy(dev, addr, reg, &val); 2116 if (ret) 2117 return ret; 2118 2119 return val; 2120 } 2121 2122 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 2123 { 2124 struct ksz_device *dev = ds->priv; 2125 int ret; 2126 2127 ret = dev->dev_ops->w_phy(dev, addr, reg, val); 2128 if (ret) 2129 return ret; 2130 2131 return 0; 2132 } 2133 2134 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 2135 { 2136 struct ksz_device *dev = ds->priv; 2137 2138 if (dev->chip_id == KSZ8830_CHIP_ID) { 2139 /* Silicon Errata Sheet (DS80000830A): 2140 * Port 1 does not work with LinkMD Cable-Testing. 2141 * Port 1 does not respond to received PAUSE control frames. 2142 */ 2143 if (!port) 2144 return MICREL_KSZ8_P1_ERRATA; 2145 } 2146 2147 return 0; 2148 } 2149 2150 static void ksz_mac_link_down(struct dsa_switch *ds, int port, 2151 unsigned int mode, phy_interface_t interface) 2152 { 2153 struct ksz_device *dev = ds->priv; 2154 struct ksz_port *p = &dev->ports[port]; 2155 2156 /* Read all MIB counters when the link is going down. */ 2157 p->read = true; 2158 /* timer started */ 2159 if (dev->mib_read_interval) 2160 schedule_delayed_work(&dev->mib_read, 0); 2161 } 2162 2163 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 2164 { 2165 struct ksz_device *dev = ds->priv; 2166 2167 if (sset != ETH_SS_STATS) 2168 return 0; 2169 2170 return dev->info->mib_cnt; 2171 } 2172 2173 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 2174 uint64_t *buf) 2175 { 2176 const struct dsa_port *dp = dsa_to_port(ds, port); 2177 struct ksz_device *dev = ds->priv; 2178 struct ksz_port_mib *mib; 2179 2180 mib = &dev->ports[port].mib; 2181 mutex_lock(&mib->cnt_mutex); 2182 2183 /* Only read dropped counters if no link. */ 2184 if (!netif_carrier_ok(dp->slave)) 2185 mib->cnt_ptr = dev->info->reg_mib_cnt; 2186 port_r_cnt(dev, port); 2187 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 2188 mutex_unlock(&mib->cnt_mutex); 2189 } 2190 2191 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 2192 struct dsa_bridge bridge, 2193 bool *tx_fwd_offload, 2194 struct netlink_ext_ack *extack) 2195 { 2196 /* port_stp_state_set() will be called after to put the port in 2197 * appropriate state so there is no need to do anything. 2198 */ 2199 2200 return 0; 2201 } 2202 2203 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 2204 struct dsa_bridge bridge) 2205 { 2206 /* port_stp_state_set() will be called after to put the port in 2207 * forwarding state so there is no need to do anything. 2208 */ 2209 } 2210 2211 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 2212 { 2213 struct ksz_device *dev = ds->priv; 2214 2215 dev->dev_ops->flush_dyn_mac_table(dev, port); 2216 } 2217 2218 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 2219 { 2220 struct ksz_device *dev = ds->priv; 2221 2222 if (!dev->dev_ops->set_ageing_time) 2223 return -EOPNOTSUPP; 2224 2225 return dev->dev_ops->set_ageing_time(dev, msecs); 2226 } 2227 2228 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 2229 const unsigned char *addr, u16 vid, 2230 struct dsa_db db) 2231 { 2232 struct ksz_device *dev = ds->priv; 2233 2234 if (!dev->dev_ops->fdb_add) 2235 return -EOPNOTSUPP; 2236 2237 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 2238 } 2239 2240 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 2241 const unsigned char *addr, 2242 u16 vid, struct dsa_db db) 2243 { 2244 struct ksz_device *dev = ds->priv; 2245 2246 if (!dev->dev_ops->fdb_del) 2247 return -EOPNOTSUPP; 2248 2249 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 2250 } 2251 2252 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 2253 dsa_fdb_dump_cb_t *cb, void *data) 2254 { 2255 struct ksz_device *dev = ds->priv; 2256 2257 if (!dev->dev_ops->fdb_dump) 2258 return -EOPNOTSUPP; 2259 2260 return dev->dev_ops->fdb_dump(dev, port, cb, data); 2261 } 2262 2263 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 2264 const struct switchdev_obj_port_mdb *mdb, 2265 struct dsa_db db) 2266 { 2267 struct ksz_device *dev = ds->priv; 2268 2269 if (!dev->dev_ops->mdb_add) 2270 return -EOPNOTSUPP; 2271 2272 return dev->dev_ops->mdb_add(dev, port, mdb, db); 2273 } 2274 2275 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 2276 const struct switchdev_obj_port_mdb *mdb, 2277 struct dsa_db db) 2278 { 2279 struct ksz_device *dev = ds->priv; 2280 2281 if (!dev->dev_ops->mdb_del) 2282 return -EOPNOTSUPP; 2283 2284 return dev->dev_ops->mdb_del(dev, port, mdb, db); 2285 } 2286 2287 static int ksz_enable_port(struct dsa_switch *ds, int port, 2288 struct phy_device *phy) 2289 { 2290 struct ksz_device *dev = ds->priv; 2291 2292 if (!dsa_is_user_port(ds, port)) 2293 return 0; 2294 2295 /* setup slave port */ 2296 dev->dev_ops->port_setup(dev, port, false); 2297 2298 /* port_stp_state_set() will be called after to enable the port so 2299 * there is no need to do anything. 2300 */ 2301 2302 return 0; 2303 } 2304 2305 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 2306 { 2307 struct ksz_device *dev = ds->priv; 2308 struct ksz_port *p; 2309 const u16 *regs; 2310 u8 data; 2311 2312 regs = dev->info->regs; 2313 2314 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 2315 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2316 2317 p = &dev->ports[port]; 2318 2319 switch (state) { 2320 case BR_STATE_DISABLED: 2321 data |= PORT_LEARN_DISABLE; 2322 break; 2323 case BR_STATE_LISTENING: 2324 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2325 break; 2326 case BR_STATE_LEARNING: 2327 data |= PORT_RX_ENABLE; 2328 if (!p->learning) 2329 data |= PORT_LEARN_DISABLE; 2330 break; 2331 case BR_STATE_FORWARDING: 2332 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 2333 if (!p->learning) 2334 data |= PORT_LEARN_DISABLE; 2335 break; 2336 case BR_STATE_BLOCKING: 2337 data |= PORT_LEARN_DISABLE; 2338 break; 2339 default: 2340 dev_err(ds->dev, "invalid STP state: %d\n", state); 2341 return; 2342 } 2343 2344 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 2345 2346 p->stp_state = state; 2347 2348 ksz_update_port_member(dev, port); 2349 } 2350 2351 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 2352 struct switchdev_brport_flags flags, 2353 struct netlink_ext_ack *extack) 2354 { 2355 if (flags.mask & ~BR_LEARNING) 2356 return -EINVAL; 2357 2358 return 0; 2359 } 2360 2361 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 2362 struct switchdev_brport_flags flags, 2363 struct netlink_ext_ack *extack) 2364 { 2365 struct ksz_device *dev = ds->priv; 2366 struct ksz_port *p = &dev->ports[port]; 2367 2368 if (flags.mask & BR_LEARNING) { 2369 p->learning = !!(flags.val & BR_LEARNING); 2370 2371 /* Make the change take effect immediately */ 2372 ksz_port_stp_state_set(ds, port, p->stp_state); 2373 } 2374 2375 return 0; 2376 } 2377 2378 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 2379 int port, 2380 enum dsa_tag_protocol mp) 2381 { 2382 struct ksz_device *dev = ds->priv; 2383 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 2384 2385 if (dev->chip_id == KSZ8795_CHIP_ID || 2386 dev->chip_id == KSZ8794_CHIP_ID || 2387 dev->chip_id == KSZ8765_CHIP_ID) 2388 proto = DSA_TAG_PROTO_KSZ8795; 2389 2390 if (dev->chip_id == KSZ8830_CHIP_ID || 2391 dev->chip_id == KSZ8563_CHIP_ID || 2392 dev->chip_id == KSZ9893_CHIP_ID) 2393 proto = DSA_TAG_PROTO_KSZ9893; 2394 2395 if (dev->chip_id == KSZ9477_CHIP_ID || 2396 dev->chip_id == KSZ9896_CHIP_ID || 2397 dev->chip_id == KSZ9897_CHIP_ID || 2398 dev->chip_id == KSZ9567_CHIP_ID) 2399 proto = DSA_TAG_PROTO_KSZ9477; 2400 2401 if (is_lan937x(dev)) 2402 proto = DSA_TAG_PROTO_LAN937X_VALUE; 2403 2404 return proto; 2405 } 2406 2407 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 2408 bool flag, struct netlink_ext_ack *extack) 2409 { 2410 struct ksz_device *dev = ds->priv; 2411 2412 if (!dev->dev_ops->vlan_filtering) 2413 return -EOPNOTSUPP; 2414 2415 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 2416 } 2417 2418 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 2419 const struct switchdev_obj_port_vlan *vlan, 2420 struct netlink_ext_ack *extack) 2421 { 2422 struct ksz_device *dev = ds->priv; 2423 2424 if (!dev->dev_ops->vlan_add) 2425 return -EOPNOTSUPP; 2426 2427 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 2428 } 2429 2430 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 2431 const struct switchdev_obj_port_vlan *vlan) 2432 { 2433 struct ksz_device *dev = ds->priv; 2434 2435 if (!dev->dev_ops->vlan_del) 2436 return -EOPNOTSUPP; 2437 2438 return dev->dev_ops->vlan_del(dev, port, vlan); 2439 } 2440 2441 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 2442 struct dsa_mall_mirror_tc_entry *mirror, 2443 bool ingress, struct netlink_ext_ack *extack) 2444 { 2445 struct ksz_device *dev = ds->priv; 2446 2447 if (!dev->dev_ops->mirror_add) 2448 return -EOPNOTSUPP; 2449 2450 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 2451 } 2452 2453 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 2454 struct dsa_mall_mirror_tc_entry *mirror) 2455 { 2456 struct ksz_device *dev = ds->priv; 2457 2458 if (dev->dev_ops->mirror_del) 2459 dev->dev_ops->mirror_del(dev, port, mirror); 2460 } 2461 2462 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 2463 { 2464 struct ksz_device *dev = ds->priv; 2465 2466 if (!dev->dev_ops->change_mtu) 2467 return -EOPNOTSUPP; 2468 2469 return dev->dev_ops->change_mtu(dev, port, mtu); 2470 } 2471 2472 static int ksz_max_mtu(struct dsa_switch *ds, int port) 2473 { 2474 struct ksz_device *dev = ds->priv; 2475 2476 if (!dev->dev_ops->max_mtu) 2477 return -EOPNOTSUPP; 2478 2479 return dev->dev_ops->max_mtu(dev, port); 2480 } 2481 2482 static void ksz_set_xmii(struct ksz_device *dev, int port, 2483 phy_interface_t interface) 2484 { 2485 const u8 *bitval = dev->info->xmii_ctrl1; 2486 struct ksz_port *p = &dev->ports[port]; 2487 const u16 *regs = dev->info->regs; 2488 u8 data8; 2489 2490 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2491 2492 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 2493 P_RGMII_ID_EG_ENABLE); 2494 2495 switch (interface) { 2496 case PHY_INTERFACE_MODE_MII: 2497 data8 |= bitval[P_MII_SEL]; 2498 break; 2499 case PHY_INTERFACE_MODE_RMII: 2500 data8 |= bitval[P_RMII_SEL]; 2501 break; 2502 case PHY_INTERFACE_MODE_GMII: 2503 data8 |= bitval[P_GMII_SEL]; 2504 break; 2505 case PHY_INTERFACE_MODE_RGMII: 2506 case PHY_INTERFACE_MODE_RGMII_ID: 2507 case PHY_INTERFACE_MODE_RGMII_TXID: 2508 case PHY_INTERFACE_MODE_RGMII_RXID: 2509 data8 |= bitval[P_RGMII_SEL]; 2510 /* On KSZ9893, disable RGMII in-band status support */ 2511 if (dev->chip_id == KSZ9893_CHIP_ID || 2512 dev->chip_id == KSZ8563_CHIP_ID) 2513 data8 &= ~P_MII_MAC_MODE; 2514 break; 2515 default: 2516 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 2517 phy_modes(interface), port); 2518 return; 2519 } 2520 2521 if (p->rgmii_tx_val) 2522 data8 |= P_RGMII_ID_EG_ENABLE; 2523 2524 if (p->rgmii_rx_val) 2525 data8 |= P_RGMII_ID_IG_ENABLE; 2526 2527 /* Write the updated value */ 2528 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 2529 } 2530 2531 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 2532 { 2533 const u8 *bitval = dev->info->xmii_ctrl1; 2534 const u16 *regs = dev->info->regs; 2535 phy_interface_t interface; 2536 u8 data8; 2537 u8 val; 2538 2539 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2540 2541 val = FIELD_GET(P_MII_SEL_M, data8); 2542 2543 if (val == bitval[P_MII_SEL]) { 2544 if (gbit) 2545 interface = PHY_INTERFACE_MODE_GMII; 2546 else 2547 interface = PHY_INTERFACE_MODE_MII; 2548 } else if (val == bitval[P_RMII_SEL]) { 2549 interface = PHY_INTERFACE_MODE_RGMII; 2550 } else { 2551 interface = PHY_INTERFACE_MODE_RGMII; 2552 if (data8 & P_RGMII_ID_EG_ENABLE) 2553 interface = PHY_INTERFACE_MODE_RGMII_TXID; 2554 if (data8 & P_RGMII_ID_IG_ENABLE) { 2555 interface = PHY_INTERFACE_MODE_RGMII_RXID; 2556 if (data8 & P_RGMII_ID_EG_ENABLE) 2557 interface = PHY_INTERFACE_MODE_RGMII_ID; 2558 } 2559 } 2560 2561 return interface; 2562 } 2563 2564 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port, 2565 unsigned int mode, 2566 const struct phylink_link_state *state) 2567 { 2568 struct ksz_device *dev = ds->priv; 2569 2570 if (ksz_is_ksz88x3(dev)) 2571 return; 2572 2573 /* Internal PHYs */ 2574 if (dev->info->internal_phy[port]) 2575 return; 2576 2577 if (phylink_autoneg_inband(mode)) { 2578 dev_err(dev->dev, "In-band AN not supported!\n"); 2579 return; 2580 } 2581 2582 ksz_set_xmii(dev, port, state->interface); 2583 2584 if (dev->dev_ops->phylink_mac_config) 2585 dev->dev_ops->phylink_mac_config(dev, port, mode, state); 2586 2587 if (dev->dev_ops->setup_rgmii_delay) 2588 dev->dev_ops->setup_rgmii_delay(dev, port); 2589 } 2590 2591 bool ksz_get_gbit(struct ksz_device *dev, int port) 2592 { 2593 const u8 *bitval = dev->info->xmii_ctrl1; 2594 const u16 *regs = dev->info->regs; 2595 bool gbit = false; 2596 u8 data8; 2597 bool val; 2598 2599 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2600 2601 val = FIELD_GET(P_GMII_1GBIT_M, data8); 2602 2603 if (val == bitval[P_GMII_1GBIT]) 2604 gbit = true; 2605 2606 return gbit; 2607 } 2608 2609 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) 2610 { 2611 const u8 *bitval = dev->info->xmii_ctrl1; 2612 const u16 *regs = dev->info->regs; 2613 u8 data8; 2614 2615 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2616 2617 data8 &= ~P_GMII_1GBIT_M; 2618 2619 if (gbit) 2620 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 2621 else 2622 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 2623 2624 /* Write the updated value */ 2625 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 2626 } 2627 2628 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) 2629 { 2630 const u8 *bitval = dev->info->xmii_ctrl0; 2631 const u16 *regs = dev->info->regs; 2632 u8 data8; 2633 2634 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 2635 2636 data8 &= ~P_MII_100MBIT_M; 2637 2638 if (speed == SPEED_100) 2639 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 2640 else 2641 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 2642 2643 /* Write the updated value */ 2644 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 2645 } 2646 2647 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) 2648 { 2649 if (speed == SPEED_1000) 2650 ksz_set_gbit(dev, port, true); 2651 else 2652 ksz_set_gbit(dev, port, false); 2653 2654 if (speed == SPEED_100 || speed == SPEED_10) 2655 ksz_set_100_10mbit(dev, port, speed); 2656 } 2657 2658 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 2659 bool tx_pause, bool rx_pause) 2660 { 2661 const u8 *bitval = dev->info->xmii_ctrl0; 2662 const u32 *masks = dev->info->masks; 2663 const u16 *regs = dev->info->regs; 2664 u8 mask; 2665 u8 val; 2666 2667 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 2668 masks[P_MII_RX_FLOW_CTRL]; 2669 2670 if (duplex == DUPLEX_FULL) 2671 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 2672 else 2673 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 2674 2675 if (tx_pause) 2676 val |= masks[P_MII_TX_FLOW_CTRL]; 2677 2678 if (rx_pause) 2679 val |= masks[P_MII_RX_FLOW_CTRL]; 2680 2681 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 2682 } 2683 2684 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, 2685 unsigned int mode, 2686 phy_interface_t interface, 2687 struct phy_device *phydev, int speed, 2688 int duplex, bool tx_pause, 2689 bool rx_pause) 2690 { 2691 struct ksz_port *p; 2692 2693 p = &dev->ports[port]; 2694 2695 /* Internal PHYs */ 2696 if (dev->info->internal_phy[port]) 2697 return; 2698 2699 p->phydev.speed = speed; 2700 2701 ksz_port_set_xmii_speed(dev, port, speed); 2702 2703 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 2704 } 2705 2706 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port, 2707 unsigned int mode, 2708 phy_interface_t interface, 2709 struct phy_device *phydev, int speed, 2710 int duplex, bool tx_pause, bool rx_pause) 2711 { 2712 struct ksz_device *dev = ds->priv; 2713 2714 if (dev->dev_ops->phylink_mac_link_up) 2715 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface, 2716 phydev, speed, duplex, 2717 tx_pause, rx_pause); 2718 } 2719 2720 static int ksz_switch_detect(struct ksz_device *dev) 2721 { 2722 u8 id1, id2, id4; 2723 u16 id16; 2724 u32 id32; 2725 int ret; 2726 2727 /* read chip id */ 2728 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 2729 if (ret) 2730 return ret; 2731 2732 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 2733 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 2734 2735 switch (id1) { 2736 case KSZ87_FAMILY_ID: 2737 if (id2 == KSZ87_CHIP_ID_95) { 2738 u8 val; 2739 2740 dev->chip_id = KSZ8795_CHIP_ID; 2741 2742 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 2743 if (val & KSZ8_PORT_FIBER_MODE) 2744 dev->chip_id = KSZ8765_CHIP_ID; 2745 } else if (id2 == KSZ87_CHIP_ID_94) { 2746 dev->chip_id = KSZ8794_CHIP_ID; 2747 } else { 2748 return -ENODEV; 2749 } 2750 break; 2751 case KSZ88_FAMILY_ID: 2752 if (id2 == KSZ88_CHIP_ID_63) 2753 dev->chip_id = KSZ8830_CHIP_ID; 2754 else 2755 return -ENODEV; 2756 break; 2757 default: 2758 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 2759 if (ret) 2760 return ret; 2761 2762 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 2763 id32 &= ~0xFF; 2764 2765 switch (id32) { 2766 case KSZ9477_CHIP_ID: 2767 case KSZ9896_CHIP_ID: 2768 case KSZ9897_CHIP_ID: 2769 case KSZ9567_CHIP_ID: 2770 case LAN9370_CHIP_ID: 2771 case LAN9371_CHIP_ID: 2772 case LAN9372_CHIP_ID: 2773 case LAN9373_CHIP_ID: 2774 case LAN9374_CHIP_ID: 2775 dev->chip_id = id32; 2776 break; 2777 case KSZ9893_CHIP_ID: 2778 ret = ksz_read8(dev, REG_CHIP_ID4, 2779 &id4); 2780 if (ret) 2781 return ret; 2782 2783 if (id4 == SKU_ID_KSZ8563) 2784 dev->chip_id = KSZ8563_CHIP_ID; 2785 else 2786 dev->chip_id = KSZ9893_CHIP_ID; 2787 2788 break; 2789 default: 2790 dev_err(dev->dev, 2791 "unsupported switch detected %x)\n", id32); 2792 return -ENODEV; 2793 } 2794 } 2795 return 0; 2796 } 2797 2798 static const struct dsa_switch_ops ksz_switch_ops = { 2799 .get_tag_protocol = ksz_get_tag_protocol, 2800 .get_phy_flags = ksz_get_phy_flags, 2801 .setup = ksz_setup, 2802 .teardown = ksz_teardown, 2803 .phy_read = ksz_phy_read16, 2804 .phy_write = ksz_phy_write16, 2805 .phylink_get_caps = ksz_phylink_get_caps, 2806 .phylink_mac_config = ksz_phylink_mac_config, 2807 .phylink_mac_link_up = ksz_phylink_mac_link_up, 2808 .phylink_mac_link_down = ksz_mac_link_down, 2809 .port_enable = ksz_enable_port, 2810 .set_ageing_time = ksz_set_ageing_time, 2811 .get_strings = ksz_get_strings, 2812 .get_ethtool_stats = ksz_get_ethtool_stats, 2813 .get_sset_count = ksz_sset_count, 2814 .port_bridge_join = ksz_port_bridge_join, 2815 .port_bridge_leave = ksz_port_bridge_leave, 2816 .port_stp_state_set = ksz_port_stp_state_set, 2817 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 2818 .port_bridge_flags = ksz_port_bridge_flags, 2819 .port_fast_age = ksz_port_fast_age, 2820 .port_vlan_filtering = ksz_port_vlan_filtering, 2821 .port_vlan_add = ksz_port_vlan_add, 2822 .port_vlan_del = ksz_port_vlan_del, 2823 .port_fdb_dump = ksz_port_fdb_dump, 2824 .port_fdb_add = ksz_port_fdb_add, 2825 .port_fdb_del = ksz_port_fdb_del, 2826 .port_mdb_add = ksz_port_mdb_add, 2827 .port_mdb_del = ksz_port_mdb_del, 2828 .port_mirror_add = ksz_port_mirror_add, 2829 .port_mirror_del = ksz_port_mirror_del, 2830 .get_stats64 = ksz_get_stats64, 2831 .get_pause_stats = ksz_get_pause_stats, 2832 .port_change_mtu = ksz_change_mtu, 2833 .port_max_mtu = ksz_max_mtu, 2834 }; 2835 2836 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 2837 { 2838 struct dsa_switch *ds; 2839 struct ksz_device *swdev; 2840 2841 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 2842 if (!ds) 2843 return NULL; 2844 2845 ds->dev = base; 2846 ds->num_ports = DSA_MAX_PORTS; 2847 ds->ops = &ksz_switch_ops; 2848 2849 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 2850 if (!swdev) 2851 return NULL; 2852 2853 ds->priv = swdev; 2854 swdev->dev = base; 2855 2856 swdev->ds = ds; 2857 swdev->priv = priv; 2858 2859 return swdev; 2860 } 2861 EXPORT_SYMBOL(ksz_switch_alloc); 2862 2863 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 2864 struct device_node *port_dn) 2865 { 2866 phy_interface_t phy_mode = dev->ports[port_num].interface; 2867 int rx_delay = -1, tx_delay = -1; 2868 2869 if (!phy_interface_mode_is_rgmii(phy_mode)) 2870 return; 2871 2872 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 2873 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 2874 2875 if (rx_delay == -1 && tx_delay == -1) { 2876 dev_warn(dev->dev, 2877 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 2878 "please update device tree to specify \"rx-internal-delay-ps\" and " 2879 "\"tx-internal-delay-ps\"", 2880 port_num); 2881 2882 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 2883 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 2884 rx_delay = 2000; 2885 2886 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 2887 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 2888 tx_delay = 2000; 2889 } 2890 2891 if (rx_delay < 0) 2892 rx_delay = 0; 2893 if (tx_delay < 0) 2894 tx_delay = 0; 2895 2896 dev->ports[port_num].rgmii_rx_val = rx_delay; 2897 dev->ports[port_num].rgmii_tx_val = tx_delay; 2898 } 2899 2900 int ksz_switch_register(struct ksz_device *dev) 2901 { 2902 const struct ksz_chip_data *info; 2903 struct device_node *port, *ports; 2904 phy_interface_t interface; 2905 unsigned int port_num; 2906 int ret; 2907 int i; 2908 2909 if (dev->pdata) 2910 dev->chip_id = dev->pdata->chip_id; 2911 2912 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 2913 GPIOD_OUT_LOW); 2914 if (IS_ERR(dev->reset_gpio)) 2915 return PTR_ERR(dev->reset_gpio); 2916 2917 if (dev->reset_gpio) { 2918 gpiod_set_value_cansleep(dev->reset_gpio, 1); 2919 usleep_range(10000, 12000); 2920 gpiod_set_value_cansleep(dev->reset_gpio, 0); 2921 msleep(100); 2922 } 2923 2924 mutex_init(&dev->dev_mutex); 2925 mutex_init(&dev->regmap_mutex); 2926 mutex_init(&dev->alu_mutex); 2927 mutex_init(&dev->vlan_mutex); 2928 2929 ret = ksz_switch_detect(dev); 2930 if (ret) 2931 return ret; 2932 2933 info = ksz_lookup_info(dev->chip_id); 2934 if (!info) 2935 return -ENODEV; 2936 2937 /* Update the compatible info with the probed one */ 2938 dev->info = info; 2939 2940 dev_info(dev->dev, "found switch: %s, rev %i\n", 2941 dev->info->dev_name, dev->chip_rev); 2942 2943 ret = ksz_check_device_id(dev); 2944 if (ret) 2945 return ret; 2946 2947 dev->dev_ops = dev->info->ops; 2948 2949 ret = dev->dev_ops->init(dev); 2950 if (ret) 2951 return ret; 2952 2953 dev->ports = devm_kzalloc(dev->dev, 2954 dev->info->port_cnt * sizeof(struct ksz_port), 2955 GFP_KERNEL); 2956 if (!dev->ports) 2957 return -ENOMEM; 2958 2959 for (i = 0; i < dev->info->port_cnt; i++) { 2960 spin_lock_init(&dev->ports[i].mib.stats64_lock); 2961 mutex_init(&dev->ports[i].mib.cnt_mutex); 2962 dev->ports[i].mib.counters = 2963 devm_kzalloc(dev->dev, 2964 sizeof(u64) * (dev->info->mib_cnt + 1), 2965 GFP_KERNEL); 2966 if (!dev->ports[i].mib.counters) 2967 return -ENOMEM; 2968 2969 dev->ports[i].ksz_dev = dev; 2970 dev->ports[i].num = i; 2971 } 2972 2973 /* set the real number of ports */ 2974 dev->ds->num_ports = dev->info->port_cnt; 2975 2976 /* Host port interface will be self detected, or specifically set in 2977 * device tree. 2978 */ 2979 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 2980 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 2981 if (dev->dev->of_node) { 2982 ret = of_get_phy_mode(dev->dev->of_node, &interface); 2983 if (ret == 0) 2984 dev->compat_interface = interface; 2985 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 2986 if (!ports) 2987 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 2988 if (ports) { 2989 for_each_available_child_of_node(ports, port) { 2990 if (of_property_read_u32(port, "reg", 2991 &port_num)) 2992 continue; 2993 if (!(dev->port_mask & BIT(port_num))) { 2994 of_node_put(port); 2995 of_node_put(ports); 2996 return -EINVAL; 2997 } 2998 of_get_phy_mode(port, 2999 &dev->ports[port_num].interface); 3000 3001 ksz_parse_rgmii_delay(dev, port_num, port); 3002 } 3003 of_node_put(ports); 3004 } 3005 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 3006 "microchip,synclko-125"); 3007 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 3008 "microchip,synclko-disable"); 3009 if (dev->synclko_125 && dev->synclko_disable) { 3010 dev_err(dev->dev, "inconsistent synclko settings\n"); 3011 return -EINVAL; 3012 } 3013 } 3014 3015 ret = dsa_register_switch(dev->ds); 3016 if (ret) { 3017 dev->dev_ops->exit(dev); 3018 return ret; 3019 } 3020 3021 /* Read MIB counters every 30 seconds to avoid overflow. */ 3022 dev->mib_read_interval = msecs_to_jiffies(5000); 3023 3024 /* Start the MIB timer. */ 3025 schedule_delayed_work(&dev->mib_read, 0); 3026 3027 return ret; 3028 } 3029 EXPORT_SYMBOL(ksz_switch_register); 3030 3031 void ksz_switch_remove(struct ksz_device *dev) 3032 { 3033 /* timer started */ 3034 if (dev->mib_read_interval) { 3035 dev->mib_read_interval = 0; 3036 cancel_delayed_work_sync(&dev->mib_read); 3037 } 3038 3039 dev->dev_ops->exit(dev); 3040 dsa_unregister_switch(dev->ds); 3041 3042 if (dev->reset_gpio) 3043 gpiod_set_value_cansleep(dev->reset_gpio, 1); 3044 3045 } 3046 EXPORT_SYMBOL(ksz_switch_remove); 3047 3048 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 3049 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 3050 MODULE_LICENSE("GPL"); 3051