1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/export.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/platform_data/microchip-ksz.h> 14 #include <linux/phy.h> 15 #include <linux/etherdevice.h> 16 #include <linux/if_bridge.h> 17 #include <linux/of_device.h> 18 #include <linux/of_net.h> 19 #include <linux/micrel_phy.h> 20 #include <net/dsa.h> 21 #include <net/switchdev.h> 22 23 #include "ksz_common.h" 24 #include "ksz8.h" 25 #include "ksz9477.h" 26 #include "lan937x.h" 27 28 #define MIB_COUNTER_NUM 0x20 29 30 struct ksz_stats_raw { 31 u64 rx_hi; 32 u64 rx_undersize; 33 u64 rx_fragments; 34 u64 rx_oversize; 35 u64 rx_jabbers; 36 u64 rx_symbol_err; 37 u64 rx_crc_err; 38 u64 rx_align_err; 39 u64 rx_mac_ctrl; 40 u64 rx_pause; 41 u64 rx_bcast; 42 u64 rx_mcast; 43 u64 rx_ucast; 44 u64 rx_64_or_less; 45 u64 rx_65_127; 46 u64 rx_128_255; 47 u64 rx_256_511; 48 u64 rx_512_1023; 49 u64 rx_1024_1522; 50 u64 rx_1523_2000; 51 u64 rx_2001; 52 u64 tx_hi; 53 u64 tx_late_col; 54 u64 tx_pause; 55 u64 tx_bcast; 56 u64 tx_mcast; 57 u64 tx_ucast; 58 u64 tx_deferred; 59 u64 tx_total_col; 60 u64 tx_exc_col; 61 u64 tx_single_col; 62 u64 tx_mult_col; 63 u64 rx_total; 64 u64 tx_total; 65 u64 rx_discards; 66 u64 tx_discards; 67 }; 68 69 static const struct ksz_mib_names ksz88xx_mib_names[] = { 70 { 0x00, "rx" }, 71 { 0x01, "rx_hi" }, 72 { 0x02, "rx_undersize" }, 73 { 0x03, "rx_fragments" }, 74 { 0x04, "rx_oversize" }, 75 { 0x05, "rx_jabbers" }, 76 { 0x06, "rx_symbol_err" }, 77 { 0x07, "rx_crc_err" }, 78 { 0x08, "rx_align_err" }, 79 { 0x09, "rx_mac_ctrl" }, 80 { 0x0a, "rx_pause" }, 81 { 0x0b, "rx_bcast" }, 82 { 0x0c, "rx_mcast" }, 83 { 0x0d, "rx_ucast" }, 84 { 0x0e, "rx_64_or_less" }, 85 { 0x0f, "rx_65_127" }, 86 { 0x10, "rx_128_255" }, 87 { 0x11, "rx_256_511" }, 88 { 0x12, "rx_512_1023" }, 89 { 0x13, "rx_1024_1522" }, 90 { 0x14, "tx" }, 91 { 0x15, "tx_hi" }, 92 { 0x16, "tx_late_col" }, 93 { 0x17, "tx_pause" }, 94 { 0x18, "tx_bcast" }, 95 { 0x19, "tx_mcast" }, 96 { 0x1a, "tx_ucast" }, 97 { 0x1b, "tx_deferred" }, 98 { 0x1c, "tx_total_col" }, 99 { 0x1d, "tx_exc_col" }, 100 { 0x1e, "tx_single_col" }, 101 { 0x1f, "tx_mult_col" }, 102 { 0x100, "rx_discards" }, 103 { 0x101, "tx_discards" }, 104 }; 105 106 static const struct ksz_mib_names ksz9477_mib_names[] = { 107 { 0x00, "rx_hi" }, 108 { 0x01, "rx_undersize" }, 109 { 0x02, "rx_fragments" }, 110 { 0x03, "rx_oversize" }, 111 { 0x04, "rx_jabbers" }, 112 { 0x05, "rx_symbol_err" }, 113 { 0x06, "rx_crc_err" }, 114 { 0x07, "rx_align_err" }, 115 { 0x08, "rx_mac_ctrl" }, 116 { 0x09, "rx_pause" }, 117 { 0x0A, "rx_bcast" }, 118 { 0x0B, "rx_mcast" }, 119 { 0x0C, "rx_ucast" }, 120 { 0x0D, "rx_64_or_less" }, 121 { 0x0E, "rx_65_127" }, 122 { 0x0F, "rx_128_255" }, 123 { 0x10, "rx_256_511" }, 124 { 0x11, "rx_512_1023" }, 125 { 0x12, "rx_1024_1522" }, 126 { 0x13, "rx_1523_2000" }, 127 { 0x14, "rx_2001" }, 128 { 0x15, "tx_hi" }, 129 { 0x16, "tx_late_col" }, 130 { 0x17, "tx_pause" }, 131 { 0x18, "tx_bcast" }, 132 { 0x19, "tx_mcast" }, 133 { 0x1A, "tx_ucast" }, 134 { 0x1B, "tx_deferred" }, 135 { 0x1C, "tx_total_col" }, 136 { 0x1D, "tx_exc_col" }, 137 { 0x1E, "tx_single_col" }, 138 { 0x1F, "tx_mult_col" }, 139 { 0x80, "rx_total" }, 140 { 0x81, "tx_total" }, 141 { 0x82, "rx_discards" }, 142 { 0x83, "tx_discards" }, 143 }; 144 145 static const struct ksz_dev_ops ksz8_dev_ops = { 146 .setup = ksz8_setup, 147 .get_port_addr = ksz8_get_port_addr, 148 .cfg_port_member = ksz8_cfg_port_member, 149 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 150 .port_setup = ksz8_port_setup, 151 .r_phy = ksz8_r_phy, 152 .w_phy = ksz8_w_phy, 153 .r_mib_cnt = ksz8_r_mib_cnt, 154 .r_mib_pkt = ksz8_r_mib_pkt, 155 .freeze_mib = ksz8_freeze_mib, 156 .port_init_cnt = ksz8_port_init_cnt, 157 .fdb_dump = ksz8_fdb_dump, 158 .mdb_add = ksz8_mdb_add, 159 .mdb_del = ksz8_mdb_del, 160 .vlan_filtering = ksz8_port_vlan_filtering, 161 .vlan_add = ksz8_port_vlan_add, 162 .vlan_del = ksz8_port_vlan_del, 163 .mirror_add = ksz8_port_mirror_add, 164 .mirror_del = ksz8_port_mirror_del, 165 .get_caps = ksz8_get_caps, 166 .config_cpu_port = ksz8_config_cpu_port, 167 .enable_stp_addr = ksz8_enable_stp_addr, 168 .reset = ksz8_reset_switch, 169 .init = ksz8_switch_init, 170 .exit = ksz8_switch_exit, 171 }; 172 173 static const struct ksz_dev_ops ksz9477_dev_ops = { 174 .setup = ksz9477_setup, 175 .get_port_addr = ksz9477_get_port_addr, 176 .cfg_port_member = ksz9477_cfg_port_member, 177 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 178 .port_setup = ksz9477_port_setup, 179 .r_phy = ksz9477_r_phy, 180 .w_phy = ksz9477_w_phy, 181 .r_mib_cnt = ksz9477_r_mib_cnt, 182 .r_mib_pkt = ksz9477_r_mib_pkt, 183 .r_mib_stat64 = ksz_r_mib_stats64, 184 .freeze_mib = ksz9477_freeze_mib, 185 .port_init_cnt = ksz9477_port_init_cnt, 186 .vlan_filtering = ksz9477_port_vlan_filtering, 187 .vlan_add = ksz9477_port_vlan_add, 188 .vlan_del = ksz9477_port_vlan_del, 189 .mirror_add = ksz9477_port_mirror_add, 190 .mirror_del = ksz9477_port_mirror_del, 191 .get_caps = ksz9477_get_caps, 192 .fdb_dump = ksz9477_fdb_dump, 193 .fdb_add = ksz9477_fdb_add, 194 .fdb_del = ksz9477_fdb_del, 195 .mdb_add = ksz9477_mdb_add, 196 .mdb_del = ksz9477_mdb_del, 197 .change_mtu = ksz9477_change_mtu, 198 .max_mtu = ksz9477_max_mtu, 199 .config_cpu_port = ksz9477_config_cpu_port, 200 .enable_stp_addr = ksz9477_enable_stp_addr, 201 .reset = ksz9477_reset_switch, 202 .init = ksz9477_switch_init, 203 .exit = ksz9477_switch_exit, 204 }; 205 206 static const struct ksz_dev_ops lan937x_dev_ops = { 207 .setup = lan937x_setup, 208 .get_port_addr = ksz9477_get_port_addr, 209 .cfg_port_member = ksz9477_cfg_port_member, 210 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 211 .port_setup = lan937x_port_setup, 212 .r_phy = lan937x_r_phy, 213 .w_phy = lan937x_w_phy, 214 .r_mib_cnt = ksz9477_r_mib_cnt, 215 .r_mib_pkt = ksz9477_r_mib_pkt, 216 .r_mib_stat64 = ksz_r_mib_stats64, 217 .freeze_mib = ksz9477_freeze_mib, 218 .port_init_cnt = ksz9477_port_init_cnt, 219 .vlan_filtering = ksz9477_port_vlan_filtering, 220 .vlan_add = ksz9477_port_vlan_add, 221 .vlan_del = ksz9477_port_vlan_del, 222 .mirror_add = ksz9477_port_mirror_add, 223 .mirror_del = ksz9477_port_mirror_del, 224 .get_caps = lan937x_phylink_get_caps, 225 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 226 .fdb_dump = ksz9477_fdb_dump, 227 .fdb_add = ksz9477_fdb_add, 228 .fdb_del = ksz9477_fdb_del, 229 .mdb_add = ksz9477_mdb_add, 230 .mdb_del = ksz9477_mdb_del, 231 .change_mtu = lan937x_change_mtu, 232 .max_mtu = ksz9477_max_mtu, 233 .config_cpu_port = lan937x_config_cpu_port, 234 .enable_stp_addr = ksz9477_enable_stp_addr, 235 .reset = lan937x_reset_switch, 236 .init = lan937x_switch_init, 237 .exit = lan937x_switch_exit, 238 }; 239 240 static const u16 ksz8795_regs[] = { 241 [REG_IND_CTRL_0] = 0x6E, 242 [REG_IND_DATA_8] = 0x70, 243 [REG_IND_DATA_CHECK] = 0x72, 244 [REG_IND_DATA_HI] = 0x71, 245 [REG_IND_DATA_LO] = 0x75, 246 [REG_IND_MIB_CHECK] = 0x74, 247 [REG_IND_BYTE] = 0xA0, 248 [P_FORCE_CTRL] = 0x0C, 249 [P_LINK_STATUS] = 0x0E, 250 [P_LOCAL_CTRL] = 0x07, 251 [P_NEG_RESTART_CTRL] = 0x0D, 252 [P_REMOTE_STATUS] = 0x08, 253 [P_SPEED_STATUS] = 0x09, 254 [S_TAIL_TAG_CTRL] = 0x0C, 255 [P_STP_CTRL] = 0x02, 256 [S_START_CTRL] = 0x01, 257 [S_BROADCAST_CTRL] = 0x06, 258 [S_MULTICAST_CTRL] = 0x04, 259 [P_XMII_CTRL_0] = 0x06, 260 [P_XMII_CTRL_1] = 0x56, 261 }; 262 263 static const u32 ksz8795_masks[] = { 264 [PORT_802_1P_REMAPPING] = BIT(7), 265 [SW_TAIL_TAG_ENABLE] = BIT(1), 266 [MIB_COUNTER_OVERFLOW] = BIT(6), 267 [MIB_COUNTER_VALID] = BIT(5), 268 [VLAN_TABLE_FID] = GENMASK(6, 0), 269 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 270 [VLAN_TABLE_VALID] = BIT(12), 271 [STATIC_MAC_TABLE_VALID] = BIT(21), 272 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 273 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 274 [STATIC_MAC_TABLE_OVERRIDE] = BIT(26), 275 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(24, 20), 276 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 277 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(8), 278 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 279 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 280 [DYNAMIC_MAC_TABLE_FID] = GENMASK(26, 20), 281 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 282 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 283 [P_MII_TX_FLOW_CTRL] = BIT(5), 284 [P_MII_RX_FLOW_CTRL] = BIT(5), 285 }; 286 287 static const u8 ksz8795_xmii_ctrl0[] = { 288 [P_MII_100MBIT] = 0, 289 [P_MII_10MBIT] = 1, 290 [P_MII_FULL_DUPLEX] = 0, 291 [P_MII_HALF_DUPLEX] = 1, 292 }; 293 294 static const u8 ksz8795_xmii_ctrl1[] = { 295 [P_RGMII_SEL] = 3, 296 [P_GMII_SEL] = 2, 297 [P_RMII_SEL] = 1, 298 [P_MII_SEL] = 0, 299 [P_GMII_1GBIT] = 1, 300 [P_GMII_NOT_1GBIT] = 0, 301 }; 302 303 static const u8 ksz8795_shifts[] = { 304 [VLAN_TABLE_MEMBERSHIP_S] = 7, 305 [VLAN_TABLE] = 16, 306 [STATIC_MAC_FWD_PORTS] = 16, 307 [STATIC_MAC_FID] = 24, 308 [DYNAMIC_MAC_ENTRIES_H] = 3, 309 [DYNAMIC_MAC_ENTRIES] = 29, 310 [DYNAMIC_MAC_FID] = 16, 311 [DYNAMIC_MAC_TIMESTAMP] = 27, 312 [DYNAMIC_MAC_SRC_PORT] = 24, 313 }; 314 315 static const u16 ksz8863_regs[] = { 316 [REG_IND_CTRL_0] = 0x79, 317 [REG_IND_DATA_8] = 0x7B, 318 [REG_IND_DATA_CHECK] = 0x7B, 319 [REG_IND_DATA_HI] = 0x7C, 320 [REG_IND_DATA_LO] = 0x80, 321 [REG_IND_MIB_CHECK] = 0x80, 322 [P_FORCE_CTRL] = 0x0C, 323 [P_LINK_STATUS] = 0x0E, 324 [P_LOCAL_CTRL] = 0x0C, 325 [P_NEG_RESTART_CTRL] = 0x0D, 326 [P_REMOTE_STATUS] = 0x0E, 327 [P_SPEED_STATUS] = 0x0F, 328 [S_TAIL_TAG_CTRL] = 0x03, 329 [P_STP_CTRL] = 0x02, 330 [S_START_CTRL] = 0x01, 331 [S_BROADCAST_CTRL] = 0x06, 332 [S_MULTICAST_CTRL] = 0x04, 333 }; 334 335 static const u32 ksz8863_masks[] = { 336 [PORT_802_1P_REMAPPING] = BIT(3), 337 [SW_TAIL_TAG_ENABLE] = BIT(6), 338 [MIB_COUNTER_OVERFLOW] = BIT(7), 339 [MIB_COUNTER_VALID] = BIT(6), 340 [VLAN_TABLE_FID] = GENMASK(15, 12), 341 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 342 [VLAN_TABLE_VALID] = BIT(19), 343 [STATIC_MAC_TABLE_VALID] = BIT(19), 344 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 345 [STATIC_MAC_TABLE_FID] = GENMASK(29, 26), 346 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 347 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 348 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(5, 0), 349 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 350 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 351 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 28), 352 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 353 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 354 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 355 }; 356 357 static u8 ksz8863_shifts[] = { 358 [VLAN_TABLE_MEMBERSHIP_S] = 16, 359 [STATIC_MAC_FWD_PORTS] = 16, 360 [STATIC_MAC_FID] = 22, 361 [DYNAMIC_MAC_ENTRIES_H] = 3, 362 [DYNAMIC_MAC_ENTRIES] = 24, 363 [DYNAMIC_MAC_FID] = 16, 364 [DYNAMIC_MAC_TIMESTAMP] = 24, 365 [DYNAMIC_MAC_SRC_PORT] = 20, 366 }; 367 368 static const u16 ksz9477_regs[] = { 369 [P_STP_CTRL] = 0x0B04, 370 [S_START_CTRL] = 0x0300, 371 [S_BROADCAST_CTRL] = 0x0332, 372 [S_MULTICAST_CTRL] = 0x0331, 373 [P_XMII_CTRL_0] = 0x0300, 374 [P_XMII_CTRL_1] = 0x0301, 375 }; 376 377 static const u32 ksz9477_masks[] = { 378 [ALU_STAT_WRITE] = 0, 379 [ALU_STAT_READ] = 1, 380 [P_MII_TX_FLOW_CTRL] = BIT(5), 381 [P_MII_RX_FLOW_CTRL] = BIT(3), 382 }; 383 384 static const u8 ksz9477_shifts[] = { 385 [ALU_STAT_INDEX] = 16, 386 }; 387 388 static const u8 ksz9477_xmii_ctrl0[] = { 389 [P_MII_100MBIT] = 1, 390 [P_MII_10MBIT] = 0, 391 [P_MII_FULL_DUPLEX] = 1, 392 [P_MII_HALF_DUPLEX] = 0, 393 }; 394 395 static const u8 ksz9477_xmii_ctrl1[] = { 396 [P_RGMII_SEL] = 0, 397 [P_RMII_SEL] = 1, 398 [P_GMII_SEL] = 2, 399 [P_MII_SEL] = 3, 400 [P_GMII_1GBIT] = 0, 401 [P_GMII_NOT_1GBIT] = 1, 402 }; 403 404 static const u32 lan937x_masks[] = { 405 [ALU_STAT_WRITE] = 1, 406 [ALU_STAT_READ] = 2, 407 [P_MII_TX_FLOW_CTRL] = BIT(5), 408 [P_MII_RX_FLOW_CTRL] = BIT(3), 409 }; 410 411 static const u8 lan937x_shifts[] = { 412 [ALU_STAT_INDEX] = 8, 413 }; 414 415 const struct ksz_chip_data ksz_switch_chips[] = { 416 [KSZ8795] = { 417 .chip_id = KSZ8795_CHIP_ID, 418 .dev_name = "KSZ8795", 419 .num_vlans = 4096, 420 .num_alus = 0, 421 .num_statics = 8, 422 .cpu_ports = 0x10, /* can be configured as cpu port */ 423 .port_cnt = 5, /* total cpu and user ports */ 424 .ops = &ksz8_dev_ops, 425 .ksz87xx_eee_link_erratum = true, 426 .mib_names = ksz9477_mib_names, 427 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 428 .reg_mib_cnt = MIB_COUNTER_NUM, 429 .regs = ksz8795_regs, 430 .masks = ksz8795_masks, 431 .shifts = ksz8795_shifts, 432 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 433 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 434 .supports_mii = {false, false, false, false, true}, 435 .supports_rmii = {false, false, false, false, true}, 436 .supports_rgmii = {false, false, false, false, true}, 437 .internal_phy = {true, true, true, true, false}, 438 }, 439 440 [KSZ8794] = { 441 /* WARNING 442 * ======= 443 * KSZ8794 is similar to KSZ8795, except the port map 444 * contains a gap between external and CPU ports, the 445 * port map is NOT continuous. The per-port register 446 * map is shifted accordingly too, i.e. registers at 447 * offset 0x40 are NOT used on KSZ8794 and they ARE 448 * used on KSZ8795 for external port 3. 449 * external cpu 450 * KSZ8794 0,1,2 4 451 * KSZ8795 0,1,2,3 4 452 * KSZ8765 0,1,2,3 4 453 * port_cnt is configured as 5, even though it is 4 454 */ 455 .chip_id = KSZ8794_CHIP_ID, 456 .dev_name = "KSZ8794", 457 .num_vlans = 4096, 458 .num_alus = 0, 459 .num_statics = 8, 460 .cpu_ports = 0x10, /* can be configured as cpu port */ 461 .port_cnt = 5, /* total cpu and user ports */ 462 .ops = &ksz8_dev_ops, 463 .ksz87xx_eee_link_erratum = true, 464 .mib_names = ksz9477_mib_names, 465 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 466 .reg_mib_cnt = MIB_COUNTER_NUM, 467 .regs = ksz8795_regs, 468 .masks = ksz8795_masks, 469 .shifts = ksz8795_shifts, 470 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 471 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 472 .supports_mii = {false, false, false, false, true}, 473 .supports_rmii = {false, false, false, false, true}, 474 .supports_rgmii = {false, false, false, false, true}, 475 .internal_phy = {true, true, true, false, false}, 476 }, 477 478 [KSZ8765] = { 479 .chip_id = KSZ8765_CHIP_ID, 480 .dev_name = "KSZ8765", 481 .num_vlans = 4096, 482 .num_alus = 0, 483 .num_statics = 8, 484 .cpu_ports = 0x10, /* can be configured as cpu port */ 485 .port_cnt = 5, /* total cpu and user ports */ 486 .ops = &ksz8_dev_ops, 487 .ksz87xx_eee_link_erratum = true, 488 .mib_names = ksz9477_mib_names, 489 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 490 .reg_mib_cnt = MIB_COUNTER_NUM, 491 .regs = ksz8795_regs, 492 .masks = ksz8795_masks, 493 .shifts = ksz8795_shifts, 494 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 495 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 496 .supports_mii = {false, false, false, false, true}, 497 .supports_rmii = {false, false, false, false, true}, 498 .supports_rgmii = {false, false, false, false, true}, 499 .internal_phy = {true, true, true, true, false}, 500 }, 501 502 [KSZ8830] = { 503 .chip_id = KSZ8830_CHIP_ID, 504 .dev_name = "KSZ8863/KSZ8873", 505 .num_vlans = 16, 506 .num_alus = 0, 507 .num_statics = 8, 508 .cpu_ports = 0x4, /* can be configured as cpu port */ 509 .port_cnt = 3, 510 .ops = &ksz8_dev_ops, 511 .mib_names = ksz88xx_mib_names, 512 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 513 .reg_mib_cnt = MIB_COUNTER_NUM, 514 .regs = ksz8863_regs, 515 .masks = ksz8863_masks, 516 .shifts = ksz8863_shifts, 517 .supports_mii = {false, false, true}, 518 .supports_rmii = {false, false, true}, 519 .internal_phy = {true, true, false}, 520 }, 521 522 [KSZ9477] = { 523 .chip_id = KSZ9477_CHIP_ID, 524 .dev_name = "KSZ9477", 525 .num_vlans = 4096, 526 .num_alus = 4096, 527 .num_statics = 16, 528 .cpu_ports = 0x7F, /* can be configured as cpu port */ 529 .port_cnt = 7, /* total physical port count */ 530 .ops = &ksz9477_dev_ops, 531 .phy_errata_9477 = true, 532 .mib_names = ksz9477_mib_names, 533 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 534 .reg_mib_cnt = MIB_COUNTER_NUM, 535 .regs = ksz9477_regs, 536 .masks = ksz9477_masks, 537 .shifts = ksz9477_shifts, 538 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 539 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 540 .supports_mii = {false, false, false, false, 541 false, true, false}, 542 .supports_rmii = {false, false, false, false, 543 false, true, false}, 544 .supports_rgmii = {false, false, false, false, 545 false, true, false}, 546 .internal_phy = {true, true, true, true, 547 true, false, false}, 548 }, 549 550 [KSZ9897] = { 551 .chip_id = KSZ9897_CHIP_ID, 552 .dev_name = "KSZ9897", 553 .num_vlans = 4096, 554 .num_alus = 4096, 555 .num_statics = 16, 556 .cpu_ports = 0x7F, /* can be configured as cpu port */ 557 .port_cnt = 7, /* total physical port count */ 558 .ops = &ksz9477_dev_ops, 559 .phy_errata_9477 = true, 560 .mib_names = ksz9477_mib_names, 561 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 562 .reg_mib_cnt = MIB_COUNTER_NUM, 563 .regs = ksz9477_regs, 564 .masks = ksz9477_masks, 565 .shifts = ksz9477_shifts, 566 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 567 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 568 .supports_mii = {false, false, false, false, 569 false, true, true}, 570 .supports_rmii = {false, false, false, false, 571 false, true, true}, 572 .supports_rgmii = {false, false, false, false, 573 false, true, true}, 574 .internal_phy = {true, true, true, true, 575 true, false, false}, 576 }, 577 578 [KSZ9893] = { 579 .chip_id = KSZ9893_CHIP_ID, 580 .dev_name = "KSZ9893", 581 .num_vlans = 4096, 582 .num_alus = 4096, 583 .num_statics = 16, 584 .cpu_ports = 0x07, /* can be configured as cpu port */ 585 .port_cnt = 3, /* total port count */ 586 .ops = &ksz9477_dev_ops, 587 .mib_names = ksz9477_mib_names, 588 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 589 .reg_mib_cnt = MIB_COUNTER_NUM, 590 .regs = ksz9477_regs, 591 .masks = ksz9477_masks, 592 .shifts = ksz9477_shifts, 593 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 594 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 595 .supports_mii = {false, false, true}, 596 .supports_rmii = {false, false, true}, 597 .supports_rgmii = {false, false, true}, 598 .internal_phy = {true, true, false}, 599 }, 600 601 [KSZ9567] = { 602 .chip_id = KSZ9567_CHIP_ID, 603 .dev_name = "KSZ9567", 604 .num_vlans = 4096, 605 .num_alus = 4096, 606 .num_statics = 16, 607 .cpu_ports = 0x7F, /* can be configured as cpu port */ 608 .port_cnt = 7, /* total physical port count */ 609 .ops = &ksz9477_dev_ops, 610 .phy_errata_9477 = true, 611 .mib_names = ksz9477_mib_names, 612 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 613 .reg_mib_cnt = MIB_COUNTER_NUM, 614 .regs = ksz9477_regs, 615 .masks = ksz9477_masks, 616 .shifts = ksz9477_shifts, 617 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 618 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 619 .supports_mii = {false, false, false, false, 620 false, true, true}, 621 .supports_rmii = {false, false, false, false, 622 false, true, true}, 623 .supports_rgmii = {false, false, false, false, 624 false, true, true}, 625 .internal_phy = {true, true, true, true, 626 true, false, false}, 627 }, 628 629 [LAN9370] = { 630 .chip_id = LAN9370_CHIP_ID, 631 .dev_name = "LAN9370", 632 .num_vlans = 4096, 633 .num_alus = 1024, 634 .num_statics = 256, 635 .cpu_ports = 0x10, /* can be configured as cpu port */ 636 .port_cnt = 5, /* total physical port count */ 637 .ops = &lan937x_dev_ops, 638 .mib_names = ksz9477_mib_names, 639 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 640 .reg_mib_cnt = MIB_COUNTER_NUM, 641 .regs = ksz9477_regs, 642 .masks = lan937x_masks, 643 .shifts = lan937x_shifts, 644 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 645 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 646 .supports_mii = {false, false, false, false, true}, 647 .supports_rmii = {false, false, false, false, true}, 648 .supports_rgmii = {false, false, false, false, true}, 649 .internal_phy = {true, true, true, true, false}, 650 }, 651 652 [LAN9371] = { 653 .chip_id = LAN9371_CHIP_ID, 654 .dev_name = "LAN9371", 655 .num_vlans = 4096, 656 .num_alus = 1024, 657 .num_statics = 256, 658 .cpu_ports = 0x30, /* can be configured as cpu port */ 659 .port_cnt = 6, /* total physical port count */ 660 .ops = &lan937x_dev_ops, 661 .mib_names = ksz9477_mib_names, 662 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 663 .reg_mib_cnt = MIB_COUNTER_NUM, 664 .regs = ksz9477_regs, 665 .masks = lan937x_masks, 666 .shifts = lan937x_shifts, 667 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 668 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 669 .supports_mii = {false, false, false, false, true, true}, 670 .supports_rmii = {false, false, false, false, true, true}, 671 .supports_rgmii = {false, false, false, false, true, true}, 672 .internal_phy = {true, true, true, true, false, false}, 673 }, 674 675 [LAN9372] = { 676 .chip_id = LAN9372_CHIP_ID, 677 .dev_name = "LAN9372", 678 .num_vlans = 4096, 679 .num_alus = 1024, 680 .num_statics = 256, 681 .cpu_ports = 0x30, /* can be configured as cpu port */ 682 .port_cnt = 8, /* total physical port count */ 683 .ops = &lan937x_dev_ops, 684 .mib_names = ksz9477_mib_names, 685 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 686 .reg_mib_cnt = MIB_COUNTER_NUM, 687 .regs = ksz9477_regs, 688 .masks = lan937x_masks, 689 .shifts = lan937x_shifts, 690 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 691 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 692 .supports_mii = {false, false, false, false, 693 true, true, false, false}, 694 .supports_rmii = {false, false, false, false, 695 true, true, false, false}, 696 .supports_rgmii = {false, false, false, false, 697 true, true, false, false}, 698 .internal_phy = {true, true, true, true, 699 false, false, true, true}, 700 }, 701 702 [LAN9373] = { 703 .chip_id = LAN9373_CHIP_ID, 704 .dev_name = "LAN9373", 705 .num_vlans = 4096, 706 .num_alus = 1024, 707 .num_statics = 256, 708 .cpu_ports = 0x38, /* can be configured as cpu port */ 709 .port_cnt = 5, /* total physical port count */ 710 .ops = &lan937x_dev_ops, 711 .mib_names = ksz9477_mib_names, 712 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 713 .reg_mib_cnt = MIB_COUNTER_NUM, 714 .regs = ksz9477_regs, 715 .masks = lan937x_masks, 716 .shifts = lan937x_shifts, 717 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 718 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 719 .supports_mii = {false, false, false, false, 720 true, true, false, false}, 721 .supports_rmii = {false, false, false, false, 722 true, true, false, false}, 723 .supports_rgmii = {false, false, false, false, 724 true, true, false, false}, 725 .internal_phy = {true, true, true, false, 726 false, false, true, true}, 727 }, 728 729 [LAN9374] = { 730 .chip_id = LAN9374_CHIP_ID, 731 .dev_name = "LAN9374", 732 .num_vlans = 4096, 733 .num_alus = 1024, 734 .num_statics = 256, 735 .cpu_ports = 0x30, /* can be configured as cpu port */ 736 .port_cnt = 8, /* total physical port count */ 737 .ops = &lan937x_dev_ops, 738 .mib_names = ksz9477_mib_names, 739 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 740 .reg_mib_cnt = MIB_COUNTER_NUM, 741 .regs = ksz9477_regs, 742 .masks = lan937x_masks, 743 .shifts = lan937x_shifts, 744 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 745 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 746 .supports_mii = {false, false, false, false, 747 true, true, false, false}, 748 .supports_rmii = {false, false, false, false, 749 true, true, false, false}, 750 .supports_rgmii = {false, false, false, false, 751 true, true, false, false}, 752 .internal_phy = {true, true, true, true, 753 false, false, true, true}, 754 }, 755 }; 756 EXPORT_SYMBOL_GPL(ksz_switch_chips); 757 758 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 759 { 760 int i; 761 762 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 763 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 764 765 if (chip->chip_id == prod_num) 766 return chip; 767 } 768 769 return NULL; 770 } 771 772 static int ksz_check_device_id(struct ksz_device *dev) 773 { 774 const struct ksz_chip_data *dt_chip_data; 775 776 dt_chip_data = of_device_get_match_data(dev->dev); 777 778 /* Check for Device Tree and Chip ID */ 779 if (dt_chip_data->chip_id != dev->chip_id) { 780 dev_err(dev->dev, 781 "Device tree specifies chip %s but found %s, please fix it!\n", 782 dt_chip_data->dev_name, dev->info->dev_name); 783 return -ENODEV; 784 } 785 786 return 0; 787 } 788 789 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 790 struct phylink_config *config) 791 { 792 struct ksz_device *dev = ds->priv; 793 794 config->legacy_pre_march2020 = false; 795 796 if (dev->info->supports_mii[port]) 797 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 798 799 if (dev->info->supports_rmii[port]) 800 __set_bit(PHY_INTERFACE_MODE_RMII, 801 config->supported_interfaces); 802 803 if (dev->info->supports_rgmii[port]) 804 phy_interface_set_rgmii(config->supported_interfaces); 805 806 if (dev->info->internal_phy[port]) 807 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 808 config->supported_interfaces); 809 810 if (dev->dev_ops->get_caps) 811 dev->dev_ops->get_caps(dev, port, config); 812 } 813 814 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 815 { 816 struct ethtool_pause_stats *pstats; 817 struct rtnl_link_stats64 *stats; 818 struct ksz_stats_raw *raw; 819 struct ksz_port_mib *mib; 820 821 mib = &dev->ports[port].mib; 822 stats = &mib->stats64; 823 pstats = &mib->pause_stats; 824 raw = (struct ksz_stats_raw *)mib->counters; 825 826 spin_lock(&mib->stats64_lock); 827 828 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 829 raw->rx_pause; 830 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 831 raw->tx_pause; 832 833 /* HW counters are counting bytes + FCS which is not acceptable 834 * for rtnl_link_stats64 interface 835 */ 836 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 837 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 838 839 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 840 raw->rx_oversize; 841 842 stats->rx_crc_errors = raw->rx_crc_err; 843 stats->rx_frame_errors = raw->rx_align_err; 844 stats->rx_dropped = raw->rx_discards; 845 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 846 stats->rx_frame_errors + stats->rx_dropped; 847 848 stats->tx_window_errors = raw->tx_late_col; 849 stats->tx_fifo_errors = raw->tx_discards; 850 stats->tx_aborted_errors = raw->tx_exc_col; 851 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 852 stats->tx_aborted_errors; 853 854 stats->multicast = raw->rx_mcast; 855 stats->collisions = raw->tx_total_col; 856 857 pstats->tx_pause_frames = raw->tx_pause; 858 pstats->rx_pause_frames = raw->rx_pause; 859 860 spin_unlock(&mib->stats64_lock); 861 } 862 863 static void ksz_get_stats64(struct dsa_switch *ds, int port, 864 struct rtnl_link_stats64 *s) 865 { 866 struct ksz_device *dev = ds->priv; 867 struct ksz_port_mib *mib; 868 869 mib = &dev->ports[port].mib; 870 871 spin_lock(&mib->stats64_lock); 872 memcpy(s, &mib->stats64, sizeof(*s)); 873 spin_unlock(&mib->stats64_lock); 874 } 875 876 static void ksz_get_pause_stats(struct dsa_switch *ds, int port, 877 struct ethtool_pause_stats *pause_stats) 878 { 879 struct ksz_device *dev = ds->priv; 880 struct ksz_port_mib *mib; 881 882 mib = &dev->ports[port].mib; 883 884 spin_lock(&mib->stats64_lock); 885 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 886 spin_unlock(&mib->stats64_lock); 887 } 888 889 static void ksz_get_strings(struct dsa_switch *ds, int port, 890 u32 stringset, uint8_t *buf) 891 { 892 struct ksz_device *dev = ds->priv; 893 int i; 894 895 if (stringset != ETH_SS_STATS) 896 return; 897 898 for (i = 0; i < dev->info->mib_cnt; i++) { 899 memcpy(buf + i * ETH_GSTRING_LEN, 900 dev->info->mib_names[i].string, ETH_GSTRING_LEN); 901 } 902 } 903 904 static void ksz_update_port_member(struct ksz_device *dev, int port) 905 { 906 struct ksz_port *p = &dev->ports[port]; 907 struct dsa_switch *ds = dev->ds; 908 u8 port_member = 0, cpu_port; 909 const struct dsa_port *dp; 910 int i, j; 911 912 if (!dsa_is_user_port(ds, port)) 913 return; 914 915 dp = dsa_to_port(ds, port); 916 cpu_port = BIT(dsa_upstream_port(ds, port)); 917 918 for (i = 0; i < ds->num_ports; i++) { 919 const struct dsa_port *other_dp = dsa_to_port(ds, i); 920 struct ksz_port *other_p = &dev->ports[i]; 921 u8 val = 0; 922 923 if (!dsa_is_user_port(ds, i)) 924 continue; 925 if (port == i) 926 continue; 927 if (!dsa_port_bridge_same(dp, other_dp)) 928 continue; 929 if (other_p->stp_state != BR_STATE_FORWARDING) 930 continue; 931 932 if (p->stp_state == BR_STATE_FORWARDING) { 933 val |= BIT(port); 934 port_member |= BIT(i); 935 } 936 937 /* Retain port [i]'s relationship to other ports than [port] */ 938 for (j = 0; j < ds->num_ports; j++) { 939 const struct dsa_port *third_dp; 940 struct ksz_port *third_p; 941 942 if (j == i) 943 continue; 944 if (j == port) 945 continue; 946 if (!dsa_is_user_port(ds, j)) 947 continue; 948 third_p = &dev->ports[j]; 949 if (third_p->stp_state != BR_STATE_FORWARDING) 950 continue; 951 third_dp = dsa_to_port(ds, j); 952 if (dsa_port_bridge_same(other_dp, third_dp)) 953 val |= BIT(j); 954 } 955 956 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 957 } 958 959 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 960 } 961 962 static int ksz_setup(struct dsa_switch *ds) 963 { 964 struct ksz_device *dev = ds->priv; 965 const u16 *regs; 966 int ret; 967 968 regs = dev->info->regs; 969 970 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 971 dev->info->num_vlans, GFP_KERNEL); 972 if (!dev->vlan_cache) 973 return -ENOMEM; 974 975 ret = dev->dev_ops->reset(dev); 976 if (ret) { 977 dev_err(ds->dev, "failed to reset switch\n"); 978 return ret; 979 } 980 981 /* set broadcast storm protection 10% rate */ 982 regmap_update_bits(dev->regmap[1], regs[S_BROADCAST_CTRL], 983 BROADCAST_STORM_RATE, 984 (BROADCAST_STORM_VALUE * 985 BROADCAST_STORM_PROT_RATE) / 100); 986 987 dev->dev_ops->config_cpu_port(ds); 988 989 dev->dev_ops->enable_stp_addr(dev); 990 991 regmap_update_bits(dev->regmap[0], regs[S_MULTICAST_CTRL], 992 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 993 994 ksz_init_mib_timer(dev); 995 996 ds->configure_vlan_while_not_filtering = false; 997 998 if (dev->dev_ops->setup) { 999 ret = dev->dev_ops->setup(ds); 1000 if (ret) 1001 return ret; 1002 } 1003 1004 /* start switch */ 1005 regmap_update_bits(dev->regmap[0], regs[S_START_CTRL], 1006 SW_START, SW_START); 1007 1008 return 0; 1009 } 1010 1011 static void port_r_cnt(struct ksz_device *dev, int port) 1012 { 1013 struct ksz_port_mib *mib = &dev->ports[port].mib; 1014 u64 *dropped; 1015 1016 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 1017 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 1018 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 1019 &mib->counters[mib->cnt_ptr]); 1020 ++mib->cnt_ptr; 1021 } 1022 1023 /* last one in storage */ 1024 dropped = &mib->counters[dev->info->mib_cnt]; 1025 1026 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 1027 while (mib->cnt_ptr < dev->info->mib_cnt) { 1028 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 1029 dropped, &mib->counters[mib->cnt_ptr]); 1030 ++mib->cnt_ptr; 1031 } 1032 mib->cnt_ptr = 0; 1033 } 1034 1035 static void ksz_mib_read_work(struct work_struct *work) 1036 { 1037 struct ksz_device *dev = container_of(work, struct ksz_device, 1038 mib_read.work); 1039 struct ksz_port_mib *mib; 1040 struct ksz_port *p; 1041 int i; 1042 1043 for (i = 0; i < dev->info->port_cnt; i++) { 1044 if (dsa_is_unused_port(dev->ds, i)) 1045 continue; 1046 1047 p = &dev->ports[i]; 1048 mib = &p->mib; 1049 mutex_lock(&mib->cnt_mutex); 1050 1051 /* Only read MIB counters when the port is told to do. 1052 * If not, read only dropped counters when link is not up. 1053 */ 1054 if (!p->read) { 1055 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 1056 1057 if (!netif_carrier_ok(dp->slave)) 1058 mib->cnt_ptr = dev->info->reg_mib_cnt; 1059 } 1060 port_r_cnt(dev, i); 1061 p->read = false; 1062 1063 if (dev->dev_ops->r_mib_stat64) 1064 dev->dev_ops->r_mib_stat64(dev, i); 1065 1066 mutex_unlock(&mib->cnt_mutex); 1067 } 1068 1069 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 1070 } 1071 1072 void ksz_init_mib_timer(struct ksz_device *dev) 1073 { 1074 int i; 1075 1076 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 1077 1078 for (i = 0; i < dev->info->port_cnt; i++) { 1079 struct ksz_port_mib *mib = &dev->ports[i].mib; 1080 1081 dev->dev_ops->port_init_cnt(dev, i); 1082 1083 mib->cnt_ptr = 0; 1084 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 1085 } 1086 } 1087 1088 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 1089 { 1090 struct ksz_device *dev = ds->priv; 1091 u16 val = 0xffff; 1092 1093 dev->dev_ops->r_phy(dev, addr, reg, &val); 1094 1095 return val; 1096 } 1097 1098 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 1099 { 1100 struct ksz_device *dev = ds->priv; 1101 1102 dev->dev_ops->w_phy(dev, addr, reg, val); 1103 1104 return 0; 1105 } 1106 1107 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 1108 { 1109 struct ksz_device *dev = ds->priv; 1110 1111 if (dev->chip_id == KSZ8830_CHIP_ID) { 1112 /* Silicon Errata Sheet (DS80000830A): 1113 * Port 1 does not work with LinkMD Cable-Testing. 1114 * Port 1 does not respond to received PAUSE control frames. 1115 */ 1116 if (!port) 1117 return MICREL_KSZ8_P1_ERRATA; 1118 } 1119 1120 return 0; 1121 } 1122 1123 static void ksz_mac_link_down(struct dsa_switch *ds, int port, 1124 unsigned int mode, phy_interface_t interface) 1125 { 1126 struct ksz_device *dev = ds->priv; 1127 struct ksz_port *p = &dev->ports[port]; 1128 1129 /* Read all MIB counters when the link is going down. */ 1130 p->read = true; 1131 /* timer started */ 1132 if (dev->mib_read_interval) 1133 schedule_delayed_work(&dev->mib_read, 0); 1134 } 1135 1136 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 1137 { 1138 struct ksz_device *dev = ds->priv; 1139 1140 if (sset != ETH_SS_STATS) 1141 return 0; 1142 1143 return dev->info->mib_cnt; 1144 } 1145 1146 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 1147 uint64_t *buf) 1148 { 1149 const struct dsa_port *dp = dsa_to_port(ds, port); 1150 struct ksz_device *dev = ds->priv; 1151 struct ksz_port_mib *mib; 1152 1153 mib = &dev->ports[port].mib; 1154 mutex_lock(&mib->cnt_mutex); 1155 1156 /* Only read dropped counters if no link. */ 1157 if (!netif_carrier_ok(dp->slave)) 1158 mib->cnt_ptr = dev->info->reg_mib_cnt; 1159 port_r_cnt(dev, port); 1160 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 1161 mutex_unlock(&mib->cnt_mutex); 1162 } 1163 1164 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 1165 struct dsa_bridge bridge, 1166 bool *tx_fwd_offload, 1167 struct netlink_ext_ack *extack) 1168 { 1169 /* port_stp_state_set() will be called after to put the port in 1170 * appropriate state so there is no need to do anything. 1171 */ 1172 1173 return 0; 1174 } 1175 1176 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 1177 struct dsa_bridge bridge) 1178 { 1179 /* port_stp_state_set() will be called after to put the port in 1180 * forwarding state so there is no need to do anything. 1181 */ 1182 } 1183 1184 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 1185 { 1186 struct ksz_device *dev = ds->priv; 1187 1188 dev->dev_ops->flush_dyn_mac_table(dev, port); 1189 } 1190 1191 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 1192 const unsigned char *addr, u16 vid, 1193 struct dsa_db db) 1194 { 1195 struct ksz_device *dev = ds->priv; 1196 1197 if (!dev->dev_ops->fdb_add) 1198 return -EOPNOTSUPP; 1199 1200 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 1201 } 1202 1203 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 1204 const unsigned char *addr, 1205 u16 vid, struct dsa_db db) 1206 { 1207 struct ksz_device *dev = ds->priv; 1208 1209 if (!dev->dev_ops->fdb_del) 1210 return -EOPNOTSUPP; 1211 1212 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 1213 } 1214 1215 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 1216 dsa_fdb_dump_cb_t *cb, void *data) 1217 { 1218 struct ksz_device *dev = ds->priv; 1219 1220 if (!dev->dev_ops->fdb_dump) 1221 return -EOPNOTSUPP; 1222 1223 return dev->dev_ops->fdb_dump(dev, port, cb, data); 1224 } 1225 1226 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 1227 const struct switchdev_obj_port_mdb *mdb, 1228 struct dsa_db db) 1229 { 1230 struct ksz_device *dev = ds->priv; 1231 1232 if (!dev->dev_ops->mdb_add) 1233 return -EOPNOTSUPP; 1234 1235 return dev->dev_ops->mdb_add(dev, port, mdb, db); 1236 } 1237 1238 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 1239 const struct switchdev_obj_port_mdb *mdb, 1240 struct dsa_db db) 1241 { 1242 struct ksz_device *dev = ds->priv; 1243 1244 if (!dev->dev_ops->mdb_del) 1245 return -EOPNOTSUPP; 1246 1247 return dev->dev_ops->mdb_del(dev, port, mdb, db); 1248 } 1249 1250 static int ksz_enable_port(struct dsa_switch *ds, int port, 1251 struct phy_device *phy) 1252 { 1253 struct ksz_device *dev = ds->priv; 1254 1255 if (!dsa_is_user_port(ds, port)) 1256 return 0; 1257 1258 /* setup slave port */ 1259 dev->dev_ops->port_setup(dev, port, false); 1260 1261 /* port_stp_state_set() will be called after to enable the port so 1262 * there is no need to do anything. 1263 */ 1264 1265 return 0; 1266 } 1267 1268 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1269 { 1270 struct ksz_device *dev = ds->priv; 1271 struct ksz_port *p; 1272 const u16 *regs; 1273 u8 data; 1274 1275 regs = dev->info->regs; 1276 1277 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 1278 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 1279 1280 switch (state) { 1281 case BR_STATE_DISABLED: 1282 data |= PORT_LEARN_DISABLE; 1283 break; 1284 case BR_STATE_LISTENING: 1285 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 1286 break; 1287 case BR_STATE_LEARNING: 1288 data |= PORT_RX_ENABLE; 1289 break; 1290 case BR_STATE_FORWARDING: 1291 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 1292 break; 1293 case BR_STATE_BLOCKING: 1294 data |= PORT_LEARN_DISABLE; 1295 break; 1296 default: 1297 dev_err(ds->dev, "invalid STP state: %d\n", state); 1298 return; 1299 } 1300 1301 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 1302 1303 p = &dev->ports[port]; 1304 p->stp_state = state; 1305 1306 ksz_update_port_member(dev, port); 1307 } 1308 1309 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 1310 int port, 1311 enum dsa_tag_protocol mp) 1312 { 1313 struct ksz_device *dev = ds->priv; 1314 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 1315 1316 if (dev->chip_id == KSZ8795_CHIP_ID || 1317 dev->chip_id == KSZ8794_CHIP_ID || 1318 dev->chip_id == KSZ8765_CHIP_ID) 1319 proto = DSA_TAG_PROTO_KSZ8795; 1320 1321 if (dev->chip_id == KSZ8830_CHIP_ID || 1322 dev->chip_id == KSZ9893_CHIP_ID) 1323 proto = DSA_TAG_PROTO_KSZ9893; 1324 1325 if (dev->chip_id == KSZ9477_CHIP_ID || 1326 dev->chip_id == KSZ9897_CHIP_ID || 1327 dev->chip_id == KSZ9567_CHIP_ID) 1328 proto = DSA_TAG_PROTO_KSZ9477; 1329 1330 if (is_lan937x(dev)) 1331 proto = DSA_TAG_PROTO_LAN937X_VALUE; 1332 1333 return proto; 1334 } 1335 1336 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 1337 bool flag, struct netlink_ext_ack *extack) 1338 { 1339 struct ksz_device *dev = ds->priv; 1340 1341 if (!dev->dev_ops->vlan_filtering) 1342 return -EOPNOTSUPP; 1343 1344 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 1345 } 1346 1347 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 1348 const struct switchdev_obj_port_vlan *vlan, 1349 struct netlink_ext_ack *extack) 1350 { 1351 struct ksz_device *dev = ds->priv; 1352 1353 if (!dev->dev_ops->vlan_add) 1354 return -EOPNOTSUPP; 1355 1356 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 1357 } 1358 1359 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 1360 const struct switchdev_obj_port_vlan *vlan) 1361 { 1362 struct ksz_device *dev = ds->priv; 1363 1364 if (!dev->dev_ops->vlan_del) 1365 return -EOPNOTSUPP; 1366 1367 return dev->dev_ops->vlan_del(dev, port, vlan); 1368 } 1369 1370 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 1371 struct dsa_mall_mirror_tc_entry *mirror, 1372 bool ingress, struct netlink_ext_ack *extack) 1373 { 1374 struct ksz_device *dev = ds->priv; 1375 1376 if (!dev->dev_ops->mirror_add) 1377 return -EOPNOTSUPP; 1378 1379 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 1380 } 1381 1382 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 1383 struct dsa_mall_mirror_tc_entry *mirror) 1384 { 1385 struct ksz_device *dev = ds->priv; 1386 1387 if (dev->dev_ops->mirror_del) 1388 dev->dev_ops->mirror_del(dev, port, mirror); 1389 } 1390 1391 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 1392 { 1393 struct ksz_device *dev = ds->priv; 1394 1395 if (!dev->dev_ops->change_mtu) 1396 return -EOPNOTSUPP; 1397 1398 return dev->dev_ops->change_mtu(dev, port, mtu); 1399 } 1400 1401 static int ksz_max_mtu(struct dsa_switch *ds, int port) 1402 { 1403 struct ksz_device *dev = ds->priv; 1404 1405 if (!dev->dev_ops->max_mtu) 1406 return -EOPNOTSUPP; 1407 1408 return dev->dev_ops->max_mtu(dev, port); 1409 } 1410 1411 static void ksz_set_xmii(struct ksz_device *dev, int port, 1412 phy_interface_t interface) 1413 { 1414 const u8 *bitval = dev->info->xmii_ctrl1; 1415 struct ksz_port *p = &dev->ports[port]; 1416 const u16 *regs = dev->info->regs; 1417 u8 data8; 1418 1419 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 1420 1421 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 1422 P_RGMII_ID_EG_ENABLE); 1423 1424 switch (interface) { 1425 case PHY_INTERFACE_MODE_MII: 1426 data8 |= bitval[P_MII_SEL]; 1427 break; 1428 case PHY_INTERFACE_MODE_RMII: 1429 data8 |= bitval[P_RMII_SEL]; 1430 break; 1431 case PHY_INTERFACE_MODE_GMII: 1432 data8 |= bitval[P_GMII_SEL]; 1433 break; 1434 case PHY_INTERFACE_MODE_RGMII: 1435 case PHY_INTERFACE_MODE_RGMII_ID: 1436 case PHY_INTERFACE_MODE_RGMII_TXID: 1437 case PHY_INTERFACE_MODE_RGMII_RXID: 1438 data8 |= bitval[P_RGMII_SEL]; 1439 /* On KSZ9893, disable RGMII in-band status support */ 1440 if (dev->features & IS_9893) 1441 data8 &= ~P_MII_MAC_MODE; 1442 break; 1443 default: 1444 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 1445 phy_modes(interface), port); 1446 return; 1447 } 1448 1449 if (p->rgmii_tx_val) 1450 data8 |= P_RGMII_ID_EG_ENABLE; 1451 1452 if (p->rgmii_rx_val) 1453 data8 |= P_RGMII_ID_IG_ENABLE; 1454 1455 /* Write the updated value */ 1456 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 1457 } 1458 1459 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 1460 { 1461 const u8 *bitval = dev->info->xmii_ctrl1; 1462 const u16 *regs = dev->info->regs; 1463 phy_interface_t interface; 1464 u8 data8; 1465 u8 val; 1466 1467 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 1468 1469 val = FIELD_GET(P_MII_SEL_M, data8); 1470 1471 if (val == bitval[P_MII_SEL]) { 1472 if (gbit) 1473 interface = PHY_INTERFACE_MODE_GMII; 1474 else 1475 interface = PHY_INTERFACE_MODE_MII; 1476 } else if (val == bitval[P_RMII_SEL]) { 1477 interface = PHY_INTERFACE_MODE_RGMII; 1478 } else { 1479 interface = PHY_INTERFACE_MODE_RGMII; 1480 if (data8 & P_RGMII_ID_EG_ENABLE) 1481 interface = PHY_INTERFACE_MODE_RGMII_TXID; 1482 if (data8 & P_RGMII_ID_IG_ENABLE) { 1483 interface = PHY_INTERFACE_MODE_RGMII_RXID; 1484 if (data8 & P_RGMII_ID_EG_ENABLE) 1485 interface = PHY_INTERFACE_MODE_RGMII_ID; 1486 } 1487 } 1488 1489 return interface; 1490 } 1491 1492 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port, 1493 unsigned int mode, 1494 const struct phylink_link_state *state) 1495 { 1496 struct ksz_device *dev = ds->priv; 1497 1498 if (ksz_is_ksz88x3(dev)) 1499 return; 1500 1501 /* Internal PHYs */ 1502 if (dev->info->internal_phy[port]) 1503 return; 1504 1505 if (phylink_autoneg_inband(mode)) { 1506 dev_err(dev->dev, "In-band AN not supported!\n"); 1507 return; 1508 } 1509 1510 ksz_set_xmii(dev, port, state->interface); 1511 1512 if (dev->dev_ops->phylink_mac_config) 1513 dev->dev_ops->phylink_mac_config(dev, port, mode, state); 1514 1515 if (dev->dev_ops->setup_rgmii_delay) 1516 dev->dev_ops->setup_rgmii_delay(dev, port); 1517 } 1518 1519 bool ksz_get_gbit(struct ksz_device *dev, int port) 1520 { 1521 const u8 *bitval = dev->info->xmii_ctrl1; 1522 const u16 *regs = dev->info->regs; 1523 bool gbit = false; 1524 u8 data8; 1525 bool val; 1526 1527 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 1528 1529 val = FIELD_GET(P_GMII_1GBIT_M, data8); 1530 1531 if (val == bitval[P_GMII_1GBIT]) 1532 gbit = true; 1533 1534 return gbit; 1535 } 1536 1537 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) 1538 { 1539 const u8 *bitval = dev->info->xmii_ctrl1; 1540 const u16 *regs = dev->info->regs; 1541 u8 data8; 1542 1543 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 1544 1545 data8 &= ~P_GMII_1GBIT_M; 1546 1547 if (gbit) 1548 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 1549 else 1550 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 1551 1552 /* Write the updated value */ 1553 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 1554 } 1555 1556 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) 1557 { 1558 const u8 *bitval = dev->info->xmii_ctrl0; 1559 const u16 *regs = dev->info->regs; 1560 u8 data8; 1561 1562 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 1563 1564 data8 &= ~P_MII_100MBIT_M; 1565 1566 if (speed == SPEED_100) 1567 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 1568 else 1569 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 1570 1571 /* Write the updated value */ 1572 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 1573 } 1574 1575 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) 1576 { 1577 if (speed == SPEED_1000) 1578 ksz_set_gbit(dev, port, true); 1579 else 1580 ksz_set_gbit(dev, port, false); 1581 1582 if (speed == SPEED_100 || speed == SPEED_10) 1583 ksz_set_100_10mbit(dev, port, speed); 1584 } 1585 1586 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 1587 bool tx_pause, bool rx_pause) 1588 { 1589 const u8 *bitval = dev->info->xmii_ctrl0; 1590 const u32 *masks = dev->info->masks; 1591 const u16 *regs = dev->info->regs; 1592 u8 mask; 1593 u8 val; 1594 1595 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 1596 masks[P_MII_RX_FLOW_CTRL]; 1597 1598 if (duplex == DUPLEX_FULL) 1599 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 1600 else 1601 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 1602 1603 if (tx_pause) 1604 val |= masks[P_MII_TX_FLOW_CTRL]; 1605 1606 if (rx_pause) 1607 val |= masks[P_MII_RX_FLOW_CTRL]; 1608 1609 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 1610 } 1611 1612 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port, 1613 unsigned int mode, 1614 phy_interface_t interface, 1615 struct phy_device *phydev, int speed, 1616 int duplex, bool tx_pause, bool rx_pause) 1617 { 1618 struct ksz_device *dev = ds->priv; 1619 struct ksz_port *p; 1620 1621 p = &dev->ports[port]; 1622 1623 /* Internal PHYs */ 1624 if (dev->info->internal_phy[port]) 1625 return; 1626 1627 p->phydev.speed = speed; 1628 1629 ksz_port_set_xmii_speed(dev, port, speed); 1630 1631 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 1632 1633 if (dev->dev_ops->phylink_mac_link_up) 1634 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface, 1635 phydev, speed, duplex, 1636 tx_pause, rx_pause); 1637 } 1638 1639 static int ksz_switch_detect(struct ksz_device *dev) 1640 { 1641 u8 id1, id2; 1642 u16 id16; 1643 u32 id32; 1644 int ret; 1645 1646 /* read chip id */ 1647 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 1648 if (ret) 1649 return ret; 1650 1651 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 1652 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 1653 1654 switch (id1) { 1655 case KSZ87_FAMILY_ID: 1656 if (id2 == KSZ87_CHIP_ID_95) { 1657 u8 val; 1658 1659 dev->chip_id = KSZ8795_CHIP_ID; 1660 1661 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 1662 if (val & KSZ8_PORT_FIBER_MODE) 1663 dev->chip_id = KSZ8765_CHIP_ID; 1664 } else if (id2 == KSZ87_CHIP_ID_94) { 1665 dev->chip_id = KSZ8794_CHIP_ID; 1666 } else { 1667 return -ENODEV; 1668 } 1669 break; 1670 case KSZ88_FAMILY_ID: 1671 if (id2 == KSZ88_CHIP_ID_63) 1672 dev->chip_id = KSZ8830_CHIP_ID; 1673 else 1674 return -ENODEV; 1675 break; 1676 default: 1677 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 1678 if (ret) 1679 return ret; 1680 1681 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 1682 id32 &= ~0xFF; 1683 1684 switch (id32) { 1685 case KSZ9477_CHIP_ID: 1686 case KSZ9897_CHIP_ID: 1687 case KSZ9893_CHIP_ID: 1688 case KSZ9567_CHIP_ID: 1689 case LAN9370_CHIP_ID: 1690 case LAN9371_CHIP_ID: 1691 case LAN9372_CHIP_ID: 1692 case LAN9373_CHIP_ID: 1693 case LAN9374_CHIP_ID: 1694 dev->chip_id = id32; 1695 break; 1696 default: 1697 dev_err(dev->dev, 1698 "unsupported switch detected %x)\n", id32); 1699 return -ENODEV; 1700 } 1701 } 1702 return 0; 1703 } 1704 1705 static const struct dsa_switch_ops ksz_switch_ops = { 1706 .get_tag_protocol = ksz_get_tag_protocol, 1707 .get_phy_flags = ksz_get_phy_flags, 1708 .setup = ksz_setup, 1709 .phy_read = ksz_phy_read16, 1710 .phy_write = ksz_phy_write16, 1711 .phylink_get_caps = ksz_phylink_get_caps, 1712 .phylink_mac_config = ksz_phylink_mac_config, 1713 .phylink_mac_link_up = ksz_phylink_mac_link_up, 1714 .phylink_mac_link_down = ksz_mac_link_down, 1715 .port_enable = ksz_enable_port, 1716 .get_strings = ksz_get_strings, 1717 .get_ethtool_stats = ksz_get_ethtool_stats, 1718 .get_sset_count = ksz_sset_count, 1719 .port_bridge_join = ksz_port_bridge_join, 1720 .port_bridge_leave = ksz_port_bridge_leave, 1721 .port_stp_state_set = ksz_port_stp_state_set, 1722 .port_fast_age = ksz_port_fast_age, 1723 .port_vlan_filtering = ksz_port_vlan_filtering, 1724 .port_vlan_add = ksz_port_vlan_add, 1725 .port_vlan_del = ksz_port_vlan_del, 1726 .port_fdb_dump = ksz_port_fdb_dump, 1727 .port_fdb_add = ksz_port_fdb_add, 1728 .port_fdb_del = ksz_port_fdb_del, 1729 .port_mdb_add = ksz_port_mdb_add, 1730 .port_mdb_del = ksz_port_mdb_del, 1731 .port_mirror_add = ksz_port_mirror_add, 1732 .port_mirror_del = ksz_port_mirror_del, 1733 .get_stats64 = ksz_get_stats64, 1734 .get_pause_stats = ksz_get_pause_stats, 1735 .port_change_mtu = ksz_change_mtu, 1736 .port_max_mtu = ksz_max_mtu, 1737 }; 1738 1739 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 1740 { 1741 struct dsa_switch *ds; 1742 struct ksz_device *swdev; 1743 1744 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 1745 if (!ds) 1746 return NULL; 1747 1748 ds->dev = base; 1749 ds->num_ports = DSA_MAX_PORTS; 1750 ds->ops = &ksz_switch_ops; 1751 1752 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 1753 if (!swdev) 1754 return NULL; 1755 1756 ds->priv = swdev; 1757 swdev->dev = base; 1758 1759 swdev->ds = ds; 1760 swdev->priv = priv; 1761 1762 return swdev; 1763 } 1764 EXPORT_SYMBOL(ksz_switch_alloc); 1765 1766 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 1767 struct device_node *port_dn) 1768 { 1769 phy_interface_t phy_mode = dev->ports[port_num].interface; 1770 int rx_delay = -1, tx_delay = -1; 1771 1772 if (!phy_interface_mode_is_rgmii(phy_mode)) 1773 return; 1774 1775 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 1776 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 1777 1778 if (rx_delay == -1 && tx_delay == -1) { 1779 dev_warn(dev->dev, 1780 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 1781 "please update device tree to specify \"rx-internal-delay-ps\" and " 1782 "\"tx-internal-delay-ps\"", 1783 port_num); 1784 1785 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 1786 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 1787 rx_delay = 2000; 1788 1789 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 1790 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 1791 tx_delay = 2000; 1792 } 1793 1794 if (rx_delay < 0) 1795 rx_delay = 0; 1796 if (tx_delay < 0) 1797 tx_delay = 0; 1798 1799 dev->ports[port_num].rgmii_rx_val = rx_delay; 1800 dev->ports[port_num].rgmii_tx_val = tx_delay; 1801 } 1802 1803 int ksz_switch_register(struct ksz_device *dev) 1804 { 1805 const struct ksz_chip_data *info; 1806 struct device_node *port, *ports; 1807 phy_interface_t interface; 1808 unsigned int port_num; 1809 int ret; 1810 int i; 1811 1812 if (dev->pdata) 1813 dev->chip_id = dev->pdata->chip_id; 1814 1815 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 1816 GPIOD_OUT_LOW); 1817 if (IS_ERR(dev->reset_gpio)) 1818 return PTR_ERR(dev->reset_gpio); 1819 1820 if (dev->reset_gpio) { 1821 gpiod_set_value_cansleep(dev->reset_gpio, 1); 1822 usleep_range(10000, 12000); 1823 gpiod_set_value_cansleep(dev->reset_gpio, 0); 1824 msleep(100); 1825 } 1826 1827 mutex_init(&dev->dev_mutex); 1828 mutex_init(&dev->regmap_mutex); 1829 mutex_init(&dev->alu_mutex); 1830 mutex_init(&dev->vlan_mutex); 1831 1832 ret = ksz_switch_detect(dev); 1833 if (ret) 1834 return ret; 1835 1836 info = ksz_lookup_info(dev->chip_id); 1837 if (!info) 1838 return -ENODEV; 1839 1840 /* Update the compatible info with the probed one */ 1841 dev->info = info; 1842 1843 dev_info(dev->dev, "found switch: %s, rev %i\n", 1844 dev->info->dev_name, dev->chip_rev); 1845 1846 ret = ksz_check_device_id(dev); 1847 if (ret) 1848 return ret; 1849 1850 dev->dev_ops = dev->info->ops; 1851 1852 ret = dev->dev_ops->init(dev); 1853 if (ret) 1854 return ret; 1855 1856 dev->ports = devm_kzalloc(dev->dev, 1857 dev->info->port_cnt * sizeof(struct ksz_port), 1858 GFP_KERNEL); 1859 if (!dev->ports) 1860 return -ENOMEM; 1861 1862 for (i = 0; i < dev->info->port_cnt; i++) { 1863 spin_lock_init(&dev->ports[i].mib.stats64_lock); 1864 mutex_init(&dev->ports[i].mib.cnt_mutex); 1865 dev->ports[i].mib.counters = 1866 devm_kzalloc(dev->dev, 1867 sizeof(u64) * (dev->info->mib_cnt + 1), 1868 GFP_KERNEL); 1869 if (!dev->ports[i].mib.counters) 1870 return -ENOMEM; 1871 } 1872 1873 /* set the real number of ports */ 1874 dev->ds->num_ports = dev->info->port_cnt; 1875 1876 /* Host port interface will be self detected, or specifically set in 1877 * device tree. 1878 */ 1879 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 1880 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 1881 if (dev->dev->of_node) { 1882 ret = of_get_phy_mode(dev->dev->of_node, &interface); 1883 if (ret == 0) 1884 dev->compat_interface = interface; 1885 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 1886 if (!ports) 1887 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 1888 if (ports) { 1889 for_each_available_child_of_node(ports, port) { 1890 if (of_property_read_u32(port, "reg", 1891 &port_num)) 1892 continue; 1893 if (!(dev->port_mask & BIT(port_num))) { 1894 of_node_put(port); 1895 of_node_put(ports); 1896 return -EINVAL; 1897 } 1898 of_get_phy_mode(port, 1899 &dev->ports[port_num].interface); 1900 1901 ksz_parse_rgmii_delay(dev, port_num, port); 1902 } 1903 of_node_put(ports); 1904 } 1905 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 1906 "microchip,synclko-125"); 1907 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 1908 "microchip,synclko-disable"); 1909 if (dev->synclko_125 && dev->synclko_disable) { 1910 dev_err(dev->dev, "inconsistent synclko settings\n"); 1911 return -EINVAL; 1912 } 1913 } 1914 1915 ret = dsa_register_switch(dev->ds); 1916 if (ret) { 1917 dev->dev_ops->exit(dev); 1918 return ret; 1919 } 1920 1921 /* Read MIB counters every 30 seconds to avoid overflow. */ 1922 dev->mib_read_interval = msecs_to_jiffies(5000); 1923 1924 /* Start the MIB timer. */ 1925 schedule_delayed_work(&dev->mib_read, 0); 1926 1927 return ret; 1928 } 1929 EXPORT_SYMBOL(ksz_switch_register); 1930 1931 void ksz_switch_remove(struct ksz_device *dev) 1932 { 1933 /* timer started */ 1934 if (dev->mib_read_interval) { 1935 dev->mib_read_interval = 0; 1936 cancel_delayed_work_sync(&dev->mib_read); 1937 } 1938 1939 dev->dev_ops->exit(dev); 1940 dsa_unregister_switch(dev->ds); 1941 1942 if (dev->reset_gpio) 1943 gpiod_set_value_cansleep(dev->reset_gpio, 1); 1944 1945 } 1946 EXPORT_SYMBOL(ksz_switch_remove); 1947 1948 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 1949 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 1950 MODULE_LICENSE("GPL"); 1951