1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/export.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/platform_data/microchip-ksz.h> 14 #include <linux/phy.h> 15 #include <linux/etherdevice.h> 16 #include <linux/if_bridge.h> 17 #include <linux/if_vlan.h> 18 #include <linux/irq.h> 19 #include <linux/irqdomain.h> 20 #include <linux/of_mdio.h> 21 #include <linux/of_device.h> 22 #include <linux/of_net.h> 23 #include <linux/micrel_phy.h> 24 #include <net/dsa.h> 25 #include <net/switchdev.h> 26 27 #include "ksz_common.h" 28 #include "ksz8.h" 29 #include "ksz9477.h" 30 #include "lan937x.h" 31 32 #define MIB_COUNTER_NUM 0x20 33 34 struct ksz_stats_raw { 35 u64 rx_hi; 36 u64 rx_undersize; 37 u64 rx_fragments; 38 u64 rx_oversize; 39 u64 rx_jabbers; 40 u64 rx_symbol_err; 41 u64 rx_crc_err; 42 u64 rx_align_err; 43 u64 rx_mac_ctrl; 44 u64 rx_pause; 45 u64 rx_bcast; 46 u64 rx_mcast; 47 u64 rx_ucast; 48 u64 rx_64_or_less; 49 u64 rx_65_127; 50 u64 rx_128_255; 51 u64 rx_256_511; 52 u64 rx_512_1023; 53 u64 rx_1024_1522; 54 u64 rx_1523_2000; 55 u64 rx_2001; 56 u64 tx_hi; 57 u64 tx_late_col; 58 u64 tx_pause; 59 u64 tx_bcast; 60 u64 tx_mcast; 61 u64 tx_ucast; 62 u64 tx_deferred; 63 u64 tx_total_col; 64 u64 tx_exc_col; 65 u64 tx_single_col; 66 u64 tx_mult_col; 67 u64 rx_total; 68 u64 tx_total; 69 u64 rx_discards; 70 u64 tx_discards; 71 }; 72 73 struct ksz88xx_stats_raw { 74 u64 rx; 75 u64 rx_hi; 76 u64 rx_undersize; 77 u64 rx_fragments; 78 u64 rx_oversize; 79 u64 rx_jabbers; 80 u64 rx_symbol_err; 81 u64 rx_crc_err; 82 u64 rx_align_err; 83 u64 rx_mac_ctrl; 84 u64 rx_pause; 85 u64 rx_bcast; 86 u64 rx_mcast; 87 u64 rx_ucast; 88 u64 rx_64_or_less; 89 u64 rx_65_127; 90 u64 rx_128_255; 91 u64 rx_256_511; 92 u64 rx_512_1023; 93 u64 rx_1024_1522; 94 u64 tx; 95 u64 tx_hi; 96 u64 tx_late_col; 97 u64 tx_pause; 98 u64 tx_bcast; 99 u64 tx_mcast; 100 u64 tx_ucast; 101 u64 tx_deferred; 102 u64 tx_total_col; 103 u64 tx_exc_col; 104 u64 tx_single_col; 105 u64 tx_mult_col; 106 u64 rx_discards; 107 u64 tx_discards; 108 }; 109 110 static const struct ksz_mib_names ksz88xx_mib_names[] = { 111 { 0x00, "rx" }, 112 { 0x01, "rx_hi" }, 113 { 0x02, "rx_undersize" }, 114 { 0x03, "rx_fragments" }, 115 { 0x04, "rx_oversize" }, 116 { 0x05, "rx_jabbers" }, 117 { 0x06, "rx_symbol_err" }, 118 { 0x07, "rx_crc_err" }, 119 { 0x08, "rx_align_err" }, 120 { 0x09, "rx_mac_ctrl" }, 121 { 0x0a, "rx_pause" }, 122 { 0x0b, "rx_bcast" }, 123 { 0x0c, "rx_mcast" }, 124 { 0x0d, "rx_ucast" }, 125 { 0x0e, "rx_64_or_less" }, 126 { 0x0f, "rx_65_127" }, 127 { 0x10, "rx_128_255" }, 128 { 0x11, "rx_256_511" }, 129 { 0x12, "rx_512_1023" }, 130 { 0x13, "rx_1024_1522" }, 131 { 0x14, "tx" }, 132 { 0x15, "tx_hi" }, 133 { 0x16, "tx_late_col" }, 134 { 0x17, "tx_pause" }, 135 { 0x18, "tx_bcast" }, 136 { 0x19, "tx_mcast" }, 137 { 0x1a, "tx_ucast" }, 138 { 0x1b, "tx_deferred" }, 139 { 0x1c, "tx_total_col" }, 140 { 0x1d, "tx_exc_col" }, 141 { 0x1e, "tx_single_col" }, 142 { 0x1f, "tx_mult_col" }, 143 { 0x100, "rx_discards" }, 144 { 0x101, "tx_discards" }, 145 }; 146 147 static const struct ksz_mib_names ksz9477_mib_names[] = { 148 { 0x00, "rx_hi" }, 149 { 0x01, "rx_undersize" }, 150 { 0x02, "rx_fragments" }, 151 { 0x03, "rx_oversize" }, 152 { 0x04, "rx_jabbers" }, 153 { 0x05, "rx_symbol_err" }, 154 { 0x06, "rx_crc_err" }, 155 { 0x07, "rx_align_err" }, 156 { 0x08, "rx_mac_ctrl" }, 157 { 0x09, "rx_pause" }, 158 { 0x0A, "rx_bcast" }, 159 { 0x0B, "rx_mcast" }, 160 { 0x0C, "rx_ucast" }, 161 { 0x0D, "rx_64_or_less" }, 162 { 0x0E, "rx_65_127" }, 163 { 0x0F, "rx_128_255" }, 164 { 0x10, "rx_256_511" }, 165 { 0x11, "rx_512_1023" }, 166 { 0x12, "rx_1024_1522" }, 167 { 0x13, "rx_1523_2000" }, 168 { 0x14, "rx_2001" }, 169 { 0x15, "tx_hi" }, 170 { 0x16, "tx_late_col" }, 171 { 0x17, "tx_pause" }, 172 { 0x18, "tx_bcast" }, 173 { 0x19, "tx_mcast" }, 174 { 0x1A, "tx_ucast" }, 175 { 0x1B, "tx_deferred" }, 176 { 0x1C, "tx_total_col" }, 177 { 0x1D, "tx_exc_col" }, 178 { 0x1E, "tx_single_col" }, 179 { 0x1F, "tx_mult_col" }, 180 { 0x80, "rx_total" }, 181 { 0x81, "tx_total" }, 182 { 0x82, "rx_discards" }, 183 { 0x83, "tx_discards" }, 184 }; 185 186 static const struct ksz_dev_ops ksz8_dev_ops = { 187 .setup = ksz8_setup, 188 .get_port_addr = ksz8_get_port_addr, 189 .cfg_port_member = ksz8_cfg_port_member, 190 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 191 .port_setup = ksz8_port_setup, 192 .r_phy = ksz8_r_phy, 193 .w_phy = ksz8_w_phy, 194 .r_mib_cnt = ksz8_r_mib_cnt, 195 .r_mib_pkt = ksz8_r_mib_pkt, 196 .r_mib_stat64 = ksz88xx_r_mib_stats64, 197 .freeze_mib = ksz8_freeze_mib, 198 .port_init_cnt = ksz8_port_init_cnt, 199 .fdb_dump = ksz8_fdb_dump, 200 .mdb_add = ksz8_mdb_add, 201 .mdb_del = ksz8_mdb_del, 202 .vlan_filtering = ksz8_port_vlan_filtering, 203 .vlan_add = ksz8_port_vlan_add, 204 .vlan_del = ksz8_port_vlan_del, 205 .mirror_add = ksz8_port_mirror_add, 206 .mirror_del = ksz8_port_mirror_del, 207 .get_caps = ksz8_get_caps, 208 .config_cpu_port = ksz8_config_cpu_port, 209 .enable_stp_addr = ksz8_enable_stp_addr, 210 .reset = ksz8_reset_switch, 211 .init = ksz8_switch_init, 212 .exit = ksz8_switch_exit, 213 .change_mtu = ksz8_change_mtu, 214 }; 215 216 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, 217 unsigned int mode, 218 phy_interface_t interface, 219 struct phy_device *phydev, int speed, 220 int duplex, bool tx_pause, 221 bool rx_pause); 222 223 static const struct ksz_dev_ops ksz9477_dev_ops = { 224 .setup = ksz9477_setup, 225 .get_port_addr = ksz9477_get_port_addr, 226 .cfg_port_member = ksz9477_cfg_port_member, 227 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 228 .port_setup = ksz9477_port_setup, 229 .set_ageing_time = ksz9477_set_ageing_time, 230 .r_phy = ksz9477_r_phy, 231 .w_phy = ksz9477_w_phy, 232 .r_mib_cnt = ksz9477_r_mib_cnt, 233 .r_mib_pkt = ksz9477_r_mib_pkt, 234 .r_mib_stat64 = ksz_r_mib_stats64, 235 .freeze_mib = ksz9477_freeze_mib, 236 .port_init_cnt = ksz9477_port_init_cnt, 237 .vlan_filtering = ksz9477_port_vlan_filtering, 238 .vlan_add = ksz9477_port_vlan_add, 239 .vlan_del = ksz9477_port_vlan_del, 240 .mirror_add = ksz9477_port_mirror_add, 241 .mirror_del = ksz9477_port_mirror_del, 242 .get_caps = ksz9477_get_caps, 243 .fdb_dump = ksz9477_fdb_dump, 244 .fdb_add = ksz9477_fdb_add, 245 .fdb_del = ksz9477_fdb_del, 246 .mdb_add = ksz9477_mdb_add, 247 .mdb_del = ksz9477_mdb_del, 248 .change_mtu = ksz9477_change_mtu, 249 .phylink_mac_link_up = ksz9477_phylink_mac_link_up, 250 .config_cpu_port = ksz9477_config_cpu_port, 251 .enable_stp_addr = ksz9477_enable_stp_addr, 252 .reset = ksz9477_reset_switch, 253 .init = ksz9477_switch_init, 254 .exit = ksz9477_switch_exit, 255 }; 256 257 static const struct ksz_dev_ops lan937x_dev_ops = { 258 .setup = lan937x_setup, 259 .teardown = lan937x_teardown, 260 .get_port_addr = ksz9477_get_port_addr, 261 .cfg_port_member = ksz9477_cfg_port_member, 262 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 263 .port_setup = lan937x_port_setup, 264 .set_ageing_time = lan937x_set_ageing_time, 265 .r_phy = lan937x_r_phy, 266 .w_phy = lan937x_w_phy, 267 .r_mib_cnt = ksz9477_r_mib_cnt, 268 .r_mib_pkt = ksz9477_r_mib_pkt, 269 .r_mib_stat64 = ksz_r_mib_stats64, 270 .freeze_mib = ksz9477_freeze_mib, 271 .port_init_cnt = ksz9477_port_init_cnt, 272 .vlan_filtering = ksz9477_port_vlan_filtering, 273 .vlan_add = ksz9477_port_vlan_add, 274 .vlan_del = ksz9477_port_vlan_del, 275 .mirror_add = ksz9477_port_mirror_add, 276 .mirror_del = ksz9477_port_mirror_del, 277 .get_caps = lan937x_phylink_get_caps, 278 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 279 .fdb_dump = ksz9477_fdb_dump, 280 .fdb_add = ksz9477_fdb_add, 281 .fdb_del = ksz9477_fdb_del, 282 .mdb_add = ksz9477_mdb_add, 283 .mdb_del = ksz9477_mdb_del, 284 .change_mtu = lan937x_change_mtu, 285 .phylink_mac_link_up = ksz9477_phylink_mac_link_up, 286 .config_cpu_port = lan937x_config_cpu_port, 287 .enable_stp_addr = ksz9477_enable_stp_addr, 288 .reset = lan937x_reset_switch, 289 .init = lan937x_switch_init, 290 .exit = lan937x_switch_exit, 291 }; 292 293 static const u16 ksz8795_regs[] = { 294 [REG_IND_CTRL_0] = 0x6E, 295 [REG_IND_DATA_8] = 0x70, 296 [REG_IND_DATA_CHECK] = 0x72, 297 [REG_IND_DATA_HI] = 0x71, 298 [REG_IND_DATA_LO] = 0x75, 299 [REG_IND_MIB_CHECK] = 0x74, 300 [REG_IND_BYTE] = 0xA0, 301 [P_FORCE_CTRL] = 0x0C, 302 [P_LINK_STATUS] = 0x0E, 303 [P_LOCAL_CTRL] = 0x07, 304 [P_NEG_RESTART_CTRL] = 0x0D, 305 [P_REMOTE_STATUS] = 0x08, 306 [P_SPEED_STATUS] = 0x09, 307 [S_TAIL_TAG_CTRL] = 0x0C, 308 [P_STP_CTRL] = 0x02, 309 [S_START_CTRL] = 0x01, 310 [S_BROADCAST_CTRL] = 0x06, 311 [S_MULTICAST_CTRL] = 0x04, 312 [P_XMII_CTRL_0] = 0x06, 313 [P_XMII_CTRL_1] = 0x56, 314 }; 315 316 static const u32 ksz8795_masks[] = { 317 [PORT_802_1P_REMAPPING] = BIT(7), 318 [SW_TAIL_TAG_ENABLE] = BIT(1), 319 [MIB_COUNTER_OVERFLOW] = BIT(6), 320 [MIB_COUNTER_VALID] = BIT(5), 321 [VLAN_TABLE_FID] = GENMASK(6, 0), 322 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 323 [VLAN_TABLE_VALID] = BIT(12), 324 [STATIC_MAC_TABLE_VALID] = BIT(21), 325 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 326 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 327 [STATIC_MAC_TABLE_OVERRIDE] = BIT(26), 328 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(24, 20), 329 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 330 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(8), 331 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 332 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 333 [DYNAMIC_MAC_TABLE_FID] = GENMASK(26, 20), 334 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 335 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 336 [P_MII_TX_FLOW_CTRL] = BIT(5), 337 [P_MII_RX_FLOW_CTRL] = BIT(5), 338 }; 339 340 static const u8 ksz8795_xmii_ctrl0[] = { 341 [P_MII_100MBIT] = 0, 342 [P_MII_10MBIT] = 1, 343 [P_MII_FULL_DUPLEX] = 0, 344 [P_MII_HALF_DUPLEX] = 1, 345 }; 346 347 static const u8 ksz8795_xmii_ctrl1[] = { 348 [P_RGMII_SEL] = 3, 349 [P_GMII_SEL] = 2, 350 [P_RMII_SEL] = 1, 351 [P_MII_SEL] = 0, 352 [P_GMII_1GBIT] = 1, 353 [P_GMII_NOT_1GBIT] = 0, 354 }; 355 356 static const u8 ksz8795_shifts[] = { 357 [VLAN_TABLE_MEMBERSHIP_S] = 7, 358 [VLAN_TABLE] = 16, 359 [STATIC_MAC_FWD_PORTS] = 16, 360 [STATIC_MAC_FID] = 24, 361 [DYNAMIC_MAC_ENTRIES_H] = 3, 362 [DYNAMIC_MAC_ENTRIES] = 29, 363 [DYNAMIC_MAC_FID] = 16, 364 [DYNAMIC_MAC_TIMESTAMP] = 27, 365 [DYNAMIC_MAC_SRC_PORT] = 24, 366 }; 367 368 static const u16 ksz8863_regs[] = { 369 [REG_IND_CTRL_0] = 0x79, 370 [REG_IND_DATA_8] = 0x7B, 371 [REG_IND_DATA_CHECK] = 0x7B, 372 [REG_IND_DATA_HI] = 0x7C, 373 [REG_IND_DATA_LO] = 0x80, 374 [REG_IND_MIB_CHECK] = 0x80, 375 [P_FORCE_CTRL] = 0x0C, 376 [P_LINK_STATUS] = 0x0E, 377 [P_LOCAL_CTRL] = 0x0C, 378 [P_NEG_RESTART_CTRL] = 0x0D, 379 [P_REMOTE_STATUS] = 0x0E, 380 [P_SPEED_STATUS] = 0x0F, 381 [S_TAIL_TAG_CTRL] = 0x03, 382 [P_STP_CTRL] = 0x02, 383 [S_START_CTRL] = 0x01, 384 [S_BROADCAST_CTRL] = 0x06, 385 [S_MULTICAST_CTRL] = 0x04, 386 }; 387 388 static const u32 ksz8863_masks[] = { 389 [PORT_802_1P_REMAPPING] = BIT(3), 390 [SW_TAIL_TAG_ENABLE] = BIT(6), 391 [MIB_COUNTER_OVERFLOW] = BIT(7), 392 [MIB_COUNTER_VALID] = BIT(6), 393 [VLAN_TABLE_FID] = GENMASK(15, 12), 394 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 395 [VLAN_TABLE_VALID] = BIT(19), 396 [STATIC_MAC_TABLE_VALID] = BIT(19), 397 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 398 [STATIC_MAC_TABLE_FID] = GENMASK(29, 26), 399 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 400 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 401 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(5, 0), 402 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 403 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 404 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 28), 405 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 406 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 407 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 408 }; 409 410 static u8 ksz8863_shifts[] = { 411 [VLAN_TABLE_MEMBERSHIP_S] = 16, 412 [STATIC_MAC_FWD_PORTS] = 16, 413 [STATIC_MAC_FID] = 22, 414 [DYNAMIC_MAC_ENTRIES_H] = 3, 415 [DYNAMIC_MAC_ENTRIES] = 24, 416 [DYNAMIC_MAC_FID] = 16, 417 [DYNAMIC_MAC_TIMESTAMP] = 24, 418 [DYNAMIC_MAC_SRC_PORT] = 20, 419 }; 420 421 static const u16 ksz9477_regs[] = { 422 [P_STP_CTRL] = 0x0B04, 423 [S_START_CTRL] = 0x0300, 424 [S_BROADCAST_CTRL] = 0x0332, 425 [S_MULTICAST_CTRL] = 0x0331, 426 [P_XMII_CTRL_0] = 0x0300, 427 [P_XMII_CTRL_1] = 0x0301, 428 }; 429 430 static const u32 ksz9477_masks[] = { 431 [ALU_STAT_WRITE] = 0, 432 [ALU_STAT_READ] = 1, 433 [P_MII_TX_FLOW_CTRL] = BIT(5), 434 [P_MII_RX_FLOW_CTRL] = BIT(3), 435 }; 436 437 static const u8 ksz9477_shifts[] = { 438 [ALU_STAT_INDEX] = 16, 439 }; 440 441 static const u8 ksz9477_xmii_ctrl0[] = { 442 [P_MII_100MBIT] = 1, 443 [P_MII_10MBIT] = 0, 444 [P_MII_FULL_DUPLEX] = 1, 445 [P_MII_HALF_DUPLEX] = 0, 446 }; 447 448 static const u8 ksz9477_xmii_ctrl1[] = { 449 [P_RGMII_SEL] = 0, 450 [P_RMII_SEL] = 1, 451 [P_GMII_SEL] = 2, 452 [P_MII_SEL] = 3, 453 [P_GMII_1GBIT] = 0, 454 [P_GMII_NOT_1GBIT] = 1, 455 }; 456 457 static const u32 lan937x_masks[] = { 458 [ALU_STAT_WRITE] = 1, 459 [ALU_STAT_READ] = 2, 460 [P_MII_TX_FLOW_CTRL] = BIT(5), 461 [P_MII_RX_FLOW_CTRL] = BIT(3), 462 }; 463 464 static const u8 lan937x_shifts[] = { 465 [ALU_STAT_INDEX] = 8, 466 }; 467 468 static const struct regmap_range ksz8563_valid_regs[] = { 469 regmap_reg_range(0x0000, 0x0003), 470 regmap_reg_range(0x0006, 0x0006), 471 regmap_reg_range(0x000f, 0x001f), 472 regmap_reg_range(0x0100, 0x0100), 473 regmap_reg_range(0x0104, 0x0107), 474 regmap_reg_range(0x010d, 0x010d), 475 regmap_reg_range(0x0110, 0x0113), 476 regmap_reg_range(0x0120, 0x012b), 477 regmap_reg_range(0x0201, 0x0201), 478 regmap_reg_range(0x0210, 0x0213), 479 regmap_reg_range(0x0300, 0x0300), 480 regmap_reg_range(0x0302, 0x031b), 481 regmap_reg_range(0x0320, 0x032b), 482 regmap_reg_range(0x0330, 0x0336), 483 regmap_reg_range(0x0338, 0x033e), 484 regmap_reg_range(0x0340, 0x035f), 485 regmap_reg_range(0x0370, 0x0370), 486 regmap_reg_range(0x0378, 0x0378), 487 regmap_reg_range(0x037c, 0x037d), 488 regmap_reg_range(0x0390, 0x0393), 489 regmap_reg_range(0x0400, 0x040e), 490 regmap_reg_range(0x0410, 0x042f), 491 regmap_reg_range(0x0500, 0x0519), 492 regmap_reg_range(0x0520, 0x054b), 493 regmap_reg_range(0x0550, 0x05b3), 494 495 /* port 1 */ 496 regmap_reg_range(0x1000, 0x1001), 497 regmap_reg_range(0x1004, 0x100b), 498 regmap_reg_range(0x1013, 0x1013), 499 regmap_reg_range(0x1017, 0x1017), 500 regmap_reg_range(0x101b, 0x101b), 501 regmap_reg_range(0x101f, 0x1021), 502 regmap_reg_range(0x1030, 0x1030), 503 regmap_reg_range(0x1100, 0x1111), 504 regmap_reg_range(0x111a, 0x111d), 505 regmap_reg_range(0x1122, 0x1127), 506 regmap_reg_range(0x112a, 0x112b), 507 regmap_reg_range(0x1136, 0x1139), 508 regmap_reg_range(0x113e, 0x113f), 509 regmap_reg_range(0x1400, 0x1401), 510 regmap_reg_range(0x1403, 0x1403), 511 regmap_reg_range(0x1410, 0x1417), 512 regmap_reg_range(0x1420, 0x1423), 513 regmap_reg_range(0x1500, 0x1507), 514 regmap_reg_range(0x1600, 0x1612), 515 regmap_reg_range(0x1800, 0x180f), 516 regmap_reg_range(0x1900, 0x1907), 517 regmap_reg_range(0x1914, 0x191b), 518 regmap_reg_range(0x1a00, 0x1a03), 519 regmap_reg_range(0x1a04, 0x1a08), 520 regmap_reg_range(0x1b00, 0x1b01), 521 regmap_reg_range(0x1b04, 0x1b04), 522 regmap_reg_range(0x1c00, 0x1c05), 523 regmap_reg_range(0x1c08, 0x1c1b), 524 525 /* port 2 */ 526 regmap_reg_range(0x2000, 0x2001), 527 regmap_reg_range(0x2004, 0x200b), 528 regmap_reg_range(0x2013, 0x2013), 529 regmap_reg_range(0x2017, 0x2017), 530 regmap_reg_range(0x201b, 0x201b), 531 regmap_reg_range(0x201f, 0x2021), 532 regmap_reg_range(0x2030, 0x2030), 533 regmap_reg_range(0x2100, 0x2111), 534 regmap_reg_range(0x211a, 0x211d), 535 regmap_reg_range(0x2122, 0x2127), 536 regmap_reg_range(0x212a, 0x212b), 537 regmap_reg_range(0x2136, 0x2139), 538 regmap_reg_range(0x213e, 0x213f), 539 regmap_reg_range(0x2400, 0x2401), 540 regmap_reg_range(0x2403, 0x2403), 541 regmap_reg_range(0x2410, 0x2417), 542 regmap_reg_range(0x2420, 0x2423), 543 regmap_reg_range(0x2500, 0x2507), 544 regmap_reg_range(0x2600, 0x2612), 545 regmap_reg_range(0x2800, 0x280f), 546 regmap_reg_range(0x2900, 0x2907), 547 regmap_reg_range(0x2914, 0x291b), 548 regmap_reg_range(0x2a00, 0x2a03), 549 regmap_reg_range(0x2a04, 0x2a08), 550 regmap_reg_range(0x2b00, 0x2b01), 551 regmap_reg_range(0x2b04, 0x2b04), 552 regmap_reg_range(0x2c00, 0x2c05), 553 regmap_reg_range(0x2c08, 0x2c1b), 554 555 /* port 3 */ 556 regmap_reg_range(0x3000, 0x3001), 557 regmap_reg_range(0x3004, 0x300b), 558 regmap_reg_range(0x3013, 0x3013), 559 regmap_reg_range(0x3017, 0x3017), 560 regmap_reg_range(0x301b, 0x301b), 561 regmap_reg_range(0x301f, 0x3021), 562 regmap_reg_range(0x3030, 0x3030), 563 regmap_reg_range(0x3300, 0x3301), 564 regmap_reg_range(0x3303, 0x3303), 565 regmap_reg_range(0x3400, 0x3401), 566 regmap_reg_range(0x3403, 0x3403), 567 regmap_reg_range(0x3410, 0x3417), 568 regmap_reg_range(0x3420, 0x3423), 569 regmap_reg_range(0x3500, 0x3507), 570 regmap_reg_range(0x3600, 0x3612), 571 regmap_reg_range(0x3800, 0x380f), 572 regmap_reg_range(0x3900, 0x3907), 573 regmap_reg_range(0x3914, 0x391b), 574 regmap_reg_range(0x3a00, 0x3a03), 575 regmap_reg_range(0x3a04, 0x3a08), 576 regmap_reg_range(0x3b00, 0x3b01), 577 regmap_reg_range(0x3b04, 0x3b04), 578 regmap_reg_range(0x3c00, 0x3c05), 579 regmap_reg_range(0x3c08, 0x3c1b), 580 }; 581 582 static const struct regmap_access_table ksz8563_register_set = { 583 .yes_ranges = ksz8563_valid_regs, 584 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), 585 }; 586 587 static const struct regmap_range ksz9477_valid_regs[] = { 588 regmap_reg_range(0x0000, 0x0003), 589 regmap_reg_range(0x0006, 0x0006), 590 regmap_reg_range(0x0010, 0x001f), 591 regmap_reg_range(0x0100, 0x0100), 592 regmap_reg_range(0x0103, 0x0107), 593 regmap_reg_range(0x010d, 0x010d), 594 regmap_reg_range(0x0110, 0x0113), 595 regmap_reg_range(0x0120, 0x012b), 596 regmap_reg_range(0x0201, 0x0201), 597 regmap_reg_range(0x0210, 0x0213), 598 regmap_reg_range(0x0300, 0x0300), 599 regmap_reg_range(0x0302, 0x031b), 600 regmap_reg_range(0x0320, 0x032b), 601 regmap_reg_range(0x0330, 0x0336), 602 regmap_reg_range(0x0338, 0x033b), 603 regmap_reg_range(0x033e, 0x033e), 604 regmap_reg_range(0x0340, 0x035f), 605 regmap_reg_range(0x0370, 0x0370), 606 regmap_reg_range(0x0378, 0x0378), 607 regmap_reg_range(0x037c, 0x037d), 608 regmap_reg_range(0x0390, 0x0393), 609 regmap_reg_range(0x0400, 0x040e), 610 regmap_reg_range(0x0410, 0x042f), 611 regmap_reg_range(0x0444, 0x044b), 612 regmap_reg_range(0x0450, 0x046f), 613 regmap_reg_range(0x0500, 0x0519), 614 regmap_reg_range(0x0520, 0x054b), 615 regmap_reg_range(0x0550, 0x05b3), 616 regmap_reg_range(0x0604, 0x060b), 617 regmap_reg_range(0x0610, 0x0612), 618 regmap_reg_range(0x0614, 0x062c), 619 regmap_reg_range(0x0640, 0x0645), 620 regmap_reg_range(0x0648, 0x064d), 621 622 /* port 1 */ 623 regmap_reg_range(0x1000, 0x1001), 624 regmap_reg_range(0x1013, 0x1013), 625 regmap_reg_range(0x1017, 0x1017), 626 regmap_reg_range(0x101b, 0x101b), 627 regmap_reg_range(0x101f, 0x1020), 628 regmap_reg_range(0x1030, 0x1030), 629 regmap_reg_range(0x1100, 0x1115), 630 regmap_reg_range(0x111a, 0x111f), 631 regmap_reg_range(0x1122, 0x1127), 632 regmap_reg_range(0x112a, 0x112b), 633 regmap_reg_range(0x1136, 0x1139), 634 regmap_reg_range(0x113e, 0x113f), 635 regmap_reg_range(0x1400, 0x1401), 636 regmap_reg_range(0x1403, 0x1403), 637 regmap_reg_range(0x1410, 0x1417), 638 regmap_reg_range(0x1420, 0x1423), 639 regmap_reg_range(0x1500, 0x1507), 640 regmap_reg_range(0x1600, 0x1613), 641 regmap_reg_range(0x1800, 0x180f), 642 regmap_reg_range(0x1820, 0x1827), 643 regmap_reg_range(0x1830, 0x1837), 644 regmap_reg_range(0x1840, 0x184b), 645 regmap_reg_range(0x1900, 0x1907), 646 regmap_reg_range(0x1914, 0x191b), 647 regmap_reg_range(0x1920, 0x1920), 648 regmap_reg_range(0x1923, 0x1927), 649 regmap_reg_range(0x1a00, 0x1a03), 650 regmap_reg_range(0x1a04, 0x1a07), 651 regmap_reg_range(0x1b00, 0x1b01), 652 regmap_reg_range(0x1b04, 0x1b04), 653 regmap_reg_range(0x1c00, 0x1c05), 654 regmap_reg_range(0x1c08, 0x1c1b), 655 656 /* port 2 */ 657 regmap_reg_range(0x2000, 0x2001), 658 regmap_reg_range(0x2013, 0x2013), 659 regmap_reg_range(0x2017, 0x2017), 660 regmap_reg_range(0x201b, 0x201b), 661 regmap_reg_range(0x201f, 0x2020), 662 regmap_reg_range(0x2030, 0x2030), 663 regmap_reg_range(0x2100, 0x2115), 664 regmap_reg_range(0x211a, 0x211f), 665 regmap_reg_range(0x2122, 0x2127), 666 regmap_reg_range(0x212a, 0x212b), 667 regmap_reg_range(0x2136, 0x2139), 668 regmap_reg_range(0x213e, 0x213f), 669 regmap_reg_range(0x2400, 0x2401), 670 regmap_reg_range(0x2403, 0x2403), 671 regmap_reg_range(0x2410, 0x2417), 672 regmap_reg_range(0x2420, 0x2423), 673 regmap_reg_range(0x2500, 0x2507), 674 regmap_reg_range(0x2600, 0x2613), 675 regmap_reg_range(0x2800, 0x280f), 676 regmap_reg_range(0x2820, 0x2827), 677 regmap_reg_range(0x2830, 0x2837), 678 regmap_reg_range(0x2840, 0x284b), 679 regmap_reg_range(0x2900, 0x2907), 680 regmap_reg_range(0x2914, 0x291b), 681 regmap_reg_range(0x2920, 0x2920), 682 regmap_reg_range(0x2923, 0x2927), 683 regmap_reg_range(0x2a00, 0x2a03), 684 regmap_reg_range(0x2a04, 0x2a07), 685 regmap_reg_range(0x2b00, 0x2b01), 686 regmap_reg_range(0x2b04, 0x2b04), 687 regmap_reg_range(0x2c00, 0x2c05), 688 regmap_reg_range(0x2c08, 0x2c1b), 689 690 /* port 3 */ 691 regmap_reg_range(0x3000, 0x3001), 692 regmap_reg_range(0x3013, 0x3013), 693 regmap_reg_range(0x3017, 0x3017), 694 regmap_reg_range(0x301b, 0x301b), 695 regmap_reg_range(0x301f, 0x3020), 696 regmap_reg_range(0x3030, 0x3030), 697 regmap_reg_range(0x3100, 0x3115), 698 regmap_reg_range(0x311a, 0x311f), 699 regmap_reg_range(0x3122, 0x3127), 700 regmap_reg_range(0x312a, 0x312b), 701 regmap_reg_range(0x3136, 0x3139), 702 regmap_reg_range(0x313e, 0x313f), 703 regmap_reg_range(0x3400, 0x3401), 704 regmap_reg_range(0x3403, 0x3403), 705 regmap_reg_range(0x3410, 0x3417), 706 regmap_reg_range(0x3420, 0x3423), 707 regmap_reg_range(0x3500, 0x3507), 708 regmap_reg_range(0x3600, 0x3613), 709 regmap_reg_range(0x3800, 0x380f), 710 regmap_reg_range(0x3820, 0x3827), 711 regmap_reg_range(0x3830, 0x3837), 712 regmap_reg_range(0x3840, 0x384b), 713 regmap_reg_range(0x3900, 0x3907), 714 regmap_reg_range(0x3914, 0x391b), 715 regmap_reg_range(0x3920, 0x3920), 716 regmap_reg_range(0x3923, 0x3927), 717 regmap_reg_range(0x3a00, 0x3a03), 718 regmap_reg_range(0x3a04, 0x3a07), 719 regmap_reg_range(0x3b00, 0x3b01), 720 regmap_reg_range(0x3b04, 0x3b04), 721 regmap_reg_range(0x3c00, 0x3c05), 722 regmap_reg_range(0x3c08, 0x3c1b), 723 724 /* port 4 */ 725 regmap_reg_range(0x4000, 0x4001), 726 regmap_reg_range(0x4013, 0x4013), 727 regmap_reg_range(0x4017, 0x4017), 728 regmap_reg_range(0x401b, 0x401b), 729 regmap_reg_range(0x401f, 0x4020), 730 regmap_reg_range(0x4030, 0x4030), 731 regmap_reg_range(0x4100, 0x4115), 732 regmap_reg_range(0x411a, 0x411f), 733 regmap_reg_range(0x4122, 0x4127), 734 regmap_reg_range(0x412a, 0x412b), 735 regmap_reg_range(0x4136, 0x4139), 736 regmap_reg_range(0x413e, 0x413f), 737 regmap_reg_range(0x4400, 0x4401), 738 regmap_reg_range(0x4403, 0x4403), 739 regmap_reg_range(0x4410, 0x4417), 740 regmap_reg_range(0x4420, 0x4423), 741 regmap_reg_range(0x4500, 0x4507), 742 regmap_reg_range(0x4600, 0x4613), 743 regmap_reg_range(0x4800, 0x480f), 744 regmap_reg_range(0x4820, 0x4827), 745 regmap_reg_range(0x4830, 0x4837), 746 regmap_reg_range(0x4840, 0x484b), 747 regmap_reg_range(0x4900, 0x4907), 748 regmap_reg_range(0x4914, 0x491b), 749 regmap_reg_range(0x4920, 0x4920), 750 regmap_reg_range(0x4923, 0x4927), 751 regmap_reg_range(0x4a00, 0x4a03), 752 regmap_reg_range(0x4a04, 0x4a07), 753 regmap_reg_range(0x4b00, 0x4b01), 754 regmap_reg_range(0x4b04, 0x4b04), 755 regmap_reg_range(0x4c00, 0x4c05), 756 regmap_reg_range(0x4c08, 0x4c1b), 757 758 /* port 5 */ 759 regmap_reg_range(0x5000, 0x5001), 760 regmap_reg_range(0x5013, 0x5013), 761 regmap_reg_range(0x5017, 0x5017), 762 regmap_reg_range(0x501b, 0x501b), 763 regmap_reg_range(0x501f, 0x5020), 764 regmap_reg_range(0x5030, 0x5030), 765 regmap_reg_range(0x5100, 0x5115), 766 regmap_reg_range(0x511a, 0x511f), 767 regmap_reg_range(0x5122, 0x5127), 768 regmap_reg_range(0x512a, 0x512b), 769 regmap_reg_range(0x5136, 0x5139), 770 regmap_reg_range(0x513e, 0x513f), 771 regmap_reg_range(0x5400, 0x5401), 772 regmap_reg_range(0x5403, 0x5403), 773 regmap_reg_range(0x5410, 0x5417), 774 regmap_reg_range(0x5420, 0x5423), 775 regmap_reg_range(0x5500, 0x5507), 776 regmap_reg_range(0x5600, 0x5613), 777 regmap_reg_range(0x5800, 0x580f), 778 regmap_reg_range(0x5820, 0x5827), 779 regmap_reg_range(0x5830, 0x5837), 780 regmap_reg_range(0x5840, 0x584b), 781 regmap_reg_range(0x5900, 0x5907), 782 regmap_reg_range(0x5914, 0x591b), 783 regmap_reg_range(0x5920, 0x5920), 784 regmap_reg_range(0x5923, 0x5927), 785 regmap_reg_range(0x5a00, 0x5a03), 786 regmap_reg_range(0x5a04, 0x5a07), 787 regmap_reg_range(0x5b00, 0x5b01), 788 regmap_reg_range(0x5b04, 0x5b04), 789 regmap_reg_range(0x5c00, 0x5c05), 790 regmap_reg_range(0x5c08, 0x5c1b), 791 792 /* port 6 */ 793 regmap_reg_range(0x6000, 0x6001), 794 regmap_reg_range(0x6013, 0x6013), 795 regmap_reg_range(0x6017, 0x6017), 796 regmap_reg_range(0x601b, 0x601b), 797 regmap_reg_range(0x601f, 0x6020), 798 regmap_reg_range(0x6030, 0x6030), 799 regmap_reg_range(0x6300, 0x6301), 800 regmap_reg_range(0x6400, 0x6401), 801 regmap_reg_range(0x6403, 0x6403), 802 regmap_reg_range(0x6410, 0x6417), 803 regmap_reg_range(0x6420, 0x6423), 804 regmap_reg_range(0x6500, 0x6507), 805 regmap_reg_range(0x6600, 0x6613), 806 regmap_reg_range(0x6800, 0x680f), 807 regmap_reg_range(0x6820, 0x6827), 808 regmap_reg_range(0x6830, 0x6837), 809 regmap_reg_range(0x6840, 0x684b), 810 regmap_reg_range(0x6900, 0x6907), 811 regmap_reg_range(0x6914, 0x691b), 812 regmap_reg_range(0x6920, 0x6920), 813 regmap_reg_range(0x6923, 0x6927), 814 regmap_reg_range(0x6a00, 0x6a03), 815 regmap_reg_range(0x6a04, 0x6a07), 816 regmap_reg_range(0x6b00, 0x6b01), 817 regmap_reg_range(0x6b04, 0x6b04), 818 regmap_reg_range(0x6c00, 0x6c05), 819 regmap_reg_range(0x6c08, 0x6c1b), 820 821 /* port 7 */ 822 regmap_reg_range(0x7000, 0x7001), 823 regmap_reg_range(0x7013, 0x7013), 824 regmap_reg_range(0x7017, 0x7017), 825 regmap_reg_range(0x701b, 0x701b), 826 regmap_reg_range(0x701f, 0x7020), 827 regmap_reg_range(0x7030, 0x7030), 828 regmap_reg_range(0x7200, 0x7203), 829 regmap_reg_range(0x7206, 0x7207), 830 regmap_reg_range(0x7300, 0x7301), 831 regmap_reg_range(0x7400, 0x7401), 832 regmap_reg_range(0x7403, 0x7403), 833 regmap_reg_range(0x7410, 0x7417), 834 regmap_reg_range(0x7420, 0x7423), 835 regmap_reg_range(0x7500, 0x7507), 836 regmap_reg_range(0x7600, 0x7613), 837 regmap_reg_range(0x7800, 0x780f), 838 regmap_reg_range(0x7820, 0x7827), 839 regmap_reg_range(0x7830, 0x7837), 840 regmap_reg_range(0x7840, 0x784b), 841 regmap_reg_range(0x7900, 0x7907), 842 regmap_reg_range(0x7914, 0x791b), 843 regmap_reg_range(0x7920, 0x7920), 844 regmap_reg_range(0x7923, 0x7927), 845 regmap_reg_range(0x7a00, 0x7a03), 846 regmap_reg_range(0x7a04, 0x7a07), 847 regmap_reg_range(0x7b00, 0x7b01), 848 regmap_reg_range(0x7b04, 0x7b04), 849 regmap_reg_range(0x7c00, 0x7c05), 850 regmap_reg_range(0x7c08, 0x7c1b), 851 }; 852 853 static const struct regmap_access_table ksz9477_register_set = { 854 .yes_ranges = ksz9477_valid_regs, 855 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), 856 }; 857 858 static const struct regmap_range ksz9896_valid_regs[] = { 859 regmap_reg_range(0x0000, 0x0003), 860 regmap_reg_range(0x0006, 0x0006), 861 regmap_reg_range(0x0010, 0x001f), 862 regmap_reg_range(0x0100, 0x0100), 863 regmap_reg_range(0x0103, 0x0107), 864 regmap_reg_range(0x010d, 0x010d), 865 regmap_reg_range(0x0110, 0x0113), 866 regmap_reg_range(0x0120, 0x0127), 867 regmap_reg_range(0x0201, 0x0201), 868 regmap_reg_range(0x0210, 0x0213), 869 regmap_reg_range(0x0300, 0x0300), 870 regmap_reg_range(0x0302, 0x030b), 871 regmap_reg_range(0x0310, 0x031b), 872 regmap_reg_range(0x0320, 0x032b), 873 regmap_reg_range(0x0330, 0x0336), 874 regmap_reg_range(0x0338, 0x033b), 875 regmap_reg_range(0x033e, 0x033e), 876 regmap_reg_range(0x0340, 0x035f), 877 regmap_reg_range(0x0370, 0x0370), 878 regmap_reg_range(0x0378, 0x0378), 879 regmap_reg_range(0x037c, 0x037d), 880 regmap_reg_range(0x0390, 0x0393), 881 regmap_reg_range(0x0400, 0x040e), 882 regmap_reg_range(0x0410, 0x042f), 883 884 /* port 1 */ 885 regmap_reg_range(0x1000, 0x1001), 886 regmap_reg_range(0x1013, 0x1013), 887 regmap_reg_range(0x1017, 0x1017), 888 regmap_reg_range(0x101b, 0x101b), 889 regmap_reg_range(0x101f, 0x1020), 890 regmap_reg_range(0x1030, 0x1030), 891 regmap_reg_range(0x1100, 0x1115), 892 regmap_reg_range(0x111a, 0x111f), 893 regmap_reg_range(0x1122, 0x1127), 894 regmap_reg_range(0x112a, 0x112b), 895 regmap_reg_range(0x1136, 0x1139), 896 regmap_reg_range(0x113e, 0x113f), 897 regmap_reg_range(0x1400, 0x1401), 898 regmap_reg_range(0x1403, 0x1403), 899 regmap_reg_range(0x1410, 0x1417), 900 regmap_reg_range(0x1420, 0x1423), 901 regmap_reg_range(0x1500, 0x1507), 902 regmap_reg_range(0x1600, 0x1612), 903 regmap_reg_range(0x1800, 0x180f), 904 regmap_reg_range(0x1820, 0x1827), 905 regmap_reg_range(0x1830, 0x1837), 906 regmap_reg_range(0x1840, 0x184b), 907 regmap_reg_range(0x1900, 0x1907), 908 regmap_reg_range(0x1914, 0x1915), 909 regmap_reg_range(0x1a00, 0x1a03), 910 regmap_reg_range(0x1a04, 0x1a07), 911 regmap_reg_range(0x1b00, 0x1b01), 912 regmap_reg_range(0x1b04, 0x1b04), 913 914 /* port 2 */ 915 regmap_reg_range(0x2000, 0x2001), 916 regmap_reg_range(0x2013, 0x2013), 917 regmap_reg_range(0x2017, 0x2017), 918 regmap_reg_range(0x201b, 0x201b), 919 regmap_reg_range(0x201f, 0x2020), 920 regmap_reg_range(0x2030, 0x2030), 921 regmap_reg_range(0x2100, 0x2115), 922 regmap_reg_range(0x211a, 0x211f), 923 regmap_reg_range(0x2122, 0x2127), 924 regmap_reg_range(0x212a, 0x212b), 925 regmap_reg_range(0x2136, 0x2139), 926 regmap_reg_range(0x213e, 0x213f), 927 regmap_reg_range(0x2400, 0x2401), 928 regmap_reg_range(0x2403, 0x2403), 929 regmap_reg_range(0x2410, 0x2417), 930 regmap_reg_range(0x2420, 0x2423), 931 regmap_reg_range(0x2500, 0x2507), 932 regmap_reg_range(0x2600, 0x2612), 933 regmap_reg_range(0x2800, 0x280f), 934 regmap_reg_range(0x2820, 0x2827), 935 regmap_reg_range(0x2830, 0x2837), 936 regmap_reg_range(0x2840, 0x284b), 937 regmap_reg_range(0x2900, 0x2907), 938 regmap_reg_range(0x2914, 0x2915), 939 regmap_reg_range(0x2a00, 0x2a03), 940 regmap_reg_range(0x2a04, 0x2a07), 941 regmap_reg_range(0x2b00, 0x2b01), 942 regmap_reg_range(0x2b04, 0x2b04), 943 944 /* port 3 */ 945 regmap_reg_range(0x3000, 0x3001), 946 regmap_reg_range(0x3013, 0x3013), 947 regmap_reg_range(0x3017, 0x3017), 948 regmap_reg_range(0x301b, 0x301b), 949 regmap_reg_range(0x301f, 0x3020), 950 regmap_reg_range(0x3030, 0x3030), 951 regmap_reg_range(0x3100, 0x3115), 952 regmap_reg_range(0x311a, 0x311f), 953 regmap_reg_range(0x3122, 0x3127), 954 regmap_reg_range(0x312a, 0x312b), 955 regmap_reg_range(0x3136, 0x3139), 956 regmap_reg_range(0x313e, 0x313f), 957 regmap_reg_range(0x3400, 0x3401), 958 regmap_reg_range(0x3403, 0x3403), 959 regmap_reg_range(0x3410, 0x3417), 960 regmap_reg_range(0x3420, 0x3423), 961 regmap_reg_range(0x3500, 0x3507), 962 regmap_reg_range(0x3600, 0x3612), 963 regmap_reg_range(0x3800, 0x380f), 964 regmap_reg_range(0x3820, 0x3827), 965 regmap_reg_range(0x3830, 0x3837), 966 regmap_reg_range(0x3840, 0x384b), 967 regmap_reg_range(0x3900, 0x3907), 968 regmap_reg_range(0x3914, 0x3915), 969 regmap_reg_range(0x3a00, 0x3a03), 970 regmap_reg_range(0x3a04, 0x3a07), 971 regmap_reg_range(0x3b00, 0x3b01), 972 regmap_reg_range(0x3b04, 0x3b04), 973 974 /* port 4 */ 975 regmap_reg_range(0x4000, 0x4001), 976 regmap_reg_range(0x4013, 0x4013), 977 regmap_reg_range(0x4017, 0x4017), 978 regmap_reg_range(0x401b, 0x401b), 979 regmap_reg_range(0x401f, 0x4020), 980 regmap_reg_range(0x4030, 0x4030), 981 regmap_reg_range(0x4100, 0x4115), 982 regmap_reg_range(0x411a, 0x411f), 983 regmap_reg_range(0x4122, 0x4127), 984 regmap_reg_range(0x412a, 0x412b), 985 regmap_reg_range(0x4136, 0x4139), 986 regmap_reg_range(0x413e, 0x413f), 987 regmap_reg_range(0x4400, 0x4401), 988 regmap_reg_range(0x4403, 0x4403), 989 regmap_reg_range(0x4410, 0x4417), 990 regmap_reg_range(0x4420, 0x4423), 991 regmap_reg_range(0x4500, 0x4507), 992 regmap_reg_range(0x4600, 0x4612), 993 regmap_reg_range(0x4800, 0x480f), 994 regmap_reg_range(0x4820, 0x4827), 995 regmap_reg_range(0x4830, 0x4837), 996 regmap_reg_range(0x4840, 0x484b), 997 regmap_reg_range(0x4900, 0x4907), 998 regmap_reg_range(0x4914, 0x4915), 999 regmap_reg_range(0x4a00, 0x4a03), 1000 regmap_reg_range(0x4a04, 0x4a07), 1001 regmap_reg_range(0x4b00, 0x4b01), 1002 regmap_reg_range(0x4b04, 0x4b04), 1003 1004 /* port 5 */ 1005 regmap_reg_range(0x5000, 0x5001), 1006 regmap_reg_range(0x5013, 0x5013), 1007 regmap_reg_range(0x5017, 0x5017), 1008 regmap_reg_range(0x501b, 0x501b), 1009 regmap_reg_range(0x501f, 0x5020), 1010 regmap_reg_range(0x5030, 0x5030), 1011 regmap_reg_range(0x5100, 0x5115), 1012 regmap_reg_range(0x511a, 0x511f), 1013 regmap_reg_range(0x5122, 0x5127), 1014 regmap_reg_range(0x512a, 0x512b), 1015 regmap_reg_range(0x5136, 0x5139), 1016 regmap_reg_range(0x513e, 0x513f), 1017 regmap_reg_range(0x5400, 0x5401), 1018 regmap_reg_range(0x5403, 0x5403), 1019 regmap_reg_range(0x5410, 0x5417), 1020 regmap_reg_range(0x5420, 0x5423), 1021 regmap_reg_range(0x5500, 0x5507), 1022 regmap_reg_range(0x5600, 0x5612), 1023 regmap_reg_range(0x5800, 0x580f), 1024 regmap_reg_range(0x5820, 0x5827), 1025 regmap_reg_range(0x5830, 0x5837), 1026 regmap_reg_range(0x5840, 0x584b), 1027 regmap_reg_range(0x5900, 0x5907), 1028 regmap_reg_range(0x5914, 0x5915), 1029 regmap_reg_range(0x5a00, 0x5a03), 1030 regmap_reg_range(0x5a04, 0x5a07), 1031 regmap_reg_range(0x5b00, 0x5b01), 1032 regmap_reg_range(0x5b04, 0x5b04), 1033 1034 /* port 6 */ 1035 regmap_reg_range(0x6000, 0x6001), 1036 regmap_reg_range(0x6013, 0x6013), 1037 regmap_reg_range(0x6017, 0x6017), 1038 regmap_reg_range(0x601b, 0x601b), 1039 regmap_reg_range(0x601f, 0x6020), 1040 regmap_reg_range(0x6030, 0x6030), 1041 regmap_reg_range(0x6100, 0x6115), 1042 regmap_reg_range(0x611a, 0x611f), 1043 regmap_reg_range(0x6122, 0x6127), 1044 regmap_reg_range(0x612a, 0x612b), 1045 regmap_reg_range(0x6136, 0x6139), 1046 regmap_reg_range(0x613e, 0x613f), 1047 regmap_reg_range(0x6300, 0x6301), 1048 regmap_reg_range(0x6400, 0x6401), 1049 regmap_reg_range(0x6403, 0x6403), 1050 regmap_reg_range(0x6410, 0x6417), 1051 regmap_reg_range(0x6420, 0x6423), 1052 regmap_reg_range(0x6500, 0x6507), 1053 regmap_reg_range(0x6600, 0x6612), 1054 regmap_reg_range(0x6800, 0x680f), 1055 regmap_reg_range(0x6820, 0x6827), 1056 regmap_reg_range(0x6830, 0x6837), 1057 regmap_reg_range(0x6840, 0x684b), 1058 regmap_reg_range(0x6900, 0x6907), 1059 regmap_reg_range(0x6914, 0x6915), 1060 regmap_reg_range(0x6a00, 0x6a03), 1061 regmap_reg_range(0x6a04, 0x6a07), 1062 regmap_reg_range(0x6b00, 0x6b01), 1063 regmap_reg_range(0x6b04, 0x6b04), 1064 }; 1065 1066 static const struct regmap_access_table ksz9896_register_set = { 1067 .yes_ranges = ksz9896_valid_regs, 1068 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs), 1069 }; 1070 1071 const struct ksz_chip_data ksz_switch_chips[] = { 1072 [KSZ8563] = { 1073 .chip_id = KSZ8563_CHIP_ID, 1074 .dev_name = "KSZ8563", 1075 .num_vlans = 4096, 1076 .num_alus = 4096, 1077 .num_statics = 16, 1078 .cpu_ports = 0x07, /* can be configured as cpu port */ 1079 .port_cnt = 3, /* total port count */ 1080 .port_nirqs = 3, 1081 .ops = &ksz9477_dev_ops, 1082 .mib_names = ksz9477_mib_names, 1083 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1084 .reg_mib_cnt = MIB_COUNTER_NUM, 1085 .regs = ksz9477_regs, 1086 .masks = ksz9477_masks, 1087 .shifts = ksz9477_shifts, 1088 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1089 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1090 .supports_mii = {false, false, true}, 1091 .supports_rmii = {false, false, true}, 1092 .supports_rgmii = {false, false, true}, 1093 .internal_phy = {true, true, false}, 1094 .gbit_capable = {false, false, true}, 1095 .wr_table = &ksz8563_register_set, 1096 .rd_table = &ksz8563_register_set, 1097 }, 1098 1099 [KSZ8795] = { 1100 .chip_id = KSZ8795_CHIP_ID, 1101 .dev_name = "KSZ8795", 1102 .num_vlans = 4096, 1103 .num_alus = 0, 1104 .num_statics = 8, 1105 .cpu_ports = 0x10, /* can be configured as cpu port */ 1106 .port_cnt = 5, /* total cpu and user ports */ 1107 .ops = &ksz8_dev_ops, 1108 .ksz87xx_eee_link_erratum = true, 1109 .mib_names = ksz9477_mib_names, 1110 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1111 .reg_mib_cnt = MIB_COUNTER_NUM, 1112 .regs = ksz8795_regs, 1113 .masks = ksz8795_masks, 1114 .shifts = ksz8795_shifts, 1115 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1116 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1117 .supports_mii = {false, false, false, false, true}, 1118 .supports_rmii = {false, false, false, false, true}, 1119 .supports_rgmii = {false, false, false, false, true}, 1120 .internal_phy = {true, true, true, true, false}, 1121 }, 1122 1123 [KSZ8794] = { 1124 /* WARNING 1125 * ======= 1126 * KSZ8794 is similar to KSZ8795, except the port map 1127 * contains a gap between external and CPU ports, the 1128 * port map is NOT continuous. The per-port register 1129 * map is shifted accordingly too, i.e. registers at 1130 * offset 0x40 are NOT used on KSZ8794 and they ARE 1131 * used on KSZ8795 for external port 3. 1132 * external cpu 1133 * KSZ8794 0,1,2 4 1134 * KSZ8795 0,1,2,3 4 1135 * KSZ8765 0,1,2,3 4 1136 * port_cnt is configured as 5, even though it is 4 1137 */ 1138 .chip_id = KSZ8794_CHIP_ID, 1139 .dev_name = "KSZ8794", 1140 .num_vlans = 4096, 1141 .num_alus = 0, 1142 .num_statics = 8, 1143 .cpu_ports = 0x10, /* can be configured as cpu port */ 1144 .port_cnt = 5, /* total cpu and user ports */ 1145 .ops = &ksz8_dev_ops, 1146 .ksz87xx_eee_link_erratum = true, 1147 .mib_names = ksz9477_mib_names, 1148 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1149 .reg_mib_cnt = MIB_COUNTER_NUM, 1150 .regs = ksz8795_regs, 1151 .masks = ksz8795_masks, 1152 .shifts = ksz8795_shifts, 1153 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1154 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1155 .supports_mii = {false, false, false, false, true}, 1156 .supports_rmii = {false, false, false, false, true}, 1157 .supports_rgmii = {false, false, false, false, true}, 1158 .internal_phy = {true, true, true, false, false}, 1159 }, 1160 1161 [KSZ8765] = { 1162 .chip_id = KSZ8765_CHIP_ID, 1163 .dev_name = "KSZ8765", 1164 .num_vlans = 4096, 1165 .num_alus = 0, 1166 .num_statics = 8, 1167 .cpu_ports = 0x10, /* can be configured as cpu port */ 1168 .port_cnt = 5, /* total cpu and user ports */ 1169 .ops = &ksz8_dev_ops, 1170 .ksz87xx_eee_link_erratum = true, 1171 .mib_names = ksz9477_mib_names, 1172 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1173 .reg_mib_cnt = MIB_COUNTER_NUM, 1174 .regs = ksz8795_regs, 1175 .masks = ksz8795_masks, 1176 .shifts = ksz8795_shifts, 1177 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1178 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1179 .supports_mii = {false, false, false, false, true}, 1180 .supports_rmii = {false, false, false, false, true}, 1181 .supports_rgmii = {false, false, false, false, true}, 1182 .internal_phy = {true, true, true, true, false}, 1183 }, 1184 1185 [KSZ8830] = { 1186 .chip_id = KSZ8830_CHIP_ID, 1187 .dev_name = "KSZ8863/KSZ8873", 1188 .num_vlans = 16, 1189 .num_alus = 0, 1190 .num_statics = 8, 1191 .cpu_ports = 0x4, /* can be configured as cpu port */ 1192 .port_cnt = 3, 1193 .ops = &ksz8_dev_ops, 1194 .mib_names = ksz88xx_mib_names, 1195 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1196 .reg_mib_cnt = MIB_COUNTER_NUM, 1197 .regs = ksz8863_regs, 1198 .masks = ksz8863_masks, 1199 .shifts = ksz8863_shifts, 1200 .supports_mii = {false, false, true}, 1201 .supports_rmii = {false, false, true}, 1202 .internal_phy = {true, true, false}, 1203 }, 1204 1205 [KSZ9477] = { 1206 .chip_id = KSZ9477_CHIP_ID, 1207 .dev_name = "KSZ9477", 1208 .num_vlans = 4096, 1209 .num_alus = 4096, 1210 .num_statics = 16, 1211 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1212 .port_cnt = 7, /* total physical port count */ 1213 .port_nirqs = 4, 1214 .ops = &ksz9477_dev_ops, 1215 .phy_errata_9477 = true, 1216 .mib_names = ksz9477_mib_names, 1217 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1218 .reg_mib_cnt = MIB_COUNTER_NUM, 1219 .regs = ksz9477_regs, 1220 .masks = ksz9477_masks, 1221 .shifts = ksz9477_shifts, 1222 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1223 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1224 .supports_mii = {false, false, false, false, 1225 false, true, false}, 1226 .supports_rmii = {false, false, false, false, 1227 false, true, false}, 1228 .supports_rgmii = {false, false, false, false, 1229 false, true, false}, 1230 .internal_phy = {true, true, true, true, 1231 true, false, false}, 1232 .gbit_capable = {true, true, true, true, true, true, true}, 1233 .wr_table = &ksz9477_register_set, 1234 .rd_table = &ksz9477_register_set, 1235 }, 1236 1237 [KSZ9896] = { 1238 .chip_id = KSZ9896_CHIP_ID, 1239 .dev_name = "KSZ9896", 1240 .num_vlans = 4096, 1241 .num_alus = 4096, 1242 .num_statics = 16, 1243 .cpu_ports = 0x3F, /* can be configured as cpu port */ 1244 .port_cnt = 6, /* total physical port count */ 1245 .port_nirqs = 2, 1246 .ops = &ksz9477_dev_ops, 1247 .phy_errata_9477 = true, 1248 .mib_names = ksz9477_mib_names, 1249 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1250 .reg_mib_cnt = MIB_COUNTER_NUM, 1251 .regs = ksz9477_regs, 1252 .masks = ksz9477_masks, 1253 .shifts = ksz9477_shifts, 1254 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1255 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1256 .supports_mii = {false, false, false, false, 1257 false, true}, 1258 .supports_rmii = {false, false, false, false, 1259 false, true}, 1260 .supports_rgmii = {false, false, false, false, 1261 false, true}, 1262 .internal_phy = {true, true, true, true, 1263 true, false}, 1264 .gbit_capable = {true, true, true, true, true, true}, 1265 .wr_table = &ksz9896_register_set, 1266 .rd_table = &ksz9896_register_set, 1267 }, 1268 1269 [KSZ9897] = { 1270 .chip_id = KSZ9897_CHIP_ID, 1271 .dev_name = "KSZ9897", 1272 .num_vlans = 4096, 1273 .num_alus = 4096, 1274 .num_statics = 16, 1275 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1276 .port_cnt = 7, /* total physical port count */ 1277 .port_nirqs = 2, 1278 .ops = &ksz9477_dev_ops, 1279 .phy_errata_9477 = true, 1280 .mib_names = ksz9477_mib_names, 1281 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1282 .reg_mib_cnt = MIB_COUNTER_NUM, 1283 .regs = ksz9477_regs, 1284 .masks = ksz9477_masks, 1285 .shifts = ksz9477_shifts, 1286 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1287 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1288 .supports_mii = {false, false, false, false, 1289 false, true, true}, 1290 .supports_rmii = {false, false, false, false, 1291 false, true, true}, 1292 .supports_rgmii = {false, false, false, false, 1293 false, true, true}, 1294 .internal_phy = {true, true, true, true, 1295 true, false, false}, 1296 .gbit_capable = {true, true, true, true, true, true, true}, 1297 }, 1298 1299 [KSZ9893] = { 1300 .chip_id = KSZ9893_CHIP_ID, 1301 .dev_name = "KSZ9893", 1302 .num_vlans = 4096, 1303 .num_alus = 4096, 1304 .num_statics = 16, 1305 .cpu_ports = 0x07, /* can be configured as cpu port */ 1306 .port_cnt = 3, /* total port count */ 1307 .port_nirqs = 2, 1308 .ops = &ksz9477_dev_ops, 1309 .mib_names = ksz9477_mib_names, 1310 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1311 .reg_mib_cnt = MIB_COUNTER_NUM, 1312 .regs = ksz9477_regs, 1313 .masks = ksz9477_masks, 1314 .shifts = ksz9477_shifts, 1315 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1316 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1317 .supports_mii = {false, false, true}, 1318 .supports_rmii = {false, false, true}, 1319 .supports_rgmii = {false, false, true}, 1320 .internal_phy = {true, true, false}, 1321 .gbit_capable = {true, true, true}, 1322 }, 1323 1324 [KSZ9563] = { 1325 .chip_id = KSZ9563_CHIP_ID, 1326 .dev_name = "KSZ9563", 1327 .num_vlans = 4096, 1328 .num_alus = 4096, 1329 .num_statics = 16, 1330 .cpu_ports = 0x07, /* can be configured as cpu port */ 1331 .port_cnt = 3, /* total port count */ 1332 .port_nirqs = 3, 1333 .ops = &ksz9477_dev_ops, 1334 .mib_names = ksz9477_mib_names, 1335 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1336 .reg_mib_cnt = MIB_COUNTER_NUM, 1337 .regs = ksz9477_regs, 1338 .masks = ksz9477_masks, 1339 .shifts = ksz9477_shifts, 1340 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1341 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1342 .supports_mii = {false, false, true}, 1343 .supports_rmii = {false, false, true}, 1344 .supports_rgmii = {false, false, true}, 1345 .internal_phy = {true, true, false}, 1346 .gbit_capable = {true, true, true}, 1347 }, 1348 1349 [KSZ9567] = { 1350 .chip_id = KSZ9567_CHIP_ID, 1351 .dev_name = "KSZ9567", 1352 .num_vlans = 4096, 1353 .num_alus = 4096, 1354 .num_statics = 16, 1355 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1356 .port_cnt = 7, /* total physical port count */ 1357 .port_nirqs = 3, 1358 .ops = &ksz9477_dev_ops, 1359 .phy_errata_9477 = true, 1360 .mib_names = ksz9477_mib_names, 1361 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1362 .reg_mib_cnt = MIB_COUNTER_NUM, 1363 .regs = ksz9477_regs, 1364 .masks = ksz9477_masks, 1365 .shifts = ksz9477_shifts, 1366 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1367 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1368 .supports_mii = {false, false, false, false, 1369 false, true, true}, 1370 .supports_rmii = {false, false, false, false, 1371 false, true, true}, 1372 .supports_rgmii = {false, false, false, false, 1373 false, true, true}, 1374 .internal_phy = {true, true, true, true, 1375 true, false, false}, 1376 .gbit_capable = {true, true, true, true, true, true, true}, 1377 }, 1378 1379 [LAN9370] = { 1380 .chip_id = LAN9370_CHIP_ID, 1381 .dev_name = "LAN9370", 1382 .num_vlans = 4096, 1383 .num_alus = 1024, 1384 .num_statics = 256, 1385 .cpu_ports = 0x10, /* can be configured as cpu port */ 1386 .port_cnt = 5, /* total physical port count */ 1387 .port_nirqs = 6, 1388 .ops = &lan937x_dev_ops, 1389 .mib_names = ksz9477_mib_names, 1390 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1391 .reg_mib_cnt = MIB_COUNTER_NUM, 1392 .regs = ksz9477_regs, 1393 .masks = lan937x_masks, 1394 .shifts = lan937x_shifts, 1395 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1396 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1397 .supports_mii = {false, false, false, false, true}, 1398 .supports_rmii = {false, false, false, false, true}, 1399 .supports_rgmii = {false, false, false, false, true}, 1400 .internal_phy = {true, true, true, true, false}, 1401 }, 1402 1403 [LAN9371] = { 1404 .chip_id = LAN9371_CHIP_ID, 1405 .dev_name = "LAN9371", 1406 .num_vlans = 4096, 1407 .num_alus = 1024, 1408 .num_statics = 256, 1409 .cpu_ports = 0x30, /* can be configured as cpu port */ 1410 .port_cnt = 6, /* total physical port count */ 1411 .port_nirqs = 6, 1412 .ops = &lan937x_dev_ops, 1413 .mib_names = ksz9477_mib_names, 1414 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1415 .reg_mib_cnt = MIB_COUNTER_NUM, 1416 .regs = ksz9477_regs, 1417 .masks = lan937x_masks, 1418 .shifts = lan937x_shifts, 1419 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1420 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1421 .supports_mii = {false, false, false, false, true, true}, 1422 .supports_rmii = {false, false, false, false, true, true}, 1423 .supports_rgmii = {false, false, false, false, true, true}, 1424 .internal_phy = {true, true, true, true, false, false}, 1425 }, 1426 1427 [LAN9372] = { 1428 .chip_id = LAN9372_CHIP_ID, 1429 .dev_name = "LAN9372", 1430 .num_vlans = 4096, 1431 .num_alus = 1024, 1432 .num_statics = 256, 1433 .cpu_ports = 0x30, /* can be configured as cpu port */ 1434 .port_cnt = 8, /* total physical port count */ 1435 .port_nirqs = 6, 1436 .ops = &lan937x_dev_ops, 1437 .mib_names = ksz9477_mib_names, 1438 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1439 .reg_mib_cnt = MIB_COUNTER_NUM, 1440 .regs = ksz9477_regs, 1441 .masks = lan937x_masks, 1442 .shifts = lan937x_shifts, 1443 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1444 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1445 .supports_mii = {false, false, false, false, 1446 true, true, false, false}, 1447 .supports_rmii = {false, false, false, false, 1448 true, true, false, false}, 1449 .supports_rgmii = {false, false, false, false, 1450 true, true, false, false}, 1451 .internal_phy = {true, true, true, true, 1452 false, false, true, true}, 1453 }, 1454 1455 [LAN9373] = { 1456 .chip_id = LAN9373_CHIP_ID, 1457 .dev_name = "LAN9373", 1458 .num_vlans = 4096, 1459 .num_alus = 1024, 1460 .num_statics = 256, 1461 .cpu_ports = 0x38, /* can be configured as cpu port */ 1462 .port_cnt = 5, /* total physical port count */ 1463 .port_nirqs = 6, 1464 .ops = &lan937x_dev_ops, 1465 .mib_names = ksz9477_mib_names, 1466 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1467 .reg_mib_cnt = MIB_COUNTER_NUM, 1468 .regs = ksz9477_regs, 1469 .masks = lan937x_masks, 1470 .shifts = lan937x_shifts, 1471 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1472 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1473 .supports_mii = {false, false, false, false, 1474 true, true, false, false}, 1475 .supports_rmii = {false, false, false, false, 1476 true, true, false, false}, 1477 .supports_rgmii = {false, false, false, false, 1478 true, true, false, false}, 1479 .internal_phy = {true, true, true, false, 1480 false, false, true, true}, 1481 }, 1482 1483 [LAN9374] = { 1484 .chip_id = LAN9374_CHIP_ID, 1485 .dev_name = "LAN9374", 1486 .num_vlans = 4096, 1487 .num_alus = 1024, 1488 .num_statics = 256, 1489 .cpu_ports = 0x30, /* can be configured as cpu port */ 1490 .port_cnt = 8, /* total physical port count */ 1491 .port_nirqs = 6, 1492 .ops = &lan937x_dev_ops, 1493 .mib_names = ksz9477_mib_names, 1494 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1495 .reg_mib_cnt = MIB_COUNTER_NUM, 1496 .regs = ksz9477_regs, 1497 .masks = lan937x_masks, 1498 .shifts = lan937x_shifts, 1499 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1500 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1501 .supports_mii = {false, false, false, false, 1502 true, true, false, false}, 1503 .supports_rmii = {false, false, false, false, 1504 true, true, false, false}, 1505 .supports_rgmii = {false, false, false, false, 1506 true, true, false, false}, 1507 .internal_phy = {true, true, true, true, 1508 false, false, true, true}, 1509 }, 1510 }; 1511 EXPORT_SYMBOL_GPL(ksz_switch_chips); 1512 1513 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 1514 { 1515 int i; 1516 1517 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 1518 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 1519 1520 if (chip->chip_id == prod_num) 1521 return chip; 1522 } 1523 1524 return NULL; 1525 } 1526 1527 static int ksz_check_device_id(struct ksz_device *dev) 1528 { 1529 const struct ksz_chip_data *dt_chip_data; 1530 1531 dt_chip_data = of_device_get_match_data(dev->dev); 1532 1533 /* Check for Device Tree and Chip ID */ 1534 if (dt_chip_data->chip_id != dev->chip_id) { 1535 dev_err(dev->dev, 1536 "Device tree specifies chip %s but found %s, please fix it!\n", 1537 dt_chip_data->dev_name, dev->info->dev_name); 1538 return -ENODEV; 1539 } 1540 1541 return 0; 1542 } 1543 1544 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 1545 struct phylink_config *config) 1546 { 1547 struct ksz_device *dev = ds->priv; 1548 1549 config->legacy_pre_march2020 = false; 1550 1551 if (dev->info->supports_mii[port]) 1552 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 1553 1554 if (dev->info->supports_rmii[port]) 1555 __set_bit(PHY_INTERFACE_MODE_RMII, 1556 config->supported_interfaces); 1557 1558 if (dev->info->supports_rgmii[port]) 1559 phy_interface_set_rgmii(config->supported_interfaces); 1560 1561 if (dev->info->internal_phy[port]) { 1562 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1563 config->supported_interfaces); 1564 /* Compatibility for phylib's default interface type when the 1565 * phy-mode property is absent 1566 */ 1567 __set_bit(PHY_INTERFACE_MODE_GMII, 1568 config->supported_interfaces); 1569 } 1570 1571 if (dev->dev_ops->get_caps) 1572 dev->dev_ops->get_caps(dev, port, config); 1573 } 1574 1575 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 1576 { 1577 struct ethtool_pause_stats *pstats; 1578 struct rtnl_link_stats64 *stats; 1579 struct ksz_stats_raw *raw; 1580 struct ksz_port_mib *mib; 1581 1582 mib = &dev->ports[port].mib; 1583 stats = &mib->stats64; 1584 pstats = &mib->pause_stats; 1585 raw = (struct ksz_stats_raw *)mib->counters; 1586 1587 spin_lock(&mib->stats64_lock); 1588 1589 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1590 raw->rx_pause; 1591 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1592 raw->tx_pause; 1593 1594 /* HW counters are counting bytes + FCS which is not acceptable 1595 * for rtnl_link_stats64 interface 1596 */ 1597 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 1598 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 1599 1600 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 1601 raw->rx_oversize; 1602 1603 stats->rx_crc_errors = raw->rx_crc_err; 1604 stats->rx_frame_errors = raw->rx_align_err; 1605 stats->rx_dropped = raw->rx_discards; 1606 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 1607 stats->rx_frame_errors + stats->rx_dropped; 1608 1609 stats->tx_window_errors = raw->tx_late_col; 1610 stats->tx_fifo_errors = raw->tx_discards; 1611 stats->tx_aborted_errors = raw->tx_exc_col; 1612 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 1613 stats->tx_aborted_errors; 1614 1615 stats->multicast = raw->rx_mcast; 1616 stats->collisions = raw->tx_total_col; 1617 1618 pstats->tx_pause_frames = raw->tx_pause; 1619 pstats->rx_pause_frames = raw->rx_pause; 1620 1621 spin_unlock(&mib->stats64_lock); 1622 } 1623 1624 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port) 1625 { 1626 struct ethtool_pause_stats *pstats; 1627 struct rtnl_link_stats64 *stats; 1628 struct ksz88xx_stats_raw *raw; 1629 struct ksz_port_mib *mib; 1630 1631 mib = &dev->ports[port].mib; 1632 stats = &mib->stats64; 1633 pstats = &mib->pause_stats; 1634 raw = (struct ksz88xx_stats_raw *)mib->counters; 1635 1636 spin_lock(&mib->stats64_lock); 1637 1638 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 1639 raw->rx_pause; 1640 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 1641 raw->tx_pause; 1642 1643 /* HW counters are counting bytes + FCS which is not acceptable 1644 * for rtnl_link_stats64 interface 1645 */ 1646 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN; 1647 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN; 1648 1649 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 1650 raw->rx_oversize; 1651 1652 stats->rx_crc_errors = raw->rx_crc_err; 1653 stats->rx_frame_errors = raw->rx_align_err; 1654 stats->rx_dropped = raw->rx_discards; 1655 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 1656 stats->rx_frame_errors + stats->rx_dropped; 1657 1658 stats->tx_window_errors = raw->tx_late_col; 1659 stats->tx_fifo_errors = raw->tx_discards; 1660 stats->tx_aborted_errors = raw->tx_exc_col; 1661 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 1662 stats->tx_aborted_errors; 1663 1664 stats->multicast = raw->rx_mcast; 1665 stats->collisions = raw->tx_total_col; 1666 1667 pstats->tx_pause_frames = raw->tx_pause; 1668 pstats->rx_pause_frames = raw->rx_pause; 1669 1670 spin_unlock(&mib->stats64_lock); 1671 } 1672 1673 static void ksz_get_stats64(struct dsa_switch *ds, int port, 1674 struct rtnl_link_stats64 *s) 1675 { 1676 struct ksz_device *dev = ds->priv; 1677 struct ksz_port_mib *mib; 1678 1679 mib = &dev->ports[port].mib; 1680 1681 spin_lock(&mib->stats64_lock); 1682 memcpy(s, &mib->stats64, sizeof(*s)); 1683 spin_unlock(&mib->stats64_lock); 1684 } 1685 1686 static void ksz_get_pause_stats(struct dsa_switch *ds, int port, 1687 struct ethtool_pause_stats *pause_stats) 1688 { 1689 struct ksz_device *dev = ds->priv; 1690 struct ksz_port_mib *mib; 1691 1692 mib = &dev->ports[port].mib; 1693 1694 spin_lock(&mib->stats64_lock); 1695 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 1696 spin_unlock(&mib->stats64_lock); 1697 } 1698 1699 static void ksz_get_strings(struct dsa_switch *ds, int port, 1700 u32 stringset, uint8_t *buf) 1701 { 1702 struct ksz_device *dev = ds->priv; 1703 int i; 1704 1705 if (stringset != ETH_SS_STATS) 1706 return; 1707 1708 for (i = 0; i < dev->info->mib_cnt; i++) { 1709 memcpy(buf + i * ETH_GSTRING_LEN, 1710 dev->info->mib_names[i].string, ETH_GSTRING_LEN); 1711 } 1712 } 1713 1714 static void ksz_update_port_member(struct ksz_device *dev, int port) 1715 { 1716 struct ksz_port *p = &dev->ports[port]; 1717 struct dsa_switch *ds = dev->ds; 1718 u8 port_member = 0, cpu_port; 1719 const struct dsa_port *dp; 1720 int i, j; 1721 1722 if (!dsa_is_user_port(ds, port)) 1723 return; 1724 1725 dp = dsa_to_port(ds, port); 1726 cpu_port = BIT(dsa_upstream_port(ds, port)); 1727 1728 for (i = 0; i < ds->num_ports; i++) { 1729 const struct dsa_port *other_dp = dsa_to_port(ds, i); 1730 struct ksz_port *other_p = &dev->ports[i]; 1731 u8 val = 0; 1732 1733 if (!dsa_is_user_port(ds, i)) 1734 continue; 1735 if (port == i) 1736 continue; 1737 if (!dsa_port_bridge_same(dp, other_dp)) 1738 continue; 1739 if (other_p->stp_state != BR_STATE_FORWARDING) 1740 continue; 1741 1742 if (p->stp_state == BR_STATE_FORWARDING) { 1743 val |= BIT(port); 1744 port_member |= BIT(i); 1745 } 1746 1747 /* Retain port [i]'s relationship to other ports than [port] */ 1748 for (j = 0; j < ds->num_ports; j++) { 1749 const struct dsa_port *third_dp; 1750 struct ksz_port *third_p; 1751 1752 if (j == i) 1753 continue; 1754 if (j == port) 1755 continue; 1756 if (!dsa_is_user_port(ds, j)) 1757 continue; 1758 third_p = &dev->ports[j]; 1759 if (third_p->stp_state != BR_STATE_FORWARDING) 1760 continue; 1761 third_dp = dsa_to_port(ds, j); 1762 if (dsa_port_bridge_same(other_dp, third_dp)) 1763 val |= BIT(j); 1764 } 1765 1766 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 1767 } 1768 1769 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 1770 } 1771 1772 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 1773 { 1774 struct ksz_device *dev = bus->priv; 1775 u16 val; 1776 int ret; 1777 1778 if (regnum & MII_ADDR_C45) 1779 return -EOPNOTSUPP; 1780 1781 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val); 1782 if (ret < 0) 1783 return ret; 1784 1785 return val; 1786 } 1787 1788 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 1789 u16 val) 1790 { 1791 struct ksz_device *dev = bus->priv; 1792 1793 if (regnum & MII_ADDR_C45) 1794 return -EOPNOTSUPP; 1795 1796 return dev->dev_ops->w_phy(dev, addr, regnum, val); 1797 } 1798 1799 static int ksz_irq_phy_setup(struct ksz_device *dev) 1800 { 1801 struct dsa_switch *ds = dev->ds; 1802 int phy; 1803 int irq; 1804 int ret; 1805 1806 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) { 1807 if (BIT(phy) & ds->phys_mii_mask) { 1808 irq = irq_find_mapping(dev->ports[phy].pirq.domain, 1809 PORT_SRC_PHY_INT); 1810 if (irq < 0) { 1811 ret = irq; 1812 goto out; 1813 } 1814 ds->slave_mii_bus->irq[phy] = irq; 1815 } 1816 } 1817 return 0; 1818 out: 1819 while (phy--) 1820 if (BIT(phy) & ds->phys_mii_mask) 1821 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]); 1822 1823 return ret; 1824 } 1825 1826 static void ksz_irq_phy_free(struct ksz_device *dev) 1827 { 1828 struct dsa_switch *ds = dev->ds; 1829 int phy; 1830 1831 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) 1832 if (BIT(phy) & ds->phys_mii_mask) 1833 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]); 1834 } 1835 1836 static int ksz_mdio_register(struct ksz_device *dev) 1837 { 1838 struct dsa_switch *ds = dev->ds; 1839 struct device_node *mdio_np; 1840 struct mii_bus *bus; 1841 int ret; 1842 1843 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); 1844 if (!mdio_np) 1845 return 0; 1846 1847 bus = devm_mdiobus_alloc(ds->dev); 1848 if (!bus) { 1849 of_node_put(mdio_np); 1850 return -ENOMEM; 1851 } 1852 1853 bus->priv = dev; 1854 bus->read = ksz_sw_mdio_read; 1855 bus->write = ksz_sw_mdio_write; 1856 bus->name = "ksz slave smi"; 1857 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); 1858 bus->parent = ds->dev; 1859 bus->phy_mask = ~ds->phys_mii_mask; 1860 1861 ds->slave_mii_bus = bus; 1862 1863 if (dev->irq > 0) { 1864 ret = ksz_irq_phy_setup(dev); 1865 if (ret) { 1866 of_node_put(mdio_np); 1867 return ret; 1868 } 1869 } 1870 1871 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); 1872 if (ret) { 1873 dev_err(ds->dev, "unable to register MDIO bus %s\n", 1874 bus->id); 1875 if (dev->irq > 0) 1876 ksz_irq_phy_free(dev); 1877 } 1878 1879 of_node_put(mdio_np); 1880 1881 return ret; 1882 } 1883 1884 static void ksz_irq_mask(struct irq_data *d) 1885 { 1886 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1887 1888 kirq->masked |= BIT(d->hwirq); 1889 } 1890 1891 static void ksz_irq_unmask(struct irq_data *d) 1892 { 1893 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1894 1895 kirq->masked &= ~BIT(d->hwirq); 1896 } 1897 1898 static void ksz_irq_bus_lock(struct irq_data *d) 1899 { 1900 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1901 1902 mutex_lock(&kirq->dev->lock_irq); 1903 } 1904 1905 static void ksz_irq_bus_sync_unlock(struct irq_data *d) 1906 { 1907 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 1908 struct ksz_device *dev = kirq->dev; 1909 int ret; 1910 1911 ret = ksz_write32(dev, kirq->reg_mask, kirq->masked); 1912 if (ret) 1913 dev_err(dev->dev, "failed to change IRQ mask\n"); 1914 1915 mutex_unlock(&dev->lock_irq); 1916 } 1917 1918 static const struct irq_chip ksz_irq_chip = { 1919 .name = "ksz-irq", 1920 .irq_mask = ksz_irq_mask, 1921 .irq_unmask = ksz_irq_unmask, 1922 .irq_bus_lock = ksz_irq_bus_lock, 1923 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock, 1924 }; 1925 1926 static int ksz_irq_domain_map(struct irq_domain *d, 1927 unsigned int irq, irq_hw_number_t hwirq) 1928 { 1929 irq_set_chip_data(irq, d->host_data); 1930 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq); 1931 irq_set_noprobe(irq); 1932 1933 return 0; 1934 } 1935 1936 static const struct irq_domain_ops ksz_irq_domain_ops = { 1937 .map = ksz_irq_domain_map, 1938 .xlate = irq_domain_xlate_twocell, 1939 }; 1940 1941 static void ksz_irq_free(struct ksz_irq *kirq) 1942 { 1943 int irq, virq; 1944 1945 free_irq(kirq->irq_num, kirq); 1946 1947 for (irq = 0; irq < kirq->nirqs; irq++) { 1948 virq = irq_find_mapping(kirq->domain, irq); 1949 irq_dispose_mapping(virq); 1950 } 1951 1952 irq_domain_remove(kirq->domain); 1953 } 1954 1955 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id) 1956 { 1957 struct ksz_irq *kirq = dev_id; 1958 unsigned int nhandled = 0; 1959 struct ksz_device *dev; 1960 unsigned int sub_irq; 1961 u8 data; 1962 int ret; 1963 u8 n; 1964 1965 dev = kirq->dev; 1966 1967 /* Read interrupt status register */ 1968 ret = ksz_read8(dev, kirq->reg_status, &data); 1969 if (ret) 1970 goto out; 1971 1972 for (n = 0; n < kirq->nirqs; ++n) { 1973 if (data & BIT(n)) { 1974 sub_irq = irq_find_mapping(kirq->domain, n); 1975 handle_nested_irq(sub_irq); 1976 ++nhandled; 1977 } 1978 } 1979 out: 1980 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 1981 } 1982 1983 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq) 1984 { 1985 int ret, n; 1986 1987 kirq->dev = dev; 1988 kirq->masked = ~0; 1989 1990 kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0, 1991 &ksz_irq_domain_ops, kirq); 1992 if (!kirq->domain) 1993 return -ENOMEM; 1994 1995 for (n = 0; n < kirq->nirqs; n++) 1996 irq_create_mapping(kirq->domain, n); 1997 1998 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn, 1999 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 2000 kirq->name, kirq); 2001 if (ret) 2002 goto out; 2003 2004 return 0; 2005 2006 out: 2007 ksz_irq_free(kirq); 2008 2009 return ret; 2010 } 2011 2012 static int ksz_girq_setup(struct ksz_device *dev) 2013 { 2014 struct ksz_irq *girq = &dev->girq; 2015 2016 girq->nirqs = dev->info->port_cnt; 2017 girq->reg_mask = REG_SW_PORT_INT_MASK__1; 2018 girq->reg_status = REG_SW_PORT_INT_STATUS__1; 2019 snprintf(girq->name, sizeof(girq->name), "global_port_irq"); 2020 2021 girq->irq_num = dev->irq; 2022 2023 return ksz_irq_common_setup(dev, girq); 2024 } 2025 2026 static int ksz_pirq_setup(struct ksz_device *dev, u8 p) 2027 { 2028 struct ksz_irq *pirq = &dev->ports[p].pirq; 2029 2030 pirq->nirqs = dev->info->port_nirqs; 2031 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK); 2032 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS); 2033 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p); 2034 2035 pirq->irq_num = irq_find_mapping(dev->girq.domain, p); 2036 if (pirq->irq_num < 0) 2037 return pirq->irq_num; 2038 2039 return ksz_irq_common_setup(dev, pirq); 2040 } 2041 2042 static int ksz_setup(struct dsa_switch *ds) 2043 { 2044 struct ksz_device *dev = ds->priv; 2045 struct dsa_port *dp; 2046 struct ksz_port *p; 2047 const u16 *regs; 2048 int ret; 2049 2050 regs = dev->info->regs; 2051 2052 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 2053 dev->info->num_vlans, GFP_KERNEL); 2054 if (!dev->vlan_cache) 2055 return -ENOMEM; 2056 2057 ret = dev->dev_ops->reset(dev); 2058 if (ret) { 2059 dev_err(ds->dev, "failed to reset switch\n"); 2060 return ret; 2061 } 2062 2063 /* set broadcast storm protection 10% rate */ 2064 regmap_update_bits(dev->regmap[1], regs[S_BROADCAST_CTRL], 2065 BROADCAST_STORM_RATE, 2066 (BROADCAST_STORM_VALUE * 2067 BROADCAST_STORM_PROT_RATE) / 100); 2068 2069 dev->dev_ops->config_cpu_port(ds); 2070 2071 dev->dev_ops->enable_stp_addr(dev); 2072 2073 regmap_update_bits(dev->regmap[0], regs[S_MULTICAST_CTRL], 2074 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 2075 2076 ksz_init_mib_timer(dev); 2077 2078 ds->configure_vlan_while_not_filtering = false; 2079 2080 if (dev->dev_ops->setup) { 2081 ret = dev->dev_ops->setup(ds); 2082 if (ret) 2083 return ret; 2084 } 2085 2086 /* Start with learning disabled on standalone user ports, and enabled 2087 * on the CPU port. In lack of other finer mechanisms, learning on the 2088 * CPU port will avoid flooding bridge local addresses on the network 2089 * in some cases. 2090 */ 2091 p = &dev->ports[dev->cpu_port]; 2092 p->learning = true; 2093 2094 if (dev->irq > 0) { 2095 ret = ksz_girq_setup(dev); 2096 if (ret) 2097 return ret; 2098 2099 dsa_switch_for_each_user_port(dp, dev->ds) { 2100 ret = ksz_pirq_setup(dev, dp->index); 2101 if (ret) 2102 goto out_girq; 2103 } 2104 } 2105 2106 ret = ksz_mdio_register(dev); 2107 if (ret < 0) { 2108 dev_err(dev->dev, "failed to register the mdio"); 2109 goto out_pirq; 2110 } 2111 2112 /* start switch */ 2113 regmap_update_bits(dev->regmap[0], regs[S_START_CTRL], 2114 SW_START, SW_START); 2115 2116 return 0; 2117 2118 out_pirq: 2119 if (dev->irq > 0) 2120 dsa_switch_for_each_user_port(dp, dev->ds) 2121 ksz_irq_free(&dev->ports[dp->index].pirq); 2122 out_girq: 2123 if (dev->irq > 0) 2124 ksz_irq_free(&dev->girq); 2125 2126 return ret; 2127 } 2128 2129 static void ksz_teardown(struct dsa_switch *ds) 2130 { 2131 struct ksz_device *dev = ds->priv; 2132 struct dsa_port *dp; 2133 2134 if (dev->irq > 0) { 2135 dsa_switch_for_each_user_port(dp, dev->ds) 2136 ksz_irq_free(&dev->ports[dp->index].pirq); 2137 2138 ksz_irq_free(&dev->girq); 2139 } 2140 2141 if (dev->dev_ops->teardown) 2142 dev->dev_ops->teardown(ds); 2143 } 2144 2145 static void port_r_cnt(struct ksz_device *dev, int port) 2146 { 2147 struct ksz_port_mib *mib = &dev->ports[port].mib; 2148 u64 *dropped; 2149 2150 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 2151 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 2152 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 2153 &mib->counters[mib->cnt_ptr]); 2154 ++mib->cnt_ptr; 2155 } 2156 2157 /* last one in storage */ 2158 dropped = &mib->counters[dev->info->mib_cnt]; 2159 2160 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 2161 while (mib->cnt_ptr < dev->info->mib_cnt) { 2162 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 2163 dropped, &mib->counters[mib->cnt_ptr]); 2164 ++mib->cnt_ptr; 2165 } 2166 mib->cnt_ptr = 0; 2167 } 2168 2169 static void ksz_mib_read_work(struct work_struct *work) 2170 { 2171 struct ksz_device *dev = container_of(work, struct ksz_device, 2172 mib_read.work); 2173 struct ksz_port_mib *mib; 2174 struct ksz_port *p; 2175 int i; 2176 2177 for (i = 0; i < dev->info->port_cnt; i++) { 2178 if (dsa_is_unused_port(dev->ds, i)) 2179 continue; 2180 2181 p = &dev->ports[i]; 2182 mib = &p->mib; 2183 mutex_lock(&mib->cnt_mutex); 2184 2185 /* Only read MIB counters when the port is told to do. 2186 * If not, read only dropped counters when link is not up. 2187 */ 2188 if (!p->read) { 2189 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 2190 2191 if (!netif_carrier_ok(dp->slave)) 2192 mib->cnt_ptr = dev->info->reg_mib_cnt; 2193 } 2194 port_r_cnt(dev, i); 2195 p->read = false; 2196 2197 if (dev->dev_ops->r_mib_stat64) 2198 dev->dev_ops->r_mib_stat64(dev, i); 2199 2200 mutex_unlock(&mib->cnt_mutex); 2201 } 2202 2203 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 2204 } 2205 2206 void ksz_init_mib_timer(struct ksz_device *dev) 2207 { 2208 int i; 2209 2210 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 2211 2212 for (i = 0; i < dev->info->port_cnt; i++) { 2213 struct ksz_port_mib *mib = &dev->ports[i].mib; 2214 2215 dev->dev_ops->port_init_cnt(dev, i); 2216 2217 mib->cnt_ptr = 0; 2218 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 2219 } 2220 } 2221 2222 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 2223 { 2224 struct ksz_device *dev = ds->priv; 2225 u16 val = 0xffff; 2226 int ret; 2227 2228 ret = dev->dev_ops->r_phy(dev, addr, reg, &val); 2229 if (ret) 2230 return ret; 2231 2232 return val; 2233 } 2234 2235 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 2236 { 2237 struct ksz_device *dev = ds->priv; 2238 int ret; 2239 2240 ret = dev->dev_ops->w_phy(dev, addr, reg, val); 2241 if (ret) 2242 return ret; 2243 2244 return 0; 2245 } 2246 2247 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 2248 { 2249 struct ksz_device *dev = ds->priv; 2250 2251 if (dev->chip_id == KSZ8830_CHIP_ID) { 2252 /* Silicon Errata Sheet (DS80000830A): 2253 * Port 1 does not work with LinkMD Cable-Testing. 2254 * Port 1 does not respond to received PAUSE control frames. 2255 */ 2256 if (!port) 2257 return MICREL_KSZ8_P1_ERRATA; 2258 } 2259 2260 return 0; 2261 } 2262 2263 static void ksz_mac_link_down(struct dsa_switch *ds, int port, 2264 unsigned int mode, phy_interface_t interface) 2265 { 2266 struct ksz_device *dev = ds->priv; 2267 struct ksz_port *p = &dev->ports[port]; 2268 2269 /* Read all MIB counters when the link is going down. */ 2270 p->read = true; 2271 /* timer started */ 2272 if (dev->mib_read_interval) 2273 schedule_delayed_work(&dev->mib_read, 0); 2274 } 2275 2276 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 2277 { 2278 struct ksz_device *dev = ds->priv; 2279 2280 if (sset != ETH_SS_STATS) 2281 return 0; 2282 2283 return dev->info->mib_cnt; 2284 } 2285 2286 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 2287 uint64_t *buf) 2288 { 2289 const struct dsa_port *dp = dsa_to_port(ds, port); 2290 struct ksz_device *dev = ds->priv; 2291 struct ksz_port_mib *mib; 2292 2293 mib = &dev->ports[port].mib; 2294 mutex_lock(&mib->cnt_mutex); 2295 2296 /* Only read dropped counters if no link. */ 2297 if (!netif_carrier_ok(dp->slave)) 2298 mib->cnt_ptr = dev->info->reg_mib_cnt; 2299 port_r_cnt(dev, port); 2300 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 2301 mutex_unlock(&mib->cnt_mutex); 2302 } 2303 2304 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 2305 struct dsa_bridge bridge, 2306 bool *tx_fwd_offload, 2307 struct netlink_ext_ack *extack) 2308 { 2309 /* port_stp_state_set() will be called after to put the port in 2310 * appropriate state so there is no need to do anything. 2311 */ 2312 2313 return 0; 2314 } 2315 2316 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 2317 struct dsa_bridge bridge) 2318 { 2319 /* port_stp_state_set() will be called after to put the port in 2320 * forwarding state so there is no need to do anything. 2321 */ 2322 } 2323 2324 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 2325 { 2326 struct ksz_device *dev = ds->priv; 2327 2328 dev->dev_ops->flush_dyn_mac_table(dev, port); 2329 } 2330 2331 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 2332 { 2333 struct ksz_device *dev = ds->priv; 2334 2335 if (!dev->dev_ops->set_ageing_time) 2336 return -EOPNOTSUPP; 2337 2338 return dev->dev_ops->set_ageing_time(dev, msecs); 2339 } 2340 2341 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 2342 const unsigned char *addr, u16 vid, 2343 struct dsa_db db) 2344 { 2345 struct ksz_device *dev = ds->priv; 2346 2347 if (!dev->dev_ops->fdb_add) 2348 return -EOPNOTSUPP; 2349 2350 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 2351 } 2352 2353 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 2354 const unsigned char *addr, 2355 u16 vid, struct dsa_db db) 2356 { 2357 struct ksz_device *dev = ds->priv; 2358 2359 if (!dev->dev_ops->fdb_del) 2360 return -EOPNOTSUPP; 2361 2362 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 2363 } 2364 2365 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 2366 dsa_fdb_dump_cb_t *cb, void *data) 2367 { 2368 struct ksz_device *dev = ds->priv; 2369 2370 if (!dev->dev_ops->fdb_dump) 2371 return -EOPNOTSUPP; 2372 2373 return dev->dev_ops->fdb_dump(dev, port, cb, data); 2374 } 2375 2376 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 2377 const struct switchdev_obj_port_mdb *mdb, 2378 struct dsa_db db) 2379 { 2380 struct ksz_device *dev = ds->priv; 2381 2382 if (!dev->dev_ops->mdb_add) 2383 return -EOPNOTSUPP; 2384 2385 return dev->dev_ops->mdb_add(dev, port, mdb, db); 2386 } 2387 2388 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 2389 const struct switchdev_obj_port_mdb *mdb, 2390 struct dsa_db db) 2391 { 2392 struct ksz_device *dev = ds->priv; 2393 2394 if (!dev->dev_ops->mdb_del) 2395 return -EOPNOTSUPP; 2396 2397 return dev->dev_ops->mdb_del(dev, port, mdb, db); 2398 } 2399 2400 static int ksz_enable_port(struct dsa_switch *ds, int port, 2401 struct phy_device *phy) 2402 { 2403 struct ksz_device *dev = ds->priv; 2404 2405 if (!dsa_is_user_port(ds, port)) 2406 return 0; 2407 2408 /* setup slave port */ 2409 dev->dev_ops->port_setup(dev, port, false); 2410 2411 /* port_stp_state_set() will be called after to enable the port so 2412 * there is no need to do anything. 2413 */ 2414 2415 return 0; 2416 } 2417 2418 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 2419 { 2420 struct ksz_device *dev = ds->priv; 2421 struct ksz_port *p; 2422 const u16 *regs; 2423 u8 data; 2424 2425 regs = dev->info->regs; 2426 2427 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 2428 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2429 2430 p = &dev->ports[port]; 2431 2432 switch (state) { 2433 case BR_STATE_DISABLED: 2434 data |= PORT_LEARN_DISABLE; 2435 break; 2436 case BR_STATE_LISTENING: 2437 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 2438 break; 2439 case BR_STATE_LEARNING: 2440 data |= PORT_RX_ENABLE; 2441 if (!p->learning) 2442 data |= PORT_LEARN_DISABLE; 2443 break; 2444 case BR_STATE_FORWARDING: 2445 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 2446 if (!p->learning) 2447 data |= PORT_LEARN_DISABLE; 2448 break; 2449 case BR_STATE_BLOCKING: 2450 data |= PORT_LEARN_DISABLE; 2451 break; 2452 default: 2453 dev_err(ds->dev, "invalid STP state: %d\n", state); 2454 return; 2455 } 2456 2457 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 2458 2459 p->stp_state = state; 2460 2461 ksz_update_port_member(dev, port); 2462 } 2463 2464 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 2465 struct switchdev_brport_flags flags, 2466 struct netlink_ext_ack *extack) 2467 { 2468 if (flags.mask & ~BR_LEARNING) 2469 return -EINVAL; 2470 2471 return 0; 2472 } 2473 2474 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 2475 struct switchdev_brport_flags flags, 2476 struct netlink_ext_ack *extack) 2477 { 2478 struct ksz_device *dev = ds->priv; 2479 struct ksz_port *p = &dev->ports[port]; 2480 2481 if (flags.mask & BR_LEARNING) { 2482 p->learning = !!(flags.val & BR_LEARNING); 2483 2484 /* Make the change take effect immediately */ 2485 ksz_port_stp_state_set(ds, port, p->stp_state); 2486 } 2487 2488 return 0; 2489 } 2490 2491 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 2492 int port, 2493 enum dsa_tag_protocol mp) 2494 { 2495 struct ksz_device *dev = ds->priv; 2496 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 2497 2498 if (dev->chip_id == KSZ8795_CHIP_ID || 2499 dev->chip_id == KSZ8794_CHIP_ID || 2500 dev->chip_id == KSZ8765_CHIP_ID) 2501 proto = DSA_TAG_PROTO_KSZ8795; 2502 2503 if (dev->chip_id == KSZ8830_CHIP_ID || 2504 dev->chip_id == KSZ8563_CHIP_ID || 2505 dev->chip_id == KSZ9893_CHIP_ID || 2506 dev->chip_id == KSZ9563_CHIP_ID) 2507 proto = DSA_TAG_PROTO_KSZ9893; 2508 2509 if (dev->chip_id == KSZ9477_CHIP_ID || 2510 dev->chip_id == KSZ9896_CHIP_ID || 2511 dev->chip_id == KSZ9897_CHIP_ID || 2512 dev->chip_id == KSZ9567_CHIP_ID) 2513 proto = DSA_TAG_PROTO_KSZ9477; 2514 2515 if (is_lan937x(dev)) 2516 proto = DSA_TAG_PROTO_LAN937X_VALUE; 2517 2518 return proto; 2519 } 2520 2521 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 2522 bool flag, struct netlink_ext_ack *extack) 2523 { 2524 struct ksz_device *dev = ds->priv; 2525 2526 if (!dev->dev_ops->vlan_filtering) 2527 return -EOPNOTSUPP; 2528 2529 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 2530 } 2531 2532 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 2533 const struct switchdev_obj_port_vlan *vlan, 2534 struct netlink_ext_ack *extack) 2535 { 2536 struct ksz_device *dev = ds->priv; 2537 2538 if (!dev->dev_ops->vlan_add) 2539 return -EOPNOTSUPP; 2540 2541 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 2542 } 2543 2544 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 2545 const struct switchdev_obj_port_vlan *vlan) 2546 { 2547 struct ksz_device *dev = ds->priv; 2548 2549 if (!dev->dev_ops->vlan_del) 2550 return -EOPNOTSUPP; 2551 2552 return dev->dev_ops->vlan_del(dev, port, vlan); 2553 } 2554 2555 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 2556 struct dsa_mall_mirror_tc_entry *mirror, 2557 bool ingress, struct netlink_ext_ack *extack) 2558 { 2559 struct ksz_device *dev = ds->priv; 2560 2561 if (!dev->dev_ops->mirror_add) 2562 return -EOPNOTSUPP; 2563 2564 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 2565 } 2566 2567 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 2568 struct dsa_mall_mirror_tc_entry *mirror) 2569 { 2570 struct ksz_device *dev = ds->priv; 2571 2572 if (dev->dev_ops->mirror_del) 2573 dev->dev_ops->mirror_del(dev, port, mirror); 2574 } 2575 2576 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 2577 { 2578 struct ksz_device *dev = ds->priv; 2579 2580 if (!dev->dev_ops->change_mtu) 2581 return -EOPNOTSUPP; 2582 2583 return dev->dev_ops->change_mtu(dev, port, mtu); 2584 } 2585 2586 static int ksz_max_mtu(struct dsa_switch *ds, int port) 2587 { 2588 struct ksz_device *dev = ds->priv; 2589 2590 switch (dev->chip_id) { 2591 case KSZ8795_CHIP_ID: 2592 case KSZ8794_CHIP_ID: 2593 case KSZ8765_CHIP_ID: 2594 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2595 case KSZ8830_CHIP_ID: 2596 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2597 case KSZ8563_CHIP_ID: 2598 case KSZ9477_CHIP_ID: 2599 case KSZ9563_CHIP_ID: 2600 case KSZ9567_CHIP_ID: 2601 case KSZ9893_CHIP_ID: 2602 case KSZ9896_CHIP_ID: 2603 case KSZ9897_CHIP_ID: 2604 case LAN9370_CHIP_ID: 2605 case LAN9371_CHIP_ID: 2606 case LAN9372_CHIP_ID: 2607 case LAN9373_CHIP_ID: 2608 case LAN9374_CHIP_ID: 2609 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 2610 } 2611 2612 return -EOPNOTSUPP; 2613 } 2614 2615 static void ksz_set_xmii(struct ksz_device *dev, int port, 2616 phy_interface_t interface) 2617 { 2618 const u8 *bitval = dev->info->xmii_ctrl1; 2619 struct ksz_port *p = &dev->ports[port]; 2620 const u16 *regs = dev->info->regs; 2621 u8 data8; 2622 2623 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2624 2625 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 2626 P_RGMII_ID_EG_ENABLE); 2627 2628 switch (interface) { 2629 case PHY_INTERFACE_MODE_MII: 2630 data8 |= bitval[P_MII_SEL]; 2631 break; 2632 case PHY_INTERFACE_MODE_RMII: 2633 data8 |= bitval[P_RMII_SEL]; 2634 break; 2635 case PHY_INTERFACE_MODE_GMII: 2636 data8 |= bitval[P_GMII_SEL]; 2637 break; 2638 case PHY_INTERFACE_MODE_RGMII: 2639 case PHY_INTERFACE_MODE_RGMII_ID: 2640 case PHY_INTERFACE_MODE_RGMII_TXID: 2641 case PHY_INTERFACE_MODE_RGMII_RXID: 2642 data8 |= bitval[P_RGMII_SEL]; 2643 /* On KSZ9893, disable RGMII in-band status support */ 2644 if (dev->chip_id == KSZ9893_CHIP_ID || 2645 dev->chip_id == KSZ8563_CHIP_ID || 2646 dev->chip_id == KSZ9563_CHIP_ID) 2647 data8 &= ~P_MII_MAC_MODE; 2648 break; 2649 default: 2650 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 2651 phy_modes(interface), port); 2652 return; 2653 } 2654 2655 if (p->rgmii_tx_val) 2656 data8 |= P_RGMII_ID_EG_ENABLE; 2657 2658 if (p->rgmii_rx_val) 2659 data8 |= P_RGMII_ID_IG_ENABLE; 2660 2661 /* Write the updated value */ 2662 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 2663 } 2664 2665 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 2666 { 2667 const u8 *bitval = dev->info->xmii_ctrl1; 2668 const u16 *regs = dev->info->regs; 2669 phy_interface_t interface; 2670 u8 data8; 2671 u8 val; 2672 2673 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2674 2675 val = FIELD_GET(P_MII_SEL_M, data8); 2676 2677 if (val == bitval[P_MII_SEL]) { 2678 if (gbit) 2679 interface = PHY_INTERFACE_MODE_GMII; 2680 else 2681 interface = PHY_INTERFACE_MODE_MII; 2682 } else if (val == bitval[P_RMII_SEL]) { 2683 interface = PHY_INTERFACE_MODE_RGMII; 2684 } else { 2685 interface = PHY_INTERFACE_MODE_RGMII; 2686 if (data8 & P_RGMII_ID_EG_ENABLE) 2687 interface = PHY_INTERFACE_MODE_RGMII_TXID; 2688 if (data8 & P_RGMII_ID_IG_ENABLE) { 2689 interface = PHY_INTERFACE_MODE_RGMII_RXID; 2690 if (data8 & P_RGMII_ID_EG_ENABLE) 2691 interface = PHY_INTERFACE_MODE_RGMII_ID; 2692 } 2693 } 2694 2695 return interface; 2696 } 2697 2698 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port, 2699 unsigned int mode, 2700 const struct phylink_link_state *state) 2701 { 2702 struct ksz_device *dev = ds->priv; 2703 2704 if (ksz_is_ksz88x3(dev)) 2705 return; 2706 2707 /* Internal PHYs */ 2708 if (dev->info->internal_phy[port]) 2709 return; 2710 2711 if (phylink_autoneg_inband(mode)) { 2712 dev_err(dev->dev, "In-band AN not supported!\n"); 2713 return; 2714 } 2715 2716 ksz_set_xmii(dev, port, state->interface); 2717 2718 if (dev->dev_ops->phylink_mac_config) 2719 dev->dev_ops->phylink_mac_config(dev, port, mode, state); 2720 2721 if (dev->dev_ops->setup_rgmii_delay) 2722 dev->dev_ops->setup_rgmii_delay(dev, port); 2723 } 2724 2725 bool ksz_get_gbit(struct ksz_device *dev, int port) 2726 { 2727 const u8 *bitval = dev->info->xmii_ctrl1; 2728 const u16 *regs = dev->info->regs; 2729 bool gbit = false; 2730 u8 data8; 2731 bool val; 2732 2733 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2734 2735 val = FIELD_GET(P_GMII_1GBIT_M, data8); 2736 2737 if (val == bitval[P_GMII_1GBIT]) 2738 gbit = true; 2739 2740 return gbit; 2741 } 2742 2743 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) 2744 { 2745 const u8 *bitval = dev->info->xmii_ctrl1; 2746 const u16 *regs = dev->info->regs; 2747 u8 data8; 2748 2749 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 2750 2751 data8 &= ~P_GMII_1GBIT_M; 2752 2753 if (gbit) 2754 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 2755 else 2756 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 2757 2758 /* Write the updated value */ 2759 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 2760 } 2761 2762 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) 2763 { 2764 const u8 *bitval = dev->info->xmii_ctrl0; 2765 const u16 *regs = dev->info->regs; 2766 u8 data8; 2767 2768 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 2769 2770 data8 &= ~P_MII_100MBIT_M; 2771 2772 if (speed == SPEED_100) 2773 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 2774 else 2775 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 2776 2777 /* Write the updated value */ 2778 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 2779 } 2780 2781 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) 2782 { 2783 if (speed == SPEED_1000) 2784 ksz_set_gbit(dev, port, true); 2785 else 2786 ksz_set_gbit(dev, port, false); 2787 2788 if (speed == SPEED_100 || speed == SPEED_10) 2789 ksz_set_100_10mbit(dev, port, speed); 2790 } 2791 2792 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 2793 bool tx_pause, bool rx_pause) 2794 { 2795 const u8 *bitval = dev->info->xmii_ctrl0; 2796 const u32 *masks = dev->info->masks; 2797 const u16 *regs = dev->info->regs; 2798 u8 mask; 2799 u8 val; 2800 2801 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 2802 masks[P_MII_RX_FLOW_CTRL]; 2803 2804 if (duplex == DUPLEX_FULL) 2805 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 2806 else 2807 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 2808 2809 if (tx_pause) 2810 val |= masks[P_MII_TX_FLOW_CTRL]; 2811 2812 if (rx_pause) 2813 val |= masks[P_MII_RX_FLOW_CTRL]; 2814 2815 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 2816 } 2817 2818 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, 2819 unsigned int mode, 2820 phy_interface_t interface, 2821 struct phy_device *phydev, int speed, 2822 int duplex, bool tx_pause, 2823 bool rx_pause) 2824 { 2825 struct ksz_port *p; 2826 2827 p = &dev->ports[port]; 2828 2829 /* Internal PHYs */ 2830 if (dev->info->internal_phy[port]) 2831 return; 2832 2833 p->phydev.speed = speed; 2834 2835 ksz_port_set_xmii_speed(dev, port, speed); 2836 2837 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 2838 } 2839 2840 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port, 2841 unsigned int mode, 2842 phy_interface_t interface, 2843 struct phy_device *phydev, int speed, 2844 int duplex, bool tx_pause, bool rx_pause) 2845 { 2846 struct ksz_device *dev = ds->priv; 2847 2848 if (dev->dev_ops->phylink_mac_link_up) 2849 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface, 2850 phydev, speed, duplex, 2851 tx_pause, rx_pause); 2852 } 2853 2854 static int ksz_switch_detect(struct ksz_device *dev) 2855 { 2856 u8 id1, id2, id4; 2857 u16 id16; 2858 u32 id32; 2859 int ret; 2860 2861 /* read chip id */ 2862 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 2863 if (ret) 2864 return ret; 2865 2866 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 2867 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 2868 2869 switch (id1) { 2870 case KSZ87_FAMILY_ID: 2871 if (id2 == KSZ87_CHIP_ID_95) { 2872 u8 val; 2873 2874 dev->chip_id = KSZ8795_CHIP_ID; 2875 2876 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 2877 if (val & KSZ8_PORT_FIBER_MODE) 2878 dev->chip_id = KSZ8765_CHIP_ID; 2879 } else if (id2 == KSZ87_CHIP_ID_94) { 2880 dev->chip_id = KSZ8794_CHIP_ID; 2881 } else { 2882 return -ENODEV; 2883 } 2884 break; 2885 case KSZ88_FAMILY_ID: 2886 if (id2 == KSZ88_CHIP_ID_63) 2887 dev->chip_id = KSZ8830_CHIP_ID; 2888 else 2889 return -ENODEV; 2890 break; 2891 default: 2892 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 2893 if (ret) 2894 return ret; 2895 2896 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 2897 id32 &= ~0xFF; 2898 2899 switch (id32) { 2900 case KSZ9477_CHIP_ID: 2901 case KSZ9896_CHIP_ID: 2902 case KSZ9897_CHIP_ID: 2903 case KSZ9567_CHIP_ID: 2904 case LAN9370_CHIP_ID: 2905 case LAN9371_CHIP_ID: 2906 case LAN9372_CHIP_ID: 2907 case LAN9373_CHIP_ID: 2908 case LAN9374_CHIP_ID: 2909 dev->chip_id = id32; 2910 break; 2911 case KSZ9893_CHIP_ID: 2912 ret = ksz_read8(dev, REG_CHIP_ID4, 2913 &id4); 2914 if (ret) 2915 return ret; 2916 2917 if (id4 == SKU_ID_KSZ8563) 2918 dev->chip_id = KSZ8563_CHIP_ID; 2919 else if (id4 == SKU_ID_KSZ9563) 2920 dev->chip_id = KSZ9563_CHIP_ID; 2921 else 2922 dev->chip_id = KSZ9893_CHIP_ID; 2923 2924 break; 2925 default: 2926 dev_err(dev->dev, 2927 "unsupported switch detected %x)\n", id32); 2928 return -ENODEV; 2929 } 2930 } 2931 return 0; 2932 } 2933 2934 static const struct dsa_switch_ops ksz_switch_ops = { 2935 .get_tag_protocol = ksz_get_tag_protocol, 2936 .get_phy_flags = ksz_get_phy_flags, 2937 .setup = ksz_setup, 2938 .teardown = ksz_teardown, 2939 .phy_read = ksz_phy_read16, 2940 .phy_write = ksz_phy_write16, 2941 .phylink_get_caps = ksz_phylink_get_caps, 2942 .phylink_mac_config = ksz_phylink_mac_config, 2943 .phylink_mac_link_up = ksz_phylink_mac_link_up, 2944 .phylink_mac_link_down = ksz_mac_link_down, 2945 .port_enable = ksz_enable_port, 2946 .set_ageing_time = ksz_set_ageing_time, 2947 .get_strings = ksz_get_strings, 2948 .get_ethtool_stats = ksz_get_ethtool_stats, 2949 .get_sset_count = ksz_sset_count, 2950 .port_bridge_join = ksz_port_bridge_join, 2951 .port_bridge_leave = ksz_port_bridge_leave, 2952 .port_stp_state_set = ksz_port_stp_state_set, 2953 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 2954 .port_bridge_flags = ksz_port_bridge_flags, 2955 .port_fast_age = ksz_port_fast_age, 2956 .port_vlan_filtering = ksz_port_vlan_filtering, 2957 .port_vlan_add = ksz_port_vlan_add, 2958 .port_vlan_del = ksz_port_vlan_del, 2959 .port_fdb_dump = ksz_port_fdb_dump, 2960 .port_fdb_add = ksz_port_fdb_add, 2961 .port_fdb_del = ksz_port_fdb_del, 2962 .port_mdb_add = ksz_port_mdb_add, 2963 .port_mdb_del = ksz_port_mdb_del, 2964 .port_mirror_add = ksz_port_mirror_add, 2965 .port_mirror_del = ksz_port_mirror_del, 2966 .get_stats64 = ksz_get_stats64, 2967 .get_pause_stats = ksz_get_pause_stats, 2968 .port_change_mtu = ksz_change_mtu, 2969 .port_max_mtu = ksz_max_mtu, 2970 }; 2971 2972 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 2973 { 2974 struct dsa_switch *ds; 2975 struct ksz_device *swdev; 2976 2977 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 2978 if (!ds) 2979 return NULL; 2980 2981 ds->dev = base; 2982 ds->num_ports = DSA_MAX_PORTS; 2983 ds->ops = &ksz_switch_ops; 2984 2985 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 2986 if (!swdev) 2987 return NULL; 2988 2989 ds->priv = swdev; 2990 swdev->dev = base; 2991 2992 swdev->ds = ds; 2993 swdev->priv = priv; 2994 2995 return swdev; 2996 } 2997 EXPORT_SYMBOL(ksz_switch_alloc); 2998 2999 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 3000 struct device_node *port_dn) 3001 { 3002 phy_interface_t phy_mode = dev->ports[port_num].interface; 3003 int rx_delay = -1, tx_delay = -1; 3004 3005 if (!phy_interface_mode_is_rgmii(phy_mode)) 3006 return; 3007 3008 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 3009 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 3010 3011 if (rx_delay == -1 && tx_delay == -1) { 3012 dev_warn(dev->dev, 3013 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 3014 "please update device tree to specify \"rx-internal-delay-ps\" and " 3015 "\"tx-internal-delay-ps\"", 3016 port_num); 3017 3018 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 3019 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 3020 rx_delay = 2000; 3021 3022 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 3023 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 3024 tx_delay = 2000; 3025 } 3026 3027 if (rx_delay < 0) 3028 rx_delay = 0; 3029 if (tx_delay < 0) 3030 tx_delay = 0; 3031 3032 dev->ports[port_num].rgmii_rx_val = rx_delay; 3033 dev->ports[port_num].rgmii_tx_val = tx_delay; 3034 } 3035 3036 int ksz_switch_register(struct ksz_device *dev) 3037 { 3038 const struct ksz_chip_data *info; 3039 struct device_node *port, *ports; 3040 phy_interface_t interface; 3041 unsigned int port_num; 3042 int ret; 3043 int i; 3044 3045 if (dev->pdata) 3046 dev->chip_id = dev->pdata->chip_id; 3047 3048 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 3049 GPIOD_OUT_LOW); 3050 if (IS_ERR(dev->reset_gpio)) 3051 return PTR_ERR(dev->reset_gpio); 3052 3053 if (dev->reset_gpio) { 3054 gpiod_set_value_cansleep(dev->reset_gpio, 1); 3055 usleep_range(10000, 12000); 3056 gpiod_set_value_cansleep(dev->reset_gpio, 0); 3057 msleep(100); 3058 } 3059 3060 mutex_init(&dev->dev_mutex); 3061 mutex_init(&dev->regmap_mutex); 3062 mutex_init(&dev->alu_mutex); 3063 mutex_init(&dev->vlan_mutex); 3064 3065 ret = ksz_switch_detect(dev); 3066 if (ret) 3067 return ret; 3068 3069 info = ksz_lookup_info(dev->chip_id); 3070 if (!info) 3071 return -ENODEV; 3072 3073 /* Update the compatible info with the probed one */ 3074 dev->info = info; 3075 3076 dev_info(dev->dev, "found switch: %s, rev %i\n", 3077 dev->info->dev_name, dev->chip_rev); 3078 3079 ret = ksz_check_device_id(dev); 3080 if (ret) 3081 return ret; 3082 3083 dev->dev_ops = dev->info->ops; 3084 3085 ret = dev->dev_ops->init(dev); 3086 if (ret) 3087 return ret; 3088 3089 dev->ports = devm_kzalloc(dev->dev, 3090 dev->info->port_cnt * sizeof(struct ksz_port), 3091 GFP_KERNEL); 3092 if (!dev->ports) 3093 return -ENOMEM; 3094 3095 for (i = 0; i < dev->info->port_cnt; i++) { 3096 spin_lock_init(&dev->ports[i].mib.stats64_lock); 3097 mutex_init(&dev->ports[i].mib.cnt_mutex); 3098 dev->ports[i].mib.counters = 3099 devm_kzalloc(dev->dev, 3100 sizeof(u64) * (dev->info->mib_cnt + 1), 3101 GFP_KERNEL); 3102 if (!dev->ports[i].mib.counters) 3103 return -ENOMEM; 3104 3105 dev->ports[i].ksz_dev = dev; 3106 dev->ports[i].num = i; 3107 } 3108 3109 /* set the real number of ports */ 3110 dev->ds->num_ports = dev->info->port_cnt; 3111 3112 /* Host port interface will be self detected, or specifically set in 3113 * device tree. 3114 */ 3115 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 3116 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 3117 if (dev->dev->of_node) { 3118 ret = of_get_phy_mode(dev->dev->of_node, &interface); 3119 if (ret == 0) 3120 dev->compat_interface = interface; 3121 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 3122 if (!ports) 3123 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 3124 if (ports) { 3125 for_each_available_child_of_node(ports, port) { 3126 if (of_property_read_u32(port, "reg", 3127 &port_num)) 3128 continue; 3129 if (!(dev->port_mask & BIT(port_num))) { 3130 of_node_put(port); 3131 of_node_put(ports); 3132 return -EINVAL; 3133 } 3134 of_get_phy_mode(port, 3135 &dev->ports[port_num].interface); 3136 3137 ksz_parse_rgmii_delay(dev, port_num, port); 3138 } 3139 of_node_put(ports); 3140 } 3141 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 3142 "microchip,synclko-125"); 3143 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 3144 "microchip,synclko-disable"); 3145 if (dev->synclko_125 && dev->synclko_disable) { 3146 dev_err(dev->dev, "inconsistent synclko settings\n"); 3147 return -EINVAL; 3148 } 3149 } 3150 3151 ret = dsa_register_switch(dev->ds); 3152 if (ret) { 3153 dev->dev_ops->exit(dev); 3154 return ret; 3155 } 3156 3157 /* Read MIB counters every 30 seconds to avoid overflow. */ 3158 dev->mib_read_interval = msecs_to_jiffies(5000); 3159 3160 /* Start the MIB timer. */ 3161 schedule_delayed_work(&dev->mib_read, 0); 3162 3163 return ret; 3164 } 3165 EXPORT_SYMBOL(ksz_switch_register); 3166 3167 void ksz_switch_remove(struct ksz_device *dev) 3168 { 3169 /* timer started */ 3170 if (dev->mib_read_interval) { 3171 dev->mib_read_interval = 0; 3172 cancel_delayed_work_sync(&dev->mib_read); 3173 } 3174 3175 dev->dev_ops->exit(dev); 3176 dsa_unregister_switch(dev->ds); 3177 3178 if (dev->reset_gpio) 3179 gpiod_set_value_cansleep(dev->reset_gpio, 1); 3180 3181 } 3182 EXPORT_SYMBOL(ksz_switch_remove); 3183 3184 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 3185 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 3186 MODULE_LICENSE("GPL"); 3187