1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/export.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/platform_data/microchip-ksz.h> 14 #include <linux/phy.h> 15 #include <linux/etherdevice.h> 16 #include <linux/if_bridge.h> 17 #include <linux/of_device.h> 18 #include <linux/of_net.h> 19 #include <linux/micrel_phy.h> 20 #include <net/dsa.h> 21 #include <net/switchdev.h> 22 23 #include "ksz_common.h" 24 #include "ksz8.h" 25 #include "ksz9477.h" 26 #include "lan937x.h" 27 28 #define MIB_COUNTER_NUM 0x20 29 30 struct ksz_stats_raw { 31 u64 rx_hi; 32 u64 rx_undersize; 33 u64 rx_fragments; 34 u64 rx_oversize; 35 u64 rx_jabbers; 36 u64 rx_symbol_err; 37 u64 rx_crc_err; 38 u64 rx_align_err; 39 u64 rx_mac_ctrl; 40 u64 rx_pause; 41 u64 rx_bcast; 42 u64 rx_mcast; 43 u64 rx_ucast; 44 u64 rx_64_or_less; 45 u64 rx_65_127; 46 u64 rx_128_255; 47 u64 rx_256_511; 48 u64 rx_512_1023; 49 u64 rx_1024_1522; 50 u64 rx_1523_2000; 51 u64 rx_2001; 52 u64 tx_hi; 53 u64 tx_late_col; 54 u64 tx_pause; 55 u64 tx_bcast; 56 u64 tx_mcast; 57 u64 tx_ucast; 58 u64 tx_deferred; 59 u64 tx_total_col; 60 u64 tx_exc_col; 61 u64 tx_single_col; 62 u64 tx_mult_col; 63 u64 rx_total; 64 u64 tx_total; 65 u64 rx_discards; 66 u64 tx_discards; 67 }; 68 69 static const struct ksz_mib_names ksz88xx_mib_names[] = { 70 { 0x00, "rx" }, 71 { 0x01, "rx_hi" }, 72 { 0x02, "rx_undersize" }, 73 { 0x03, "rx_fragments" }, 74 { 0x04, "rx_oversize" }, 75 { 0x05, "rx_jabbers" }, 76 { 0x06, "rx_symbol_err" }, 77 { 0x07, "rx_crc_err" }, 78 { 0x08, "rx_align_err" }, 79 { 0x09, "rx_mac_ctrl" }, 80 { 0x0a, "rx_pause" }, 81 { 0x0b, "rx_bcast" }, 82 { 0x0c, "rx_mcast" }, 83 { 0x0d, "rx_ucast" }, 84 { 0x0e, "rx_64_or_less" }, 85 { 0x0f, "rx_65_127" }, 86 { 0x10, "rx_128_255" }, 87 { 0x11, "rx_256_511" }, 88 { 0x12, "rx_512_1023" }, 89 { 0x13, "rx_1024_1522" }, 90 { 0x14, "tx" }, 91 { 0x15, "tx_hi" }, 92 { 0x16, "tx_late_col" }, 93 { 0x17, "tx_pause" }, 94 { 0x18, "tx_bcast" }, 95 { 0x19, "tx_mcast" }, 96 { 0x1a, "tx_ucast" }, 97 { 0x1b, "tx_deferred" }, 98 { 0x1c, "tx_total_col" }, 99 { 0x1d, "tx_exc_col" }, 100 { 0x1e, "tx_single_col" }, 101 { 0x1f, "tx_mult_col" }, 102 { 0x100, "rx_discards" }, 103 { 0x101, "tx_discards" }, 104 }; 105 106 static const struct ksz_mib_names ksz9477_mib_names[] = { 107 { 0x00, "rx_hi" }, 108 { 0x01, "rx_undersize" }, 109 { 0x02, "rx_fragments" }, 110 { 0x03, "rx_oversize" }, 111 { 0x04, "rx_jabbers" }, 112 { 0x05, "rx_symbol_err" }, 113 { 0x06, "rx_crc_err" }, 114 { 0x07, "rx_align_err" }, 115 { 0x08, "rx_mac_ctrl" }, 116 { 0x09, "rx_pause" }, 117 { 0x0A, "rx_bcast" }, 118 { 0x0B, "rx_mcast" }, 119 { 0x0C, "rx_ucast" }, 120 { 0x0D, "rx_64_or_less" }, 121 { 0x0E, "rx_65_127" }, 122 { 0x0F, "rx_128_255" }, 123 { 0x10, "rx_256_511" }, 124 { 0x11, "rx_512_1023" }, 125 { 0x12, "rx_1024_1522" }, 126 { 0x13, "rx_1523_2000" }, 127 { 0x14, "rx_2001" }, 128 { 0x15, "tx_hi" }, 129 { 0x16, "tx_late_col" }, 130 { 0x17, "tx_pause" }, 131 { 0x18, "tx_bcast" }, 132 { 0x19, "tx_mcast" }, 133 { 0x1A, "tx_ucast" }, 134 { 0x1B, "tx_deferred" }, 135 { 0x1C, "tx_total_col" }, 136 { 0x1D, "tx_exc_col" }, 137 { 0x1E, "tx_single_col" }, 138 { 0x1F, "tx_mult_col" }, 139 { 0x80, "rx_total" }, 140 { 0x81, "tx_total" }, 141 { 0x82, "rx_discards" }, 142 { 0x83, "tx_discards" }, 143 }; 144 145 static const struct ksz_dev_ops ksz8_dev_ops = { 146 .setup = ksz8_setup, 147 .get_port_addr = ksz8_get_port_addr, 148 .cfg_port_member = ksz8_cfg_port_member, 149 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 150 .port_setup = ksz8_port_setup, 151 .r_phy = ksz8_r_phy, 152 .w_phy = ksz8_w_phy, 153 .r_mib_cnt = ksz8_r_mib_cnt, 154 .r_mib_pkt = ksz8_r_mib_pkt, 155 .freeze_mib = ksz8_freeze_mib, 156 .port_init_cnt = ksz8_port_init_cnt, 157 .fdb_dump = ksz8_fdb_dump, 158 .mdb_add = ksz8_mdb_add, 159 .mdb_del = ksz8_mdb_del, 160 .vlan_filtering = ksz8_port_vlan_filtering, 161 .vlan_add = ksz8_port_vlan_add, 162 .vlan_del = ksz8_port_vlan_del, 163 .mirror_add = ksz8_port_mirror_add, 164 .mirror_del = ksz8_port_mirror_del, 165 .get_caps = ksz8_get_caps, 166 .config_cpu_port = ksz8_config_cpu_port, 167 .enable_stp_addr = ksz8_enable_stp_addr, 168 .reset = ksz8_reset_switch, 169 .init = ksz8_switch_init, 170 .exit = ksz8_switch_exit, 171 }; 172 173 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, 174 unsigned int mode, 175 phy_interface_t interface, 176 struct phy_device *phydev, int speed, 177 int duplex, bool tx_pause, 178 bool rx_pause); 179 180 static const struct ksz_dev_ops ksz9477_dev_ops = { 181 .setup = ksz9477_setup, 182 .get_port_addr = ksz9477_get_port_addr, 183 .cfg_port_member = ksz9477_cfg_port_member, 184 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 185 .port_setup = ksz9477_port_setup, 186 .r_phy = ksz9477_r_phy, 187 .w_phy = ksz9477_w_phy, 188 .r_mib_cnt = ksz9477_r_mib_cnt, 189 .r_mib_pkt = ksz9477_r_mib_pkt, 190 .r_mib_stat64 = ksz_r_mib_stats64, 191 .freeze_mib = ksz9477_freeze_mib, 192 .port_init_cnt = ksz9477_port_init_cnt, 193 .vlan_filtering = ksz9477_port_vlan_filtering, 194 .vlan_add = ksz9477_port_vlan_add, 195 .vlan_del = ksz9477_port_vlan_del, 196 .mirror_add = ksz9477_port_mirror_add, 197 .mirror_del = ksz9477_port_mirror_del, 198 .get_caps = ksz9477_get_caps, 199 .fdb_dump = ksz9477_fdb_dump, 200 .fdb_add = ksz9477_fdb_add, 201 .fdb_del = ksz9477_fdb_del, 202 .mdb_add = ksz9477_mdb_add, 203 .mdb_del = ksz9477_mdb_del, 204 .change_mtu = ksz9477_change_mtu, 205 .max_mtu = ksz9477_max_mtu, 206 .phylink_mac_link_up = ksz9477_phylink_mac_link_up, 207 .config_cpu_port = ksz9477_config_cpu_port, 208 .enable_stp_addr = ksz9477_enable_stp_addr, 209 .reset = ksz9477_reset_switch, 210 .init = ksz9477_switch_init, 211 .exit = ksz9477_switch_exit, 212 }; 213 214 static const struct ksz_dev_ops lan937x_dev_ops = { 215 .setup = lan937x_setup, 216 .get_port_addr = ksz9477_get_port_addr, 217 .cfg_port_member = ksz9477_cfg_port_member, 218 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 219 .port_setup = lan937x_port_setup, 220 .r_phy = lan937x_r_phy, 221 .w_phy = lan937x_w_phy, 222 .r_mib_cnt = ksz9477_r_mib_cnt, 223 .r_mib_pkt = ksz9477_r_mib_pkt, 224 .r_mib_stat64 = ksz_r_mib_stats64, 225 .freeze_mib = ksz9477_freeze_mib, 226 .port_init_cnt = ksz9477_port_init_cnt, 227 .vlan_filtering = ksz9477_port_vlan_filtering, 228 .vlan_add = ksz9477_port_vlan_add, 229 .vlan_del = ksz9477_port_vlan_del, 230 .mirror_add = ksz9477_port_mirror_add, 231 .mirror_del = ksz9477_port_mirror_del, 232 .get_caps = lan937x_phylink_get_caps, 233 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 234 .fdb_dump = ksz9477_fdb_dump, 235 .fdb_add = ksz9477_fdb_add, 236 .fdb_del = ksz9477_fdb_del, 237 .mdb_add = ksz9477_mdb_add, 238 .mdb_del = ksz9477_mdb_del, 239 .change_mtu = lan937x_change_mtu, 240 .max_mtu = ksz9477_max_mtu, 241 .phylink_mac_link_up = ksz9477_phylink_mac_link_up, 242 .config_cpu_port = lan937x_config_cpu_port, 243 .enable_stp_addr = ksz9477_enable_stp_addr, 244 .reset = lan937x_reset_switch, 245 .init = lan937x_switch_init, 246 .exit = lan937x_switch_exit, 247 }; 248 249 static const u16 ksz8795_regs[] = { 250 [REG_IND_CTRL_0] = 0x6E, 251 [REG_IND_DATA_8] = 0x70, 252 [REG_IND_DATA_CHECK] = 0x72, 253 [REG_IND_DATA_HI] = 0x71, 254 [REG_IND_DATA_LO] = 0x75, 255 [REG_IND_MIB_CHECK] = 0x74, 256 [REG_IND_BYTE] = 0xA0, 257 [P_FORCE_CTRL] = 0x0C, 258 [P_LINK_STATUS] = 0x0E, 259 [P_LOCAL_CTRL] = 0x07, 260 [P_NEG_RESTART_CTRL] = 0x0D, 261 [P_REMOTE_STATUS] = 0x08, 262 [P_SPEED_STATUS] = 0x09, 263 [S_TAIL_TAG_CTRL] = 0x0C, 264 [P_STP_CTRL] = 0x02, 265 [S_START_CTRL] = 0x01, 266 [S_BROADCAST_CTRL] = 0x06, 267 [S_MULTICAST_CTRL] = 0x04, 268 [P_XMII_CTRL_0] = 0x06, 269 [P_XMII_CTRL_1] = 0x56, 270 }; 271 272 static const u32 ksz8795_masks[] = { 273 [PORT_802_1P_REMAPPING] = BIT(7), 274 [SW_TAIL_TAG_ENABLE] = BIT(1), 275 [MIB_COUNTER_OVERFLOW] = BIT(6), 276 [MIB_COUNTER_VALID] = BIT(5), 277 [VLAN_TABLE_FID] = GENMASK(6, 0), 278 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 279 [VLAN_TABLE_VALID] = BIT(12), 280 [STATIC_MAC_TABLE_VALID] = BIT(21), 281 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 282 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 283 [STATIC_MAC_TABLE_OVERRIDE] = BIT(26), 284 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(24, 20), 285 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 286 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(8), 287 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 288 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 289 [DYNAMIC_MAC_TABLE_FID] = GENMASK(26, 20), 290 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 291 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 292 [P_MII_TX_FLOW_CTRL] = BIT(5), 293 [P_MII_RX_FLOW_CTRL] = BIT(5), 294 }; 295 296 static const u8 ksz8795_xmii_ctrl0[] = { 297 [P_MII_100MBIT] = 0, 298 [P_MII_10MBIT] = 1, 299 [P_MII_FULL_DUPLEX] = 0, 300 [P_MII_HALF_DUPLEX] = 1, 301 }; 302 303 static const u8 ksz8795_xmii_ctrl1[] = { 304 [P_RGMII_SEL] = 3, 305 [P_GMII_SEL] = 2, 306 [P_RMII_SEL] = 1, 307 [P_MII_SEL] = 0, 308 [P_GMII_1GBIT] = 1, 309 [P_GMII_NOT_1GBIT] = 0, 310 }; 311 312 static const u8 ksz8795_shifts[] = { 313 [VLAN_TABLE_MEMBERSHIP_S] = 7, 314 [VLAN_TABLE] = 16, 315 [STATIC_MAC_FWD_PORTS] = 16, 316 [STATIC_MAC_FID] = 24, 317 [DYNAMIC_MAC_ENTRIES_H] = 3, 318 [DYNAMIC_MAC_ENTRIES] = 29, 319 [DYNAMIC_MAC_FID] = 16, 320 [DYNAMIC_MAC_TIMESTAMP] = 27, 321 [DYNAMIC_MAC_SRC_PORT] = 24, 322 }; 323 324 static const u16 ksz8863_regs[] = { 325 [REG_IND_CTRL_0] = 0x79, 326 [REG_IND_DATA_8] = 0x7B, 327 [REG_IND_DATA_CHECK] = 0x7B, 328 [REG_IND_DATA_HI] = 0x7C, 329 [REG_IND_DATA_LO] = 0x80, 330 [REG_IND_MIB_CHECK] = 0x80, 331 [P_FORCE_CTRL] = 0x0C, 332 [P_LINK_STATUS] = 0x0E, 333 [P_LOCAL_CTRL] = 0x0C, 334 [P_NEG_RESTART_CTRL] = 0x0D, 335 [P_REMOTE_STATUS] = 0x0E, 336 [P_SPEED_STATUS] = 0x0F, 337 [S_TAIL_TAG_CTRL] = 0x03, 338 [P_STP_CTRL] = 0x02, 339 [S_START_CTRL] = 0x01, 340 [S_BROADCAST_CTRL] = 0x06, 341 [S_MULTICAST_CTRL] = 0x04, 342 }; 343 344 static const u32 ksz8863_masks[] = { 345 [PORT_802_1P_REMAPPING] = BIT(3), 346 [SW_TAIL_TAG_ENABLE] = BIT(6), 347 [MIB_COUNTER_OVERFLOW] = BIT(7), 348 [MIB_COUNTER_VALID] = BIT(6), 349 [VLAN_TABLE_FID] = GENMASK(15, 12), 350 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 351 [VLAN_TABLE_VALID] = BIT(19), 352 [STATIC_MAC_TABLE_VALID] = BIT(19), 353 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 354 [STATIC_MAC_TABLE_FID] = GENMASK(29, 26), 355 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 356 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 357 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(5, 0), 358 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 359 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 360 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 28), 361 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 362 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 363 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 364 }; 365 366 static u8 ksz8863_shifts[] = { 367 [VLAN_TABLE_MEMBERSHIP_S] = 16, 368 [STATIC_MAC_FWD_PORTS] = 16, 369 [STATIC_MAC_FID] = 22, 370 [DYNAMIC_MAC_ENTRIES_H] = 3, 371 [DYNAMIC_MAC_ENTRIES] = 24, 372 [DYNAMIC_MAC_FID] = 16, 373 [DYNAMIC_MAC_TIMESTAMP] = 24, 374 [DYNAMIC_MAC_SRC_PORT] = 20, 375 }; 376 377 static const u16 ksz9477_regs[] = { 378 [P_STP_CTRL] = 0x0B04, 379 [S_START_CTRL] = 0x0300, 380 [S_BROADCAST_CTRL] = 0x0332, 381 [S_MULTICAST_CTRL] = 0x0331, 382 [P_XMII_CTRL_0] = 0x0300, 383 [P_XMII_CTRL_1] = 0x0301, 384 }; 385 386 static const u32 ksz9477_masks[] = { 387 [ALU_STAT_WRITE] = 0, 388 [ALU_STAT_READ] = 1, 389 [P_MII_TX_FLOW_CTRL] = BIT(5), 390 [P_MII_RX_FLOW_CTRL] = BIT(3), 391 }; 392 393 static const u8 ksz9477_shifts[] = { 394 [ALU_STAT_INDEX] = 16, 395 }; 396 397 static const u8 ksz9477_xmii_ctrl0[] = { 398 [P_MII_100MBIT] = 1, 399 [P_MII_10MBIT] = 0, 400 [P_MII_FULL_DUPLEX] = 1, 401 [P_MII_HALF_DUPLEX] = 0, 402 }; 403 404 static const u8 ksz9477_xmii_ctrl1[] = { 405 [P_RGMII_SEL] = 0, 406 [P_RMII_SEL] = 1, 407 [P_GMII_SEL] = 2, 408 [P_MII_SEL] = 3, 409 [P_GMII_1GBIT] = 0, 410 [P_GMII_NOT_1GBIT] = 1, 411 }; 412 413 static const u32 lan937x_masks[] = { 414 [ALU_STAT_WRITE] = 1, 415 [ALU_STAT_READ] = 2, 416 [P_MII_TX_FLOW_CTRL] = BIT(5), 417 [P_MII_RX_FLOW_CTRL] = BIT(3), 418 }; 419 420 static const u8 lan937x_shifts[] = { 421 [ALU_STAT_INDEX] = 8, 422 }; 423 424 const struct ksz_chip_data ksz_switch_chips[] = { 425 [KSZ8795] = { 426 .chip_id = KSZ8795_CHIP_ID, 427 .dev_name = "KSZ8795", 428 .num_vlans = 4096, 429 .num_alus = 0, 430 .num_statics = 8, 431 .cpu_ports = 0x10, /* can be configured as cpu port */ 432 .port_cnt = 5, /* total cpu and user ports */ 433 .ops = &ksz8_dev_ops, 434 .ksz87xx_eee_link_erratum = true, 435 .mib_names = ksz9477_mib_names, 436 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 437 .reg_mib_cnt = MIB_COUNTER_NUM, 438 .regs = ksz8795_regs, 439 .masks = ksz8795_masks, 440 .shifts = ksz8795_shifts, 441 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 442 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 443 .supports_mii = {false, false, false, false, true}, 444 .supports_rmii = {false, false, false, false, true}, 445 .supports_rgmii = {false, false, false, false, true}, 446 .internal_phy = {true, true, true, true, false}, 447 }, 448 449 [KSZ8794] = { 450 /* WARNING 451 * ======= 452 * KSZ8794 is similar to KSZ8795, except the port map 453 * contains a gap between external and CPU ports, the 454 * port map is NOT continuous. The per-port register 455 * map is shifted accordingly too, i.e. registers at 456 * offset 0x40 are NOT used on KSZ8794 and they ARE 457 * used on KSZ8795 for external port 3. 458 * external cpu 459 * KSZ8794 0,1,2 4 460 * KSZ8795 0,1,2,3 4 461 * KSZ8765 0,1,2,3 4 462 * port_cnt is configured as 5, even though it is 4 463 */ 464 .chip_id = KSZ8794_CHIP_ID, 465 .dev_name = "KSZ8794", 466 .num_vlans = 4096, 467 .num_alus = 0, 468 .num_statics = 8, 469 .cpu_ports = 0x10, /* can be configured as cpu port */ 470 .port_cnt = 5, /* total cpu and user ports */ 471 .ops = &ksz8_dev_ops, 472 .ksz87xx_eee_link_erratum = true, 473 .mib_names = ksz9477_mib_names, 474 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 475 .reg_mib_cnt = MIB_COUNTER_NUM, 476 .regs = ksz8795_regs, 477 .masks = ksz8795_masks, 478 .shifts = ksz8795_shifts, 479 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 480 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 481 .supports_mii = {false, false, false, false, true}, 482 .supports_rmii = {false, false, false, false, true}, 483 .supports_rgmii = {false, false, false, false, true}, 484 .internal_phy = {true, true, true, false, false}, 485 }, 486 487 [KSZ8765] = { 488 .chip_id = KSZ8765_CHIP_ID, 489 .dev_name = "KSZ8765", 490 .num_vlans = 4096, 491 .num_alus = 0, 492 .num_statics = 8, 493 .cpu_ports = 0x10, /* can be configured as cpu port */ 494 .port_cnt = 5, /* total cpu and user ports */ 495 .ops = &ksz8_dev_ops, 496 .ksz87xx_eee_link_erratum = true, 497 .mib_names = ksz9477_mib_names, 498 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 499 .reg_mib_cnt = MIB_COUNTER_NUM, 500 .regs = ksz8795_regs, 501 .masks = ksz8795_masks, 502 .shifts = ksz8795_shifts, 503 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 504 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 505 .supports_mii = {false, false, false, false, true}, 506 .supports_rmii = {false, false, false, false, true}, 507 .supports_rgmii = {false, false, false, false, true}, 508 .internal_phy = {true, true, true, true, false}, 509 }, 510 511 [KSZ8830] = { 512 .chip_id = KSZ8830_CHIP_ID, 513 .dev_name = "KSZ8863/KSZ8873", 514 .num_vlans = 16, 515 .num_alus = 0, 516 .num_statics = 8, 517 .cpu_ports = 0x4, /* can be configured as cpu port */ 518 .port_cnt = 3, 519 .ops = &ksz8_dev_ops, 520 .mib_names = ksz88xx_mib_names, 521 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 522 .reg_mib_cnt = MIB_COUNTER_NUM, 523 .regs = ksz8863_regs, 524 .masks = ksz8863_masks, 525 .shifts = ksz8863_shifts, 526 .supports_mii = {false, false, true}, 527 .supports_rmii = {false, false, true}, 528 .internal_phy = {true, true, false}, 529 }, 530 531 [KSZ9477] = { 532 .chip_id = KSZ9477_CHIP_ID, 533 .dev_name = "KSZ9477", 534 .num_vlans = 4096, 535 .num_alus = 4096, 536 .num_statics = 16, 537 .cpu_ports = 0x7F, /* can be configured as cpu port */ 538 .port_cnt = 7, /* total physical port count */ 539 .ops = &ksz9477_dev_ops, 540 .phy_errata_9477 = true, 541 .mib_names = ksz9477_mib_names, 542 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 543 .reg_mib_cnt = MIB_COUNTER_NUM, 544 .regs = ksz9477_regs, 545 .masks = ksz9477_masks, 546 .shifts = ksz9477_shifts, 547 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 548 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 549 .supports_mii = {false, false, false, false, 550 false, true, false}, 551 .supports_rmii = {false, false, false, false, 552 false, true, false}, 553 .supports_rgmii = {false, false, false, false, 554 false, true, false}, 555 .internal_phy = {true, true, true, true, 556 true, false, false}, 557 }, 558 559 [KSZ9897] = { 560 .chip_id = KSZ9897_CHIP_ID, 561 .dev_name = "KSZ9897", 562 .num_vlans = 4096, 563 .num_alus = 4096, 564 .num_statics = 16, 565 .cpu_ports = 0x7F, /* can be configured as cpu port */ 566 .port_cnt = 7, /* total physical port count */ 567 .ops = &ksz9477_dev_ops, 568 .phy_errata_9477 = true, 569 .mib_names = ksz9477_mib_names, 570 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 571 .reg_mib_cnt = MIB_COUNTER_NUM, 572 .regs = ksz9477_regs, 573 .masks = ksz9477_masks, 574 .shifts = ksz9477_shifts, 575 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 576 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 577 .supports_mii = {false, false, false, false, 578 false, true, true}, 579 .supports_rmii = {false, false, false, false, 580 false, true, true}, 581 .supports_rgmii = {false, false, false, false, 582 false, true, true}, 583 .internal_phy = {true, true, true, true, 584 true, false, false}, 585 }, 586 587 [KSZ9893] = { 588 .chip_id = KSZ9893_CHIP_ID, 589 .dev_name = "KSZ9893", 590 .num_vlans = 4096, 591 .num_alus = 4096, 592 .num_statics = 16, 593 .cpu_ports = 0x07, /* can be configured as cpu port */ 594 .port_cnt = 3, /* total port count */ 595 .ops = &ksz9477_dev_ops, 596 .mib_names = ksz9477_mib_names, 597 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 598 .reg_mib_cnt = MIB_COUNTER_NUM, 599 .regs = ksz9477_regs, 600 .masks = ksz9477_masks, 601 .shifts = ksz9477_shifts, 602 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 603 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 604 .supports_mii = {false, false, true}, 605 .supports_rmii = {false, false, true}, 606 .supports_rgmii = {false, false, true}, 607 .internal_phy = {true, true, false}, 608 }, 609 610 [KSZ9567] = { 611 .chip_id = KSZ9567_CHIP_ID, 612 .dev_name = "KSZ9567", 613 .num_vlans = 4096, 614 .num_alus = 4096, 615 .num_statics = 16, 616 .cpu_ports = 0x7F, /* can be configured as cpu port */ 617 .port_cnt = 7, /* total physical port count */ 618 .ops = &ksz9477_dev_ops, 619 .phy_errata_9477 = true, 620 .mib_names = ksz9477_mib_names, 621 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 622 .reg_mib_cnt = MIB_COUNTER_NUM, 623 .regs = ksz9477_regs, 624 .masks = ksz9477_masks, 625 .shifts = ksz9477_shifts, 626 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 627 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 628 .supports_mii = {false, false, false, false, 629 false, true, true}, 630 .supports_rmii = {false, false, false, false, 631 false, true, true}, 632 .supports_rgmii = {false, false, false, false, 633 false, true, true}, 634 .internal_phy = {true, true, true, true, 635 true, false, false}, 636 }, 637 638 [LAN9370] = { 639 .chip_id = LAN9370_CHIP_ID, 640 .dev_name = "LAN9370", 641 .num_vlans = 4096, 642 .num_alus = 1024, 643 .num_statics = 256, 644 .cpu_ports = 0x10, /* can be configured as cpu port */ 645 .port_cnt = 5, /* total physical port count */ 646 .ops = &lan937x_dev_ops, 647 .mib_names = ksz9477_mib_names, 648 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 649 .reg_mib_cnt = MIB_COUNTER_NUM, 650 .regs = ksz9477_regs, 651 .masks = lan937x_masks, 652 .shifts = lan937x_shifts, 653 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 654 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 655 .supports_mii = {false, false, false, false, true}, 656 .supports_rmii = {false, false, false, false, true}, 657 .supports_rgmii = {false, false, false, false, true}, 658 .internal_phy = {true, true, true, true, false}, 659 }, 660 661 [LAN9371] = { 662 .chip_id = LAN9371_CHIP_ID, 663 .dev_name = "LAN9371", 664 .num_vlans = 4096, 665 .num_alus = 1024, 666 .num_statics = 256, 667 .cpu_ports = 0x30, /* can be configured as cpu port */ 668 .port_cnt = 6, /* total physical port count */ 669 .ops = &lan937x_dev_ops, 670 .mib_names = ksz9477_mib_names, 671 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 672 .reg_mib_cnt = MIB_COUNTER_NUM, 673 .regs = ksz9477_regs, 674 .masks = lan937x_masks, 675 .shifts = lan937x_shifts, 676 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 677 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 678 .supports_mii = {false, false, false, false, true, true}, 679 .supports_rmii = {false, false, false, false, true, true}, 680 .supports_rgmii = {false, false, false, false, true, true}, 681 .internal_phy = {true, true, true, true, false, false}, 682 }, 683 684 [LAN9372] = { 685 .chip_id = LAN9372_CHIP_ID, 686 .dev_name = "LAN9372", 687 .num_vlans = 4096, 688 .num_alus = 1024, 689 .num_statics = 256, 690 .cpu_ports = 0x30, /* can be configured as cpu port */ 691 .port_cnt = 8, /* total physical port count */ 692 .ops = &lan937x_dev_ops, 693 .mib_names = ksz9477_mib_names, 694 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 695 .reg_mib_cnt = MIB_COUNTER_NUM, 696 .regs = ksz9477_regs, 697 .masks = lan937x_masks, 698 .shifts = lan937x_shifts, 699 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 700 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 701 .supports_mii = {false, false, false, false, 702 true, true, false, false}, 703 .supports_rmii = {false, false, false, false, 704 true, true, false, false}, 705 .supports_rgmii = {false, false, false, false, 706 true, true, false, false}, 707 .internal_phy = {true, true, true, true, 708 false, false, true, true}, 709 }, 710 711 [LAN9373] = { 712 .chip_id = LAN9373_CHIP_ID, 713 .dev_name = "LAN9373", 714 .num_vlans = 4096, 715 .num_alus = 1024, 716 .num_statics = 256, 717 .cpu_ports = 0x38, /* can be configured as cpu port */ 718 .port_cnt = 5, /* total physical port count */ 719 .ops = &lan937x_dev_ops, 720 .mib_names = ksz9477_mib_names, 721 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 722 .reg_mib_cnt = MIB_COUNTER_NUM, 723 .regs = ksz9477_regs, 724 .masks = lan937x_masks, 725 .shifts = lan937x_shifts, 726 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 727 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 728 .supports_mii = {false, false, false, false, 729 true, true, false, false}, 730 .supports_rmii = {false, false, false, false, 731 true, true, false, false}, 732 .supports_rgmii = {false, false, false, false, 733 true, true, false, false}, 734 .internal_phy = {true, true, true, false, 735 false, false, true, true}, 736 }, 737 738 [LAN9374] = { 739 .chip_id = LAN9374_CHIP_ID, 740 .dev_name = "LAN9374", 741 .num_vlans = 4096, 742 .num_alus = 1024, 743 .num_statics = 256, 744 .cpu_ports = 0x30, /* can be configured as cpu port */ 745 .port_cnt = 8, /* total physical port count */ 746 .ops = &lan937x_dev_ops, 747 .mib_names = ksz9477_mib_names, 748 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 749 .reg_mib_cnt = MIB_COUNTER_NUM, 750 .regs = ksz9477_regs, 751 .masks = lan937x_masks, 752 .shifts = lan937x_shifts, 753 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 754 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 755 .supports_mii = {false, false, false, false, 756 true, true, false, false}, 757 .supports_rmii = {false, false, false, false, 758 true, true, false, false}, 759 .supports_rgmii = {false, false, false, false, 760 true, true, false, false}, 761 .internal_phy = {true, true, true, true, 762 false, false, true, true}, 763 }, 764 }; 765 EXPORT_SYMBOL_GPL(ksz_switch_chips); 766 767 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 768 { 769 int i; 770 771 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 772 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 773 774 if (chip->chip_id == prod_num) 775 return chip; 776 } 777 778 return NULL; 779 } 780 781 static int ksz_check_device_id(struct ksz_device *dev) 782 { 783 const struct ksz_chip_data *dt_chip_data; 784 785 dt_chip_data = of_device_get_match_data(dev->dev); 786 787 /* Check for Device Tree and Chip ID */ 788 if (dt_chip_data->chip_id != dev->chip_id) { 789 dev_err(dev->dev, 790 "Device tree specifies chip %s but found %s, please fix it!\n", 791 dt_chip_data->dev_name, dev->info->dev_name); 792 return -ENODEV; 793 } 794 795 return 0; 796 } 797 798 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 799 struct phylink_config *config) 800 { 801 struct ksz_device *dev = ds->priv; 802 803 config->legacy_pre_march2020 = false; 804 805 if (dev->info->supports_mii[port]) 806 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 807 808 if (dev->info->supports_rmii[port]) 809 __set_bit(PHY_INTERFACE_MODE_RMII, 810 config->supported_interfaces); 811 812 if (dev->info->supports_rgmii[port]) 813 phy_interface_set_rgmii(config->supported_interfaces); 814 815 if (dev->info->internal_phy[port]) { 816 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 817 config->supported_interfaces); 818 /* Compatibility for phylib's default interface type when the 819 * phy-mode property is absent 820 */ 821 __set_bit(PHY_INTERFACE_MODE_GMII, 822 config->supported_interfaces); 823 } 824 825 if (dev->dev_ops->get_caps) 826 dev->dev_ops->get_caps(dev, port, config); 827 } 828 829 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 830 { 831 struct ethtool_pause_stats *pstats; 832 struct rtnl_link_stats64 *stats; 833 struct ksz_stats_raw *raw; 834 struct ksz_port_mib *mib; 835 836 mib = &dev->ports[port].mib; 837 stats = &mib->stats64; 838 pstats = &mib->pause_stats; 839 raw = (struct ksz_stats_raw *)mib->counters; 840 841 spin_lock(&mib->stats64_lock); 842 843 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 844 raw->rx_pause; 845 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 846 raw->tx_pause; 847 848 /* HW counters are counting bytes + FCS which is not acceptable 849 * for rtnl_link_stats64 interface 850 */ 851 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 852 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 853 854 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 855 raw->rx_oversize; 856 857 stats->rx_crc_errors = raw->rx_crc_err; 858 stats->rx_frame_errors = raw->rx_align_err; 859 stats->rx_dropped = raw->rx_discards; 860 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 861 stats->rx_frame_errors + stats->rx_dropped; 862 863 stats->tx_window_errors = raw->tx_late_col; 864 stats->tx_fifo_errors = raw->tx_discards; 865 stats->tx_aborted_errors = raw->tx_exc_col; 866 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 867 stats->tx_aborted_errors; 868 869 stats->multicast = raw->rx_mcast; 870 stats->collisions = raw->tx_total_col; 871 872 pstats->tx_pause_frames = raw->tx_pause; 873 pstats->rx_pause_frames = raw->rx_pause; 874 875 spin_unlock(&mib->stats64_lock); 876 } 877 878 static void ksz_get_stats64(struct dsa_switch *ds, int port, 879 struct rtnl_link_stats64 *s) 880 { 881 struct ksz_device *dev = ds->priv; 882 struct ksz_port_mib *mib; 883 884 mib = &dev->ports[port].mib; 885 886 spin_lock(&mib->stats64_lock); 887 memcpy(s, &mib->stats64, sizeof(*s)); 888 spin_unlock(&mib->stats64_lock); 889 } 890 891 static void ksz_get_pause_stats(struct dsa_switch *ds, int port, 892 struct ethtool_pause_stats *pause_stats) 893 { 894 struct ksz_device *dev = ds->priv; 895 struct ksz_port_mib *mib; 896 897 mib = &dev->ports[port].mib; 898 899 spin_lock(&mib->stats64_lock); 900 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 901 spin_unlock(&mib->stats64_lock); 902 } 903 904 static void ksz_get_strings(struct dsa_switch *ds, int port, 905 u32 stringset, uint8_t *buf) 906 { 907 struct ksz_device *dev = ds->priv; 908 int i; 909 910 if (stringset != ETH_SS_STATS) 911 return; 912 913 for (i = 0; i < dev->info->mib_cnt; i++) { 914 memcpy(buf + i * ETH_GSTRING_LEN, 915 dev->info->mib_names[i].string, ETH_GSTRING_LEN); 916 } 917 } 918 919 static void ksz_update_port_member(struct ksz_device *dev, int port) 920 { 921 struct ksz_port *p = &dev->ports[port]; 922 struct dsa_switch *ds = dev->ds; 923 u8 port_member = 0, cpu_port; 924 const struct dsa_port *dp; 925 int i, j; 926 927 if (!dsa_is_user_port(ds, port)) 928 return; 929 930 dp = dsa_to_port(ds, port); 931 cpu_port = BIT(dsa_upstream_port(ds, port)); 932 933 for (i = 0; i < ds->num_ports; i++) { 934 const struct dsa_port *other_dp = dsa_to_port(ds, i); 935 struct ksz_port *other_p = &dev->ports[i]; 936 u8 val = 0; 937 938 if (!dsa_is_user_port(ds, i)) 939 continue; 940 if (port == i) 941 continue; 942 if (!dsa_port_bridge_same(dp, other_dp)) 943 continue; 944 if (other_p->stp_state != BR_STATE_FORWARDING) 945 continue; 946 947 if (p->stp_state == BR_STATE_FORWARDING) { 948 val |= BIT(port); 949 port_member |= BIT(i); 950 } 951 952 /* Retain port [i]'s relationship to other ports than [port] */ 953 for (j = 0; j < ds->num_ports; j++) { 954 const struct dsa_port *third_dp; 955 struct ksz_port *third_p; 956 957 if (j == i) 958 continue; 959 if (j == port) 960 continue; 961 if (!dsa_is_user_port(ds, j)) 962 continue; 963 third_p = &dev->ports[j]; 964 if (third_p->stp_state != BR_STATE_FORWARDING) 965 continue; 966 third_dp = dsa_to_port(ds, j); 967 if (dsa_port_bridge_same(other_dp, third_dp)) 968 val |= BIT(j); 969 } 970 971 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 972 } 973 974 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 975 } 976 977 static int ksz_setup(struct dsa_switch *ds) 978 { 979 struct ksz_device *dev = ds->priv; 980 struct ksz_port *p; 981 const u16 *regs; 982 int ret; 983 984 regs = dev->info->regs; 985 986 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 987 dev->info->num_vlans, GFP_KERNEL); 988 if (!dev->vlan_cache) 989 return -ENOMEM; 990 991 ret = dev->dev_ops->reset(dev); 992 if (ret) { 993 dev_err(ds->dev, "failed to reset switch\n"); 994 return ret; 995 } 996 997 /* set broadcast storm protection 10% rate */ 998 regmap_update_bits(dev->regmap[1], regs[S_BROADCAST_CTRL], 999 BROADCAST_STORM_RATE, 1000 (BROADCAST_STORM_VALUE * 1001 BROADCAST_STORM_PROT_RATE) / 100); 1002 1003 dev->dev_ops->config_cpu_port(ds); 1004 1005 dev->dev_ops->enable_stp_addr(dev); 1006 1007 regmap_update_bits(dev->regmap[0], regs[S_MULTICAST_CTRL], 1008 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 1009 1010 ksz_init_mib_timer(dev); 1011 1012 ds->configure_vlan_while_not_filtering = false; 1013 1014 if (dev->dev_ops->setup) { 1015 ret = dev->dev_ops->setup(ds); 1016 if (ret) 1017 return ret; 1018 } 1019 1020 /* Start with learning disabled on standalone user ports, and enabled 1021 * on the CPU port. In lack of other finer mechanisms, learning on the 1022 * CPU port will avoid flooding bridge local addresses on the network 1023 * in some cases. 1024 */ 1025 p = &dev->ports[dev->cpu_port]; 1026 p->learning = true; 1027 1028 /* start switch */ 1029 regmap_update_bits(dev->regmap[0], regs[S_START_CTRL], 1030 SW_START, SW_START); 1031 1032 return 0; 1033 } 1034 1035 static void port_r_cnt(struct ksz_device *dev, int port) 1036 { 1037 struct ksz_port_mib *mib = &dev->ports[port].mib; 1038 u64 *dropped; 1039 1040 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 1041 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 1042 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 1043 &mib->counters[mib->cnt_ptr]); 1044 ++mib->cnt_ptr; 1045 } 1046 1047 /* last one in storage */ 1048 dropped = &mib->counters[dev->info->mib_cnt]; 1049 1050 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 1051 while (mib->cnt_ptr < dev->info->mib_cnt) { 1052 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 1053 dropped, &mib->counters[mib->cnt_ptr]); 1054 ++mib->cnt_ptr; 1055 } 1056 mib->cnt_ptr = 0; 1057 } 1058 1059 static void ksz_mib_read_work(struct work_struct *work) 1060 { 1061 struct ksz_device *dev = container_of(work, struct ksz_device, 1062 mib_read.work); 1063 struct ksz_port_mib *mib; 1064 struct ksz_port *p; 1065 int i; 1066 1067 for (i = 0; i < dev->info->port_cnt; i++) { 1068 if (dsa_is_unused_port(dev->ds, i)) 1069 continue; 1070 1071 p = &dev->ports[i]; 1072 mib = &p->mib; 1073 mutex_lock(&mib->cnt_mutex); 1074 1075 /* Only read MIB counters when the port is told to do. 1076 * If not, read only dropped counters when link is not up. 1077 */ 1078 if (!p->read) { 1079 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 1080 1081 if (!netif_carrier_ok(dp->slave)) 1082 mib->cnt_ptr = dev->info->reg_mib_cnt; 1083 } 1084 port_r_cnt(dev, i); 1085 p->read = false; 1086 1087 if (dev->dev_ops->r_mib_stat64) 1088 dev->dev_ops->r_mib_stat64(dev, i); 1089 1090 mutex_unlock(&mib->cnt_mutex); 1091 } 1092 1093 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 1094 } 1095 1096 void ksz_init_mib_timer(struct ksz_device *dev) 1097 { 1098 int i; 1099 1100 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 1101 1102 for (i = 0; i < dev->info->port_cnt; i++) { 1103 struct ksz_port_mib *mib = &dev->ports[i].mib; 1104 1105 dev->dev_ops->port_init_cnt(dev, i); 1106 1107 mib->cnt_ptr = 0; 1108 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 1109 } 1110 } 1111 1112 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 1113 { 1114 struct ksz_device *dev = ds->priv; 1115 u16 val = 0xffff; 1116 1117 dev->dev_ops->r_phy(dev, addr, reg, &val); 1118 1119 return val; 1120 } 1121 1122 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 1123 { 1124 struct ksz_device *dev = ds->priv; 1125 1126 dev->dev_ops->w_phy(dev, addr, reg, val); 1127 1128 return 0; 1129 } 1130 1131 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 1132 { 1133 struct ksz_device *dev = ds->priv; 1134 1135 if (dev->chip_id == KSZ8830_CHIP_ID) { 1136 /* Silicon Errata Sheet (DS80000830A): 1137 * Port 1 does not work with LinkMD Cable-Testing. 1138 * Port 1 does not respond to received PAUSE control frames. 1139 */ 1140 if (!port) 1141 return MICREL_KSZ8_P1_ERRATA; 1142 } 1143 1144 return 0; 1145 } 1146 1147 static void ksz_mac_link_down(struct dsa_switch *ds, int port, 1148 unsigned int mode, phy_interface_t interface) 1149 { 1150 struct ksz_device *dev = ds->priv; 1151 struct ksz_port *p = &dev->ports[port]; 1152 1153 /* Read all MIB counters when the link is going down. */ 1154 p->read = true; 1155 /* timer started */ 1156 if (dev->mib_read_interval) 1157 schedule_delayed_work(&dev->mib_read, 0); 1158 } 1159 1160 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 1161 { 1162 struct ksz_device *dev = ds->priv; 1163 1164 if (sset != ETH_SS_STATS) 1165 return 0; 1166 1167 return dev->info->mib_cnt; 1168 } 1169 1170 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 1171 uint64_t *buf) 1172 { 1173 const struct dsa_port *dp = dsa_to_port(ds, port); 1174 struct ksz_device *dev = ds->priv; 1175 struct ksz_port_mib *mib; 1176 1177 mib = &dev->ports[port].mib; 1178 mutex_lock(&mib->cnt_mutex); 1179 1180 /* Only read dropped counters if no link. */ 1181 if (!netif_carrier_ok(dp->slave)) 1182 mib->cnt_ptr = dev->info->reg_mib_cnt; 1183 port_r_cnt(dev, port); 1184 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 1185 mutex_unlock(&mib->cnt_mutex); 1186 } 1187 1188 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 1189 struct dsa_bridge bridge, 1190 bool *tx_fwd_offload, 1191 struct netlink_ext_ack *extack) 1192 { 1193 /* port_stp_state_set() will be called after to put the port in 1194 * appropriate state so there is no need to do anything. 1195 */ 1196 1197 return 0; 1198 } 1199 1200 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 1201 struct dsa_bridge bridge) 1202 { 1203 /* port_stp_state_set() will be called after to put the port in 1204 * forwarding state so there is no need to do anything. 1205 */ 1206 } 1207 1208 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 1209 { 1210 struct ksz_device *dev = ds->priv; 1211 1212 dev->dev_ops->flush_dyn_mac_table(dev, port); 1213 } 1214 1215 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 1216 const unsigned char *addr, u16 vid, 1217 struct dsa_db db) 1218 { 1219 struct ksz_device *dev = ds->priv; 1220 1221 if (!dev->dev_ops->fdb_add) 1222 return -EOPNOTSUPP; 1223 1224 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 1225 } 1226 1227 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 1228 const unsigned char *addr, 1229 u16 vid, struct dsa_db db) 1230 { 1231 struct ksz_device *dev = ds->priv; 1232 1233 if (!dev->dev_ops->fdb_del) 1234 return -EOPNOTSUPP; 1235 1236 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 1237 } 1238 1239 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 1240 dsa_fdb_dump_cb_t *cb, void *data) 1241 { 1242 struct ksz_device *dev = ds->priv; 1243 1244 if (!dev->dev_ops->fdb_dump) 1245 return -EOPNOTSUPP; 1246 1247 return dev->dev_ops->fdb_dump(dev, port, cb, data); 1248 } 1249 1250 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 1251 const struct switchdev_obj_port_mdb *mdb, 1252 struct dsa_db db) 1253 { 1254 struct ksz_device *dev = ds->priv; 1255 1256 if (!dev->dev_ops->mdb_add) 1257 return -EOPNOTSUPP; 1258 1259 return dev->dev_ops->mdb_add(dev, port, mdb, db); 1260 } 1261 1262 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 1263 const struct switchdev_obj_port_mdb *mdb, 1264 struct dsa_db db) 1265 { 1266 struct ksz_device *dev = ds->priv; 1267 1268 if (!dev->dev_ops->mdb_del) 1269 return -EOPNOTSUPP; 1270 1271 return dev->dev_ops->mdb_del(dev, port, mdb, db); 1272 } 1273 1274 static int ksz_enable_port(struct dsa_switch *ds, int port, 1275 struct phy_device *phy) 1276 { 1277 struct ksz_device *dev = ds->priv; 1278 1279 if (!dsa_is_user_port(ds, port)) 1280 return 0; 1281 1282 /* setup slave port */ 1283 dev->dev_ops->port_setup(dev, port, false); 1284 1285 /* port_stp_state_set() will be called after to enable the port so 1286 * there is no need to do anything. 1287 */ 1288 1289 return 0; 1290 } 1291 1292 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1293 { 1294 struct ksz_device *dev = ds->priv; 1295 struct ksz_port *p; 1296 const u16 *regs; 1297 u8 data; 1298 1299 regs = dev->info->regs; 1300 1301 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 1302 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 1303 1304 p = &dev->ports[port]; 1305 1306 switch (state) { 1307 case BR_STATE_DISABLED: 1308 data |= PORT_LEARN_DISABLE; 1309 break; 1310 case BR_STATE_LISTENING: 1311 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 1312 break; 1313 case BR_STATE_LEARNING: 1314 data |= PORT_RX_ENABLE; 1315 if (!p->learning) 1316 data |= PORT_LEARN_DISABLE; 1317 break; 1318 case BR_STATE_FORWARDING: 1319 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 1320 if (!p->learning) 1321 data |= PORT_LEARN_DISABLE; 1322 break; 1323 case BR_STATE_BLOCKING: 1324 data |= PORT_LEARN_DISABLE; 1325 break; 1326 default: 1327 dev_err(ds->dev, "invalid STP state: %d\n", state); 1328 return; 1329 } 1330 1331 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 1332 1333 p->stp_state = state; 1334 1335 ksz_update_port_member(dev, port); 1336 } 1337 1338 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1339 struct switchdev_brport_flags flags, 1340 struct netlink_ext_ack *extack) 1341 { 1342 if (flags.mask & ~BR_LEARNING) 1343 return -EINVAL; 1344 1345 return 0; 1346 } 1347 1348 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 1349 struct switchdev_brport_flags flags, 1350 struct netlink_ext_ack *extack) 1351 { 1352 struct ksz_device *dev = ds->priv; 1353 struct ksz_port *p = &dev->ports[port]; 1354 1355 if (flags.mask & BR_LEARNING) { 1356 p->learning = !!(flags.val & BR_LEARNING); 1357 1358 /* Make the change take effect immediately */ 1359 ksz_port_stp_state_set(ds, port, p->stp_state); 1360 } 1361 1362 return 0; 1363 } 1364 1365 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 1366 int port, 1367 enum dsa_tag_protocol mp) 1368 { 1369 struct ksz_device *dev = ds->priv; 1370 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 1371 1372 if (dev->chip_id == KSZ8795_CHIP_ID || 1373 dev->chip_id == KSZ8794_CHIP_ID || 1374 dev->chip_id == KSZ8765_CHIP_ID) 1375 proto = DSA_TAG_PROTO_KSZ8795; 1376 1377 if (dev->chip_id == KSZ8830_CHIP_ID || 1378 dev->chip_id == KSZ9893_CHIP_ID) 1379 proto = DSA_TAG_PROTO_KSZ9893; 1380 1381 if (dev->chip_id == KSZ9477_CHIP_ID || 1382 dev->chip_id == KSZ9897_CHIP_ID || 1383 dev->chip_id == KSZ9567_CHIP_ID) 1384 proto = DSA_TAG_PROTO_KSZ9477; 1385 1386 if (is_lan937x(dev)) 1387 proto = DSA_TAG_PROTO_LAN937X_VALUE; 1388 1389 return proto; 1390 } 1391 1392 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 1393 bool flag, struct netlink_ext_ack *extack) 1394 { 1395 struct ksz_device *dev = ds->priv; 1396 1397 if (!dev->dev_ops->vlan_filtering) 1398 return -EOPNOTSUPP; 1399 1400 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 1401 } 1402 1403 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 1404 const struct switchdev_obj_port_vlan *vlan, 1405 struct netlink_ext_ack *extack) 1406 { 1407 struct ksz_device *dev = ds->priv; 1408 1409 if (!dev->dev_ops->vlan_add) 1410 return -EOPNOTSUPP; 1411 1412 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 1413 } 1414 1415 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 1416 const struct switchdev_obj_port_vlan *vlan) 1417 { 1418 struct ksz_device *dev = ds->priv; 1419 1420 if (!dev->dev_ops->vlan_del) 1421 return -EOPNOTSUPP; 1422 1423 return dev->dev_ops->vlan_del(dev, port, vlan); 1424 } 1425 1426 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 1427 struct dsa_mall_mirror_tc_entry *mirror, 1428 bool ingress, struct netlink_ext_ack *extack) 1429 { 1430 struct ksz_device *dev = ds->priv; 1431 1432 if (!dev->dev_ops->mirror_add) 1433 return -EOPNOTSUPP; 1434 1435 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 1436 } 1437 1438 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 1439 struct dsa_mall_mirror_tc_entry *mirror) 1440 { 1441 struct ksz_device *dev = ds->priv; 1442 1443 if (dev->dev_ops->mirror_del) 1444 dev->dev_ops->mirror_del(dev, port, mirror); 1445 } 1446 1447 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 1448 { 1449 struct ksz_device *dev = ds->priv; 1450 1451 if (!dev->dev_ops->change_mtu) 1452 return -EOPNOTSUPP; 1453 1454 return dev->dev_ops->change_mtu(dev, port, mtu); 1455 } 1456 1457 static int ksz_max_mtu(struct dsa_switch *ds, int port) 1458 { 1459 struct ksz_device *dev = ds->priv; 1460 1461 if (!dev->dev_ops->max_mtu) 1462 return -EOPNOTSUPP; 1463 1464 return dev->dev_ops->max_mtu(dev, port); 1465 } 1466 1467 static void ksz_set_xmii(struct ksz_device *dev, int port, 1468 phy_interface_t interface) 1469 { 1470 const u8 *bitval = dev->info->xmii_ctrl1; 1471 struct ksz_port *p = &dev->ports[port]; 1472 const u16 *regs = dev->info->regs; 1473 u8 data8; 1474 1475 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 1476 1477 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 1478 P_RGMII_ID_EG_ENABLE); 1479 1480 switch (interface) { 1481 case PHY_INTERFACE_MODE_MII: 1482 data8 |= bitval[P_MII_SEL]; 1483 break; 1484 case PHY_INTERFACE_MODE_RMII: 1485 data8 |= bitval[P_RMII_SEL]; 1486 break; 1487 case PHY_INTERFACE_MODE_GMII: 1488 data8 |= bitval[P_GMII_SEL]; 1489 break; 1490 case PHY_INTERFACE_MODE_RGMII: 1491 case PHY_INTERFACE_MODE_RGMII_ID: 1492 case PHY_INTERFACE_MODE_RGMII_TXID: 1493 case PHY_INTERFACE_MODE_RGMII_RXID: 1494 data8 |= bitval[P_RGMII_SEL]; 1495 /* On KSZ9893, disable RGMII in-band status support */ 1496 if (dev->features & IS_9893) 1497 data8 &= ~P_MII_MAC_MODE; 1498 break; 1499 default: 1500 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 1501 phy_modes(interface), port); 1502 return; 1503 } 1504 1505 if (p->rgmii_tx_val) 1506 data8 |= P_RGMII_ID_EG_ENABLE; 1507 1508 if (p->rgmii_rx_val) 1509 data8 |= P_RGMII_ID_IG_ENABLE; 1510 1511 /* Write the updated value */ 1512 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 1513 } 1514 1515 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 1516 { 1517 const u8 *bitval = dev->info->xmii_ctrl1; 1518 const u16 *regs = dev->info->regs; 1519 phy_interface_t interface; 1520 u8 data8; 1521 u8 val; 1522 1523 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 1524 1525 val = FIELD_GET(P_MII_SEL_M, data8); 1526 1527 if (val == bitval[P_MII_SEL]) { 1528 if (gbit) 1529 interface = PHY_INTERFACE_MODE_GMII; 1530 else 1531 interface = PHY_INTERFACE_MODE_MII; 1532 } else if (val == bitval[P_RMII_SEL]) { 1533 interface = PHY_INTERFACE_MODE_RGMII; 1534 } else { 1535 interface = PHY_INTERFACE_MODE_RGMII; 1536 if (data8 & P_RGMII_ID_EG_ENABLE) 1537 interface = PHY_INTERFACE_MODE_RGMII_TXID; 1538 if (data8 & P_RGMII_ID_IG_ENABLE) { 1539 interface = PHY_INTERFACE_MODE_RGMII_RXID; 1540 if (data8 & P_RGMII_ID_EG_ENABLE) 1541 interface = PHY_INTERFACE_MODE_RGMII_ID; 1542 } 1543 } 1544 1545 return interface; 1546 } 1547 1548 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port, 1549 unsigned int mode, 1550 const struct phylink_link_state *state) 1551 { 1552 struct ksz_device *dev = ds->priv; 1553 1554 if (ksz_is_ksz88x3(dev)) 1555 return; 1556 1557 /* Internal PHYs */ 1558 if (dev->info->internal_phy[port]) 1559 return; 1560 1561 if (phylink_autoneg_inband(mode)) { 1562 dev_err(dev->dev, "In-band AN not supported!\n"); 1563 return; 1564 } 1565 1566 ksz_set_xmii(dev, port, state->interface); 1567 1568 if (dev->dev_ops->phylink_mac_config) 1569 dev->dev_ops->phylink_mac_config(dev, port, mode, state); 1570 1571 if (dev->dev_ops->setup_rgmii_delay) 1572 dev->dev_ops->setup_rgmii_delay(dev, port); 1573 } 1574 1575 bool ksz_get_gbit(struct ksz_device *dev, int port) 1576 { 1577 const u8 *bitval = dev->info->xmii_ctrl1; 1578 const u16 *regs = dev->info->regs; 1579 bool gbit = false; 1580 u8 data8; 1581 bool val; 1582 1583 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 1584 1585 val = FIELD_GET(P_GMII_1GBIT_M, data8); 1586 1587 if (val == bitval[P_GMII_1GBIT]) 1588 gbit = true; 1589 1590 return gbit; 1591 } 1592 1593 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) 1594 { 1595 const u8 *bitval = dev->info->xmii_ctrl1; 1596 const u16 *regs = dev->info->regs; 1597 u8 data8; 1598 1599 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 1600 1601 data8 &= ~P_GMII_1GBIT_M; 1602 1603 if (gbit) 1604 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 1605 else 1606 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 1607 1608 /* Write the updated value */ 1609 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 1610 } 1611 1612 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) 1613 { 1614 const u8 *bitval = dev->info->xmii_ctrl0; 1615 const u16 *regs = dev->info->regs; 1616 u8 data8; 1617 1618 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 1619 1620 data8 &= ~P_MII_100MBIT_M; 1621 1622 if (speed == SPEED_100) 1623 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 1624 else 1625 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 1626 1627 /* Write the updated value */ 1628 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 1629 } 1630 1631 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) 1632 { 1633 if (speed == SPEED_1000) 1634 ksz_set_gbit(dev, port, true); 1635 else 1636 ksz_set_gbit(dev, port, false); 1637 1638 if (speed == SPEED_100 || speed == SPEED_10) 1639 ksz_set_100_10mbit(dev, port, speed); 1640 } 1641 1642 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 1643 bool tx_pause, bool rx_pause) 1644 { 1645 const u8 *bitval = dev->info->xmii_ctrl0; 1646 const u32 *masks = dev->info->masks; 1647 const u16 *regs = dev->info->regs; 1648 u8 mask; 1649 u8 val; 1650 1651 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 1652 masks[P_MII_RX_FLOW_CTRL]; 1653 1654 if (duplex == DUPLEX_FULL) 1655 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 1656 else 1657 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 1658 1659 if (tx_pause) 1660 val |= masks[P_MII_TX_FLOW_CTRL]; 1661 1662 if (rx_pause) 1663 val |= masks[P_MII_RX_FLOW_CTRL]; 1664 1665 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 1666 } 1667 1668 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, 1669 unsigned int mode, 1670 phy_interface_t interface, 1671 struct phy_device *phydev, int speed, 1672 int duplex, bool tx_pause, 1673 bool rx_pause) 1674 { 1675 struct ksz_port *p; 1676 1677 p = &dev->ports[port]; 1678 1679 /* Internal PHYs */ 1680 if (dev->info->internal_phy[port]) 1681 return; 1682 1683 p->phydev.speed = speed; 1684 1685 ksz_port_set_xmii_speed(dev, port, speed); 1686 1687 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 1688 } 1689 1690 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port, 1691 unsigned int mode, 1692 phy_interface_t interface, 1693 struct phy_device *phydev, int speed, 1694 int duplex, bool tx_pause, bool rx_pause) 1695 { 1696 struct ksz_device *dev = ds->priv; 1697 1698 if (dev->dev_ops->phylink_mac_link_up) 1699 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface, 1700 phydev, speed, duplex, 1701 tx_pause, rx_pause); 1702 } 1703 1704 static int ksz_switch_detect(struct ksz_device *dev) 1705 { 1706 u8 id1, id2; 1707 u16 id16; 1708 u32 id32; 1709 int ret; 1710 1711 /* read chip id */ 1712 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 1713 if (ret) 1714 return ret; 1715 1716 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 1717 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 1718 1719 switch (id1) { 1720 case KSZ87_FAMILY_ID: 1721 if (id2 == KSZ87_CHIP_ID_95) { 1722 u8 val; 1723 1724 dev->chip_id = KSZ8795_CHIP_ID; 1725 1726 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 1727 if (val & KSZ8_PORT_FIBER_MODE) 1728 dev->chip_id = KSZ8765_CHIP_ID; 1729 } else if (id2 == KSZ87_CHIP_ID_94) { 1730 dev->chip_id = KSZ8794_CHIP_ID; 1731 } else { 1732 return -ENODEV; 1733 } 1734 break; 1735 case KSZ88_FAMILY_ID: 1736 if (id2 == KSZ88_CHIP_ID_63) 1737 dev->chip_id = KSZ8830_CHIP_ID; 1738 else 1739 return -ENODEV; 1740 break; 1741 default: 1742 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 1743 if (ret) 1744 return ret; 1745 1746 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 1747 id32 &= ~0xFF; 1748 1749 switch (id32) { 1750 case KSZ9477_CHIP_ID: 1751 case KSZ9897_CHIP_ID: 1752 case KSZ9893_CHIP_ID: 1753 case KSZ9567_CHIP_ID: 1754 case LAN9370_CHIP_ID: 1755 case LAN9371_CHIP_ID: 1756 case LAN9372_CHIP_ID: 1757 case LAN9373_CHIP_ID: 1758 case LAN9374_CHIP_ID: 1759 dev->chip_id = id32; 1760 break; 1761 default: 1762 dev_err(dev->dev, 1763 "unsupported switch detected %x)\n", id32); 1764 return -ENODEV; 1765 } 1766 } 1767 return 0; 1768 } 1769 1770 static const struct dsa_switch_ops ksz_switch_ops = { 1771 .get_tag_protocol = ksz_get_tag_protocol, 1772 .get_phy_flags = ksz_get_phy_flags, 1773 .setup = ksz_setup, 1774 .phy_read = ksz_phy_read16, 1775 .phy_write = ksz_phy_write16, 1776 .phylink_get_caps = ksz_phylink_get_caps, 1777 .phylink_mac_config = ksz_phylink_mac_config, 1778 .phylink_mac_link_up = ksz_phylink_mac_link_up, 1779 .phylink_mac_link_down = ksz_mac_link_down, 1780 .port_enable = ksz_enable_port, 1781 .get_strings = ksz_get_strings, 1782 .get_ethtool_stats = ksz_get_ethtool_stats, 1783 .get_sset_count = ksz_sset_count, 1784 .port_bridge_join = ksz_port_bridge_join, 1785 .port_bridge_leave = ksz_port_bridge_leave, 1786 .port_stp_state_set = ksz_port_stp_state_set, 1787 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 1788 .port_bridge_flags = ksz_port_bridge_flags, 1789 .port_fast_age = ksz_port_fast_age, 1790 .port_vlan_filtering = ksz_port_vlan_filtering, 1791 .port_vlan_add = ksz_port_vlan_add, 1792 .port_vlan_del = ksz_port_vlan_del, 1793 .port_fdb_dump = ksz_port_fdb_dump, 1794 .port_fdb_add = ksz_port_fdb_add, 1795 .port_fdb_del = ksz_port_fdb_del, 1796 .port_mdb_add = ksz_port_mdb_add, 1797 .port_mdb_del = ksz_port_mdb_del, 1798 .port_mirror_add = ksz_port_mirror_add, 1799 .port_mirror_del = ksz_port_mirror_del, 1800 .get_stats64 = ksz_get_stats64, 1801 .get_pause_stats = ksz_get_pause_stats, 1802 .port_change_mtu = ksz_change_mtu, 1803 .port_max_mtu = ksz_max_mtu, 1804 }; 1805 1806 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 1807 { 1808 struct dsa_switch *ds; 1809 struct ksz_device *swdev; 1810 1811 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 1812 if (!ds) 1813 return NULL; 1814 1815 ds->dev = base; 1816 ds->num_ports = DSA_MAX_PORTS; 1817 ds->ops = &ksz_switch_ops; 1818 1819 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 1820 if (!swdev) 1821 return NULL; 1822 1823 ds->priv = swdev; 1824 swdev->dev = base; 1825 1826 swdev->ds = ds; 1827 swdev->priv = priv; 1828 1829 return swdev; 1830 } 1831 EXPORT_SYMBOL(ksz_switch_alloc); 1832 1833 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 1834 struct device_node *port_dn) 1835 { 1836 phy_interface_t phy_mode = dev->ports[port_num].interface; 1837 int rx_delay = -1, tx_delay = -1; 1838 1839 if (!phy_interface_mode_is_rgmii(phy_mode)) 1840 return; 1841 1842 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 1843 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 1844 1845 if (rx_delay == -1 && tx_delay == -1) { 1846 dev_warn(dev->dev, 1847 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 1848 "please update device tree to specify \"rx-internal-delay-ps\" and " 1849 "\"tx-internal-delay-ps\"", 1850 port_num); 1851 1852 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 1853 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 1854 rx_delay = 2000; 1855 1856 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 1857 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 1858 tx_delay = 2000; 1859 } 1860 1861 if (rx_delay < 0) 1862 rx_delay = 0; 1863 if (tx_delay < 0) 1864 tx_delay = 0; 1865 1866 dev->ports[port_num].rgmii_rx_val = rx_delay; 1867 dev->ports[port_num].rgmii_tx_val = tx_delay; 1868 } 1869 1870 int ksz_switch_register(struct ksz_device *dev) 1871 { 1872 const struct ksz_chip_data *info; 1873 struct device_node *port, *ports; 1874 phy_interface_t interface; 1875 unsigned int port_num; 1876 int ret; 1877 int i; 1878 1879 if (dev->pdata) 1880 dev->chip_id = dev->pdata->chip_id; 1881 1882 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 1883 GPIOD_OUT_LOW); 1884 if (IS_ERR(dev->reset_gpio)) 1885 return PTR_ERR(dev->reset_gpio); 1886 1887 if (dev->reset_gpio) { 1888 gpiod_set_value_cansleep(dev->reset_gpio, 1); 1889 usleep_range(10000, 12000); 1890 gpiod_set_value_cansleep(dev->reset_gpio, 0); 1891 msleep(100); 1892 } 1893 1894 mutex_init(&dev->dev_mutex); 1895 mutex_init(&dev->regmap_mutex); 1896 mutex_init(&dev->alu_mutex); 1897 mutex_init(&dev->vlan_mutex); 1898 1899 ret = ksz_switch_detect(dev); 1900 if (ret) 1901 return ret; 1902 1903 info = ksz_lookup_info(dev->chip_id); 1904 if (!info) 1905 return -ENODEV; 1906 1907 /* Update the compatible info with the probed one */ 1908 dev->info = info; 1909 1910 dev_info(dev->dev, "found switch: %s, rev %i\n", 1911 dev->info->dev_name, dev->chip_rev); 1912 1913 ret = ksz_check_device_id(dev); 1914 if (ret) 1915 return ret; 1916 1917 dev->dev_ops = dev->info->ops; 1918 1919 ret = dev->dev_ops->init(dev); 1920 if (ret) 1921 return ret; 1922 1923 dev->ports = devm_kzalloc(dev->dev, 1924 dev->info->port_cnt * sizeof(struct ksz_port), 1925 GFP_KERNEL); 1926 if (!dev->ports) 1927 return -ENOMEM; 1928 1929 for (i = 0; i < dev->info->port_cnt; i++) { 1930 spin_lock_init(&dev->ports[i].mib.stats64_lock); 1931 mutex_init(&dev->ports[i].mib.cnt_mutex); 1932 dev->ports[i].mib.counters = 1933 devm_kzalloc(dev->dev, 1934 sizeof(u64) * (dev->info->mib_cnt + 1), 1935 GFP_KERNEL); 1936 if (!dev->ports[i].mib.counters) 1937 return -ENOMEM; 1938 } 1939 1940 /* set the real number of ports */ 1941 dev->ds->num_ports = dev->info->port_cnt; 1942 1943 /* Host port interface will be self detected, or specifically set in 1944 * device tree. 1945 */ 1946 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 1947 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 1948 if (dev->dev->of_node) { 1949 ret = of_get_phy_mode(dev->dev->of_node, &interface); 1950 if (ret == 0) 1951 dev->compat_interface = interface; 1952 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 1953 if (!ports) 1954 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 1955 if (ports) { 1956 for_each_available_child_of_node(ports, port) { 1957 if (of_property_read_u32(port, "reg", 1958 &port_num)) 1959 continue; 1960 if (!(dev->port_mask & BIT(port_num))) { 1961 of_node_put(port); 1962 of_node_put(ports); 1963 return -EINVAL; 1964 } 1965 of_get_phy_mode(port, 1966 &dev->ports[port_num].interface); 1967 1968 ksz_parse_rgmii_delay(dev, port_num, port); 1969 } 1970 of_node_put(ports); 1971 } 1972 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 1973 "microchip,synclko-125"); 1974 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 1975 "microchip,synclko-disable"); 1976 if (dev->synclko_125 && dev->synclko_disable) { 1977 dev_err(dev->dev, "inconsistent synclko settings\n"); 1978 return -EINVAL; 1979 } 1980 } 1981 1982 ret = dsa_register_switch(dev->ds); 1983 if (ret) { 1984 dev->dev_ops->exit(dev); 1985 return ret; 1986 } 1987 1988 /* Read MIB counters every 30 seconds to avoid overflow. */ 1989 dev->mib_read_interval = msecs_to_jiffies(5000); 1990 1991 /* Start the MIB timer. */ 1992 schedule_delayed_work(&dev->mib_read, 0); 1993 1994 return ret; 1995 } 1996 EXPORT_SYMBOL(ksz_switch_register); 1997 1998 void ksz_switch_remove(struct ksz_device *dev) 1999 { 2000 /* timer started */ 2001 if (dev->mib_read_interval) { 2002 dev->mib_read_interval = 0; 2003 cancel_delayed_work_sync(&dev->mib_read); 2004 } 2005 2006 dev->dev_ops->exit(dev); 2007 dsa_unregister_switch(dev->ds); 2008 2009 if (dev->reset_gpio) 2010 gpiod_set_value_cansleep(dev->reset_gpio, 1); 2011 2012 } 2013 EXPORT_SYMBOL(ksz_switch_remove); 2014 2015 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 2016 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 2017 MODULE_LICENSE("GPL"); 2018