1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/export.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/platform_data/microchip-ksz.h> 14 #include <linux/phy.h> 15 #include <linux/etherdevice.h> 16 #include <linux/if_bridge.h> 17 #include <linux/of_device.h> 18 #include <linux/of_net.h> 19 #include <net/dsa.h> 20 #include <net/switchdev.h> 21 22 #include "ksz_common.h" 23 24 #define MIB_COUNTER_NUM 0x20 25 26 struct ksz_stats_raw { 27 u64 rx_hi; 28 u64 rx_undersize; 29 u64 rx_fragments; 30 u64 rx_oversize; 31 u64 rx_jabbers; 32 u64 rx_symbol_err; 33 u64 rx_crc_err; 34 u64 rx_align_err; 35 u64 rx_mac_ctrl; 36 u64 rx_pause; 37 u64 rx_bcast; 38 u64 rx_mcast; 39 u64 rx_ucast; 40 u64 rx_64_or_less; 41 u64 rx_65_127; 42 u64 rx_128_255; 43 u64 rx_256_511; 44 u64 rx_512_1023; 45 u64 rx_1024_1522; 46 u64 rx_1523_2000; 47 u64 rx_2001; 48 u64 tx_hi; 49 u64 tx_late_col; 50 u64 tx_pause; 51 u64 tx_bcast; 52 u64 tx_mcast; 53 u64 tx_ucast; 54 u64 tx_deferred; 55 u64 tx_total_col; 56 u64 tx_exc_col; 57 u64 tx_single_col; 58 u64 tx_mult_col; 59 u64 rx_total; 60 u64 tx_total; 61 u64 rx_discards; 62 u64 tx_discards; 63 }; 64 65 static const struct ksz_mib_names ksz88xx_mib_names[] = { 66 { 0x00, "rx" }, 67 { 0x01, "rx_hi" }, 68 { 0x02, "rx_undersize" }, 69 { 0x03, "rx_fragments" }, 70 { 0x04, "rx_oversize" }, 71 { 0x05, "rx_jabbers" }, 72 { 0x06, "rx_symbol_err" }, 73 { 0x07, "rx_crc_err" }, 74 { 0x08, "rx_align_err" }, 75 { 0x09, "rx_mac_ctrl" }, 76 { 0x0a, "rx_pause" }, 77 { 0x0b, "rx_bcast" }, 78 { 0x0c, "rx_mcast" }, 79 { 0x0d, "rx_ucast" }, 80 { 0x0e, "rx_64_or_less" }, 81 { 0x0f, "rx_65_127" }, 82 { 0x10, "rx_128_255" }, 83 { 0x11, "rx_256_511" }, 84 { 0x12, "rx_512_1023" }, 85 { 0x13, "rx_1024_1522" }, 86 { 0x14, "tx" }, 87 { 0x15, "tx_hi" }, 88 { 0x16, "tx_late_col" }, 89 { 0x17, "tx_pause" }, 90 { 0x18, "tx_bcast" }, 91 { 0x19, "tx_mcast" }, 92 { 0x1a, "tx_ucast" }, 93 { 0x1b, "tx_deferred" }, 94 { 0x1c, "tx_total_col" }, 95 { 0x1d, "tx_exc_col" }, 96 { 0x1e, "tx_single_col" }, 97 { 0x1f, "tx_mult_col" }, 98 { 0x100, "rx_discards" }, 99 { 0x101, "tx_discards" }, 100 }; 101 102 static const struct ksz_mib_names ksz9477_mib_names[] = { 103 { 0x00, "rx_hi" }, 104 { 0x01, "rx_undersize" }, 105 { 0x02, "rx_fragments" }, 106 { 0x03, "rx_oversize" }, 107 { 0x04, "rx_jabbers" }, 108 { 0x05, "rx_symbol_err" }, 109 { 0x06, "rx_crc_err" }, 110 { 0x07, "rx_align_err" }, 111 { 0x08, "rx_mac_ctrl" }, 112 { 0x09, "rx_pause" }, 113 { 0x0A, "rx_bcast" }, 114 { 0x0B, "rx_mcast" }, 115 { 0x0C, "rx_ucast" }, 116 { 0x0D, "rx_64_or_less" }, 117 { 0x0E, "rx_65_127" }, 118 { 0x0F, "rx_128_255" }, 119 { 0x10, "rx_256_511" }, 120 { 0x11, "rx_512_1023" }, 121 { 0x12, "rx_1024_1522" }, 122 { 0x13, "rx_1523_2000" }, 123 { 0x14, "rx_2001" }, 124 { 0x15, "tx_hi" }, 125 { 0x16, "tx_late_col" }, 126 { 0x17, "tx_pause" }, 127 { 0x18, "tx_bcast" }, 128 { 0x19, "tx_mcast" }, 129 { 0x1A, "tx_ucast" }, 130 { 0x1B, "tx_deferred" }, 131 { 0x1C, "tx_total_col" }, 132 { 0x1D, "tx_exc_col" }, 133 { 0x1E, "tx_single_col" }, 134 { 0x1F, "tx_mult_col" }, 135 { 0x80, "rx_total" }, 136 { 0x81, "tx_total" }, 137 { 0x82, "rx_discards" }, 138 { 0x83, "tx_discards" }, 139 }; 140 141 const struct ksz_chip_data ksz_switch_chips[] = { 142 [KSZ8795] = { 143 .chip_id = KSZ8795_CHIP_ID, 144 .dev_name = "KSZ8795", 145 .num_vlans = 4096, 146 .num_alus = 0, 147 .num_statics = 8, 148 .cpu_ports = 0x10, /* can be configured as cpu port */ 149 .port_cnt = 5, /* total cpu and user ports */ 150 .ksz87xx_eee_link_erratum = true, 151 .mib_names = ksz9477_mib_names, 152 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 153 .reg_mib_cnt = MIB_COUNTER_NUM, 154 .supports_mii = {false, false, false, false, true}, 155 .supports_rmii = {false, false, false, false, true}, 156 .supports_rgmii = {false, false, false, false, true}, 157 .internal_phy = {true, true, true, true, false}, 158 }, 159 160 [KSZ8794] = { 161 /* WARNING 162 * ======= 163 * KSZ8794 is similar to KSZ8795, except the port map 164 * contains a gap between external and CPU ports, the 165 * port map is NOT continuous. The per-port register 166 * map is shifted accordingly too, i.e. registers at 167 * offset 0x40 are NOT used on KSZ8794 and they ARE 168 * used on KSZ8795 for external port 3. 169 * external cpu 170 * KSZ8794 0,1,2 4 171 * KSZ8795 0,1,2,3 4 172 * KSZ8765 0,1,2,3 4 173 * port_cnt is configured as 5, even though it is 4 174 */ 175 .chip_id = KSZ8794_CHIP_ID, 176 .dev_name = "KSZ8794", 177 .num_vlans = 4096, 178 .num_alus = 0, 179 .num_statics = 8, 180 .cpu_ports = 0x10, /* can be configured as cpu port */ 181 .port_cnt = 5, /* total cpu and user ports */ 182 .ksz87xx_eee_link_erratum = true, 183 .mib_names = ksz9477_mib_names, 184 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 185 .reg_mib_cnt = MIB_COUNTER_NUM, 186 .supports_mii = {false, false, false, false, true}, 187 .supports_rmii = {false, false, false, false, true}, 188 .supports_rgmii = {false, false, false, false, true}, 189 .internal_phy = {true, true, true, false, false}, 190 }, 191 192 [KSZ8765] = { 193 .chip_id = KSZ8765_CHIP_ID, 194 .dev_name = "KSZ8765", 195 .num_vlans = 4096, 196 .num_alus = 0, 197 .num_statics = 8, 198 .cpu_ports = 0x10, /* can be configured as cpu port */ 199 .port_cnt = 5, /* total cpu and user ports */ 200 .ksz87xx_eee_link_erratum = true, 201 .mib_names = ksz9477_mib_names, 202 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 203 .reg_mib_cnt = MIB_COUNTER_NUM, 204 .supports_mii = {false, false, false, false, true}, 205 .supports_rmii = {false, false, false, false, true}, 206 .supports_rgmii = {false, false, false, false, true}, 207 .internal_phy = {true, true, true, true, false}, 208 }, 209 210 [KSZ8830] = { 211 .chip_id = KSZ8830_CHIP_ID, 212 .dev_name = "KSZ8863/KSZ8873", 213 .num_vlans = 16, 214 .num_alus = 0, 215 .num_statics = 8, 216 .cpu_ports = 0x4, /* can be configured as cpu port */ 217 .port_cnt = 3, 218 .mib_names = ksz88xx_mib_names, 219 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 220 .reg_mib_cnt = MIB_COUNTER_NUM, 221 .supports_mii = {false, false, true}, 222 .supports_rmii = {false, false, true}, 223 .internal_phy = {true, true, false}, 224 }, 225 226 [KSZ9477] = { 227 .chip_id = KSZ9477_CHIP_ID, 228 .dev_name = "KSZ9477", 229 .num_vlans = 4096, 230 .num_alus = 4096, 231 .num_statics = 16, 232 .cpu_ports = 0x7F, /* can be configured as cpu port */ 233 .port_cnt = 7, /* total physical port count */ 234 .phy_errata_9477 = true, 235 .mib_names = ksz9477_mib_names, 236 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 237 .reg_mib_cnt = MIB_COUNTER_NUM, 238 .supports_mii = {false, false, false, false, 239 false, true, false}, 240 .supports_rmii = {false, false, false, false, 241 false, true, false}, 242 .supports_rgmii = {false, false, false, false, 243 false, true, false}, 244 .internal_phy = {true, true, true, true, 245 true, false, false}, 246 }, 247 248 [KSZ9897] = { 249 .chip_id = KSZ9897_CHIP_ID, 250 .dev_name = "KSZ9897", 251 .num_vlans = 4096, 252 .num_alus = 4096, 253 .num_statics = 16, 254 .cpu_ports = 0x7F, /* can be configured as cpu port */ 255 .port_cnt = 7, /* total physical port count */ 256 .phy_errata_9477 = true, 257 .mib_names = ksz9477_mib_names, 258 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 259 .reg_mib_cnt = MIB_COUNTER_NUM, 260 .supports_mii = {false, false, false, false, 261 false, true, true}, 262 .supports_rmii = {false, false, false, false, 263 false, true, true}, 264 .supports_rgmii = {false, false, false, false, 265 false, true, true}, 266 .internal_phy = {true, true, true, true, 267 true, false, false}, 268 }, 269 270 [KSZ9893] = { 271 .chip_id = KSZ9893_CHIP_ID, 272 .dev_name = "KSZ9893", 273 .num_vlans = 4096, 274 .num_alus = 4096, 275 .num_statics = 16, 276 .cpu_ports = 0x07, /* can be configured as cpu port */ 277 .port_cnt = 3, /* total port count */ 278 .mib_names = ksz9477_mib_names, 279 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 280 .reg_mib_cnt = MIB_COUNTER_NUM, 281 .supports_mii = {false, false, true}, 282 .supports_rmii = {false, false, true}, 283 .supports_rgmii = {false, false, true}, 284 .internal_phy = {true, true, false}, 285 }, 286 287 [KSZ9567] = { 288 .chip_id = KSZ9567_CHIP_ID, 289 .dev_name = "KSZ9567", 290 .num_vlans = 4096, 291 .num_alus = 4096, 292 .num_statics = 16, 293 .cpu_ports = 0x7F, /* can be configured as cpu port */ 294 .port_cnt = 7, /* total physical port count */ 295 .phy_errata_9477 = true, 296 .mib_names = ksz9477_mib_names, 297 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 298 .reg_mib_cnt = MIB_COUNTER_NUM, 299 .supports_mii = {false, false, false, false, 300 false, true, true}, 301 .supports_rmii = {false, false, false, false, 302 false, true, true}, 303 .supports_rgmii = {false, false, false, false, 304 false, true, true}, 305 .internal_phy = {true, true, true, true, 306 true, false, false}, 307 }, 308 309 [LAN9370] = { 310 .chip_id = LAN9370_CHIP_ID, 311 .dev_name = "LAN9370", 312 .num_vlans = 4096, 313 .num_alus = 1024, 314 .num_statics = 256, 315 .cpu_ports = 0x10, /* can be configured as cpu port */ 316 .port_cnt = 5, /* total physical port count */ 317 .mib_names = ksz9477_mib_names, 318 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 319 .reg_mib_cnt = MIB_COUNTER_NUM, 320 .supports_mii = {false, false, false, false, true}, 321 .supports_rmii = {false, false, false, false, true}, 322 .supports_rgmii = {false, false, false, false, true}, 323 .internal_phy = {true, true, true, true, false}, 324 }, 325 326 [LAN9371] = { 327 .chip_id = LAN9371_CHIP_ID, 328 .dev_name = "LAN9371", 329 .num_vlans = 4096, 330 .num_alus = 1024, 331 .num_statics = 256, 332 .cpu_ports = 0x30, /* can be configured as cpu port */ 333 .port_cnt = 6, /* total physical port count */ 334 .mib_names = ksz9477_mib_names, 335 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 336 .reg_mib_cnt = MIB_COUNTER_NUM, 337 .supports_mii = {false, false, false, false, true, true}, 338 .supports_rmii = {false, false, false, false, true, true}, 339 .supports_rgmii = {false, false, false, false, true, true}, 340 .internal_phy = {true, true, true, true, false, false}, 341 }, 342 343 [LAN9372] = { 344 .chip_id = LAN9372_CHIP_ID, 345 .dev_name = "LAN9372", 346 .num_vlans = 4096, 347 .num_alus = 1024, 348 .num_statics = 256, 349 .cpu_ports = 0x30, /* can be configured as cpu port */ 350 .port_cnt = 8, /* total physical port count */ 351 .mib_names = ksz9477_mib_names, 352 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 353 .reg_mib_cnt = MIB_COUNTER_NUM, 354 .supports_mii = {false, false, false, false, 355 true, true, false, false}, 356 .supports_rmii = {false, false, false, false, 357 true, true, false, false}, 358 .supports_rgmii = {false, false, false, false, 359 true, true, false, false}, 360 .internal_phy = {true, true, true, true, 361 false, false, true, true}, 362 }, 363 364 [LAN9373] = { 365 .chip_id = LAN9373_CHIP_ID, 366 .dev_name = "LAN9373", 367 .num_vlans = 4096, 368 .num_alus = 1024, 369 .num_statics = 256, 370 .cpu_ports = 0x38, /* can be configured as cpu port */ 371 .port_cnt = 5, /* total physical port count */ 372 .mib_names = ksz9477_mib_names, 373 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 374 .reg_mib_cnt = MIB_COUNTER_NUM, 375 .supports_mii = {false, false, false, false, 376 true, true, false, false}, 377 .supports_rmii = {false, false, false, false, 378 true, true, false, false}, 379 .supports_rgmii = {false, false, false, false, 380 true, true, false, false}, 381 .internal_phy = {true, true, true, false, 382 false, false, true, true}, 383 }, 384 385 [LAN9374] = { 386 .chip_id = LAN9374_CHIP_ID, 387 .dev_name = "LAN9374", 388 .num_vlans = 4096, 389 .num_alus = 1024, 390 .num_statics = 256, 391 .cpu_ports = 0x30, /* can be configured as cpu port */ 392 .port_cnt = 8, /* total physical port count */ 393 .mib_names = ksz9477_mib_names, 394 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 395 .reg_mib_cnt = MIB_COUNTER_NUM, 396 .supports_mii = {false, false, false, false, 397 true, true, false, false}, 398 .supports_rmii = {false, false, false, false, 399 true, true, false, false}, 400 .supports_rgmii = {false, false, false, false, 401 true, true, false, false}, 402 .internal_phy = {true, true, true, true, 403 false, false, true, true}, 404 }, 405 }; 406 EXPORT_SYMBOL_GPL(ksz_switch_chips); 407 408 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 409 { 410 int i; 411 412 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 413 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 414 415 if (chip->chip_id == prod_num) 416 return chip; 417 } 418 419 return NULL; 420 } 421 422 static int ksz_check_device_id(struct ksz_device *dev) 423 { 424 const struct ksz_chip_data *dt_chip_data; 425 426 dt_chip_data = of_device_get_match_data(dev->dev); 427 428 /* Check for Device Tree and Chip ID */ 429 if (dt_chip_data->chip_id != dev->chip_id) { 430 dev_err(dev->dev, 431 "Device tree specifies chip %s but found %s, please fix it!\n", 432 dt_chip_data->dev_name, dev->info->dev_name); 433 return -ENODEV; 434 } 435 436 return 0; 437 } 438 439 void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 440 struct phylink_config *config) 441 { 442 struct ksz_device *dev = ds->priv; 443 444 config->legacy_pre_march2020 = false; 445 446 if (dev->info->supports_mii[port]) 447 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 448 449 if (dev->info->supports_rmii[port]) 450 __set_bit(PHY_INTERFACE_MODE_RMII, 451 config->supported_interfaces); 452 453 if (dev->info->supports_rgmii[port]) 454 phy_interface_set_rgmii(config->supported_interfaces); 455 456 if (dev->info->internal_phy[port]) 457 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 458 config->supported_interfaces); 459 } 460 EXPORT_SYMBOL_GPL(ksz_phylink_get_caps); 461 462 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 463 { 464 struct rtnl_link_stats64 *stats; 465 struct ksz_stats_raw *raw; 466 struct ksz_port_mib *mib; 467 468 mib = &dev->ports[port].mib; 469 stats = &mib->stats64; 470 raw = (struct ksz_stats_raw *)mib->counters; 471 472 spin_lock(&mib->stats64_lock); 473 474 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast; 475 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast; 476 477 /* HW counters are counting bytes + FCS which is not acceptable 478 * for rtnl_link_stats64 interface 479 */ 480 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 481 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 482 483 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 484 raw->rx_oversize; 485 486 stats->rx_crc_errors = raw->rx_crc_err; 487 stats->rx_frame_errors = raw->rx_align_err; 488 stats->rx_dropped = raw->rx_discards; 489 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 490 stats->rx_frame_errors + stats->rx_dropped; 491 492 stats->tx_window_errors = raw->tx_late_col; 493 stats->tx_fifo_errors = raw->tx_discards; 494 stats->tx_aborted_errors = raw->tx_exc_col; 495 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 496 stats->tx_aborted_errors; 497 498 stats->multicast = raw->rx_mcast; 499 stats->collisions = raw->tx_total_col; 500 501 spin_unlock(&mib->stats64_lock); 502 } 503 EXPORT_SYMBOL_GPL(ksz_r_mib_stats64); 504 505 void ksz_get_stats64(struct dsa_switch *ds, int port, 506 struct rtnl_link_stats64 *s) 507 { 508 struct ksz_device *dev = ds->priv; 509 struct ksz_port_mib *mib; 510 511 mib = &dev->ports[port].mib; 512 513 spin_lock(&mib->stats64_lock); 514 memcpy(s, &mib->stats64, sizeof(*s)); 515 spin_unlock(&mib->stats64_lock); 516 } 517 EXPORT_SYMBOL_GPL(ksz_get_stats64); 518 519 void ksz_get_strings(struct dsa_switch *ds, int port, 520 u32 stringset, uint8_t *buf) 521 { 522 struct ksz_device *dev = ds->priv; 523 int i; 524 525 if (stringset != ETH_SS_STATS) 526 return; 527 528 for (i = 0; i < dev->info->mib_cnt; i++) { 529 memcpy(buf + i * ETH_GSTRING_LEN, 530 dev->info->mib_names[i].string, ETH_GSTRING_LEN); 531 } 532 } 533 EXPORT_SYMBOL_GPL(ksz_get_strings); 534 535 void ksz_update_port_member(struct ksz_device *dev, int port) 536 { 537 struct ksz_port *p = &dev->ports[port]; 538 struct dsa_switch *ds = dev->ds; 539 u8 port_member = 0, cpu_port; 540 const struct dsa_port *dp; 541 int i, j; 542 543 if (!dsa_is_user_port(ds, port)) 544 return; 545 546 dp = dsa_to_port(ds, port); 547 cpu_port = BIT(dsa_upstream_port(ds, port)); 548 549 for (i = 0; i < ds->num_ports; i++) { 550 const struct dsa_port *other_dp = dsa_to_port(ds, i); 551 struct ksz_port *other_p = &dev->ports[i]; 552 u8 val = 0; 553 554 if (!dsa_is_user_port(ds, i)) 555 continue; 556 if (port == i) 557 continue; 558 if (!dsa_port_bridge_same(dp, other_dp)) 559 continue; 560 if (other_p->stp_state != BR_STATE_FORWARDING) 561 continue; 562 563 if (p->stp_state == BR_STATE_FORWARDING) { 564 val |= BIT(port); 565 port_member |= BIT(i); 566 } 567 568 /* Retain port [i]'s relationship to other ports than [port] */ 569 for (j = 0; j < ds->num_ports; j++) { 570 const struct dsa_port *third_dp; 571 struct ksz_port *third_p; 572 573 if (j == i) 574 continue; 575 if (j == port) 576 continue; 577 if (!dsa_is_user_port(ds, j)) 578 continue; 579 third_p = &dev->ports[j]; 580 if (third_p->stp_state != BR_STATE_FORWARDING) 581 continue; 582 third_dp = dsa_to_port(ds, j); 583 if (dsa_port_bridge_same(other_dp, third_dp)) 584 val |= BIT(j); 585 } 586 587 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 588 } 589 590 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 591 } 592 EXPORT_SYMBOL_GPL(ksz_update_port_member); 593 594 static void port_r_cnt(struct ksz_device *dev, int port) 595 { 596 struct ksz_port_mib *mib = &dev->ports[port].mib; 597 u64 *dropped; 598 599 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 600 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 601 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 602 &mib->counters[mib->cnt_ptr]); 603 ++mib->cnt_ptr; 604 } 605 606 /* last one in storage */ 607 dropped = &mib->counters[dev->info->mib_cnt]; 608 609 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 610 while (mib->cnt_ptr < dev->info->mib_cnt) { 611 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 612 dropped, &mib->counters[mib->cnt_ptr]); 613 ++mib->cnt_ptr; 614 } 615 mib->cnt_ptr = 0; 616 } 617 618 static void ksz_mib_read_work(struct work_struct *work) 619 { 620 struct ksz_device *dev = container_of(work, struct ksz_device, 621 mib_read.work); 622 struct ksz_port_mib *mib; 623 struct ksz_port *p; 624 int i; 625 626 for (i = 0; i < dev->info->port_cnt; i++) { 627 if (dsa_is_unused_port(dev->ds, i)) 628 continue; 629 630 p = &dev->ports[i]; 631 mib = &p->mib; 632 mutex_lock(&mib->cnt_mutex); 633 634 /* Only read MIB counters when the port is told to do. 635 * If not, read only dropped counters when link is not up. 636 */ 637 if (!p->read) { 638 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 639 640 if (!netif_carrier_ok(dp->slave)) 641 mib->cnt_ptr = dev->info->reg_mib_cnt; 642 } 643 port_r_cnt(dev, i); 644 p->read = false; 645 646 if (dev->dev_ops->r_mib_stat64) 647 dev->dev_ops->r_mib_stat64(dev, i); 648 649 mutex_unlock(&mib->cnt_mutex); 650 } 651 652 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 653 } 654 655 void ksz_init_mib_timer(struct ksz_device *dev) 656 { 657 int i; 658 659 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 660 661 for (i = 0; i < dev->info->port_cnt; i++) { 662 struct ksz_port_mib *mib = &dev->ports[i].mib; 663 664 dev->dev_ops->port_init_cnt(dev, i); 665 666 mib->cnt_ptr = 0; 667 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 668 } 669 } 670 EXPORT_SYMBOL_GPL(ksz_init_mib_timer); 671 672 int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 673 { 674 struct ksz_device *dev = ds->priv; 675 u16 val = 0xffff; 676 677 dev->dev_ops->r_phy(dev, addr, reg, &val); 678 679 return val; 680 } 681 EXPORT_SYMBOL_GPL(ksz_phy_read16); 682 683 int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 684 { 685 struct ksz_device *dev = ds->priv; 686 687 dev->dev_ops->w_phy(dev, addr, reg, val); 688 689 return 0; 690 } 691 EXPORT_SYMBOL_GPL(ksz_phy_write16); 692 693 void ksz_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode, 694 phy_interface_t interface) 695 { 696 struct ksz_device *dev = ds->priv; 697 struct ksz_port *p = &dev->ports[port]; 698 699 /* Read all MIB counters when the link is going down. */ 700 p->read = true; 701 /* timer started */ 702 if (dev->mib_read_interval) 703 schedule_delayed_work(&dev->mib_read, 0); 704 } 705 EXPORT_SYMBOL_GPL(ksz_mac_link_down); 706 707 int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 708 { 709 struct ksz_device *dev = ds->priv; 710 711 if (sset != ETH_SS_STATS) 712 return 0; 713 714 return dev->info->mib_cnt; 715 } 716 EXPORT_SYMBOL_GPL(ksz_sset_count); 717 718 void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *buf) 719 { 720 const struct dsa_port *dp = dsa_to_port(ds, port); 721 struct ksz_device *dev = ds->priv; 722 struct ksz_port_mib *mib; 723 724 mib = &dev->ports[port].mib; 725 mutex_lock(&mib->cnt_mutex); 726 727 /* Only read dropped counters if no link. */ 728 if (!netif_carrier_ok(dp->slave)) 729 mib->cnt_ptr = dev->info->reg_mib_cnt; 730 port_r_cnt(dev, port); 731 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 732 mutex_unlock(&mib->cnt_mutex); 733 } 734 EXPORT_SYMBOL_GPL(ksz_get_ethtool_stats); 735 736 int ksz_port_bridge_join(struct dsa_switch *ds, int port, 737 struct dsa_bridge bridge, 738 bool *tx_fwd_offload, 739 struct netlink_ext_ack *extack) 740 { 741 /* port_stp_state_set() will be called after to put the port in 742 * appropriate state so there is no need to do anything. 743 */ 744 745 return 0; 746 } 747 EXPORT_SYMBOL_GPL(ksz_port_bridge_join); 748 749 void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 750 struct dsa_bridge bridge) 751 { 752 /* port_stp_state_set() will be called after to put the port in 753 * forwarding state so there is no need to do anything. 754 */ 755 } 756 EXPORT_SYMBOL_GPL(ksz_port_bridge_leave); 757 758 void ksz_port_fast_age(struct dsa_switch *ds, int port) 759 { 760 struct ksz_device *dev = ds->priv; 761 762 dev->dev_ops->flush_dyn_mac_table(dev, port); 763 } 764 EXPORT_SYMBOL_GPL(ksz_port_fast_age); 765 766 int ksz_port_fdb_dump(struct dsa_switch *ds, int port, dsa_fdb_dump_cb_t *cb, 767 void *data) 768 { 769 struct ksz_device *dev = ds->priv; 770 int ret = 0; 771 u16 i = 0; 772 u16 entries = 0; 773 u8 timestamp = 0; 774 u8 fid; 775 u8 member; 776 struct alu_struct alu; 777 778 do { 779 alu.is_static = false; 780 ret = dev->dev_ops->r_dyn_mac_table(dev, i, alu.mac, &fid, 781 &member, ×tamp, 782 &entries); 783 if (!ret && (member & BIT(port))) { 784 ret = cb(alu.mac, alu.fid, alu.is_static, data); 785 if (ret) 786 break; 787 } 788 i++; 789 } while (i < entries); 790 if (i >= entries) 791 ret = 0; 792 793 return ret; 794 } 795 EXPORT_SYMBOL_GPL(ksz_port_fdb_dump); 796 797 int ksz_port_mdb_add(struct dsa_switch *ds, int port, 798 const struct switchdev_obj_port_mdb *mdb, 799 struct dsa_db db) 800 { 801 struct ksz_device *dev = ds->priv; 802 struct alu_struct alu; 803 int index; 804 int empty = 0; 805 806 alu.port_forward = 0; 807 for (index = 0; index < dev->info->num_statics; index++) { 808 if (!dev->dev_ops->r_sta_mac_table(dev, index, &alu)) { 809 /* Found one already in static MAC table. */ 810 if (!memcmp(alu.mac, mdb->addr, ETH_ALEN) && 811 alu.fid == mdb->vid) 812 break; 813 /* Remember the first empty entry. */ 814 } else if (!empty) { 815 empty = index + 1; 816 } 817 } 818 819 /* no available entry */ 820 if (index == dev->info->num_statics && !empty) 821 return -ENOSPC; 822 823 /* add entry */ 824 if (index == dev->info->num_statics) { 825 index = empty - 1; 826 memset(&alu, 0, sizeof(alu)); 827 memcpy(alu.mac, mdb->addr, ETH_ALEN); 828 alu.is_static = true; 829 } 830 alu.port_forward |= BIT(port); 831 if (mdb->vid) { 832 alu.is_use_fid = true; 833 834 /* Need a way to map VID to FID. */ 835 alu.fid = mdb->vid; 836 } 837 dev->dev_ops->w_sta_mac_table(dev, index, &alu); 838 839 return 0; 840 } 841 EXPORT_SYMBOL_GPL(ksz_port_mdb_add); 842 843 int ksz_port_mdb_del(struct dsa_switch *ds, int port, 844 const struct switchdev_obj_port_mdb *mdb, 845 struct dsa_db db) 846 { 847 struct ksz_device *dev = ds->priv; 848 struct alu_struct alu; 849 int index; 850 851 for (index = 0; index < dev->info->num_statics; index++) { 852 if (!dev->dev_ops->r_sta_mac_table(dev, index, &alu)) { 853 /* Found one already in static MAC table. */ 854 if (!memcmp(alu.mac, mdb->addr, ETH_ALEN) && 855 alu.fid == mdb->vid) 856 break; 857 } 858 } 859 860 /* no available entry */ 861 if (index == dev->info->num_statics) 862 goto exit; 863 864 /* clear port */ 865 alu.port_forward &= ~BIT(port); 866 if (!alu.port_forward) 867 alu.is_static = false; 868 dev->dev_ops->w_sta_mac_table(dev, index, &alu); 869 870 exit: 871 return 0; 872 } 873 EXPORT_SYMBOL_GPL(ksz_port_mdb_del); 874 875 int ksz_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy) 876 { 877 struct ksz_device *dev = ds->priv; 878 879 if (!dsa_is_user_port(ds, port)) 880 return 0; 881 882 /* setup slave port */ 883 dev->dev_ops->port_setup(dev, port, false); 884 885 /* port_stp_state_set() will be called after to enable the port so 886 * there is no need to do anything. 887 */ 888 889 return 0; 890 } 891 EXPORT_SYMBOL_GPL(ksz_enable_port); 892 893 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, 894 u8 state, int reg) 895 { 896 struct ksz_device *dev = ds->priv; 897 struct ksz_port *p; 898 u8 data; 899 900 ksz_pread8(dev, port, reg, &data); 901 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 902 903 switch (state) { 904 case BR_STATE_DISABLED: 905 data |= PORT_LEARN_DISABLE; 906 break; 907 case BR_STATE_LISTENING: 908 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 909 break; 910 case BR_STATE_LEARNING: 911 data |= PORT_RX_ENABLE; 912 break; 913 case BR_STATE_FORWARDING: 914 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 915 break; 916 case BR_STATE_BLOCKING: 917 data |= PORT_LEARN_DISABLE; 918 break; 919 default: 920 dev_err(ds->dev, "invalid STP state: %d\n", state); 921 return; 922 } 923 924 ksz_pwrite8(dev, port, reg, data); 925 926 p = &dev->ports[port]; 927 p->stp_state = state; 928 929 ksz_update_port_member(dev, port); 930 } 931 EXPORT_SYMBOL_GPL(ksz_port_stp_state_set); 932 933 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 934 { 935 struct dsa_switch *ds; 936 struct ksz_device *swdev; 937 938 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 939 if (!ds) 940 return NULL; 941 942 ds->dev = base; 943 ds->num_ports = DSA_MAX_PORTS; 944 945 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 946 if (!swdev) 947 return NULL; 948 949 ds->priv = swdev; 950 swdev->dev = base; 951 952 swdev->ds = ds; 953 swdev->priv = priv; 954 955 return swdev; 956 } 957 EXPORT_SYMBOL(ksz_switch_alloc); 958 959 int ksz_switch_register(struct ksz_device *dev, 960 const struct ksz_dev_ops *ops) 961 { 962 const struct ksz_chip_data *info; 963 struct device_node *port, *ports; 964 phy_interface_t interface; 965 unsigned int port_num; 966 int ret; 967 int i; 968 969 if (dev->pdata) 970 dev->chip_id = dev->pdata->chip_id; 971 972 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 973 GPIOD_OUT_LOW); 974 if (IS_ERR(dev->reset_gpio)) 975 return PTR_ERR(dev->reset_gpio); 976 977 if (dev->reset_gpio) { 978 gpiod_set_value_cansleep(dev->reset_gpio, 1); 979 usleep_range(10000, 12000); 980 gpiod_set_value_cansleep(dev->reset_gpio, 0); 981 msleep(100); 982 } 983 984 mutex_init(&dev->dev_mutex); 985 mutex_init(&dev->regmap_mutex); 986 mutex_init(&dev->alu_mutex); 987 mutex_init(&dev->vlan_mutex); 988 989 dev->dev_ops = ops; 990 991 if (dev->dev_ops->detect(dev)) 992 return -EINVAL; 993 994 info = ksz_lookup_info(dev->chip_id); 995 if (!info) 996 return -ENODEV; 997 998 /* Update the compatible info with the probed one */ 999 dev->info = info; 1000 1001 ret = ksz_check_device_id(dev); 1002 if (ret) 1003 return ret; 1004 1005 ret = dev->dev_ops->init(dev); 1006 if (ret) 1007 return ret; 1008 1009 dev->ports = devm_kzalloc(dev->dev, 1010 dev->info->port_cnt * sizeof(struct ksz_port), 1011 GFP_KERNEL); 1012 if (!dev->ports) 1013 return -ENOMEM; 1014 1015 for (i = 0; i < dev->info->port_cnt; i++) { 1016 spin_lock_init(&dev->ports[i].mib.stats64_lock); 1017 mutex_init(&dev->ports[i].mib.cnt_mutex); 1018 dev->ports[i].mib.counters = 1019 devm_kzalloc(dev->dev, 1020 sizeof(u64) * (dev->info->mib_cnt + 1), 1021 GFP_KERNEL); 1022 if (!dev->ports[i].mib.counters) 1023 return -ENOMEM; 1024 } 1025 1026 /* set the real number of ports */ 1027 dev->ds->num_ports = dev->info->port_cnt; 1028 1029 /* Host port interface will be self detected, or specifically set in 1030 * device tree. 1031 */ 1032 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 1033 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 1034 if (dev->dev->of_node) { 1035 ret = of_get_phy_mode(dev->dev->of_node, &interface); 1036 if (ret == 0) 1037 dev->compat_interface = interface; 1038 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 1039 if (!ports) 1040 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 1041 if (ports) 1042 for_each_available_child_of_node(ports, port) { 1043 if (of_property_read_u32(port, "reg", 1044 &port_num)) 1045 continue; 1046 if (!(dev->port_mask & BIT(port_num))) { 1047 of_node_put(port); 1048 return -EINVAL; 1049 } 1050 of_get_phy_mode(port, 1051 &dev->ports[port_num].interface); 1052 } 1053 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 1054 "microchip,synclko-125"); 1055 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 1056 "microchip,synclko-disable"); 1057 if (dev->synclko_125 && dev->synclko_disable) { 1058 dev_err(dev->dev, "inconsistent synclko settings\n"); 1059 return -EINVAL; 1060 } 1061 } 1062 1063 ret = dsa_register_switch(dev->ds); 1064 if (ret) { 1065 dev->dev_ops->exit(dev); 1066 return ret; 1067 } 1068 1069 /* Read MIB counters every 30 seconds to avoid overflow. */ 1070 dev->mib_read_interval = msecs_to_jiffies(5000); 1071 1072 /* Start the MIB timer. */ 1073 schedule_delayed_work(&dev->mib_read, 0); 1074 1075 return 0; 1076 } 1077 EXPORT_SYMBOL(ksz_switch_register); 1078 1079 void ksz_switch_remove(struct ksz_device *dev) 1080 { 1081 /* timer started */ 1082 if (dev->mib_read_interval) { 1083 dev->mib_read_interval = 0; 1084 cancel_delayed_work_sync(&dev->mib_read); 1085 } 1086 1087 dev->dev_ops->exit(dev); 1088 dsa_unregister_switch(dev->ds); 1089 1090 if (dev->reset_gpio) 1091 gpiod_set_value_cansleep(dev->reset_gpio, 1); 1092 1093 } 1094 EXPORT_SYMBOL(ksz_switch_remove); 1095 1096 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 1097 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 1098 MODULE_LICENSE("GPL"); 1099