1 /* 2 * Microchip switch driver main logic 3 * 4 * Copyright (C) 2017 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include <linux/delay.h> 20 #include <linux/export.h> 21 #include <linux/gpio.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/platform_data/microchip-ksz.h> 25 #include <linux/phy.h> 26 #include <linux/etherdevice.h> 27 #include <linux/if_bridge.h> 28 #include <net/dsa.h> 29 #include <net/switchdev.h> 30 31 #include "ksz_priv.h" 32 33 static const struct { 34 int index; 35 char string[ETH_GSTRING_LEN]; 36 } mib_names[TOTAL_SWITCH_COUNTER_NUM] = { 37 { 0x00, "rx_hi" }, 38 { 0x01, "rx_undersize" }, 39 { 0x02, "rx_fragments" }, 40 { 0x03, "rx_oversize" }, 41 { 0x04, "rx_jabbers" }, 42 { 0x05, "rx_symbol_err" }, 43 { 0x06, "rx_crc_err" }, 44 { 0x07, "rx_align_err" }, 45 { 0x08, "rx_mac_ctrl" }, 46 { 0x09, "rx_pause" }, 47 { 0x0A, "rx_bcast" }, 48 { 0x0B, "rx_mcast" }, 49 { 0x0C, "rx_ucast" }, 50 { 0x0D, "rx_64_or_less" }, 51 { 0x0E, "rx_65_127" }, 52 { 0x0F, "rx_128_255" }, 53 { 0x10, "rx_256_511" }, 54 { 0x11, "rx_512_1023" }, 55 { 0x12, "rx_1024_1522" }, 56 { 0x13, "rx_1523_2000" }, 57 { 0x14, "rx_2001" }, 58 { 0x15, "tx_hi" }, 59 { 0x16, "tx_late_col" }, 60 { 0x17, "tx_pause" }, 61 { 0x18, "tx_bcast" }, 62 { 0x19, "tx_mcast" }, 63 { 0x1A, "tx_ucast" }, 64 { 0x1B, "tx_deferred" }, 65 { 0x1C, "tx_total_col" }, 66 { 0x1D, "tx_exc_col" }, 67 { 0x1E, "tx_single_col" }, 68 { 0x1F, "tx_mult_col" }, 69 { 0x80, "rx_total" }, 70 { 0x81, "tx_total" }, 71 { 0x82, "rx_discards" }, 72 { 0x83, "tx_discards" }, 73 }; 74 75 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 76 { 77 u8 data; 78 79 ksz_read8(dev, addr, &data); 80 if (set) 81 data |= bits; 82 else 83 data &= ~bits; 84 ksz_write8(dev, addr, data); 85 } 86 87 static void ksz_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set) 88 { 89 u32 data; 90 91 ksz_read32(dev, addr, &data); 92 if (set) 93 data |= bits; 94 else 95 data &= ~bits; 96 ksz_write32(dev, addr, data); 97 } 98 99 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 100 bool set) 101 { 102 u32 addr; 103 u8 data; 104 105 addr = PORT_CTRL_ADDR(port, offset); 106 ksz_read8(dev, addr, &data); 107 108 if (set) 109 data |= bits; 110 else 111 data &= ~bits; 112 113 ksz_write8(dev, addr, data); 114 } 115 116 static void ksz_port_cfg32(struct ksz_device *dev, int port, int offset, 117 u32 bits, bool set) 118 { 119 u32 addr; 120 u32 data; 121 122 addr = PORT_CTRL_ADDR(port, offset); 123 ksz_read32(dev, addr, &data); 124 125 if (set) 126 data |= bits; 127 else 128 data &= ~bits; 129 130 ksz_write32(dev, addr, data); 131 } 132 133 static int wait_vlan_ctrl_ready(struct ksz_device *dev, u32 waiton, int timeout) 134 { 135 u8 data; 136 137 do { 138 ksz_read8(dev, REG_SW_VLAN_CTRL, &data); 139 if (!(data & waiton)) 140 break; 141 usleep_range(1, 10); 142 } while (timeout-- > 0); 143 144 if (timeout <= 0) 145 return -ETIMEDOUT; 146 147 return 0; 148 } 149 150 static int get_vlan_table(struct dsa_switch *ds, u16 vid, u32 *vlan_table) 151 { 152 struct ksz_device *dev = ds->priv; 153 int ret; 154 155 mutex_lock(&dev->vlan_mutex); 156 157 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 158 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START); 159 160 /* wait to be cleared */ 161 ret = wait_vlan_ctrl_ready(dev, VLAN_START, 1000); 162 if (ret < 0) { 163 dev_dbg(dev->dev, "Failed to read vlan table\n"); 164 goto exit; 165 } 166 167 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]); 168 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]); 169 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]); 170 171 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 172 173 exit: 174 mutex_unlock(&dev->vlan_mutex); 175 176 return ret; 177 } 178 179 static int set_vlan_table(struct dsa_switch *ds, u16 vid, u32 *vlan_table) 180 { 181 struct ksz_device *dev = ds->priv; 182 int ret; 183 184 mutex_lock(&dev->vlan_mutex); 185 186 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]); 187 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]); 188 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]); 189 190 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 191 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE); 192 193 /* wait to be cleared */ 194 ret = wait_vlan_ctrl_ready(dev, VLAN_START, 1000); 195 if (ret < 0) { 196 dev_dbg(dev->dev, "Failed to write vlan table\n"); 197 goto exit; 198 } 199 200 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 201 202 /* update vlan cache table */ 203 dev->vlan_cache[vid].table[0] = vlan_table[0]; 204 dev->vlan_cache[vid].table[1] = vlan_table[1]; 205 dev->vlan_cache[vid].table[2] = vlan_table[2]; 206 207 exit: 208 mutex_unlock(&dev->vlan_mutex); 209 210 return ret; 211 } 212 213 static void read_table(struct dsa_switch *ds, u32 *table) 214 { 215 struct ksz_device *dev = ds->priv; 216 217 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]); 218 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]); 219 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]); 220 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]); 221 } 222 223 static void write_table(struct dsa_switch *ds, u32 *table) 224 { 225 struct ksz_device *dev = ds->priv; 226 227 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]); 228 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]); 229 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]); 230 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]); 231 } 232 233 static int wait_alu_ready(struct ksz_device *dev, u32 waiton, int timeout) 234 { 235 u32 data; 236 237 do { 238 ksz_read32(dev, REG_SW_ALU_CTRL__4, &data); 239 if (!(data & waiton)) 240 break; 241 usleep_range(1, 10); 242 } while (timeout-- > 0); 243 244 if (timeout <= 0) 245 return -ETIMEDOUT; 246 247 return 0; 248 } 249 250 static int wait_alu_sta_ready(struct ksz_device *dev, u32 waiton, int timeout) 251 { 252 u32 data; 253 254 do { 255 ksz_read32(dev, REG_SW_ALU_STAT_CTRL__4, &data); 256 if (!(data & waiton)) 257 break; 258 usleep_range(1, 10); 259 } while (timeout-- > 0); 260 261 if (timeout <= 0) 262 return -ETIMEDOUT; 263 264 return 0; 265 } 266 267 static int ksz_reset_switch(struct dsa_switch *ds) 268 { 269 struct ksz_device *dev = ds->priv; 270 u8 data8; 271 u16 data16; 272 u32 data32; 273 274 /* reset switch */ 275 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 276 277 /* turn off SPI DO Edge select */ 278 ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 279 data8 &= ~SPI_AUTO_EDGE_DETECTION; 280 ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 281 282 /* default configuration */ 283 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8); 284 data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING | 285 SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE; 286 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8); 287 288 /* disable interrupts */ 289 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 290 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F); 291 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 292 293 /* set broadcast storm protection 10% rate */ 294 ksz_read16(dev, REG_SW_MAC_CTRL_2, &data16); 295 data16 &= ~BROADCAST_STORM_RATE; 296 data16 |= (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100; 297 ksz_write16(dev, REG_SW_MAC_CTRL_2, data16); 298 299 return 0; 300 } 301 302 static void port_setup(struct ksz_device *dev, int port, bool cpu_port) 303 { 304 u8 data8; 305 u16 data16; 306 307 /* enable tag tail for host port */ 308 if (cpu_port) 309 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE, 310 true); 311 312 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false); 313 314 /* set back pressure */ 315 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true); 316 317 /* set flow control */ 318 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 319 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, true); 320 321 /* enable broadcast storm limit */ 322 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 323 324 /* disable DiffServ priority */ 325 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false); 326 327 /* replace priority */ 328 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING, 329 false); 330 ksz_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4, 331 MTI_PVID_REPLACE, false); 332 333 /* enable 802.1p priority */ 334 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); 335 336 /* configure MAC to 1G & RGMII mode */ 337 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 338 data8 |= PORT_RGMII_ID_EG_ENABLE; 339 data8 &= ~PORT_MII_NOT_1GBIT; 340 data8 &= ~PORT_MII_SEL_M; 341 data8 |= PORT_RGMII_SEL; 342 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8); 343 344 /* clear pending interrupts */ 345 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16); 346 } 347 348 static void ksz_config_cpu_port(struct dsa_switch *ds) 349 { 350 struct ksz_device *dev = ds->priv; 351 int i; 352 353 ds->num_ports = dev->port_cnt; 354 355 for (i = 0; i < ds->num_ports; i++) { 356 if (dsa_is_cpu_port(ds, i) && (dev->cpu_ports & (1 << i))) { 357 dev->cpu_port = i; 358 359 /* enable cpu port */ 360 port_setup(dev, i, true); 361 } 362 } 363 } 364 365 static int ksz_setup(struct dsa_switch *ds) 366 { 367 struct ksz_device *dev = ds->priv; 368 int ret = 0; 369 370 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 371 dev->num_vlans, GFP_KERNEL); 372 if (!dev->vlan_cache) 373 return -ENOMEM; 374 375 ret = ksz_reset_switch(ds); 376 if (ret) { 377 dev_err(ds->dev, "failed to reset switch\n"); 378 return ret; 379 } 380 381 /* accept packet up to 2000bytes */ 382 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_LEGAL_PACKET_DISABLE, true); 383 384 ksz_config_cpu_port(ds); 385 386 ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true); 387 388 /* queue based egress rate limit */ 389 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true); 390 391 /* start switch */ 392 ksz_cfg(dev, REG_SW_OPERATION, SW_START, true); 393 394 return 0; 395 } 396 397 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 398 int port) 399 { 400 return DSA_TAG_PROTO_KSZ; 401 } 402 403 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 404 { 405 struct ksz_device *dev = ds->priv; 406 u16 val = 0; 407 408 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val); 409 410 return val; 411 } 412 413 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 414 { 415 struct ksz_device *dev = ds->priv; 416 417 ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val); 418 419 return 0; 420 } 421 422 static int ksz_enable_port(struct dsa_switch *ds, int port, 423 struct phy_device *phy) 424 { 425 struct ksz_device *dev = ds->priv; 426 427 /* setup slave port */ 428 port_setup(dev, port, false); 429 430 return 0; 431 } 432 433 static void ksz_disable_port(struct dsa_switch *ds, int port, 434 struct phy_device *phy) 435 { 436 struct ksz_device *dev = ds->priv; 437 438 /* there is no port disable */ 439 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, true); 440 } 441 442 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 443 { 444 if (sset != ETH_SS_STATS) 445 return 0; 446 447 return TOTAL_SWITCH_COUNTER_NUM; 448 } 449 450 static void ksz_get_strings(struct dsa_switch *ds, int port, 451 u32 stringset, uint8_t *buf) 452 { 453 int i; 454 455 if (stringset != ETH_SS_STATS) 456 return; 457 458 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) { 459 memcpy(buf + i * ETH_GSTRING_LEN, mib_names[i].string, 460 ETH_GSTRING_LEN); 461 } 462 } 463 464 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 465 uint64_t *buf) 466 { 467 struct ksz_device *dev = ds->priv; 468 int i; 469 u32 data; 470 int timeout; 471 472 mutex_lock(&dev->stats_mutex); 473 474 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) { 475 data = MIB_COUNTER_READ; 476 data |= ((mib_names[i].index & 0xFF) << MIB_COUNTER_INDEX_S); 477 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data); 478 479 timeout = 1000; 480 do { 481 ksz_pread32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 482 &data); 483 usleep_range(1, 10); 484 if (!(data & MIB_COUNTER_READ)) 485 break; 486 } while (timeout-- > 0); 487 488 /* failed to read MIB. get out of loop */ 489 if (!timeout) { 490 dev_dbg(dev->dev, "Failed to get MIB\n"); 491 break; 492 } 493 494 /* count resets upon read */ 495 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data); 496 497 dev->mib_value[i] += (uint64_t)data; 498 buf[i] = dev->mib_value[i]; 499 } 500 501 mutex_unlock(&dev->stats_mutex); 502 } 503 504 static void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 505 { 506 struct ksz_device *dev = ds->priv; 507 u8 data; 508 509 ksz_pread8(dev, port, P_STP_CTRL, &data); 510 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 511 512 switch (state) { 513 case BR_STATE_DISABLED: 514 data |= PORT_LEARN_DISABLE; 515 break; 516 case BR_STATE_LISTENING: 517 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 518 break; 519 case BR_STATE_LEARNING: 520 data |= PORT_RX_ENABLE; 521 break; 522 case BR_STATE_FORWARDING: 523 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 524 break; 525 case BR_STATE_BLOCKING: 526 data |= PORT_LEARN_DISABLE; 527 break; 528 default: 529 dev_err(ds->dev, "invalid STP state: %d\n", state); 530 return; 531 } 532 533 ksz_pwrite8(dev, port, P_STP_CTRL, data); 534 } 535 536 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 537 { 538 struct ksz_device *dev = ds->priv; 539 u8 data8; 540 541 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8); 542 data8 |= SW_FAST_AGING; 543 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8); 544 545 data8 &= ~SW_FAST_AGING; 546 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8); 547 } 548 549 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, bool flag) 550 { 551 struct ksz_device *dev = ds->priv; 552 553 if (flag) { 554 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 555 PORT_VLAN_LOOKUP_VID_0, true); 556 ksz_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, true); 557 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true); 558 } else { 559 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false); 560 ksz_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, false); 561 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 562 PORT_VLAN_LOOKUP_VID_0, false); 563 } 564 565 return 0; 566 } 567 568 static int ksz_port_vlan_prepare(struct dsa_switch *ds, int port, 569 const struct switchdev_obj_port_vlan *vlan) 570 { 571 /* nothing needed */ 572 573 return 0; 574 } 575 576 static void ksz_port_vlan_add(struct dsa_switch *ds, int port, 577 const struct switchdev_obj_port_vlan *vlan) 578 { 579 struct ksz_device *dev = ds->priv; 580 u32 vlan_table[3]; 581 u16 vid; 582 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 583 584 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 585 if (get_vlan_table(ds, vid, vlan_table)) { 586 dev_dbg(dev->dev, "Failed to get vlan table\n"); 587 return; 588 } 589 590 vlan_table[0] = VLAN_VALID | (vid & VLAN_FID_M); 591 if (untagged) 592 vlan_table[1] |= BIT(port); 593 else 594 vlan_table[1] &= ~BIT(port); 595 vlan_table[1] &= ~(BIT(dev->cpu_port)); 596 597 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port); 598 599 if (set_vlan_table(ds, vid, vlan_table)) { 600 dev_dbg(dev->dev, "Failed to set vlan table\n"); 601 return; 602 } 603 604 /* change PVID */ 605 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 606 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vid); 607 } 608 } 609 610 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 611 const struct switchdev_obj_port_vlan *vlan) 612 { 613 struct ksz_device *dev = ds->priv; 614 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 615 u32 vlan_table[3]; 616 u16 vid; 617 u16 pvid; 618 619 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid); 620 pvid = pvid & 0xFFF; 621 622 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 623 if (get_vlan_table(ds, vid, vlan_table)) { 624 dev_dbg(dev->dev, "Failed to get vlan table\n"); 625 return -ETIMEDOUT; 626 } 627 628 vlan_table[2] &= ~BIT(port); 629 630 if (pvid == vid) 631 pvid = 1; 632 633 if (untagged) 634 vlan_table[1] &= ~BIT(port); 635 636 if (set_vlan_table(ds, vid, vlan_table)) { 637 dev_dbg(dev->dev, "Failed to set vlan table\n"); 638 return -ETIMEDOUT; 639 } 640 } 641 642 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid); 643 644 return 0; 645 } 646 647 struct alu_struct { 648 /* entry 1 */ 649 u8 is_static:1; 650 u8 is_src_filter:1; 651 u8 is_dst_filter:1; 652 u8 prio_age:3; 653 u32 _reserv_0_1:23; 654 u8 mstp:3; 655 /* entry 2 */ 656 u8 is_override:1; 657 u8 is_use_fid:1; 658 u32 _reserv_1_1:23; 659 u8 port_forward:7; 660 /* entry 3 & 4*/ 661 u32 _reserv_2_1:9; 662 u8 fid:7; 663 u8 mac[ETH_ALEN]; 664 }; 665 666 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 667 const unsigned char *addr, u16 vid) 668 { 669 struct ksz_device *dev = ds->priv; 670 u32 alu_table[4]; 671 u32 data; 672 int ret = 0; 673 674 mutex_lock(&dev->alu_mutex); 675 676 /* find any entry with mac & vid */ 677 data = vid << ALU_FID_INDEX_S; 678 data |= ((addr[0] << 8) | addr[1]); 679 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 680 681 data = ((addr[2] << 24) | (addr[3] << 16)); 682 data |= ((addr[4] << 8) | addr[5]); 683 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 684 685 /* start read operation */ 686 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 687 688 /* wait to be finished */ 689 ret = wait_alu_ready(dev, ALU_START, 1000); 690 if (ret < 0) { 691 dev_dbg(dev->dev, "Failed to read ALU\n"); 692 goto exit; 693 } 694 695 /* read ALU entry */ 696 read_table(ds, alu_table); 697 698 /* update ALU entry */ 699 alu_table[0] = ALU_V_STATIC_VALID; 700 alu_table[1] |= BIT(port); 701 if (vid) 702 alu_table[1] |= ALU_V_USE_FID; 703 alu_table[2] = (vid << ALU_V_FID_S); 704 alu_table[2] |= ((addr[0] << 8) | addr[1]); 705 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16)); 706 alu_table[3] |= ((addr[4] << 8) | addr[5]); 707 708 write_table(ds, alu_table); 709 710 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 711 712 /* wait to be finished */ 713 ret = wait_alu_ready(dev, ALU_START, 1000); 714 if (ret < 0) 715 dev_dbg(dev->dev, "Failed to write ALU\n"); 716 717 exit: 718 mutex_unlock(&dev->alu_mutex); 719 720 return ret; 721 } 722 723 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 724 const unsigned char *addr, u16 vid) 725 { 726 struct ksz_device *dev = ds->priv; 727 u32 alu_table[4]; 728 u32 data; 729 int ret = 0; 730 731 mutex_lock(&dev->alu_mutex); 732 733 /* read any entry with mac & vid */ 734 data = vid << ALU_FID_INDEX_S; 735 data |= ((addr[0] << 8) | addr[1]); 736 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 737 738 data = ((addr[2] << 24) | (addr[3] << 16)); 739 data |= ((addr[4] << 8) | addr[5]); 740 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 741 742 /* start read operation */ 743 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 744 745 /* wait to be finished */ 746 ret = wait_alu_ready(dev, ALU_START, 1000); 747 if (ret < 0) { 748 dev_dbg(dev->dev, "Failed to read ALU\n"); 749 goto exit; 750 } 751 752 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]); 753 if (alu_table[0] & ALU_V_STATIC_VALID) { 754 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]); 755 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]); 756 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]); 757 758 /* clear forwarding port */ 759 alu_table[2] &= ~BIT(port); 760 761 /* if there is no port to forward, clear table */ 762 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) { 763 alu_table[0] = 0; 764 alu_table[1] = 0; 765 alu_table[2] = 0; 766 alu_table[3] = 0; 767 } 768 } else { 769 alu_table[0] = 0; 770 alu_table[1] = 0; 771 alu_table[2] = 0; 772 alu_table[3] = 0; 773 } 774 775 write_table(ds, alu_table); 776 777 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 778 779 /* wait to be finished */ 780 ret = wait_alu_ready(dev, ALU_START, 1000); 781 if (ret < 0) 782 dev_dbg(dev->dev, "Failed to write ALU\n"); 783 784 exit: 785 mutex_unlock(&dev->alu_mutex); 786 787 return ret; 788 } 789 790 static void convert_alu(struct alu_struct *alu, u32 *alu_table) 791 { 792 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID); 793 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER); 794 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER); 795 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) & 796 ALU_V_PRIO_AGE_CNT_M; 797 alu->mstp = alu_table[0] & ALU_V_MSTP_M; 798 799 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE); 800 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID); 801 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP; 802 803 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M; 804 805 alu->mac[0] = (alu_table[2] >> 8) & 0xFF; 806 alu->mac[1] = alu_table[2] & 0xFF; 807 alu->mac[2] = (alu_table[3] >> 24) & 0xFF; 808 alu->mac[3] = (alu_table[3] >> 16) & 0xFF; 809 alu->mac[4] = (alu_table[3] >> 8) & 0xFF; 810 alu->mac[5] = alu_table[3] & 0xFF; 811 } 812 813 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 814 dsa_fdb_dump_cb_t *cb, void *data) 815 { 816 struct ksz_device *dev = ds->priv; 817 int ret = 0; 818 u32 ksz_data; 819 u32 alu_table[4]; 820 struct alu_struct alu; 821 int timeout; 822 823 mutex_lock(&dev->alu_mutex); 824 825 /* start ALU search */ 826 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH); 827 828 do { 829 timeout = 1000; 830 do { 831 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data); 832 if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START)) 833 break; 834 usleep_range(1, 10); 835 } while (timeout-- > 0); 836 837 if (!timeout) { 838 dev_dbg(dev->dev, "Failed to search ALU\n"); 839 ret = -ETIMEDOUT; 840 goto exit; 841 } 842 843 /* read ALU table */ 844 read_table(ds, alu_table); 845 846 convert_alu(&alu, alu_table); 847 848 if (alu.port_forward & BIT(port)) { 849 ret = cb(alu.mac, alu.fid, alu.is_static, data); 850 if (ret) 851 goto exit; 852 } 853 } while (ksz_data & ALU_START); 854 855 exit: 856 857 /* stop ALU search */ 858 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0); 859 860 mutex_unlock(&dev->alu_mutex); 861 862 return ret; 863 } 864 865 static int ksz_port_mdb_prepare(struct dsa_switch *ds, int port, 866 const struct switchdev_obj_port_mdb *mdb) 867 { 868 /* nothing to do */ 869 return 0; 870 } 871 872 static void ksz_port_mdb_add(struct dsa_switch *ds, int port, 873 const struct switchdev_obj_port_mdb *mdb) 874 { 875 struct ksz_device *dev = ds->priv; 876 u32 static_table[4]; 877 u32 data; 878 int index; 879 u32 mac_hi, mac_lo; 880 881 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 882 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 883 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 884 885 mutex_lock(&dev->alu_mutex); 886 887 for (index = 0; index < dev->num_statics; index++) { 888 /* find empty slot first */ 889 data = (index << ALU_STAT_INDEX_S) | 890 ALU_STAT_READ | ALU_STAT_START; 891 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 892 893 /* wait to be finished */ 894 if (wait_alu_sta_ready(dev, ALU_STAT_START, 1000) < 0) { 895 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 896 goto exit; 897 } 898 899 /* read ALU static table */ 900 read_table(ds, static_table); 901 902 if (static_table[0] & ALU_V_STATIC_VALID) { 903 /* check this has same vid & mac address */ 904 if (((static_table[2] >> ALU_V_FID_S) == (mdb->vid)) && 905 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 906 (static_table[3] == mac_lo)) { 907 /* found matching one */ 908 break; 909 } 910 } else { 911 /* found empty one */ 912 break; 913 } 914 } 915 916 /* no available entry */ 917 if (index == dev->num_statics) 918 goto exit; 919 920 /* add entry */ 921 static_table[0] = ALU_V_STATIC_VALID; 922 static_table[1] |= BIT(port); 923 if (mdb->vid) 924 static_table[1] |= ALU_V_USE_FID; 925 static_table[2] = (mdb->vid << ALU_V_FID_S); 926 static_table[2] |= mac_hi; 927 static_table[3] = mac_lo; 928 929 write_table(ds, static_table); 930 931 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 932 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 933 934 /* wait to be finished */ 935 if (wait_alu_sta_ready(dev, ALU_STAT_START, 1000) < 0) 936 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 937 938 exit: 939 mutex_unlock(&dev->alu_mutex); 940 } 941 942 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 943 const struct switchdev_obj_port_mdb *mdb) 944 { 945 struct ksz_device *dev = ds->priv; 946 u32 static_table[4]; 947 u32 data; 948 int index; 949 int ret = 0; 950 u32 mac_hi, mac_lo; 951 952 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 953 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 954 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 955 956 mutex_lock(&dev->alu_mutex); 957 958 for (index = 0; index < dev->num_statics; index++) { 959 /* find empty slot first */ 960 data = (index << ALU_STAT_INDEX_S) | 961 ALU_STAT_READ | ALU_STAT_START; 962 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 963 964 /* wait to be finished */ 965 ret = wait_alu_sta_ready(dev, ALU_STAT_START, 1000); 966 if (ret < 0) { 967 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 968 goto exit; 969 } 970 971 /* read ALU static table */ 972 read_table(ds, static_table); 973 974 if (static_table[0] & ALU_V_STATIC_VALID) { 975 /* check this has same vid & mac address */ 976 977 if (((static_table[2] >> ALU_V_FID_S) == (mdb->vid)) && 978 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 979 (static_table[3] == mac_lo)) { 980 /* found matching one */ 981 break; 982 } 983 } 984 } 985 986 /* no available entry */ 987 if (index == dev->num_statics) { 988 ret = -EINVAL; 989 goto exit; 990 } 991 992 /* clear port */ 993 static_table[1] &= ~BIT(port); 994 995 if ((static_table[1] & ALU_V_PORT_MAP) == 0) { 996 /* delete entry */ 997 static_table[0] = 0; 998 static_table[1] = 0; 999 static_table[2] = 0; 1000 static_table[3] = 0; 1001 } 1002 1003 write_table(ds, static_table); 1004 1005 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 1006 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 1007 1008 /* wait to be finished */ 1009 ret = wait_alu_sta_ready(dev, ALU_STAT_START, 1000); 1010 if (ret < 0) 1011 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 1012 1013 exit: 1014 mutex_unlock(&dev->alu_mutex); 1015 1016 return ret; 1017 } 1018 1019 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 1020 struct dsa_mall_mirror_tc_entry *mirror, 1021 bool ingress) 1022 { 1023 struct ksz_device *dev = ds->priv; 1024 1025 if (ingress) 1026 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 1027 else 1028 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 1029 1030 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false); 1031 1032 /* configure mirror port */ 1033 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1034 PORT_MIRROR_SNIFFER, true); 1035 1036 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 1037 1038 return 0; 1039 } 1040 1041 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 1042 struct dsa_mall_mirror_tc_entry *mirror) 1043 { 1044 struct ksz_device *dev = ds->priv; 1045 u8 data; 1046 1047 if (mirror->ingress) 1048 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 1049 else 1050 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 1051 1052 ksz_pread8(dev, port, P_MIRROR_CTRL, &data); 1053 1054 if (!(data & (PORT_MIRROR_RX | PORT_MIRROR_TX))) 1055 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1056 PORT_MIRROR_SNIFFER, false); 1057 } 1058 1059 static const struct dsa_switch_ops ksz_switch_ops = { 1060 .get_tag_protocol = ksz_get_tag_protocol, 1061 .setup = ksz_setup, 1062 .phy_read = ksz_phy_read16, 1063 .phy_write = ksz_phy_write16, 1064 .port_enable = ksz_enable_port, 1065 .port_disable = ksz_disable_port, 1066 .get_strings = ksz_get_strings, 1067 .get_ethtool_stats = ksz_get_ethtool_stats, 1068 .get_sset_count = ksz_sset_count, 1069 .port_stp_state_set = ksz_port_stp_state_set, 1070 .port_fast_age = ksz_port_fast_age, 1071 .port_vlan_filtering = ksz_port_vlan_filtering, 1072 .port_vlan_prepare = ksz_port_vlan_prepare, 1073 .port_vlan_add = ksz_port_vlan_add, 1074 .port_vlan_del = ksz_port_vlan_del, 1075 .port_fdb_dump = ksz_port_fdb_dump, 1076 .port_fdb_add = ksz_port_fdb_add, 1077 .port_fdb_del = ksz_port_fdb_del, 1078 .port_mdb_prepare = ksz_port_mdb_prepare, 1079 .port_mdb_add = ksz_port_mdb_add, 1080 .port_mdb_del = ksz_port_mdb_del, 1081 .port_mirror_add = ksz_port_mirror_add, 1082 .port_mirror_del = ksz_port_mirror_del, 1083 }; 1084 1085 struct ksz_chip_data { 1086 u32 chip_id; 1087 const char *dev_name; 1088 int num_vlans; 1089 int num_alus; 1090 int num_statics; 1091 int cpu_ports; 1092 int port_cnt; 1093 }; 1094 1095 static const struct ksz_chip_data ksz_switch_chips[] = { 1096 { 1097 .chip_id = 0x00947700, 1098 .dev_name = "KSZ9477", 1099 .num_vlans = 4096, 1100 .num_alus = 4096, 1101 .num_statics = 16, 1102 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1103 .port_cnt = 7, /* total physical port count */ 1104 }, 1105 { 1106 .chip_id = 0x00989700, 1107 .dev_name = "KSZ9897", 1108 .num_vlans = 4096, 1109 .num_alus = 4096, 1110 .num_statics = 16, 1111 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1112 .port_cnt = 7, /* total physical port count */ 1113 }, 1114 }; 1115 1116 static int ksz_switch_init(struct ksz_device *dev) 1117 { 1118 int i; 1119 1120 mutex_init(&dev->reg_mutex); 1121 mutex_init(&dev->stats_mutex); 1122 mutex_init(&dev->alu_mutex); 1123 mutex_init(&dev->vlan_mutex); 1124 1125 dev->ds->ops = &ksz_switch_ops; 1126 1127 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 1128 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 1129 1130 if (dev->chip_id == chip->chip_id) { 1131 dev->name = chip->dev_name; 1132 dev->num_vlans = chip->num_vlans; 1133 dev->num_alus = chip->num_alus; 1134 dev->num_statics = chip->num_statics; 1135 dev->port_cnt = chip->port_cnt; 1136 dev->cpu_ports = chip->cpu_ports; 1137 1138 break; 1139 } 1140 } 1141 1142 /* no switch found */ 1143 if (!dev->port_cnt) 1144 return -ENODEV; 1145 1146 return 0; 1147 } 1148 1149 struct ksz_device *ksz_switch_alloc(struct device *base, 1150 const struct ksz_io_ops *ops, 1151 void *priv) 1152 { 1153 struct dsa_switch *ds; 1154 struct ksz_device *swdev; 1155 1156 ds = dsa_switch_alloc(base, DSA_MAX_PORTS); 1157 if (!ds) 1158 return NULL; 1159 1160 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 1161 if (!swdev) 1162 return NULL; 1163 1164 ds->priv = swdev; 1165 swdev->dev = base; 1166 1167 swdev->ds = ds; 1168 swdev->priv = priv; 1169 swdev->ops = ops; 1170 1171 return swdev; 1172 } 1173 EXPORT_SYMBOL(ksz_switch_alloc); 1174 1175 int ksz_switch_detect(struct ksz_device *dev) 1176 { 1177 u8 data8; 1178 u32 id32; 1179 int ret; 1180 1181 /* turn off SPI DO Edge select */ 1182 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 1183 if (ret) 1184 return ret; 1185 1186 data8 &= ~SPI_AUTO_EDGE_DETECTION; 1187 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 1188 if (ret) 1189 return ret; 1190 1191 /* read chip id */ 1192 ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32); 1193 if (ret) 1194 return ret; 1195 1196 dev->chip_id = id32; 1197 1198 return 0; 1199 } 1200 EXPORT_SYMBOL(ksz_switch_detect); 1201 1202 int ksz_switch_register(struct ksz_device *dev) 1203 { 1204 int ret; 1205 1206 if (dev->pdata) 1207 dev->chip_id = dev->pdata->chip_id; 1208 1209 if (ksz_switch_detect(dev)) 1210 return -EINVAL; 1211 1212 ret = ksz_switch_init(dev); 1213 if (ret) 1214 return ret; 1215 1216 return dsa_register_switch(dev->ds); 1217 } 1218 EXPORT_SYMBOL(ksz_switch_register); 1219 1220 void ksz_switch_remove(struct ksz_device *dev) 1221 { 1222 dsa_unregister_switch(dev->ds); 1223 } 1224 EXPORT_SYMBOL(ksz_switch_remove); 1225 1226 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 1227 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 1228 MODULE_LICENSE("GPL"); 1229