1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/export.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/platform_data/microchip-ksz.h> 14 #include <linux/phy.h> 15 #include <linux/etherdevice.h> 16 #include <linux/if_bridge.h> 17 #include <linux/of_device.h> 18 #include <linux/of_net.h> 19 #include <linux/micrel_phy.h> 20 #include <net/dsa.h> 21 #include <net/switchdev.h> 22 23 #include "ksz_common.h" 24 #include "ksz8.h" 25 #include "ksz9477.h" 26 #include "lan937x.h" 27 28 #define MIB_COUNTER_NUM 0x20 29 30 struct ksz_stats_raw { 31 u64 rx_hi; 32 u64 rx_undersize; 33 u64 rx_fragments; 34 u64 rx_oversize; 35 u64 rx_jabbers; 36 u64 rx_symbol_err; 37 u64 rx_crc_err; 38 u64 rx_align_err; 39 u64 rx_mac_ctrl; 40 u64 rx_pause; 41 u64 rx_bcast; 42 u64 rx_mcast; 43 u64 rx_ucast; 44 u64 rx_64_or_less; 45 u64 rx_65_127; 46 u64 rx_128_255; 47 u64 rx_256_511; 48 u64 rx_512_1023; 49 u64 rx_1024_1522; 50 u64 rx_1523_2000; 51 u64 rx_2001; 52 u64 tx_hi; 53 u64 tx_late_col; 54 u64 tx_pause; 55 u64 tx_bcast; 56 u64 tx_mcast; 57 u64 tx_ucast; 58 u64 tx_deferred; 59 u64 tx_total_col; 60 u64 tx_exc_col; 61 u64 tx_single_col; 62 u64 tx_mult_col; 63 u64 rx_total; 64 u64 tx_total; 65 u64 rx_discards; 66 u64 tx_discards; 67 }; 68 69 static const struct ksz_mib_names ksz88xx_mib_names[] = { 70 { 0x00, "rx" }, 71 { 0x01, "rx_hi" }, 72 { 0x02, "rx_undersize" }, 73 { 0x03, "rx_fragments" }, 74 { 0x04, "rx_oversize" }, 75 { 0x05, "rx_jabbers" }, 76 { 0x06, "rx_symbol_err" }, 77 { 0x07, "rx_crc_err" }, 78 { 0x08, "rx_align_err" }, 79 { 0x09, "rx_mac_ctrl" }, 80 { 0x0a, "rx_pause" }, 81 { 0x0b, "rx_bcast" }, 82 { 0x0c, "rx_mcast" }, 83 { 0x0d, "rx_ucast" }, 84 { 0x0e, "rx_64_or_less" }, 85 { 0x0f, "rx_65_127" }, 86 { 0x10, "rx_128_255" }, 87 { 0x11, "rx_256_511" }, 88 { 0x12, "rx_512_1023" }, 89 { 0x13, "rx_1024_1522" }, 90 { 0x14, "tx" }, 91 { 0x15, "tx_hi" }, 92 { 0x16, "tx_late_col" }, 93 { 0x17, "tx_pause" }, 94 { 0x18, "tx_bcast" }, 95 { 0x19, "tx_mcast" }, 96 { 0x1a, "tx_ucast" }, 97 { 0x1b, "tx_deferred" }, 98 { 0x1c, "tx_total_col" }, 99 { 0x1d, "tx_exc_col" }, 100 { 0x1e, "tx_single_col" }, 101 { 0x1f, "tx_mult_col" }, 102 { 0x100, "rx_discards" }, 103 { 0x101, "tx_discards" }, 104 }; 105 106 static const struct ksz_mib_names ksz9477_mib_names[] = { 107 { 0x00, "rx_hi" }, 108 { 0x01, "rx_undersize" }, 109 { 0x02, "rx_fragments" }, 110 { 0x03, "rx_oversize" }, 111 { 0x04, "rx_jabbers" }, 112 { 0x05, "rx_symbol_err" }, 113 { 0x06, "rx_crc_err" }, 114 { 0x07, "rx_align_err" }, 115 { 0x08, "rx_mac_ctrl" }, 116 { 0x09, "rx_pause" }, 117 { 0x0A, "rx_bcast" }, 118 { 0x0B, "rx_mcast" }, 119 { 0x0C, "rx_ucast" }, 120 { 0x0D, "rx_64_or_less" }, 121 { 0x0E, "rx_65_127" }, 122 { 0x0F, "rx_128_255" }, 123 { 0x10, "rx_256_511" }, 124 { 0x11, "rx_512_1023" }, 125 { 0x12, "rx_1024_1522" }, 126 { 0x13, "rx_1523_2000" }, 127 { 0x14, "rx_2001" }, 128 { 0x15, "tx_hi" }, 129 { 0x16, "tx_late_col" }, 130 { 0x17, "tx_pause" }, 131 { 0x18, "tx_bcast" }, 132 { 0x19, "tx_mcast" }, 133 { 0x1A, "tx_ucast" }, 134 { 0x1B, "tx_deferred" }, 135 { 0x1C, "tx_total_col" }, 136 { 0x1D, "tx_exc_col" }, 137 { 0x1E, "tx_single_col" }, 138 { 0x1F, "tx_mult_col" }, 139 { 0x80, "rx_total" }, 140 { 0x81, "tx_total" }, 141 { 0x82, "rx_discards" }, 142 { 0x83, "tx_discards" }, 143 }; 144 145 static const struct ksz_dev_ops ksz8_dev_ops = { 146 .setup = ksz8_setup, 147 .get_port_addr = ksz8_get_port_addr, 148 .cfg_port_member = ksz8_cfg_port_member, 149 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 150 .port_setup = ksz8_port_setup, 151 .r_phy = ksz8_r_phy, 152 .w_phy = ksz8_w_phy, 153 .r_mib_cnt = ksz8_r_mib_cnt, 154 .r_mib_pkt = ksz8_r_mib_pkt, 155 .freeze_mib = ksz8_freeze_mib, 156 .port_init_cnt = ksz8_port_init_cnt, 157 .fdb_dump = ksz8_fdb_dump, 158 .mdb_add = ksz8_mdb_add, 159 .mdb_del = ksz8_mdb_del, 160 .vlan_filtering = ksz8_port_vlan_filtering, 161 .vlan_add = ksz8_port_vlan_add, 162 .vlan_del = ksz8_port_vlan_del, 163 .mirror_add = ksz8_port_mirror_add, 164 .mirror_del = ksz8_port_mirror_del, 165 .get_caps = ksz8_get_caps, 166 .config_cpu_port = ksz8_config_cpu_port, 167 .enable_stp_addr = ksz8_enable_stp_addr, 168 .reset = ksz8_reset_switch, 169 .init = ksz8_switch_init, 170 .exit = ksz8_switch_exit, 171 }; 172 173 static const struct ksz_dev_ops ksz9477_dev_ops = { 174 .setup = ksz9477_setup, 175 .get_port_addr = ksz9477_get_port_addr, 176 .cfg_port_member = ksz9477_cfg_port_member, 177 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 178 .port_setup = ksz9477_port_setup, 179 .r_phy = ksz9477_r_phy, 180 .w_phy = ksz9477_w_phy, 181 .r_mib_cnt = ksz9477_r_mib_cnt, 182 .r_mib_pkt = ksz9477_r_mib_pkt, 183 .r_mib_stat64 = ksz_r_mib_stats64, 184 .freeze_mib = ksz9477_freeze_mib, 185 .port_init_cnt = ksz9477_port_init_cnt, 186 .vlan_filtering = ksz9477_port_vlan_filtering, 187 .vlan_add = ksz9477_port_vlan_add, 188 .vlan_del = ksz9477_port_vlan_del, 189 .mirror_add = ksz9477_port_mirror_add, 190 .mirror_del = ksz9477_port_mirror_del, 191 .get_caps = ksz9477_get_caps, 192 .fdb_dump = ksz9477_fdb_dump, 193 .fdb_add = ksz9477_fdb_add, 194 .fdb_del = ksz9477_fdb_del, 195 .mdb_add = ksz9477_mdb_add, 196 .mdb_del = ksz9477_mdb_del, 197 .change_mtu = ksz9477_change_mtu, 198 .max_mtu = ksz9477_max_mtu, 199 .config_cpu_port = ksz9477_config_cpu_port, 200 .enable_stp_addr = ksz9477_enable_stp_addr, 201 .reset = ksz9477_reset_switch, 202 .init = ksz9477_switch_init, 203 .exit = ksz9477_switch_exit, 204 }; 205 206 static const struct ksz_dev_ops lan937x_dev_ops = { 207 .setup = lan937x_setup, 208 .get_port_addr = ksz9477_get_port_addr, 209 .cfg_port_member = ksz9477_cfg_port_member, 210 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 211 .port_setup = lan937x_port_setup, 212 .r_phy = lan937x_r_phy, 213 .w_phy = lan937x_w_phy, 214 .r_mib_cnt = ksz9477_r_mib_cnt, 215 .r_mib_pkt = ksz9477_r_mib_pkt, 216 .r_mib_stat64 = ksz_r_mib_stats64, 217 .freeze_mib = ksz9477_freeze_mib, 218 .port_init_cnt = ksz9477_port_init_cnt, 219 .vlan_filtering = ksz9477_port_vlan_filtering, 220 .vlan_add = ksz9477_port_vlan_add, 221 .vlan_del = ksz9477_port_vlan_del, 222 .mirror_add = ksz9477_port_mirror_add, 223 .mirror_del = ksz9477_port_mirror_del, 224 .get_caps = lan937x_phylink_get_caps, 225 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 226 .fdb_dump = ksz9477_fdb_dump, 227 .fdb_add = ksz9477_fdb_add, 228 .fdb_del = ksz9477_fdb_del, 229 .mdb_add = ksz9477_mdb_add, 230 .mdb_del = ksz9477_mdb_del, 231 .change_mtu = lan937x_change_mtu, 232 .max_mtu = ksz9477_max_mtu, 233 .config_cpu_port = lan937x_config_cpu_port, 234 .enable_stp_addr = ksz9477_enable_stp_addr, 235 .reset = lan937x_reset_switch, 236 .init = lan937x_switch_init, 237 .exit = lan937x_switch_exit, 238 }; 239 240 static const u16 ksz8795_regs[] = { 241 [REG_IND_CTRL_0] = 0x6E, 242 [REG_IND_DATA_8] = 0x70, 243 [REG_IND_DATA_CHECK] = 0x72, 244 [REG_IND_DATA_HI] = 0x71, 245 [REG_IND_DATA_LO] = 0x75, 246 [REG_IND_MIB_CHECK] = 0x74, 247 [REG_IND_BYTE] = 0xA0, 248 [P_FORCE_CTRL] = 0x0C, 249 [P_LINK_STATUS] = 0x0E, 250 [P_LOCAL_CTRL] = 0x07, 251 [P_NEG_RESTART_CTRL] = 0x0D, 252 [P_REMOTE_STATUS] = 0x08, 253 [P_SPEED_STATUS] = 0x09, 254 [S_TAIL_TAG_CTRL] = 0x0C, 255 [P_STP_CTRL] = 0x02, 256 [S_START_CTRL] = 0x01, 257 [S_BROADCAST_CTRL] = 0x06, 258 [S_MULTICAST_CTRL] = 0x04, 259 [P_XMII_CTRL_0] = 0x06, 260 [P_XMII_CTRL_1] = 0x56, 261 }; 262 263 static const u32 ksz8795_masks[] = { 264 [PORT_802_1P_REMAPPING] = BIT(7), 265 [SW_TAIL_TAG_ENABLE] = BIT(1), 266 [MIB_COUNTER_OVERFLOW] = BIT(6), 267 [MIB_COUNTER_VALID] = BIT(5), 268 [VLAN_TABLE_FID] = GENMASK(6, 0), 269 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 270 [VLAN_TABLE_VALID] = BIT(12), 271 [STATIC_MAC_TABLE_VALID] = BIT(21), 272 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 273 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 274 [STATIC_MAC_TABLE_OVERRIDE] = BIT(26), 275 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(24, 20), 276 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 277 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(8), 278 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 279 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 280 [DYNAMIC_MAC_TABLE_FID] = GENMASK(26, 20), 281 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 282 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 283 [P_MII_TX_FLOW_CTRL] = BIT(5), 284 [P_MII_RX_FLOW_CTRL] = BIT(5), 285 }; 286 287 static const u8 ksz8795_xmii_ctrl0[] = { 288 [P_MII_100MBIT] = 0, 289 [P_MII_10MBIT] = 1, 290 [P_MII_FULL_DUPLEX] = 0, 291 [P_MII_HALF_DUPLEX] = 1, 292 }; 293 294 static const u8 ksz8795_xmii_ctrl1[] = { 295 [P_RGMII_SEL] = 3, 296 [P_GMII_SEL] = 2, 297 [P_RMII_SEL] = 1, 298 [P_MII_SEL] = 0, 299 [P_GMII_1GBIT] = 1, 300 [P_GMII_NOT_1GBIT] = 0, 301 }; 302 303 static const u8 ksz8795_shifts[] = { 304 [VLAN_TABLE_MEMBERSHIP_S] = 7, 305 [VLAN_TABLE] = 16, 306 [STATIC_MAC_FWD_PORTS] = 16, 307 [STATIC_MAC_FID] = 24, 308 [DYNAMIC_MAC_ENTRIES_H] = 3, 309 [DYNAMIC_MAC_ENTRIES] = 29, 310 [DYNAMIC_MAC_FID] = 16, 311 [DYNAMIC_MAC_TIMESTAMP] = 27, 312 [DYNAMIC_MAC_SRC_PORT] = 24, 313 }; 314 315 static const u16 ksz8863_regs[] = { 316 [REG_IND_CTRL_0] = 0x79, 317 [REG_IND_DATA_8] = 0x7B, 318 [REG_IND_DATA_CHECK] = 0x7B, 319 [REG_IND_DATA_HI] = 0x7C, 320 [REG_IND_DATA_LO] = 0x80, 321 [REG_IND_MIB_CHECK] = 0x80, 322 [P_FORCE_CTRL] = 0x0C, 323 [P_LINK_STATUS] = 0x0E, 324 [P_LOCAL_CTRL] = 0x0C, 325 [P_NEG_RESTART_CTRL] = 0x0D, 326 [P_REMOTE_STATUS] = 0x0E, 327 [P_SPEED_STATUS] = 0x0F, 328 [S_TAIL_TAG_CTRL] = 0x03, 329 [P_STP_CTRL] = 0x02, 330 [S_START_CTRL] = 0x01, 331 [S_BROADCAST_CTRL] = 0x06, 332 [S_MULTICAST_CTRL] = 0x04, 333 }; 334 335 static const u32 ksz8863_masks[] = { 336 [PORT_802_1P_REMAPPING] = BIT(3), 337 [SW_TAIL_TAG_ENABLE] = BIT(6), 338 [MIB_COUNTER_OVERFLOW] = BIT(7), 339 [MIB_COUNTER_VALID] = BIT(6), 340 [VLAN_TABLE_FID] = GENMASK(15, 12), 341 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 342 [VLAN_TABLE_VALID] = BIT(19), 343 [STATIC_MAC_TABLE_VALID] = BIT(19), 344 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 345 [STATIC_MAC_TABLE_FID] = GENMASK(29, 26), 346 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 347 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 348 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(5, 0), 349 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 350 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 351 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 28), 352 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 353 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 354 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 355 }; 356 357 static u8 ksz8863_shifts[] = { 358 [VLAN_TABLE_MEMBERSHIP_S] = 16, 359 [STATIC_MAC_FWD_PORTS] = 16, 360 [STATIC_MAC_FID] = 22, 361 [DYNAMIC_MAC_ENTRIES_H] = 3, 362 [DYNAMIC_MAC_ENTRIES] = 24, 363 [DYNAMIC_MAC_FID] = 16, 364 [DYNAMIC_MAC_TIMESTAMP] = 24, 365 [DYNAMIC_MAC_SRC_PORT] = 20, 366 }; 367 368 static const u16 ksz9477_regs[] = { 369 [P_STP_CTRL] = 0x0B04, 370 [S_START_CTRL] = 0x0300, 371 [S_BROADCAST_CTRL] = 0x0332, 372 [S_MULTICAST_CTRL] = 0x0331, 373 [P_XMII_CTRL_0] = 0x0300, 374 [P_XMII_CTRL_1] = 0x0301, 375 }; 376 377 static const u32 ksz9477_masks[] = { 378 [ALU_STAT_WRITE] = 0, 379 [ALU_STAT_READ] = 1, 380 [P_MII_TX_FLOW_CTRL] = BIT(5), 381 [P_MII_RX_FLOW_CTRL] = BIT(3), 382 }; 383 384 static const u8 ksz9477_shifts[] = { 385 [ALU_STAT_INDEX] = 16, 386 }; 387 388 static const u8 ksz9477_xmii_ctrl0[] = { 389 [P_MII_100MBIT] = 1, 390 [P_MII_10MBIT] = 0, 391 [P_MII_FULL_DUPLEX] = 1, 392 [P_MII_HALF_DUPLEX] = 0, 393 }; 394 395 static const u8 ksz9477_xmii_ctrl1[] = { 396 [P_RGMII_SEL] = 0, 397 [P_RMII_SEL] = 1, 398 [P_GMII_SEL] = 2, 399 [P_MII_SEL] = 3, 400 [P_GMII_1GBIT] = 0, 401 [P_GMII_NOT_1GBIT] = 1, 402 }; 403 404 static const u32 lan937x_masks[] = { 405 [ALU_STAT_WRITE] = 1, 406 [ALU_STAT_READ] = 2, 407 [P_MII_TX_FLOW_CTRL] = BIT(5), 408 [P_MII_RX_FLOW_CTRL] = BIT(3), 409 }; 410 411 static const u8 lan937x_shifts[] = { 412 [ALU_STAT_INDEX] = 8, 413 }; 414 415 const struct ksz_chip_data ksz_switch_chips[] = { 416 [KSZ8795] = { 417 .chip_id = KSZ8795_CHIP_ID, 418 .dev_name = "KSZ8795", 419 .num_vlans = 4096, 420 .num_alus = 0, 421 .num_statics = 8, 422 .cpu_ports = 0x10, /* can be configured as cpu port */ 423 .port_cnt = 5, /* total cpu and user ports */ 424 .ops = &ksz8_dev_ops, 425 .ksz87xx_eee_link_erratum = true, 426 .mib_names = ksz9477_mib_names, 427 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 428 .reg_mib_cnt = MIB_COUNTER_NUM, 429 .regs = ksz8795_regs, 430 .masks = ksz8795_masks, 431 .shifts = ksz8795_shifts, 432 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 433 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 434 .supports_mii = {false, false, false, false, true}, 435 .supports_rmii = {false, false, false, false, true}, 436 .supports_rgmii = {false, false, false, false, true}, 437 .internal_phy = {true, true, true, true, false}, 438 }, 439 440 [KSZ8794] = { 441 /* WARNING 442 * ======= 443 * KSZ8794 is similar to KSZ8795, except the port map 444 * contains a gap between external and CPU ports, the 445 * port map is NOT continuous. The per-port register 446 * map is shifted accordingly too, i.e. registers at 447 * offset 0x40 are NOT used on KSZ8794 and they ARE 448 * used on KSZ8795 for external port 3. 449 * external cpu 450 * KSZ8794 0,1,2 4 451 * KSZ8795 0,1,2,3 4 452 * KSZ8765 0,1,2,3 4 453 * port_cnt is configured as 5, even though it is 4 454 */ 455 .chip_id = KSZ8794_CHIP_ID, 456 .dev_name = "KSZ8794", 457 .num_vlans = 4096, 458 .num_alus = 0, 459 .num_statics = 8, 460 .cpu_ports = 0x10, /* can be configured as cpu port */ 461 .port_cnt = 5, /* total cpu and user ports */ 462 .ops = &ksz8_dev_ops, 463 .ksz87xx_eee_link_erratum = true, 464 .mib_names = ksz9477_mib_names, 465 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 466 .reg_mib_cnt = MIB_COUNTER_NUM, 467 .regs = ksz8795_regs, 468 .masks = ksz8795_masks, 469 .shifts = ksz8795_shifts, 470 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 471 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 472 .supports_mii = {false, false, false, false, true}, 473 .supports_rmii = {false, false, false, false, true}, 474 .supports_rgmii = {false, false, false, false, true}, 475 .internal_phy = {true, true, true, false, false}, 476 }, 477 478 [KSZ8765] = { 479 .chip_id = KSZ8765_CHIP_ID, 480 .dev_name = "KSZ8765", 481 .num_vlans = 4096, 482 .num_alus = 0, 483 .num_statics = 8, 484 .cpu_ports = 0x10, /* can be configured as cpu port */ 485 .port_cnt = 5, /* total cpu and user ports */ 486 .ops = &ksz8_dev_ops, 487 .ksz87xx_eee_link_erratum = true, 488 .mib_names = ksz9477_mib_names, 489 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 490 .reg_mib_cnt = MIB_COUNTER_NUM, 491 .regs = ksz8795_regs, 492 .masks = ksz8795_masks, 493 .shifts = ksz8795_shifts, 494 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 495 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 496 .supports_mii = {false, false, false, false, true}, 497 .supports_rmii = {false, false, false, false, true}, 498 .supports_rgmii = {false, false, false, false, true}, 499 .internal_phy = {true, true, true, true, false}, 500 }, 501 502 [KSZ8830] = { 503 .chip_id = KSZ8830_CHIP_ID, 504 .dev_name = "KSZ8863/KSZ8873", 505 .num_vlans = 16, 506 .num_alus = 0, 507 .num_statics = 8, 508 .cpu_ports = 0x4, /* can be configured as cpu port */ 509 .port_cnt = 3, 510 .ops = &ksz8_dev_ops, 511 .mib_names = ksz88xx_mib_names, 512 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 513 .reg_mib_cnt = MIB_COUNTER_NUM, 514 .regs = ksz8863_regs, 515 .masks = ksz8863_masks, 516 .shifts = ksz8863_shifts, 517 .supports_mii = {false, false, true}, 518 .supports_rmii = {false, false, true}, 519 .internal_phy = {true, true, false}, 520 }, 521 522 [KSZ9477] = { 523 .chip_id = KSZ9477_CHIP_ID, 524 .dev_name = "KSZ9477", 525 .num_vlans = 4096, 526 .num_alus = 4096, 527 .num_statics = 16, 528 .cpu_ports = 0x7F, /* can be configured as cpu port */ 529 .port_cnt = 7, /* total physical port count */ 530 .ops = &ksz9477_dev_ops, 531 .phy_errata_9477 = true, 532 .mib_names = ksz9477_mib_names, 533 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 534 .reg_mib_cnt = MIB_COUNTER_NUM, 535 .regs = ksz9477_regs, 536 .masks = ksz9477_masks, 537 .shifts = ksz9477_shifts, 538 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 539 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 540 .supports_mii = {false, false, false, false, 541 false, true, false}, 542 .supports_rmii = {false, false, false, false, 543 false, true, false}, 544 .supports_rgmii = {false, false, false, false, 545 false, true, false}, 546 .internal_phy = {true, true, true, true, 547 true, false, false}, 548 }, 549 550 [KSZ9897] = { 551 .chip_id = KSZ9897_CHIP_ID, 552 .dev_name = "KSZ9897", 553 .num_vlans = 4096, 554 .num_alus = 4096, 555 .num_statics = 16, 556 .cpu_ports = 0x7F, /* can be configured as cpu port */ 557 .port_cnt = 7, /* total physical port count */ 558 .ops = &ksz9477_dev_ops, 559 .phy_errata_9477 = true, 560 .mib_names = ksz9477_mib_names, 561 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 562 .reg_mib_cnt = MIB_COUNTER_NUM, 563 .regs = ksz9477_regs, 564 .masks = ksz9477_masks, 565 .shifts = ksz9477_shifts, 566 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 567 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 568 .supports_mii = {false, false, false, false, 569 false, true, true}, 570 .supports_rmii = {false, false, false, false, 571 false, true, true}, 572 .supports_rgmii = {false, false, false, false, 573 false, true, true}, 574 .internal_phy = {true, true, true, true, 575 true, false, false}, 576 }, 577 578 [KSZ9893] = { 579 .chip_id = KSZ9893_CHIP_ID, 580 .dev_name = "KSZ9893", 581 .num_vlans = 4096, 582 .num_alus = 4096, 583 .num_statics = 16, 584 .cpu_ports = 0x07, /* can be configured as cpu port */ 585 .port_cnt = 3, /* total port count */ 586 .ops = &ksz9477_dev_ops, 587 .mib_names = ksz9477_mib_names, 588 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 589 .reg_mib_cnt = MIB_COUNTER_NUM, 590 .regs = ksz9477_regs, 591 .masks = ksz9477_masks, 592 .shifts = ksz9477_shifts, 593 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 594 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 595 .supports_mii = {false, false, true}, 596 .supports_rmii = {false, false, true}, 597 .supports_rgmii = {false, false, true}, 598 .internal_phy = {true, true, false}, 599 }, 600 601 [KSZ9567] = { 602 .chip_id = KSZ9567_CHIP_ID, 603 .dev_name = "KSZ9567", 604 .num_vlans = 4096, 605 .num_alus = 4096, 606 .num_statics = 16, 607 .cpu_ports = 0x7F, /* can be configured as cpu port */ 608 .port_cnt = 7, /* total physical port count */ 609 .ops = &ksz9477_dev_ops, 610 .phy_errata_9477 = true, 611 .mib_names = ksz9477_mib_names, 612 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 613 .reg_mib_cnt = MIB_COUNTER_NUM, 614 .regs = ksz9477_regs, 615 .masks = ksz9477_masks, 616 .shifts = ksz9477_shifts, 617 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 618 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 619 .supports_mii = {false, false, false, false, 620 false, true, true}, 621 .supports_rmii = {false, false, false, false, 622 false, true, true}, 623 .supports_rgmii = {false, false, false, false, 624 false, true, true}, 625 .internal_phy = {true, true, true, true, 626 true, false, false}, 627 }, 628 629 [LAN9370] = { 630 .chip_id = LAN9370_CHIP_ID, 631 .dev_name = "LAN9370", 632 .num_vlans = 4096, 633 .num_alus = 1024, 634 .num_statics = 256, 635 .cpu_ports = 0x10, /* can be configured as cpu port */ 636 .port_cnt = 5, /* total physical port count */ 637 .ops = &lan937x_dev_ops, 638 .mib_names = ksz9477_mib_names, 639 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 640 .reg_mib_cnt = MIB_COUNTER_NUM, 641 .regs = ksz9477_regs, 642 .masks = lan937x_masks, 643 .shifts = lan937x_shifts, 644 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 645 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 646 .supports_mii = {false, false, false, false, true}, 647 .supports_rmii = {false, false, false, false, true}, 648 .supports_rgmii = {false, false, false, false, true}, 649 .internal_phy = {true, true, true, true, false}, 650 }, 651 652 [LAN9371] = { 653 .chip_id = LAN9371_CHIP_ID, 654 .dev_name = "LAN9371", 655 .num_vlans = 4096, 656 .num_alus = 1024, 657 .num_statics = 256, 658 .cpu_ports = 0x30, /* can be configured as cpu port */ 659 .port_cnt = 6, /* total physical port count */ 660 .ops = &lan937x_dev_ops, 661 .mib_names = ksz9477_mib_names, 662 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 663 .reg_mib_cnt = MIB_COUNTER_NUM, 664 .regs = ksz9477_regs, 665 .masks = lan937x_masks, 666 .shifts = lan937x_shifts, 667 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 668 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 669 .supports_mii = {false, false, false, false, true, true}, 670 .supports_rmii = {false, false, false, false, true, true}, 671 .supports_rgmii = {false, false, false, false, true, true}, 672 .internal_phy = {true, true, true, true, false, false}, 673 }, 674 675 [LAN9372] = { 676 .chip_id = LAN9372_CHIP_ID, 677 .dev_name = "LAN9372", 678 .num_vlans = 4096, 679 .num_alus = 1024, 680 .num_statics = 256, 681 .cpu_ports = 0x30, /* can be configured as cpu port */ 682 .port_cnt = 8, /* total physical port count */ 683 .ops = &lan937x_dev_ops, 684 .mib_names = ksz9477_mib_names, 685 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 686 .reg_mib_cnt = MIB_COUNTER_NUM, 687 .regs = ksz9477_regs, 688 .masks = lan937x_masks, 689 .shifts = lan937x_shifts, 690 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 691 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 692 .supports_mii = {false, false, false, false, 693 true, true, false, false}, 694 .supports_rmii = {false, false, false, false, 695 true, true, false, false}, 696 .supports_rgmii = {false, false, false, false, 697 true, true, false, false}, 698 .internal_phy = {true, true, true, true, 699 false, false, true, true}, 700 }, 701 702 [LAN9373] = { 703 .chip_id = LAN9373_CHIP_ID, 704 .dev_name = "LAN9373", 705 .num_vlans = 4096, 706 .num_alus = 1024, 707 .num_statics = 256, 708 .cpu_ports = 0x38, /* can be configured as cpu port */ 709 .port_cnt = 5, /* total physical port count */ 710 .ops = &lan937x_dev_ops, 711 .mib_names = ksz9477_mib_names, 712 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 713 .reg_mib_cnt = MIB_COUNTER_NUM, 714 .regs = ksz9477_regs, 715 .masks = lan937x_masks, 716 .shifts = lan937x_shifts, 717 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 718 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 719 .supports_mii = {false, false, false, false, 720 true, true, false, false}, 721 .supports_rmii = {false, false, false, false, 722 true, true, false, false}, 723 .supports_rgmii = {false, false, false, false, 724 true, true, false, false}, 725 .internal_phy = {true, true, true, false, 726 false, false, true, true}, 727 }, 728 729 [LAN9374] = { 730 .chip_id = LAN9374_CHIP_ID, 731 .dev_name = "LAN9374", 732 .num_vlans = 4096, 733 .num_alus = 1024, 734 .num_statics = 256, 735 .cpu_ports = 0x30, /* can be configured as cpu port */ 736 .port_cnt = 8, /* total physical port count */ 737 .ops = &lan937x_dev_ops, 738 .mib_names = ksz9477_mib_names, 739 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 740 .reg_mib_cnt = MIB_COUNTER_NUM, 741 .regs = ksz9477_regs, 742 .masks = lan937x_masks, 743 .shifts = lan937x_shifts, 744 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 745 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 746 .supports_mii = {false, false, false, false, 747 true, true, false, false}, 748 .supports_rmii = {false, false, false, false, 749 true, true, false, false}, 750 .supports_rgmii = {false, false, false, false, 751 true, true, false, false}, 752 .internal_phy = {true, true, true, true, 753 false, false, true, true}, 754 }, 755 }; 756 EXPORT_SYMBOL_GPL(ksz_switch_chips); 757 758 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 759 { 760 int i; 761 762 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 763 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 764 765 if (chip->chip_id == prod_num) 766 return chip; 767 } 768 769 return NULL; 770 } 771 772 static int ksz_check_device_id(struct ksz_device *dev) 773 { 774 const struct ksz_chip_data *dt_chip_data; 775 776 dt_chip_data = of_device_get_match_data(dev->dev); 777 778 /* Check for Device Tree and Chip ID */ 779 if (dt_chip_data->chip_id != dev->chip_id) { 780 dev_err(dev->dev, 781 "Device tree specifies chip %s but found %s, please fix it!\n", 782 dt_chip_data->dev_name, dev->info->dev_name); 783 return -ENODEV; 784 } 785 786 return 0; 787 } 788 789 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 790 struct phylink_config *config) 791 { 792 struct ksz_device *dev = ds->priv; 793 794 config->legacy_pre_march2020 = false; 795 796 if (dev->info->supports_mii[port]) 797 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 798 799 if (dev->info->supports_rmii[port]) 800 __set_bit(PHY_INTERFACE_MODE_RMII, 801 config->supported_interfaces); 802 803 if (dev->info->supports_rgmii[port]) 804 phy_interface_set_rgmii(config->supported_interfaces); 805 806 if (dev->info->internal_phy[port]) { 807 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 808 config->supported_interfaces); 809 /* Compatibility for phylib's default interface type when the 810 * phy-mode property is absent 811 */ 812 __set_bit(PHY_INTERFACE_MODE_GMII, 813 config->supported_interfaces); 814 } 815 816 if (dev->dev_ops->get_caps) 817 dev->dev_ops->get_caps(dev, port, config); 818 } 819 820 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 821 { 822 struct ethtool_pause_stats *pstats; 823 struct rtnl_link_stats64 *stats; 824 struct ksz_stats_raw *raw; 825 struct ksz_port_mib *mib; 826 827 mib = &dev->ports[port].mib; 828 stats = &mib->stats64; 829 pstats = &mib->pause_stats; 830 raw = (struct ksz_stats_raw *)mib->counters; 831 832 spin_lock(&mib->stats64_lock); 833 834 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 835 raw->rx_pause; 836 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 837 raw->tx_pause; 838 839 /* HW counters are counting bytes + FCS which is not acceptable 840 * for rtnl_link_stats64 interface 841 */ 842 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 843 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 844 845 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 846 raw->rx_oversize; 847 848 stats->rx_crc_errors = raw->rx_crc_err; 849 stats->rx_frame_errors = raw->rx_align_err; 850 stats->rx_dropped = raw->rx_discards; 851 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 852 stats->rx_frame_errors + stats->rx_dropped; 853 854 stats->tx_window_errors = raw->tx_late_col; 855 stats->tx_fifo_errors = raw->tx_discards; 856 stats->tx_aborted_errors = raw->tx_exc_col; 857 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 858 stats->tx_aborted_errors; 859 860 stats->multicast = raw->rx_mcast; 861 stats->collisions = raw->tx_total_col; 862 863 pstats->tx_pause_frames = raw->tx_pause; 864 pstats->rx_pause_frames = raw->rx_pause; 865 866 spin_unlock(&mib->stats64_lock); 867 } 868 869 static void ksz_get_stats64(struct dsa_switch *ds, int port, 870 struct rtnl_link_stats64 *s) 871 { 872 struct ksz_device *dev = ds->priv; 873 struct ksz_port_mib *mib; 874 875 mib = &dev->ports[port].mib; 876 877 spin_lock(&mib->stats64_lock); 878 memcpy(s, &mib->stats64, sizeof(*s)); 879 spin_unlock(&mib->stats64_lock); 880 } 881 882 static void ksz_get_pause_stats(struct dsa_switch *ds, int port, 883 struct ethtool_pause_stats *pause_stats) 884 { 885 struct ksz_device *dev = ds->priv; 886 struct ksz_port_mib *mib; 887 888 mib = &dev->ports[port].mib; 889 890 spin_lock(&mib->stats64_lock); 891 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 892 spin_unlock(&mib->stats64_lock); 893 } 894 895 static void ksz_get_strings(struct dsa_switch *ds, int port, 896 u32 stringset, uint8_t *buf) 897 { 898 struct ksz_device *dev = ds->priv; 899 int i; 900 901 if (stringset != ETH_SS_STATS) 902 return; 903 904 for (i = 0; i < dev->info->mib_cnt; i++) { 905 memcpy(buf + i * ETH_GSTRING_LEN, 906 dev->info->mib_names[i].string, ETH_GSTRING_LEN); 907 } 908 } 909 910 static void ksz_update_port_member(struct ksz_device *dev, int port) 911 { 912 struct ksz_port *p = &dev->ports[port]; 913 struct dsa_switch *ds = dev->ds; 914 u8 port_member = 0, cpu_port; 915 const struct dsa_port *dp; 916 int i, j; 917 918 if (!dsa_is_user_port(ds, port)) 919 return; 920 921 dp = dsa_to_port(ds, port); 922 cpu_port = BIT(dsa_upstream_port(ds, port)); 923 924 for (i = 0; i < ds->num_ports; i++) { 925 const struct dsa_port *other_dp = dsa_to_port(ds, i); 926 struct ksz_port *other_p = &dev->ports[i]; 927 u8 val = 0; 928 929 if (!dsa_is_user_port(ds, i)) 930 continue; 931 if (port == i) 932 continue; 933 if (!dsa_port_bridge_same(dp, other_dp)) 934 continue; 935 if (other_p->stp_state != BR_STATE_FORWARDING) 936 continue; 937 938 if (p->stp_state == BR_STATE_FORWARDING) { 939 val |= BIT(port); 940 port_member |= BIT(i); 941 } 942 943 /* Retain port [i]'s relationship to other ports than [port] */ 944 for (j = 0; j < ds->num_ports; j++) { 945 const struct dsa_port *third_dp; 946 struct ksz_port *third_p; 947 948 if (j == i) 949 continue; 950 if (j == port) 951 continue; 952 if (!dsa_is_user_port(ds, j)) 953 continue; 954 third_p = &dev->ports[j]; 955 if (third_p->stp_state != BR_STATE_FORWARDING) 956 continue; 957 third_dp = dsa_to_port(ds, j); 958 if (dsa_port_bridge_same(other_dp, third_dp)) 959 val |= BIT(j); 960 } 961 962 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 963 } 964 965 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 966 } 967 968 static int ksz_setup(struct dsa_switch *ds) 969 { 970 struct ksz_device *dev = ds->priv; 971 struct ksz_port *p; 972 const u16 *regs; 973 int ret; 974 975 regs = dev->info->regs; 976 977 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 978 dev->info->num_vlans, GFP_KERNEL); 979 if (!dev->vlan_cache) 980 return -ENOMEM; 981 982 ret = dev->dev_ops->reset(dev); 983 if (ret) { 984 dev_err(ds->dev, "failed to reset switch\n"); 985 return ret; 986 } 987 988 /* set broadcast storm protection 10% rate */ 989 regmap_update_bits(dev->regmap[1], regs[S_BROADCAST_CTRL], 990 BROADCAST_STORM_RATE, 991 (BROADCAST_STORM_VALUE * 992 BROADCAST_STORM_PROT_RATE) / 100); 993 994 dev->dev_ops->config_cpu_port(ds); 995 996 dev->dev_ops->enable_stp_addr(dev); 997 998 regmap_update_bits(dev->regmap[0], regs[S_MULTICAST_CTRL], 999 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 1000 1001 ksz_init_mib_timer(dev); 1002 1003 ds->configure_vlan_while_not_filtering = false; 1004 1005 if (dev->dev_ops->setup) { 1006 ret = dev->dev_ops->setup(ds); 1007 if (ret) 1008 return ret; 1009 } 1010 1011 /* Start with learning disabled on standalone user ports, and enabled 1012 * on the CPU port. In lack of other finer mechanisms, learning on the 1013 * CPU port will avoid flooding bridge local addresses on the network 1014 * in some cases. 1015 */ 1016 p = &dev->ports[dev->cpu_port]; 1017 p->learning = true; 1018 1019 /* start switch */ 1020 regmap_update_bits(dev->regmap[0], regs[S_START_CTRL], 1021 SW_START, SW_START); 1022 1023 return 0; 1024 } 1025 1026 static void port_r_cnt(struct ksz_device *dev, int port) 1027 { 1028 struct ksz_port_mib *mib = &dev->ports[port].mib; 1029 u64 *dropped; 1030 1031 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 1032 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 1033 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 1034 &mib->counters[mib->cnt_ptr]); 1035 ++mib->cnt_ptr; 1036 } 1037 1038 /* last one in storage */ 1039 dropped = &mib->counters[dev->info->mib_cnt]; 1040 1041 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 1042 while (mib->cnt_ptr < dev->info->mib_cnt) { 1043 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 1044 dropped, &mib->counters[mib->cnt_ptr]); 1045 ++mib->cnt_ptr; 1046 } 1047 mib->cnt_ptr = 0; 1048 } 1049 1050 static void ksz_mib_read_work(struct work_struct *work) 1051 { 1052 struct ksz_device *dev = container_of(work, struct ksz_device, 1053 mib_read.work); 1054 struct ksz_port_mib *mib; 1055 struct ksz_port *p; 1056 int i; 1057 1058 for (i = 0; i < dev->info->port_cnt; i++) { 1059 if (dsa_is_unused_port(dev->ds, i)) 1060 continue; 1061 1062 p = &dev->ports[i]; 1063 mib = &p->mib; 1064 mutex_lock(&mib->cnt_mutex); 1065 1066 /* Only read MIB counters when the port is told to do. 1067 * If not, read only dropped counters when link is not up. 1068 */ 1069 if (!p->read) { 1070 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 1071 1072 if (!netif_carrier_ok(dp->slave)) 1073 mib->cnt_ptr = dev->info->reg_mib_cnt; 1074 } 1075 port_r_cnt(dev, i); 1076 p->read = false; 1077 1078 if (dev->dev_ops->r_mib_stat64) 1079 dev->dev_ops->r_mib_stat64(dev, i); 1080 1081 mutex_unlock(&mib->cnt_mutex); 1082 } 1083 1084 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 1085 } 1086 1087 void ksz_init_mib_timer(struct ksz_device *dev) 1088 { 1089 int i; 1090 1091 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 1092 1093 for (i = 0; i < dev->info->port_cnt; i++) { 1094 struct ksz_port_mib *mib = &dev->ports[i].mib; 1095 1096 dev->dev_ops->port_init_cnt(dev, i); 1097 1098 mib->cnt_ptr = 0; 1099 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 1100 } 1101 } 1102 1103 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 1104 { 1105 struct ksz_device *dev = ds->priv; 1106 u16 val = 0xffff; 1107 1108 dev->dev_ops->r_phy(dev, addr, reg, &val); 1109 1110 return val; 1111 } 1112 1113 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 1114 { 1115 struct ksz_device *dev = ds->priv; 1116 1117 dev->dev_ops->w_phy(dev, addr, reg, val); 1118 1119 return 0; 1120 } 1121 1122 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 1123 { 1124 struct ksz_device *dev = ds->priv; 1125 1126 if (dev->chip_id == KSZ8830_CHIP_ID) { 1127 /* Silicon Errata Sheet (DS80000830A): 1128 * Port 1 does not work with LinkMD Cable-Testing. 1129 * Port 1 does not respond to received PAUSE control frames. 1130 */ 1131 if (!port) 1132 return MICREL_KSZ8_P1_ERRATA; 1133 } 1134 1135 return 0; 1136 } 1137 1138 static void ksz_mac_link_down(struct dsa_switch *ds, int port, 1139 unsigned int mode, phy_interface_t interface) 1140 { 1141 struct ksz_device *dev = ds->priv; 1142 struct ksz_port *p = &dev->ports[port]; 1143 1144 /* Read all MIB counters when the link is going down. */ 1145 p->read = true; 1146 /* timer started */ 1147 if (dev->mib_read_interval) 1148 schedule_delayed_work(&dev->mib_read, 0); 1149 } 1150 1151 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 1152 { 1153 struct ksz_device *dev = ds->priv; 1154 1155 if (sset != ETH_SS_STATS) 1156 return 0; 1157 1158 return dev->info->mib_cnt; 1159 } 1160 1161 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 1162 uint64_t *buf) 1163 { 1164 const struct dsa_port *dp = dsa_to_port(ds, port); 1165 struct ksz_device *dev = ds->priv; 1166 struct ksz_port_mib *mib; 1167 1168 mib = &dev->ports[port].mib; 1169 mutex_lock(&mib->cnt_mutex); 1170 1171 /* Only read dropped counters if no link. */ 1172 if (!netif_carrier_ok(dp->slave)) 1173 mib->cnt_ptr = dev->info->reg_mib_cnt; 1174 port_r_cnt(dev, port); 1175 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 1176 mutex_unlock(&mib->cnt_mutex); 1177 } 1178 1179 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 1180 struct dsa_bridge bridge, 1181 bool *tx_fwd_offload, 1182 struct netlink_ext_ack *extack) 1183 { 1184 /* port_stp_state_set() will be called after to put the port in 1185 * appropriate state so there is no need to do anything. 1186 */ 1187 1188 return 0; 1189 } 1190 1191 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 1192 struct dsa_bridge bridge) 1193 { 1194 /* port_stp_state_set() will be called after to put the port in 1195 * forwarding state so there is no need to do anything. 1196 */ 1197 } 1198 1199 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 1200 { 1201 struct ksz_device *dev = ds->priv; 1202 1203 dev->dev_ops->flush_dyn_mac_table(dev, port); 1204 } 1205 1206 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 1207 const unsigned char *addr, u16 vid, 1208 struct dsa_db db) 1209 { 1210 struct ksz_device *dev = ds->priv; 1211 1212 if (!dev->dev_ops->fdb_add) 1213 return -EOPNOTSUPP; 1214 1215 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 1216 } 1217 1218 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 1219 const unsigned char *addr, 1220 u16 vid, struct dsa_db db) 1221 { 1222 struct ksz_device *dev = ds->priv; 1223 1224 if (!dev->dev_ops->fdb_del) 1225 return -EOPNOTSUPP; 1226 1227 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 1228 } 1229 1230 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 1231 dsa_fdb_dump_cb_t *cb, void *data) 1232 { 1233 struct ksz_device *dev = ds->priv; 1234 1235 if (!dev->dev_ops->fdb_dump) 1236 return -EOPNOTSUPP; 1237 1238 return dev->dev_ops->fdb_dump(dev, port, cb, data); 1239 } 1240 1241 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 1242 const struct switchdev_obj_port_mdb *mdb, 1243 struct dsa_db db) 1244 { 1245 struct ksz_device *dev = ds->priv; 1246 1247 if (!dev->dev_ops->mdb_add) 1248 return -EOPNOTSUPP; 1249 1250 return dev->dev_ops->mdb_add(dev, port, mdb, db); 1251 } 1252 1253 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 1254 const struct switchdev_obj_port_mdb *mdb, 1255 struct dsa_db db) 1256 { 1257 struct ksz_device *dev = ds->priv; 1258 1259 if (!dev->dev_ops->mdb_del) 1260 return -EOPNOTSUPP; 1261 1262 return dev->dev_ops->mdb_del(dev, port, mdb, db); 1263 } 1264 1265 static int ksz_enable_port(struct dsa_switch *ds, int port, 1266 struct phy_device *phy) 1267 { 1268 struct ksz_device *dev = ds->priv; 1269 1270 if (!dsa_is_user_port(ds, port)) 1271 return 0; 1272 1273 /* setup slave port */ 1274 dev->dev_ops->port_setup(dev, port, false); 1275 1276 /* port_stp_state_set() will be called after to enable the port so 1277 * there is no need to do anything. 1278 */ 1279 1280 return 0; 1281 } 1282 1283 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1284 { 1285 struct ksz_device *dev = ds->priv; 1286 struct ksz_port *p; 1287 const u16 *regs; 1288 u8 data; 1289 1290 regs = dev->info->regs; 1291 1292 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 1293 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 1294 1295 p = &dev->ports[port]; 1296 1297 switch (state) { 1298 case BR_STATE_DISABLED: 1299 data |= PORT_LEARN_DISABLE; 1300 break; 1301 case BR_STATE_LISTENING: 1302 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 1303 break; 1304 case BR_STATE_LEARNING: 1305 data |= PORT_RX_ENABLE; 1306 if (!p->learning) 1307 data |= PORT_LEARN_DISABLE; 1308 break; 1309 case BR_STATE_FORWARDING: 1310 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 1311 if (!p->learning) 1312 data |= PORT_LEARN_DISABLE; 1313 break; 1314 case BR_STATE_BLOCKING: 1315 data |= PORT_LEARN_DISABLE; 1316 break; 1317 default: 1318 dev_err(ds->dev, "invalid STP state: %d\n", state); 1319 return; 1320 } 1321 1322 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 1323 1324 p->stp_state = state; 1325 1326 ksz_update_port_member(dev, port); 1327 } 1328 1329 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1330 struct switchdev_brport_flags flags, 1331 struct netlink_ext_ack *extack) 1332 { 1333 if (flags.mask & ~BR_LEARNING) 1334 return -EINVAL; 1335 1336 return 0; 1337 } 1338 1339 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 1340 struct switchdev_brport_flags flags, 1341 struct netlink_ext_ack *extack) 1342 { 1343 struct ksz_device *dev = ds->priv; 1344 struct ksz_port *p = &dev->ports[port]; 1345 1346 if (flags.mask & BR_LEARNING) { 1347 p->learning = !!(flags.val & BR_LEARNING); 1348 1349 /* Make the change take effect immediately */ 1350 ksz_port_stp_state_set(ds, port, p->stp_state); 1351 } 1352 1353 return 0; 1354 } 1355 1356 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 1357 int port, 1358 enum dsa_tag_protocol mp) 1359 { 1360 struct ksz_device *dev = ds->priv; 1361 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 1362 1363 if (dev->chip_id == KSZ8795_CHIP_ID || 1364 dev->chip_id == KSZ8794_CHIP_ID || 1365 dev->chip_id == KSZ8765_CHIP_ID) 1366 proto = DSA_TAG_PROTO_KSZ8795; 1367 1368 if (dev->chip_id == KSZ8830_CHIP_ID || 1369 dev->chip_id == KSZ9893_CHIP_ID) 1370 proto = DSA_TAG_PROTO_KSZ9893; 1371 1372 if (dev->chip_id == KSZ9477_CHIP_ID || 1373 dev->chip_id == KSZ9897_CHIP_ID || 1374 dev->chip_id == KSZ9567_CHIP_ID) 1375 proto = DSA_TAG_PROTO_KSZ9477; 1376 1377 if (is_lan937x(dev)) 1378 proto = DSA_TAG_PROTO_LAN937X_VALUE; 1379 1380 return proto; 1381 } 1382 1383 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 1384 bool flag, struct netlink_ext_ack *extack) 1385 { 1386 struct ksz_device *dev = ds->priv; 1387 1388 if (!dev->dev_ops->vlan_filtering) 1389 return -EOPNOTSUPP; 1390 1391 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 1392 } 1393 1394 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 1395 const struct switchdev_obj_port_vlan *vlan, 1396 struct netlink_ext_ack *extack) 1397 { 1398 struct ksz_device *dev = ds->priv; 1399 1400 if (!dev->dev_ops->vlan_add) 1401 return -EOPNOTSUPP; 1402 1403 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 1404 } 1405 1406 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 1407 const struct switchdev_obj_port_vlan *vlan) 1408 { 1409 struct ksz_device *dev = ds->priv; 1410 1411 if (!dev->dev_ops->vlan_del) 1412 return -EOPNOTSUPP; 1413 1414 return dev->dev_ops->vlan_del(dev, port, vlan); 1415 } 1416 1417 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 1418 struct dsa_mall_mirror_tc_entry *mirror, 1419 bool ingress, struct netlink_ext_ack *extack) 1420 { 1421 struct ksz_device *dev = ds->priv; 1422 1423 if (!dev->dev_ops->mirror_add) 1424 return -EOPNOTSUPP; 1425 1426 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 1427 } 1428 1429 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 1430 struct dsa_mall_mirror_tc_entry *mirror) 1431 { 1432 struct ksz_device *dev = ds->priv; 1433 1434 if (dev->dev_ops->mirror_del) 1435 dev->dev_ops->mirror_del(dev, port, mirror); 1436 } 1437 1438 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 1439 { 1440 struct ksz_device *dev = ds->priv; 1441 1442 if (!dev->dev_ops->change_mtu) 1443 return -EOPNOTSUPP; 1444 1445 return dev->dev_ops->change_mtu(dev, port, mtu); 1446 } 1447 1448 static int ksz_max_mtu(struct dsa_switch *ds, int port) 1449 { 1450 struct ksz_device *dev = ds->priv; 1451 1452 if (!dev->dev_ops->max_mtu) 1453 return -EOPNOTSUPP; 1454 1455 return dev->dev_ops->max_mtu(dev, port); 1456 } 1457 1458 static void ksz_set_xmii(struct ksz_device *dev, int port, 1459 phy_interface_t interface) 1460 { 1461 const u8 *bitval = dev->info->xmii_ctrl1; 1462 struct ksz_port *p = &dev->ports[port]; 1463 const u16 *regs = dev->info->regs; 1464 u8 data8; 1465 1466 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 1467 1468 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 1469 P_RGMII_ID_EG_ENABLE); 1470 1471 switch (interface) { 1472 case PHY_INTERFACE_MODE_MII: 1473 data8 |= bitval[P_MII_SEL]; 1474 break; 1475 case PHY_INTERFACE_MODE_RMII: 1476 data8 |= bitval[P_RMII_SEL]; 1477 break; 1478 case PHY_INTERFACE_MODE_GMII: 1479 data8 |= bitval[P_GMII_SEL]; 1480 break; 1481 case PHY_INTERFACE_MODE_RGMII: 1482 case PHY_INTERFACE_MODE_RGMII_ID: 1483 case PHY_INTERFACE_MODE_RGMII_TXID: 1484 case PHY_INTERFACE_MODE_RGMII_RXID: 1485 data8 |= bitval[P_RGMII_SEL]; 1486 /* On KSZ9893, disable RGMII in-band status support */ 1487 if (dev->features & IS_9893) 1488 data8 &= ~P_MII_MAC_MODE; 1489 break; 1490 default: 1491 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 1492 phy_modes(interface), port); 1493 return; 1494 } 1495 1496 if (p->rgmii_tx_val) 1497 data8 |= P_RGMII_ID_EG_ENABLE; 1498 1499 if (p->rgmii_rx_val) 1500 data8 |= P_RGMII_ID_IG_ENABLE; 1501 1502 /* Write the updated value */ 1503 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 1504 } 1505 1506 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 1507 { 1508 const u8 *bitval = dev->info->xmii_ctrl1; 1509 const u16 *regs = dev->info->regs; 1510 phy_interface_t interface; 1511 u8 data8; 1512 u8 val; 1513 1514 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 1515 1516 val = FIELD_GET(P_MII_SEL_M, data8); 1517 1518 if (val == bitval[P_MII_SEL]) { 1519 if (gbit) 1520 interface = PHY_INTERFACE_MODE_GMII; 1521 else 1522 interface = PHY_INTERFACE_MODE_MII; 1523 } else if (val == bitval[P_RMII_SEL]) { 1524 interface = PHY_INTERFACE_MODE_RGMII; 1525 } else { 1526 interface = PHY_INTERFACE_MODE_RGMII; 1527 if (data8 & P_RGMII_ID_EG_ENABLE) 1528 interface = PHY_INTERFACE_MODE_RGMII_TXID; 1529 if (data8 & P_RGMII_ID_IG_ENABLE) { 1530 interface = PHY_INTERFACE_MODE_RGMII_RXID; 1531 if (data8 & P_RGMII_ID_EG_ENABLE) 1532 interface = PHY_INTERFACE_MODE_RGMII_ID; 1533 } 1534 } 1535 1536 return interface; 1537 } 1538 1539 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port, 1540 unsigned int mode, 1541 const struct phylink_link_state *state) 1542 { 1543 struct ksz_device *dev = ds->priv; 1544 1545 if (ksz_is_ksz88x3(dev)) 1546 return; 1547 1548 /* Internal PHYs */ 1549 if (dev->info->internal_phy[port]) 1550 return; 1551 1552 if (phylink_autoneg_inband(mode)) { 1553 dev_err(dev->dev, "In-band AN not supported!\n"); 1554 return; 1555 } 1556 1557 ksz_set_xmii(dev, port, state->interface); 1558 1559 if (dev->dev_ops->phylink_mac_config) 1560 dev->dev_ops->phylink_mac_config(dev, port, mode, state); 1561 1562 if (dev->dev_ops->setup_rgmii_delay) 1563 dev->dev_ops->setup_rgmii_delay(dev, port); 1564 } 1565 1566 bool ksz_get_gbit(struct ksz_device *dev, int port) 1567 { 1568 const u8 *bitval = dev->info->xmii_ctrl1; 1569 const u16 *regs = dev->info->regs; 1570 bool gbit = false; 1571 u8 data8; 1572 bool val; 1573 1574 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 1575 1576 val = FIELD_GET(P_GMII_1GBIT_M, data8); 1577 1578 if (val == bitval[P_GMII_1GBIT]) 1579 gbit = true; 1580 1581 return gbit; 1582 } 1583 1584 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) 1585 { 1586 const u8 *bitval = dev->info->xmii_ctrl1; 1587 const u16 *regs = dev->info->regs; 1588 u8 data8; 1589 1590 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 1591 1592 data8 &= ~P_GMII_1GBIT_M; 1593 1594 if (gbit) 1595 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 1596 else 1597 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 1598 1599 /* Write the updated value */ 1600 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 1601 } 1602 1603 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) 1604 { 1605 const u8 *bitval = dev->info->xmii_ctrl0; 1606 const u16 *regs = dev->info->regs; 1607 u8 data8; 1608 1609 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 1610 1611 data8 &= ~P_MII_100MBIT_M; 1612 1613 if (speed == SPEED_100) 1614 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 1615 else 1616 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 1617 1618 /* Write the updated value */ 1619 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 1620 } 1621 1622 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) 1623 { 1624 if (speed == SPEED_1000) 1625 ksz_set_gbit(dev, port, true); 1626 else 1627 ksz_set_gbit(dev, port, false); 1628 1629 if (speed == SPEED_100 || speed == SPEED_10) 1630 ksz_set_100_10mbit(dev, port, speed); 1631 } 1632 1633 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 1634 bool tx_pause, bool rx_pause) 1635 { 1636 const u8 *bitval = dev->info->xmii_ctrl0; 1637 const u32 *masks = dev->info->masks; 1638 const u16 *regs = dev->info->regs; 1639 u8 mask; 1640 u8 val; 1641 1642 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 1643 masks[P_MII_RX_FLOW_CTRL]; 1644 1645 if (duplex == DUPLEX_FULL) 1646 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 1647 else 1648 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 1649 1650 if (tx_pause) 1651 val |= masks[P_MII_TX_FLOW_CTRL]; 1652 1653 if (rx_pause) 1654 val |= masks[P_MII_RX_FLOW_CTRL]; 1655 1656 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 1657 } 1658 1659 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port, 1660 unsigned int mode, 1661 phy_interface_t interface, 1662 struct phy_device *phydev, int speed, 1663 int duplex, bool tx_pause, bool rx_pause) 1664 { 1665 struct ksz_device *dev = ds->priv; 1666 struct ksz_port *p; 1667 1668 p = &dev->ports[port]; 1669 1670 /* Internal PHYs */ 1671 if (dev->info->internal_phy[port]) 1672 return; 1673 1674 p->phydev.speed = speed; 1675 1676 ksz_port_set_xmii_speed(dev, port, speed); 1677 1678 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 1679 1680 if (dev->dev_ops->phylink_mac_link_up) 1681 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface, 1682 phydev, speed, duplex, 1683 tx_pause, rx_pause); 1684 } 1685 1686 static int ksz_switch_detect(struct ksz_device *dev) 1687 { 1688 u8 id1, id2; 1689 u16 id16; 1690 u32 id32; 1691 int ret; 1692 1693 /* read chip id */ 1694 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 1695 if (ret) 1696 return ret; 1697 1698 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 1699 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 1700 1701 switch (id1) { 1702 case KSZ87_FAMILY_ID: 1703 if (id2 == KSZ87_CHIP_ID_95) { 1704 u8 val; 1705 1706 dev->chip_id = KSZ8795_CHIP_ID; 1707 1708 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 1709 if (val & KSZ8_PORT_FIBER_MODE) 1710 dev->chip_id = KSZ8765_CHIP_ID; 1711 } else if (id2 == KSZ87_CHIP_ID_94) { 1712 dev->chip_id = KSZ8794_CHIP_ID; 1713 } else { 1714 return -ENODEV; 1715 } 1716 break; 1717 case KSZ88_FAMILY_ID: 1718 if (id2 == KSZ88_CHIP_ID_63) 1719 dev->chip_id = KSZ8830_CHIP_ID; 1720 else 1721 return -ENODEV; 1722 break; 1723 default: 1724 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 1725 if (ret) 1726 return ret; 1727 1728 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 1729 id32 &= ~0xFF; 1730 1731 switch (id32) { 1732 case KSZ9477_CHIP_ID: 1733 case KSZ9897_CHIP_ID: 1734 case KSZ9893_CHIP_ID: 1735 case KSZ9567_CHIP_ID: 1736 case LAN9370_CHIP_ID: 1737 case LAN9371_CHIP_ID: 1738 case LAN9372_CHIP_ID: 1739 case LAN9373_CHIP_ID: 1740 case LAN9374_CHIP_ID: 1741 dev->chip_id = id32; 1742 break; 1743 default: 1744 dev_err(dev->dev, 1745 "unsupported switch detected %x)\n", id32); 1746 return -ENODEV; 1747 } 1748 } 1749 return 0; 1750 } 1751 1752 static const struct dsa_switch_ops ksz_switch_ops = { 1753 .get_tag_protocol = ksz_get_tag_protocol, 1754 .get_phy_flags = ksz_get_phy_flags, 1755 .setup = ksz_setup, 1756 .phy_read = ksz_phy_read16, 1757 .phy_write = ksz_phy_write16, 1758 .phylink_get_caps = ksz_phylink_get_caps, 1759 .phylink_mac_config = ksz_phylink_mac_config, 1760 .phylink_mac_link_up = ksz_phylink_mac_link_up, 1761 .phylink_mac_link_down = ksz_mac_link_down, 1762 .port_enable = ksz_enable_port, 1763 .get_strings = ksz_get_strings, 1764 .get_ethtool_stats = ksz_get_ethtool_stats, 1765 .get_sset_count = ksz_sset_count, 1766 .port_bridge_join = ksz_port_bridge_join, 1767 .port_bridge_leave = ksz_port_bridge_leave, 1768 .port_stp_state_set = ksz_port_stp_state_set, 1769 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 1770 .port_bridge_flags = ksz_port_bridge_flags, 1771 .port_fast_age = ksz_port_fast_age, 1772 .port_vlan_filtering = ksz_port_vlan_filtering, 1773 .port_vlan_add = ksz_port_vlan_add, 1774 .port_vlan_del = ksz_port_vlan_del, 1775 .port_fdb_dump = ksz_port_fdb_dump, 1776 .port_fdb_add = ksz_port_fdb_add, 1777 .port_fdb_del = ksz_port_fdb_del, 1778 .port_mdb_add = ksz_port_mdb_add, 1779 .port_mdb_del = ksz_port_mdb_del, 1780 .port_mirror_add = ksz_port_mirror_add, 1781 .port_mirror_del = ksz_port_mirror_del, 1782 .get_stats64 = ksz_get_stats64, 1783 .get_pause_stats = ksz_get_pause_stats, 1784 .port_change_mtu = ksz_change_mtu, 1785 .port_max_mtu = ksz_max_mtu, 1786 }; 1787 1788 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 1789 { 1790 struct dsa_switch *ds; 1791 struct ksz_device *swdev; 1792 1793 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 1794 if (!ds) 1795 return NULL; 1796 1797 ds->dev = base; 1798 ds->num_ports = DSA_MAX_PORTS; 1799 ds->ops = &ksz_switch_ops; 1800 1801 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 1802 if (!swdev) 1803 return NULL; 1804 1805 ds->priv = swdev; 1806 swdev->dev = base; 1807 1808 swdev->ds = ds; 1809 swdev->priv = priv; 1810 1811 return swdev; 1812 } 1813 EXPORT_SYMBOL(ksz_switch_alloc); 1814 1815 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 1816 struct device_node *port_dn) 1817 { 1818 phy_interface_t phy_mode = dev->ports[port_num].interface; 1819 int rx_delay = -1, tx_delay = -1; 1820 1821 if (!phy_interface_mode_is_rgmii(phy_mode)) 1822 return; 1823 1824 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 1825 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 1826 1827 if (rx_delay == -1 && tx_delay == -1) { 1828 dev_warn(dev->dev, 1829 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 1830 "please update device tree to specify \"rx-internal-delay-ps\" and " 1831 "\"tx-internal-delay-ps\"", 1832 port_num); 1833 1834 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 1835 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 1836 rx_delay = 2000; 1837 1838 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 1839 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 1840 tx_delay = 2000; 1841 } 1842 1843 if (rx_delay < 0) 1844 rx_delay = 0; 1845 if (tx_delay < 0) 1846 tx_delay = 0; 1847 1848 dev->ports[port_num].rgmii_rx_val = rx_delay; 1849 dev->ports[port_num].rgmii_tx_val = tx_delay; 1850 } 1851 1852 int ksz_switch_register(struct ksz_device *dev) 1853 { 1854 const struct ksz_chip_data *info; 1855 struct device_node *port, *ports; 1856 phy_interface_t interface; 1857 unsigned int port_num; 1858 int ret; 1859 int i; 1860 1861 if (dev->pdata) 1862 dev->chip_id = dev->pdata->chip_id; 1863 1864 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 1865 GPIOD_OUT_LOW); 1866 if (IS_ERR(dev->reset_gpio)) 1867 return PTR_ERR(dev->reset_gpio); 1868 1869 if (dev->reset_gpio) { 1870 gpiod_set_value_cansleep(dev->reset_gpio, 1); 1871 usleep_range(10000, 12000); 1872 gpiod_set_value_cansleep(dev->reset_gpio, 0); 1873 msleep(100); 1874 } 1875 1876 mutex_init(&dev->dev_mutex); 1877 mutex_init(&dev->regmap_mutex); 1878 mutex_init(&dev->alu_mutex); 1879 mutex_init(&dev->vlan_mutex); 1880 1881 ret = ksz_switch_detect(dev); 1882 if (ret) 1883 return ret; 1884 1885 info = ksz_lookup_info(dev->chip_id); 1886 if (!info) 1887 return -ENODEV; 1888 1889 /* Update the compatible info with the probed one */ 1890 dev->info = info; 1891 1892 dev_info(dev->dev, "found switch: %s, rev %i\n", 1893 dev->info->dev_name, dev->chip_rev); 1894 1895 ret = ksz_check_device_id(dev); 1896 if (ret) 1897 return ret; 1898 1899 dev->dev_ops = dev->info->ops; 1900 1901 ret = dev->dev_ops->init(dev); 1902 if (ret) 1903 return ret; 1904 1905 dev->ports = devm_kzalloc(dev->dev, 1906 dev->info->port_cnt * sizeof(struct ksz_port), 1907 GFP_KERNEL); 1908 if (!dev->ports) 1909 return -ENOMEM; 1910 1911 for (i = 0; i < dev->info->port_cnt; i++) { 1912 spin_lock_init(&dev->ports[i].mib.stats64_lock); 1913 mutex_init(&dev->ports[i].mib.cnt_mutex); 1914 dev->ports[i].mib.counters = 1915 devm_kzalloc(dev->dev, 1916 sizeof(u64) * (dev->info->mib_cnt + 1), 1917 GFP_KERNEL); 1918 if (!dev->ports[i].mib.counters) 1919 return -ENOMEM; 1920 } 1921 1922 /* set the real number of ports */ 1923 dev->ds->num_ports = dev->info->port_cnt; 1924 1925 /* Host port interface will be self detected, or specifically set in 1926 * device tree. 1927 */ 1928 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 1929 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 1930 if (dev->dev->of_node) { 1931 ret = of_get_phy_mode(dev->dev->of_node, &interface); 1932 if (ret == 0) 1933 dev->compat_interface = interface; 1934 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 1935 if (!ports) 1936 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 1937 if (ports) { 1938 for_each_available_child_of_node(ports, port) { 1939 if (of_property_read_u32(port, "reg", 1940 &port_num)) 1941 continue; 1942 if (!(dev->port_mask & BIT(port_num))) { 1943 of_node_put(port); 1944 of_node_put(ports); 1945 return -EINVAL; 1946 } 1947 of_get_phy_mode(port, 1948 &dev->ports[port_num].interface); 1949 1950 ksz_parse_rgmii_delay(dev, port_num, port); 1951 } 1952 of_node_put(ports); 1953 } 1954 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 1955 "microchip,synclko-125"); 1956 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 1957 "microchip,synclko-disable"); 1958 if (dev->synclko_125 && dev->synclko_disable) { 1959 dev_err(dev->dev, "inconsistent synclko settings\n"); 1960 return -EINVAL; 1961 } 1962 } 1963 1964 ret = dsa_register_switch(dev->ds); 1965 if (ret) { 1966 dev->dev_ops->exit(dev); 1967 return ret; 1968 } 1969 1970 /* Read MIB counters every 30 seconds to avoid overflow. */ 1971 dev->mib_read_interval = msecs_to_jiffies(5000); 1972 1973 /* Start the MIB timer. */ 1974 schedule_delayed_work(&dev->mib_read, 0); 1975 1976 return ret; 1977 } 1978 EXPORT_SYMBOL(ksz_switch_register); 1979 1980 void ksz_switch_remove(struct ksz_device *dev) 1981 { 1982 /* timer started */ 1983 if (dev->mib_read_interval) { 1984 dev->mib_read_interval = 0; 1985 cancel_delayed_work_sync(&dev->mib_read); 1986 } 1987 1988 dev->dev_ops->exit(dev); 1989 dsa_unregister_switch(dev->ds); 1990 1991 if (dev->reset_gpio) 1992 gpiod_set_value_cansleep(dev->reset_gpio, 1); 1993 1994 } 1995 EXPORT_SYMBOL(ksz_switch_remove); 1996 1997 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 1998 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 1999 MODULE_LICENSE("GPL"); 2000