1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Microchip KSZ9477 register definitions
4  *
5  * Copyright (C) 2017-2018 Microchip Technology Inc.
6  */
7 
8 #ifndef __KSZ9477_REGS_H
9 #define __KSZ9477_REGS_H
10 
11 #define KS_PRIO_M			0x7
12 #define KS_PRIO_S			4
13 
14 /* 0 - Operation */
15 #define REG_CHIP_ID0__1			0x0000
16 
17 #define REG_CHIP_ID1__1			0x0001
18 
19 #define FAMILY_ID			0x95
20 #define FAMILY_ID_94			0x94
21 #define FAMILY_ID_95			0x95
22 #define FAMILY_ID_85			0x85
23 #define FAMILY_ID_98			0x98
24 #define FAMILY_ID_88			0x88
25 
26 #define REG_CHIP_ID2__1			0x0002
27 
28 #define CHIP_ID_66			0x66
29 #define CHIP_ID_67			0x67
30 #define CHIP_ID_77			0x77
31 #define CHIP_ID_93			0x93
32 #define CHIP_ID_96			0x96
33 #define CHIP_ID_97			0x97
34 
35 #define REG_CHIP_ID3__1			0x0003
36 
37 #define SWITCH_REVISION_M		0x0F
38 #define SWITCH_REVISION_S		4
39 #define SWITCH_RESET			0x01
40 
41 #define REG_SW_PME_CTRL			0x0006
42 
43 #define PME_ENABLE			BIT(1)
44 #define PME_POLARITY			BIT(0)
45 
46 #define REG_GLOBAL_OPTIONS		0x000F
47 
48 #define SW_GIGABIT_ABLE			BIT(6)
49 #define SW_REDUNDANCY_ABLE		BIT(5)
50 #define SW_AVB_ABLE			BIT(4)
51 #define SW_9567_RL_5_2			0xC
52 #define SW_9477_SL_5_2			0xD
53 
54 #define SW_9896_GL_5_1			0xB
55 #define SW_9896_RL_5_1			0x8
56 #define SW_9896_SL_5_1			0x9
57 
58 #define SW_9895_GL_4_1			0x7
59 #define SW_9895_RL_4_1			0x4
60 #define SW_9895_SL_4_1			0x5
61 
62 #define SW_9896_RL_4_2			0x6
63 
64 #define SW_9893_RL_2_1			0x0
65 #define SW_9893_SL_2_1			0x1
66 #define SW_9893_GL_2_1			0x3
67 
68 #define SW_QW_ABLE			BIT(5)
69 #define SW_9893_RN_2_1			0xC
70 
71 #define REG_SW_INT_STATUS__4		0x0010
72 #define REG_SW_INT_MASK__4		0x0014
73 
74 #define LUE_INT				BIT(31)
75 #define TRIG_TS_INT			BIT(30)
76 #define APB_TIMEOUT_INT			BIT(29)
77 
78 #define SWITCH_INT_MASK			(TRIG_TS_INT | APB_TIMEOUT_INT)
79 
80 #define REG_SW_PORT_INT_STATUS__4	0x0018
81 #define REG_SW_PORT_INT_MASK__4		0x001C
82 #define REG_SW_PHY_INT_STATUS		0x0020
83 #define REG_SW_PHY_INT_ENABLE		0x0024
84 
85 /* 1 - Global */
86 #define REG_SW_GLOBAL_SERIAL_CTRL_0	0x0100
87 #define SW_SPARE_REG_2			BIT(7)
88 #define SW_SPARE_REG_1			BIT(6)
89 #define SW_SPARE_REG_0			BIT(5)
90 #define SW_BIG_ENDIAN			BIT(4)
91 #define SPI_AUTO_EDGE_DETECTION		BIT(1)
92 #define SPI_CLOCK_OUT_RISING_EDGE	BIT(0)
93 
94 #define REG_SW_GLOBAL_OUTPUT_CTRL__1	0x0103
95 #define SW_ENABLE_REFCLKO		BIT(1)
96 #define SW_REFCLKO_IS_125MHZ		BIT(0)
97 
98 #define REG_SW_IBA__4			0x0104
99 
100 #define SW_IBA_ENABLE			BIT(31)
101 #define SW_IBA_DA_MATCH			BIT(30)
102 #define SW_IBA_INIT			BIT(29)
103 #define SW_IBA_QID_M			0xF
104 #define SW_IBA_QID_S			22
105 #define SW_IBA_PORT_M			0x2F
106 #define SW_IBA_PORT_S			16
107 #define SW_IBA_FRAME_TPID_M		0xFFFF
108 
109 #define REG_SW_APB_TIMEOUT_ADDR__4	0x0108
110 
111 #define APB_TIMEOUT_ACKNOWLEDGE		BIT(31)
112 
113 #define REG_SW_IBA_SYNC__1		0x010C
114 
115 #define REG_SW_IO_STRENGTH__1		0x010D
116 #define SW_DRIVE_STRENGTH_M		0x7
117 #define SW_DRIVE_STRENGTH_2MA		0
118 #define SW_DRIVE_STRENGTH_4MA		1
119 #define SW_DRIVE_STRENGTH_8MA		2
120 #define SW_DRIVE_STRENGTH_12MA		3
121 #define SW_DRIVE_STRENGTH_16MA		4
122 #define SW_DRIVE_STRENGTH_20MA		5
123 #define SW_DRIVE_STRENGTH_24MA		6
124 #define SW_DRIVE_STRENGTH_28MA		7
125 #define SW_HI_SPEED_DRIVE_STRENGTH_S	4
126 #define SW_LO_SPEED_DRIVE_STRENGTH_S	0
127 
128 #define REG_SW_IBA_STATUS__4		0x0110
129 
130 #define SW_IBA_REQ			BIT(31)
131 #define SW_IBA_RESP			BIT(30)
132 #define SW_IBA_DA_MISMATCH		BIT(14)
133 #define SW_IBA_FMT_MISMATCH		BIT(13)
134 #define SW_IBA_CODE_ERROR		BIT(12)
135 #define SW_IBA_CMD_ERROR		BIT(11)
136 #define SW_IBA_CMD_LOC_M		(BIT(6) - 1)
137 
138 #define REG_SW_IBA_STATES__4		0x0114
139 
140 #define SW_IBA_BUF_STATE_S		30
141 #define SW_IBA_CMD_STATE_S		28
142 #define SW_IBA_RESP_STATE_S		26
143 #define SW_IBA_STATE_M			0x3
144 #define SW_IBA_PACKET_SIZE_M		0x7F
145 #define SW_IBA_PACKET_SIZE_S		16
146 #define SW_IBA_FMT_ID_M			0xFFFF
147 
148 #define REG_SW_IBA_RESULT__4		0x0118
149 
150 #define SW_IBA_SIZE_S			24
151 
152 #define SW_IBA_RETRY_CNT_M		(BIT(5) - 1)
153 
154 /* 2 - PHY */
155 #define REG_SW_POWER_MANAGEMENT_CTRL	0x0201
156 
157 #define SW_PLL_POWER_DOWN		BIT(5)
158 #define SW_POWER_DOWN_MODE		0x3
159 #define SW_ENERGY_DETECTION		1
160 #define SW_SOFT_POWER_DOWN		2
161 #define SW_POWER_SAVING			3
162 
163 /* 3 - Operation Control */
164 #define REG_SW_OPERATION		0x0300
165 
166 #define SW_DOUBLE_TAG			BIT(7)
167 #define SW_RESET			BIT(1)
168 
169 #define REG_SW_MAC_ADDR_0		0x0302
170 #define REG_SW_MAC_ADDR_1		0x0303
171 #define REG_SW_MAC_ADDR_2		0x0304
172 #define REG_SW_MAC_ADDR_3		0x0305
173 #define REG_SW_MAC_ADDR_4		0x0306
174 #define REG_SW_MAC_ADDR_5		0x0307
175 
176 #define REG_SW_MTU__2			0x0308
177 #define REG_SW_MTU_MASK			GENMASK(13, 0)
178 
179 #define REG_SW_ISP_TPID__2		0x030A
180 
181 #define REG_SW_HSR_TPID__2		0x030C
182 
183 #define REG_AVB_STRATEGY__2		0x030E
184 
185 #define SW_SHAPING_CREDIT_ACCT		BIT(1)
186 #define SW_POLICING_CREDIT_ACCT		BIT(0)
187 
188 #define REG_SW_LUE_CTRL_0		0x0310
189 
190 #define SW_VLAN_ENABLE			BIT(7)
191 #define SW_DROP_INVALID_VID		BIT(6)
192 #define SW_AGE_CNT_M			GENMASK(5, 3)
193 #define SW_AGE_CNT_S			3
194 #define SW_AGE_PERIOD_10_8_M		GENMASK(10, 8)
195 #define SW_RESV_MCAST_ENABLE		BIT(2)
196 #define SW_HASH_OPTION_M		0x03
197 #define SW_HASH_OPTION_CRC		1
198 #define SW_HASH_OPTION_XOR		2
199 #define SW_HASH_OPTION_DIRECT		3
200 
201 #define REG_SW_LUE_CTRL_1		0x0311
202 
203 #define UNICAST_LEARN_DISABLE		BIT(7)
204 #define SW_SRC_ADDR_FILTER		BIT(6)
205 #define SW_FLUSH_STP_TABLE		BIT(5)
206 #define SW_FLUSH_MSTP_TABLE		BIT(4)
207 #define SW_FWD_MCAST_SRC_ADDR		BIT(3)
208 #define SW_AGING_ENABLE			BIT(2)
209 #define SW_FAST_AGING			BIT(1)
210 #define SW_LINK_AUTO_AGING		BIT(0)
211 
212 #define REG_SW_LUE_CTRL_2		0x0312
213 
214 #define SW_TRAP_DOUBLE_TAG		BIT(6)
215 #define SW_EGRESS_VLAN_FILTER_DYN	BIT(5)
216 #define SW_EGRESS_VLAN_FILTER_STA	BIT(4)
217 #define SW_FLUSH_OPTION_M		0x3
218 #define SW_FLUSH_OPTION_S		2
219 #define SW_FLUSH_OPTION_DYN_MAC		1
220 #define SW_FLUSH_OPTION_STA_MAC		2
221 #define SW_FLUSH_OPTION_BOTH		3
222 #define SW_PRIO_M			0x3
223 #define SW_PRIO_DA			0
224 #define SW_PRIO_SA			1
225 #define SW_PRIO_HIGHEST_DA_SA		2
226 #define SW_PRIO_LOWEST_DA_SA		3
227 
228 #define REG_SW_LUE_CTRL_3		0x0313
229 #define SW_AGE_PERIOD_7_0_M		GENMASK(7, 0)
230 
231 #define REG_SW_LUE_INT_STATUS		0x0314
232 #define REG_SW_LUE_INT_ENABLE		0x0315
233 
234 #define LEARN_FAIL_INT			BIT(2)
235 #define ALMOST_FULL_INT			BIT(1)
236 #define WRITE_FAIL_INT			BIT(0)
237 
238 #define REG_SW_LUE_INDEX_0__2		0x0316
239 
240 #define ENTRY_INDEX_M			0x0FFF
241 
242 #define REG_SW_LUE_INDEX_1__2		0x0318
243 
244 #define FAIL_INDEX_M			0x03FF
245 
246 #define REG_SW_LUE_INDEX_2__2		0x031A
247 
248 #define REG_SW_LUE_UNK_UCAST_CTRL__4	0x0320
249 
250 #define SW_UNK_UCAST_ENABLE		BIT(31)
251 
252 #define REG_SW_LUE_UNK_MCAST_CTRL__4	0x0324
253 
254 #define SW_UNK_MCAST_ENABLE		BIT(31)
255 
256 #define REG_SW_LUE_UNK_VID_CTRL__4	0x0328
257 
258 #define SW_UNK_VID_ENABLE		BIT(31)
259 
260 #define REG_SW_MAC_CTRL_0		0x0330
261 
262 #define SW_NEW_BACKOFF			BIT(7)
263 #define SW_CHECK_LENGTH			BIT(3)
264 #define SW_PAUSE_UNH_MODE		BIT(1)
265 #define SW_AGGR_BACKOFF			BIT(0)
266 
267 #define REG_SW_MAC_CTRL_1		0x0331
268 
269 #define SW_BACK_PRESSURE		BIT(5)
270 #define FAIR_FLOW_CTRL			BIT(4)
271 #define NO_EXC_COLLISION_DROP		BIT(3)
272 #define SW_JUMBO_PACKET			BIT(2)
273 #define SW_LEGAL_PACKET_DISABLE		BIT(1)
274 #define SW_PASS_SHORT_FRAME		BIT(0)
275 
276 #define REG_SW_MAC_CTRL_2		0x0332
277 
278 #define SW_REPLACE_VID			BIT(3)
279 
280 #define REG_SW_MAC_CTRL_3		0x0333
281 
282 #define REG_SW_MAC_CTRL_4		0x0334
283 
284 #define SW_PASS_PAUSE			BIT(3)
285 
286 #define REG_SW_MAC_CTRL_5		0x0335
287 
288 #define SW_OUT_RATE_LIMIT_QUEUE_BASED	BIT(3)
289 
290 #define REG_SW_MAC_CTRL_6		0x0336
291 
292 #define SW_MIB_COUNTER_FLUSH		BIT(7)
293 #define SW_MIB_COUNTER_FREEZE		BIT(6)
294 
295 #define REG_SW_MAC_802_1P_MAP_0		0x0338
296 #define REG_SW_MAC_802_1P_MAP_1		0x0339
297 #define REG_SW_MAC_802_1P_MAP_2		0x033A
298 #define REG_SW_MAC_802_1P_MAP_3		0x033B
299 
300 #define SW_802_1P_MAP_M			KS_PRIO_M
301 #define SW_802_1P_MAP_S			KS_PRIO_S
302 
303 #define REG_SW_MAC_ISP_CTRL		0x033C
304 
305 #define REG_SW_MAC_TOS_CTRL		0x033E
306 
307 #define SW_TOS_DSCP_REMARK		BIT(1)
308 #define SW_TOS_DSCP_REMAP		BIT(0)
309 
310 #define REG_SW_MAC_TOS_PRIO_0		0x0340
311 #define REG_SW_MAC_TOS_PRIO_1		0x0341
312 #define REG_SW_MAC_TOS_PRIO_2		0x0342
313 #define REG_SW_MAC_TOS_PRIO_3		0x0343
314 #define REG_SW_MAC_TOS_PRIO_4		0x0344
315 #define REG_SW_MAC_TOS_PRIO_5		0x0345
316 #define REG_SW_MAC_TOS_PRIO_6		0x0346
317 #define REG_SW_MAC_TOS_PRIO_7		0x0347
318 #define REG_SW_MAC_TOS_PRIO_8		0x0348
319 #define REG_SW_MAC_TOS_PRIO_9		0x0349
320 #define REG_SW_MAC_TOS_PRIO_10		0x034A
321 #define REG_SW_MAC_TOS_PRIO_11		0x034B
322 #define REG_SW_MAC_TOS_PRIO_12		0x034C
323 #define REG_SW_MAC_TOS_PRIO_13		0x034D
324 #define REG_SW_MAC_TOS_PRIO_14		0x034E
325 #define REG_SW_MAC_TOS_PRIO_15		0x034F
326 #define REG_SW_MAC_TOS_PRIO_16		0x0350
327 #define REG_SW_MAC_TOS_PRIO_17		0x0351
328 #define REG_SW_MAC_TOS_PRIO_18		0x0352
329 #define REG_SW_MAC_TOS_PRIO_19		0x0353
330 #define REG_SW_MAC_TOS_PRIO_20		0x0354
331 #define REG_SW_MAC_TOS_PRIO_21		0x0355
332 #define REG_SW_MAC_TOS_PRIO_22		0x0356
333 #define REG_SW_MAC_TOS_PRIO_23		0x0357
334 #define REG_SW_MAC_TOS_PRIO_24		0x0358
335 #define REG_SW_MAC_TOS_PRIO_25		0x0359
336 #define REG_SW_MAC_TOS_PRIO_26		0x035A
337 #define REG_SW_MAC_TOS_PRIO_27		0x035B
338 #define REG_SW_MAC_TOS_PRIO_28		0x035C
339 #define REG_SW_MAC_TOS_PRIO_29		0x035D
340 #define REG_SW_MAC_TOS_PRIO_30		0x035E
341 #define REG_SW_MAC_TOS_PRIO_31		0x035F
342 
343 #define REG_SW_MRI_CTRL_0		0x0370
344 
345 #define SW_IGMP_SNOOP			BIT(6)
346 #define SW_IPV6_MLD_OPTION		BIT(3)
347 #define SW_IPV6_MLD_SNOOP		BIT(2)
348 #define SW_MIRROR_RX_TX			BIT(0)
349 
350 #define REG_SW_CLASS_D_IP_CTRL__4	0x0374
351 
352 #define SW_CLASS_D_IP_ENABLE		BIT(31)
353 
354 #define REG_SW_MRI_CTRL_8		0x0378
355 
356 #define SW_NO_COLOR_S			6
357 #define SW_RED_COLOR_S			4
358 #define SW_YELLOW_COLOR_S		2
359 #define SW_GREEN_COLOR_S		0
360 #define SW_COLOR_M			0x3
361 
362 #define REG_SW_QM_CTRL__4		0x0390
363 
364 #define PRIO_SCHEME_SELECT_M		KS_PRIO_M
365 #define PRIO_SCHEME_SELECT_S		6
366 #define PRIO_MAP_3_HI			0
367 #define PRIO_MAP_2_HI			2
368 #define PRIO_MAP_0_LO			3
369 #define UNICAST_VLAN_BOUNDARY		BIT(1)
370 
371 #define REG_SW_EEE_QM_CTRL__2		0x03C0
372 
373 #define REG_SW_EEE_TXQ_WAIT_TIME__2	0x03C2
374 
375 /* 4 - */
376 #define REG_SW_VLAN_ENTRY__4		0x0400
377 
378 #define VLAN_VALID			BIT(31)
379 #define VLAN_FORWARD_OPTION		BIT(27)
380 #define VLAN_PRIO_M			KS_PRIO_M
381 #define VLAN_PRIO_S			24
382 #define VLAN_MSTP_M			0x7
383 #define VLAN_MSTP_S			12
384 #define VLAN_FID_M			0x7F
385 
386 #define REG_SW_VLAN_ENTRY_UNTAG__4	0x0404
387 #define REG_SW_VLAN_ENTRY_PORTS__4	0x0408
388 
389 #define REG_SW_VLAN_ENTRY_INDEX__2	0x040C
390 
391 #define VLAN_INDEX_M			0x0FFF
392 
393 #define REG_SW_VLAN_CTRL		0x040E
394 
395 #define VLAN_START			BIT(7)
396 #define VLAN_ACTION			0x3
397 #define VLAN_WRITE			1
398 #define VLAN_READ			2
399 #define VLAN_CLEAR			3
400 
401 #define REG_SW_ALU_INDEX_0		0x0410
402 
403 #define ALU_FID_INDEX_S			16
404 #define ALU_MAC_ADDR_HI			0xFFFF
405 
406 #define REG_SW_ALU_INDEX_1		0x0414
407 
408 #define ALU_DIRECT_INDEX_M		(BIT(12) - 1)
409 
410 #define REG_SW_ALU_CTRL__4		0x0418
411 
412 #define ALU_VALID_CNT_M			(BIT(14) - 1)
413 #define ALU_VALID_CNT_S			16
414 #define ALU_START			BIT(7)
415 #define ALU_VALID			BIT(6)
416 #define ALU_DIRECT			BIT(2)
417 #define ALU_ACTION			0x3
418 #define ALU_WRITE			1
419 #define ALU_READ			2
420 #define ALU_SEARCH			3
421 
422 #define REG_SW_ALU_STAT_CTRL__4		0x041C
423 
424 #define ALU_RESV_MCAST_INDEX_M		(BIT(6) - 1)
425 #define ALU_STAT_START			BIT(7)
426 #define ALU_RESV_MCAST_ADDR		BIT(1)
427 
428 #define REG_SW_ALU_VAL_A		0x0420
429 
430 #define ALU_V_STATIC_VALID		BIT(31)
431 #define ALU_V_SRC_FILTER		BIT(30)
432 #define ALU_V_DST_FILTER		BIT(29)
433 #define ALU_V_PRIO_AGE_CNT_M		(BIT(3) - 1)
434 #define ALU_V_PRIO_AGE_CNT_S		26
435 #define ALU_V_MSTP_M			0x7
436 
437 #define REG_SW_ALU_VAL_B		0x0424
438 
439 #define ALU_V_OVERRIDE			BIT(31)
440 #define ALU_V_USE_FID			BIT(30)
441 #define ALU_V_PORT_MAP			(BIT(24) - 1)
442 
443 #define REG_SW_ALU_VAL_C		0x0428
444 
445 #define ALU_V_FID_M			(BIT(16) - 1)
446 #define ALU_V_FID_S			16
447 #define ALU_V_MAC_ADDR_HI		0xFFFF
448 
449 #define REG_SW_ALU_VAL_D		0x042C
450 
451 #define REG_HSR_ALU_INDEX_0		0x0440
452 
453 #define REG_HSR_ALU_INDEX_1		0x0444
454 
455 #define HSR_DST_MAC_INDEX_LO_S		16
456 #define HSR_SRC_MAC_INDEX_HI		0xFFFF
457 
458 #define REG_HSR_ALU_INDEX_2		0x0448
459 
460 #define HSR_INDEX_MAX			BIT(9)
461 #define HSR_DIRECT_INDEX_M		(HSR_INDEX_MAX - 1)
462 
463 #define REG_HSR_ALU_INDEX_3		0x044C
464 
465 #define HSR_PATH_INDEX_M		(BIT(4) - 1)
466 
467 #define REG_HSR_ALU_CTRL__4		0x0450
468 
469 #define HSR_VALID_CNT_M			(BIT(14) - 1)
470 #define HSR_VALID_CNT_S			16
471 #define HSR_START			BIT(7)
472 #define HSR_VALID			BIT(6)
473 #define HSR_SEARCH_END			BIT(5)
474 #define HSR_DIRECT			BIT(2)
475 #define HSR_ACTION			0x3
476 #define HSR_WRITE			1
477 #define HSR_READ			2
478 #define HSR_SEARCH			3
479 
480 #define REG_HSR_ALU_VAL_A		0x0454
481 
482 #define HSR_V_STATIC_VALID		BIT(31)
483 #define HSR_V_AGE_CNT_M			(BIT(3) - 1)
484 #define HSR_V_AGE_CNT_S			26
485 #define HSR_V_PATH_ID_M			(BIT(4) - 1)
486 
487 #define REG_HSR_ALU_VAL_B		0x0458
488 
489 #define REG_HSR_ALU_VAL_C		0x045C
490 
491 #define HSR_V_DST_MAC_ADDR_LO_S		16
492 #define HSR_V_SRC_MAC_ADDR_HI		0xFFFF
493 
494 #define REG_HSR_ALU_VAL_D		0x0460
495 
496 #define REG_HSR_ALU_VAL_E		0x0464
497 
498 #define HSR_V_START_SEQ_1_S		16
499 #define HSR_V_START_SEQ_2_S		0
500 
501 #define REG_HSR_ALU_VAL_F		0x0468
502 
503 #define HSR_V_EXP_SEQ_1_S		16
504 #define HSR_V_EXP_SEQ_2_S		0
505 
506 #define REG_HSR_ALU_VAL_G		0x046C
507 
508 #define HSR_V_SEQ_CNT_1_S		16
509 #define HSR_V_SEQ_CNT_2_S		0
510 
511 #define HSR_V_SEQ_M			(BIT(16) - 1)
512 
513 /* 5 - PTP Clock */
514 #define REG_PTP_CLK_CTRL		0x0500
515 
516 #define PTP_STEP_ADJ			BIT(6)
517 #define PTP_STEP_DIR			BIT(5)
518 #define PTP_READ_TIME			BIT(4)
519 #define PTP_LOAD_TIME			BIT(3)
520 #define PTP_CLK_ADJ_ENABLE		BIT(2)
521 #define PTP_CLK_ENABLE			BIT(1)
522 #define PTP_CLK_RESET			BIT(0)
523 
524 #define REG_PTP_RTC_SUB_NANOSEC__2	0x0502
525 
526 #define PTP_RTC_SUB_NANOSEC_M		0x0007
527 
528 #define REG_PTP_RTC_NANOSEC		0x0504
529 #define REG_PTP_RTC_NANOSEC_H		0x0504
530 #define REG_PTP_RTC_NANOSEC_L		0x0506
531 
532 #define REG_PTP_RTC_SEC			0x0508
533 #define REG_PTP_RTC_SEC_H		0x0508
534 #define REG_PTP_RTC_SEC_L		0x050A
535 
536 #define REG_PTP_SUBNANOSEC_RATE		0x050C
537 #define REG_PTP_SUBNANOSEC_RATE_H	0x050C
538 
539 #define PTP_RATE_DIR			BIT(31)
540 #define PTP_TMP_RATE_ENABLE		BIT(30)
541 
542 #define REG_PTP_SUBNANOSEC_RATE_L	0x050E
543 
544 #define REG_PTP_RATE_DURATION		0x0510
545 #define REG_PTP_RATE_DURATION_H		0x0510
546 #define REG_PTP_RATE_DURATION_L		0x0512
547 
548 #define REG_PTP_MSG_CONF1		0x0514
549 
550 #define PTP_802_1AS			BIT(7)
551 #define PTP_ENABLE			BIT(6)
552 #define PTP_ETH_ENABLE			BIT(5)
553 #define PTP_IPV4_UDP_ENABLE		BIT(4)
554 #define PTP_IPV6_UDP_ENABLE		BIT(3)
555 #define PTP_TC_P2P			BIT(2)
556 #define PTP_MASTER			BIT(1)
557 #define PTP_1STEP			BIT(0)
558 
559 #define REG_PTP_MSG_CONF2		0x0516
560 
561 #define PTP_UNICAST_ENABLE		BIT(12)
562 #define PTP_ALTERNATE_MASTER		BIT(11)
563 #define PTP_ALL_HIGH_PRIO		BIT(10)
564 #define PTP_SYNC_CHECK			BIT(9)
565 #define PTP_DELAY_CHECK			BIT(8)
566 #define PTP_PDELAY_CHECK		BIT(7)
567 #define PTP_DROP_SYNC_DELAY_REQ		BIT(5)
568 #define PTP_DOMAIN_CHECK		BIT(4)
569 #define PTP_UDP_CHECKSUM		BIT(2)
570 
571 #define REG_PTP_DOMAIN_VERSION		0x0518
572 #define PTP_VERSION_M			0xFF00
573 #define PTP_DOMAIN_M			0x00FF
574 
575 #define REG_PTP_UNIT_INDEX__4		0x0520
576 
577 #define PTP_UNIT_M			0xF
578 
579 #define PTP_GPIO_INDEX_S		16
580 #define PTP_TSI_INDEX_S			8
581 #define PTP_TOU_INDEX_S			0
582 
583 #define REG_PTP_TRIG_STATUS__4		0x0524
584 
585 #define TRIG_ERROR_S			16
586 #define TRIG_DONE_S			0
587 
588 #define REG_PTP_INT_STATUS__4		0x0528
589 
590 #define TRIG_INT_S			16
591 #define TS_INT_S			0
592 
593 #define TRIG_UNIT_M			0x7
594 #define TS_UNIT_M			0x3
595 
596 #define REG_PTP_CTRL_STAT__4		0x052C
597 
598 #define GPIO_IN				BIT(7)
599 #define GPIO_OUT			BIT(6)
600 #define TS_INT_ENABLE			BIT(5)
601 #define TRIG_ACTIVE			BIT(4)
602 #define TRIG_ENABLE			BIT(3)
603 #define TRIG_RESET			BIT(2)
604 #define TS_ENABLE			BIT(1)
605 #define TS_RESET			BIT(0)
606 
607 #define GPIO_CTRL_M			(GPIO_IN | GPIO_OUT)
608 
609 #define TRIG_CTRL_M			\
610 	(TRIG_ACTIVE | TRIG_ENABLE | TRIG_RESET)
611 
612 #define TS_CTRL_M			\
613 	(TS_INT_ENABLE | TS_ENABLE | TS_RESET)
614 
615 #define REG_TRIG_TARGET_NANOSEC		0x0530
616 #define REG_TRIG_TARGET_SEC		0x0534
617 
618 #define REG_TRIG_CTRL__4		0x0538
619 
620 #define TRIG_CASCADE_ENABLE		BIT(31)
621 #define TRIG_CASCADE_TAIL		BIT(30)
622 #define TRIG_CASCADE_UPS_M		0xF
623 #define TRIG_CASCADE_UPS_S		26
624 #define TRIG_NOW			BIT(25)
625 #define TRIG_NOTIFY			BIT(24)
626 #define TRIG_EDGE			BIT(23)
627 #define TRIG_PATTERN_S			20
628 #define TRIG_PATTERN_M			0x7
629 #define TRIG_NEG_EDGE			0
630 #define TRIG_POS_EDGE			1
631 #define TRIG_NEG_PULSE			2
632 #define TRIG_POS_PULSE			3
633 #define TRIG_NEG_PERIOD			4
634 #define TRIG_POS_PERIOD			5
635 #define TRIG_REG_OUTPUT			6
636 #define TRIG_GPO_S			16
637 #define TRIG_GPO_M			0xF
638 #define TRIG_CASCADE_ITERATE_CNT_M	0xFFFF
639 
640 #define REG_TRIG_CYCLE_WIDTH		0x053C
641 
642 #define REG_TRIG_CYCLE_CNT		0x0540
643 
644 #define TRIG_CYCLE_CNT_M		0xFFFF
645 #define TRIG_CYCLE_CNT_S		16
646 #define TRIG_BIT_PATTERN_M		0xFFFF
647 
648 #define REG_TRIG_ITERATE_TIME		0x0544
649 
650 #define REG_TRIG_PULSE_WIDTH__4		0x0548
651 
652 #define TRIG_PULSE_WIDTH_M		0x00FFFFFF
653 
654 #define REG_TS_CTRL_STAT__4		0x0550
655 
656 #define TS_EVENT_DETECT_M		0xF
657 #define TS_EVENT_DETECT_S		17
658 #define TS_EVENT_OVERFLOW		BIT(16)
659 #define TS_GPI_M			0xF
660 #define TS_GPI_S			8
661 #define TS_DETECT_RISE			BIT(7)
662 #define TS_DETECT_FALL			BIT(6)
663 #define TS_DETECT_S			6
664 #define TS_CASCADE_TAIL			BIT(5)
665 #define TS_CASCADE_UPS_M		0xF
666 #define TS_CASCADE_UPS_S		1
667 #define TS_CASCADE_ENABLE		BIT(0)
668 
669 #define DETECT_RISE			(TS_DETECT_RISE >> TS_DETECT_S)
670 #define DETECT_FALL			(TS_DETECT_FALL >> TS_DETECT_S)
671 
672 #define REG_TS_EVENT_0_NANOSEC		0x0554
673 #define REG_TS_EVENT_0_SEC		0x0558
674 #define REG_TS_EVENT_0_SUB_NANOSEC	0x055C
675 
676 #define REG_TS_EVENT_1_NANOSEC		0x0560
677 #define REG_TS_EVENT_1_SEC		0x0564
678 #define REG_TS_EVENT_1_SUB_NANOSEC	0x0568
679 
680 #define REG_TS_EVENT_2_NANOSEC		0x056C
681 #define REG_TS_EVENT_2_SEC		0x0570
682 #define REG_TS_EVENT_2_SUB_NANOSEC	0x0574
683 
684 #define REG_TS_EVENT_3_NANOSEC		0x0578
685 #define REG_TS_EVENT_3_SEC		0x057C
686 #define REG_TS_EVENT_3_SUB_NANOSEC	0x0580
687 
688 #define REG_TS_EVENT_4_NANOSEC		0x0584
689 #define REG_TS_EVENT_4_SEC		0x0588
690 #define REG_TS_EVENT_4_SUB_NANOSEC	0x058C
691 
692 #define REG_TS_EVENT_5_NANOSEC		0x0590
693 #define REG_TS_EVENT_5_SEC		0x0594
694 #define REG_TS_EVENT_5_SUB_NANOSEC	0x0598
695 
696 #define REG_TS_EVENT_6_NANOSEC		0x059C
697 #define REG_TS_EVENT_6_SEC		0x05A0
698 #define REG_TS_EVENT_6_SUB_NANOSEC	0x05A4
699 
700 #define REG_TS_EVENT_7_NANOSEC		0x05A8
701 #define REG_TS_EVENT_7_SEC		0x05AC
702 #define REG_TS_EVENT_7_SUB_NANOSEC	0x05B0
703 
704 #define TS_EVENT_EDGE_M			0x1
705 #define TS_EVENT_EDGE_S			30
706 #define TS_EVENT_NANOSEC_M		(BIT(30) - 1)
707 
708 #define TS_EVENT_SUB_NANOSEC_M		0x7
709 
710 #define TS_EVENT_SAMPLE			\
711 	(REG_TS_EVENT_1_NANOSEC - REG_TS_EVENT_0_NANOSEC)
712 
713 #define PORT_CTRL_ADDR(port, addr)	((addr) | (((port) + 1) << 12))
714 
715 #define REG_GLOBAL_RR_INDEX__1		0x0600
716 
717 /* DLR */
718 #define REG_DLR_SRC_PORT__4		0x0604
719 
720 #define DLR_SRC_PORT_UNICAST		BIT(31)
721 #define DLR_SRC_PORT_M			0x3
722 #define DLR_SRC_PORT_BOTH		0
723 #define DLR_SRC_PORT_EACH		1
724 
725 #define REG_DLR_IP_ADDR__4		0x0608
726 
727 #define REG_DLR_CTRL__1			0x0610
728 
729 #define DLR_RESET_SEQ_ID		BIT(3)
730 #define DLR_BACKUP_AUTO_ON		BIT(2)
731 #define DLR_BEACON_TX_ENABLE		BIT(1)
732 #define DLR_ASSIST_ENABLE		BIT(0)
733 
734 #define REG_DLR_STATE__1		0x0611
735 
736 #define DLR_NODE_STATE_M		0x3
737 #define DLR_NODE_STATE_S		1
738 #define DLR_NODE_STATE_IDLE		0
739 #define DLR_NODE_STATE_FAULT		1
740 #define DLR_NODE_STATE_NORMAL		2
741 #define DLR_RING_STATE_FAULT		0
742 #define DLR_RING_STATE_NORMAL		1
743 
744 #define REG_DLR_PRECEDENCE__1		0x0612
745 
746 #define REG_DLR_BEACON_INTERVAL__4	0x0614
747 
748 #define REG_DLR_BEACON_TIMEOUT__4	0x0618
749 
750 #define REG_DLR_TIMEOUT_WINDOW__4	0x061C
751 
752 #define DLR_TIMEOUT_WINDOW_M		(BIT(22) - 1)
753 
754 #define REG_DLR_VLAN_ID__2		0x0620
755 
756 #define DLR_VLAN_ID_M			(BIT(12) - 1)
757 
758 #define REG_DLR_DEST_ADDR_0		0x0622
759 #define REG_DLR_DEST_ADDR_1		0x0623
760 #define REG_DLR_DEST_ADDR_2		0x0624
761 #define REG_DLR_DEST_ADDR_3		0x0625
762 #define REG_DLR_DEST_ADDR_4		0x0626
763 #define REG_DLR_DEST_ADDR_5		0x0627
764 
765 #define REG_DLR_PORT_MAP__4		0x0628
766 
767 #define REG_DLR_CLASS__1		0x062C
768 
769 #define DLR_FRAME_QID_M			0x3
770 
771 /* HSR */
772 #define REG_HSR_PORT_MAP__4		0x0640
773 
774 #define REG_HSR_ALU_CTRL_0__1		0x0644
775 
776 #define HSR_DUPLICATE_DISCARD		BIT(7)
777 #define HSR_NODE_UNICAST		BIT(6)
778 #define HSR_AGE_CNT_DEFAULT_M		0x7
779 #define HSR_AGE_CNT_DEFAULT_S		3
780 #define HSR_LEARN_MCAST_DISABLE		BIT(2)
781 #define HSR_HASH_OPTION_M		0x3
782 #define HSR_HASH_DISABLE		0
783 #define HSR_HASH_UPPER_BITS		1
784 #define HSR_HASH_LOWER_BITS		2
785 #define HSR_HASH_XOR_BOTH_BITS		3
786 
787 #define REG_HSR_ALU_CTRL_1__1		0x0645
788 
789 #define HSR_LEARN_UCAST_DISABLE		BIT(7)
790 #define HSR_FLUSH_TABLE			BIT(5)
791 #define HSR_PROC_MCAST_SRC		BIT(3)
792 #define HSR_AGING_ENABLE		BIT(2)
793 
794 #define REG_HSR_ALU_CTRL_2__2		0x0646
795 
796 #define REG_HSR_ALU_AGE_PERIOD__4	0x0648
797 
798 #define REG_HSR_ALU_INT_STATUS__1	0x064C
799 #define REG_HSR_ALU_INT_MASK__1		0x064D
800 
801 #define HSR_WINDOW_OVERFLOW_INT		BIT(3)
802 #define HSR_LEARN_FAIL_INT		BIT(2)
803 #define HSR_ALMOST_FULL_INT		BIT(1)
804 #define HSR_WRITE_FAIL_INT		BIT(0)
805 
806 #define REG_HSR_ALU_ENTRY_0__2		0x0650
807 
808 #define HSR_ENTRY_INDEX_M		(BIT(10) - 1)
809 #define HSR_FAIL_INDEX_M		(BIT(8) - 1)
810 
811 #define REG_HSR_ALU_ENTRY_1__2		0x0652
812 
813 #define HSR_FAIL_LEARN_INDEX_M		(BIT(8) - 1)
814 
815 #define REG_HSR_ALU_ENTRY_3__2		0x0654
816 
817 #define HSR_CPU_ACCESS_ENTRY_INDEX_M	(BIT(8) - 1)
818 
819 /* 0 - Operation */
820 #define REG_PORT_DEFAULT_VID		0x0000
821 
822 #define REG_PORT_CUSTOM_VID		0x0002
823 #define REG_PORT_AVB_SR_1_VID		0x0004
824 #define REG_PORT_AVB_SR_2_VID		0x0006
825 
826 #define REG_PORT_AVB_SR_1_TYPE		0x0008
827 #define REG_PORT_AVB_SR_2_TYPE		0x000A
828 
829 #define REG_PORT_PME_STATUS		0x0013
830 #define REG_PORT_PME_CTRL		0x0017
831 
832 #define PME_WOL_MAGICPKT		BIT(2)
833 #define PME_WOL_LINKUP			BIT(1)
834 #define PME_WOL_ENERGY			BIT(0)
835 
836 #define REG_PORT_INT_STATUS		0x001B
837 #define REG_PORT_INT_MASK		0x001F
838 
839 #define PORT_SGMII_INT			BIT(3)
840 #define PORT_PTP_INT			BIT(2)
841 #define PORT_PHY_INT			BIT(1)
842 #define PORT_ACL_INT			BIT(0)
843 
844 #define PORT_INT_MASK			\
845 	(PORT_SGMII_INT | PORT_PTP_INT | PORT_PHY_INT | PORT_ACL_INT)
846 
847 #define REG_PORT_CTRL_0			0x0020
848 
849 #define PORT_MAC_LOOPBACK		BIT(7)
850 #define PORT_FORCE_TX_FLOW_CTRL		BIT(4)
851 #define PORT_FORCE_RX_FLOW_CTRL		BIT(3)
852 #define PORT_TAIL_TAG_ENABLE		BIT(2)
853 #define PORT_QUEUE_SPLIT_ENABLE		0x3
854 
855 #define REG_PORT_CTRL_1			0x0021
856 
857 #define PORT_SRP_ENABLE			0x3
858 
859 #define REG_PORT_STATUS_0		0x0030
860 
861 #define PORT_INTF_SPEED_M		0x3
862 #define PORT_INTF_SPEED_S		3
863 #define PORT_INTF_FULL_DUPLEX		BIT(2)
864 #define PORT_TX_FLOW_CTRL		BIT(1)
865 #define PORT_RX_FLOW_CTRL		BIT(0)
866 
867 #define REG_PORT_STATUS_1		0x0034
868 
869 /* 1 - PHY */
870 #define REG_PORT_PHY_CTRL		0x0100
871 
872 #define PORT_PHY_RESET			BIT(15)
873 #define PORT_PHY_LOOPBACK		BIT(14)
874 #define PORT_SPEED_100MBIT		BIT(13)
875 #define PORT_AUTO_NEG_ENABLE		BIT(12)
876 #define PORT_POWER_DOWN			BIT(11)
877 #define PORT_ISOLATE			BIT(10)
878 #define PORT_AUTO_NEG_RESTART		BIT(9)
879 #define PORT_FULL_DUPLEX		BIT(8)
880 #define PORT_COLLISION_TEST		BIT(7)
881 #define PORT_SPEED_1000MBIT		BIT(6)
882 
883 #define REG_PORT_PHY_STATUS		0x0102
884 
885 #define PORT_100BT4_CAPABLE		BIT(15)
886 #define PORT_100BTX_FD_CAPABLE		BIT(14)
887 #define PORT_100BTX_CAPABLE		BIT(13)
888 #define PORT_10BT_FD_CAPABLE		BIT(12)
889 #define PORT_10BT_CAPABLE		BIT(11)
890 #define PORT_EXTENDED_STATUS		BIT(8)
891 #define PORT_MII_SUPPRESS_CAPABLE	BIT(6)
892 #define PORT_AUTO_NEG_ACKNOWLEDGE	BIT(5)
893 #define PORT_REMOTE_FAULT		BIT(4)
894 #define PORT_AUTO_NEG_CAPABLE		BIT(3)
895 #define PORT_LINK_STATUS		BIT(2)
896 #define PORT_JABBER_DETECT		BIT(1)
897 #define PORT_EXTENDED_CAPABILITY	BIT(0)
898 
899 #define REG_PORT_PHY_ID_HI		0x0104
900 #define REG_PORT_PHY_ID_LO		0x0106
901 
902 #define KSZ9477_ID_HI			0x0022
903 #define KSZ9477_ID_LO			0x1622
904 
905 #define REG_PORT_PHY_AUTO_NEGOTIATION	0x0108
906 
907 #define PORT_AUTO_NEG_NEXT_PAGE		BIT(15)
908 #define PORT_AUTO_NEG_REMOTE_FAULT	BIT(13)
909 #define PORT_AUTO_NEG_ASYM_PAUSE	BIT(11)
910 #define PORT_AUTO_NEG_SYM_PAUSE		BIT(10)
911 #define PORT_AUTO_NEG_100BT4		BIT(9)
912 #define PORT_AUTO_NEG_100BTX_FD		BIT(8)
913 #define PORT_AUTO_NEG_100BTX		BIT(7)
914 #define PORT_AUTO_NEG_10BT_FD		BIT(6)
915 #define PORT_AUTO_NEG_10BT		BIT(5)
916 #define PORT_AUTO_NEG_SELECTOR		0x001F
917 #define PORT_AUTO_NEG_802_3		0x0001
918 
919 #define PORT_AUTO_NEG_PAUSE		\
920 	(PORT_AUTO_NEG_ASYM_PAUSE | PORT_AUTO_NEG_SYM_PAUSE)
921 
922 #define REG_PORT_PHY_REMOTE_CAPABILITY	0x010A
923 
924 #define PORT_REMOTE_NEXT_PAGE		BIT(15)
925 #define PORT_REMOTE_ACKNOWLEDGE		BIT(14)
926 #define PORT_REMOTE_REMOTE_FAULT	BIT(13)
927 #define PORT_REMOTE_ASYM_PAUSE		BIT(11)
928 #define PORT_REMOTE_SYM_PAUSE		BIT(10)
929 #define PORT_REMOTE_100BTX_FD		BIT(8)
930 #define PORT_REMOTE_100BTX		BIT(7)
931 #define PORT_REMOTE_10BT_FD		BIT(6)
932 #define PORT_REMOTE_10BT		BIT(5)
933 
934 #define REG_PORT_PHY_1000_CTRL		0x0112
935 
936 #define PORT_AUTO_NEG_MANUAL		BIT(12)
937 #define PORT_AUTO_NEG_MASTER		BIT(11)
938 #define PORT_AUTO_NEG_MASTER_PREFERRED	BIT(10)
939 #define PORT_AUTO_NEG_1000BT_FD		BIT(9)
940 #define PORT_AUTO_NEG_1000BT		BIT(8)
941 
942 #define REG_PORT_PHY_1000_STATUS	0x0114
943 
944 #define PORT_MASTER_FAULT		BIT(15)
945 #define PORT_LOCAL_MASTER		BIT(14)
946 #define PORT_LOCAL_RX_OK		BIT(13)
947 #define PORT_REMOTE_RX_OK		BIT(12)
948 #define PORT_REMOTE_1000BT_FD		BIT(11)
949 #define PORT_REMOTE_1000BT		BIT(10)
950 #define PORT_REMOTE_IDLE_CNT_M		0x0F
951 
952 #define PORT_PHY_1000_STATIC_STATUS	\
953 	(PORT_LOCAL_RX_OK |		\
954 	PORT_REMOTE_RX_OK |		\
955 	PORT_REMOTE_1000BT_FD |		\
956 	PORT_REMOTE_1000BT)
957 
958 #define REG_PORT_PHY_MMD_SETUP		0x011A
959 
960 #define PORT_MMD_OP_MODE_M		0x3
961 #define PORT_MMD_OP_MODE_S		14
962 #define PORT_MMD_OP_INDEX		0
963 #define PORT_MMD_OP_DATA_NO_INCR	1
964 #define PORT_MMD_OP_DATA_INCR_RW	2
965 #define PORT_MMD_OP_DATA_INCR_W		3
966 #define PORT_MMD_DEVICE_ID_M		0x1F
967 
968 #define MMD_SETUP(mode, dev)		\
969 	(((u16)(mode) << PORT_MMD_OP_MODE_S) | (dev))
970 
971 #define REG_PORT_PHY_MMD_INDEX_DATA	0x011C
972 
973 #define MMD_DEVICE_ID_DSP		1
974 
975 #define MMD_DSP_SQI_CHAN_A		0xAC
976 #define MMD_DSP_SQI_CHAN_B		0xAD
977 #define MMD_DSP_SQI_CHAN_C		0xAE
978 #define MMD_DSP_SQI_CHAN_D		0xAF
979 
980 #define DSP_SQI_ERR_DETECTED		BIT(15)
981 #define DSP_SQI_AVG_ERR			0x7FFF
982 
983 #define MMD_DEVICE_ID_COMMON		2
984 
985 #define MMD_DEVICE_ID_EEE_ADV		7
986 
987 #define MMD_EEE_ADV			0x3C
988 #define EEE_ADV_100MBIT			BIT(1)
989 #define EEE_ADV_1GBIT			BIT(2)
990 
991 #define MMD_EEE_LP_ADV			0x3D
992 #define MMD_EEE_MSG_CODE		0x3F
993 
994 #define MMD_DEVICE_ID_AFED		0x1C
995 
996 #define REG_PORT_PHY_EXTENDED_STATUS	0x011E
997 
998 #define PORT_100BTX_FD_ABLE		BIT(15)
999 #define PORT_100BTX_ABLE		BIT(14)
1000 #define PORT_10BT_FD_ABLE		BIT(13)
1001 #define PORT_10BT_ABLE			BIT(12)
1002 
1003 #define REG_PORT_SGMII_ADDR__4		0x0200
1004 #define PORT_SGMII_AUTO_INCR		BIT(23)
1005 #define PORT_SGMII_DEVICE_ID_M		0x1F
1006 #define PORT_SGMII_DEVICE_ID_S		16
1007 #define PORT_SGMII_ADDR_M		(BIT(21) - 1)
1008 
1009 #define REG_PORT_SGMII_DATA__4		0x0204
1010 #define PORT_SGMII_DATA_M		(BIT(16) - 1)
1011 
1012 #define MMD_DEVICE_ID_PMA		0x01
1013 #define MMD_DEVICE_ID_PCS		0x03
1014 #define MMD_DEVICE_ID_PHY_XS		0x04
1015 #define MMD_DEVICE_ID_DTE_XS		0x05
1016 #define MMD_DEVICE_ID_AN		0x07
1017 #define MMD_DEVICE_ID_VENDOR_CTRL	0x1E
1018 #define MMD_DEVICE_ID_VENDOR_MII	0x1F
1019 
1020 #define SR_MII				MMD_DEVICE_ID_VENDOR_MII
1021 
1022 #define MMD_SR_MII_CTRL			0x0000
1023 
1024 #define SR_MII_RESET			BIT(15)
1025 #define SR_MII_LOOPBACK			BIT(14)
1026 #define SR_MII_SPEED_100MBIT		BIT(13)
1027 #define SR_MII_AUTO_NEG_ENABLE		BIT(12)
1028 #define SR_MII_POWER_DOWN		BIT(11)
1029 #define SR_MII_AUTO_NEG_RESTART		BIT(9)
1030 #define SR_MII_FULL_DUPLEX		BIT(8)
1031 #define SR_MII_SPEED_1000MBIT		BIT(6)
1032 
1033 #define MMD_SR_MII_STATUS		0x0001
1034 #define MMD_SR_MII_ID_1			0x0002
1035 #define MMD_SR_MII_ID_2			0x0003
1036 #define MMD_SR_MII_AUTO_NEGOTIATION	0x0004
1037 
1038 #define SR_MII_AUTO_NEG_NEXT_PAGE	BIT(15)
1039 #define SR_MII_AUTO_NEG_REMOTE_FAULT_M	0x3
1040 #define SR_MII_AUTO_NEG_REMOTE_FAULT_S	12
1041 #define SR_MII_AUTO_NEG_NO_ERROR	0
1042 #define SR_MII_AUTO_NEG_OFFLINE		1
1043 #define SR_MII_AUTO_NEG_LINK_FAILURE	2
1044 #define SR_MII_AUTO_NEG_ERROR		3
1045 #define SR_MII_AUTO_NEG_PAUSE_M		0x3
1046 #define SR_MII_AUTO_NEG_PAUSE_S		7
1047 #define SR_MII_AUTO_NEG_NO_PAUSE	0
1048 #define SR_MII_AUTO_NEG_ASYM_PAUSE_TX	1
1049 #define SR_MII_AUTO_NEG_SYM_PAUSE	2
1050 #define SR_MII_AUTO_NEG_ASYM_PAUSE_RX	3
1051 #define SR_MII_AUTO_NEG_HALF_DUPLEX	BIT(6)
1052 #define SR_MII_AUTO_NEG_FULL_DUPLEX	BIT(5)
1053 
1054 #define MMD_SR_MII_REMOTE_CAPABILITY	0x0005
1055 #define MMD_SR_MII_AUTO_NEG_EXP		0x0006
1056 #define MMD_SR_MII_AUTO_NEG_EXT		0x000F
1057 
1058 #define MMD_SR_MII_DIGITAL_CTRL_1	0x8000
1059 
1060 #define MMD_SR_MII_AUTO_NEG_CTRL	0x8001
1061 
1062 #define SR_MII_8_BIT			BIT(8)
1063 #define SR_MII_SGMII_LINK_UP		BIT(4)
1064 #define SR_MII_TX_CFG_PHY_MASTER	BIT(3)
1065 #define SR_MII_PCS_MODE_M		0x3
1066 #define SR_MII_PCS_MODE_S		1
1067 #define SR_MII_PCS_SGMII		2
1068 #define SR_MII_AUTO_NEG_COMPLETE_INTR	BIT(0)
1069 
1070 #define MMD_SR_MII_AUTO_NEG_STATUS	0x8002
1071 
1072 #define SR_MII_STAT_LINK_UP		BIT(4)
1073 #define SR_MII_STAT_M			0x3
1074 #define SR_MII_STAT_S			2
1075 #define SR_MII_STAT_10_MBPS		0
1076 #define SR_MII_STAT_100_MBPS		1
1077 #define SR_MII_STAT_1000_MBPS		2
1078 #define SR_MII_STAT_FULL_DUPLEX		BIT(1)
1079 
1080 #define MMD_SR_MII_PHY_CTRL		0x80A0
1081 
1082 #define SR_MII_PHY_LANE_SEL_M		0xF
1083 #define SR_MII_PHY_LANE_SEL_S		8
1084 #define SR_MII_PHY_WRITE		BIT(1)
1085 #define SR_MII_PHY_START_BUSY		BIT(0)
1086 
1087 #define MMD_SR_MII_PHY_ADDR		0x80A1
1088 
1089 #define SR_MII_PHY_ADDR_M		(BIT(16) - 1)
1090 
1091 #define MMD_SR_MII_PHY_DATA		0x80A2
1092 
1093 #define SR_MII_PHY_DATA_M		(BIT(16) - 1)
1094 
1095 #define SR_MII_PHY_JTAG_CHIP_ID_HI	0x000C
1096 #define SR_MII_PHY_JTAG_CHIP_ID_LO	0x000D
1097 
1098 #define REG_PORT_PHY_REMOTE_LB_LED	0x0122
1099 
1100 #define PORT_REMOTE_LOOPBACK		BIT(8)
1101 #define PORT_LED_SELECT			(3 << 6)
1102 #define PORT_LED_CTRL			(3 << 4)
1103 #define PORT_LED_CTRL_TEST		BIT(3)
1104 #define PORT_10BT_PREAMBLE		BIT(2)
1105 #define PORT_LINK_MD_10BT_ENABLE	BIT(1)
1106 #define PORT_LINK_MD_PASS		BIT(0)
1107 
1108 #define REG_PORT_PHY_LINK_MD		0x0124
1109 
1110 #define PORT_START_CABLE_DIAG		BIT(15)
1111 #define PORT_TX_DISABLE			BIT(14)
1112 #define PORT_CABLE_DIAG_PAIR_M		0x3
1113 #define PORT_CABLE_DIAG_PAIR_S		12
1114 #define PORT_CABLE_DIAG_SELECT_M	0x3
1115 #define PORT_CABLE_DIAG_SELECT_S	10
1116 #define PORT_CABLE_DIAG_RESULT_M	0x3
1117 #define PORT_CABLE_DIAG_RESULT_S	8
1118 #define PORT_CABLE_STAT_NORMAL		0
1119 #define PORT_CABLE_STAT_OPEN		1
1120 #define PORT_CABLE_STAT_SHORT		2
1121 #define PORT_CABLE_STAT_FAILED		3
1122 #define PORT_CABLE_FAULT_COUNTER	0x00FF
1123 
1124 #define REG_PORT_PHY_PMA_STATUS		0x0126
1125 
1126 #define PORT_1000_LINK_GOOD		BIT(1)
1127 #define PORT_100_LINK_GOOD		BIT(0)
1128 
1129 #define REG_PORT_PHY_DIGITAL_STATUS	0x0128
1130 
1131 #define PORT_LINK_DETECT		BIT(14)
1132 #define PORT_SIGNAL_DETECT		BIT(13)
1133 #define PORT_PHY_STAT_MDI		BIT(12)
1134 #define PORT_PHY_STAT_MASTER		BIT(11)
1135 
1136 #define REG_PORT_PHY_RXER_COUNTER	0x012A
1137 
1138 #define REG_PORT_PHY_INT_ENABLE		0x0136
1139 #define REG_PORT_PHY_INT_STATUS		0x0137
1140 
1141 #define JABBER_INT			BIT(7)
1142 #define RX_ERR_INT			BIT(6)
1143 #define PAGE_RX_INT			BIT(5)
1144 #define PARALLEL_DETECT_FAULT_INT	BIT(4)
1145 #define LINK_PARTNER_ACK_INT		BIT(3)
1146 #define LINK_DOWN_INT			BIT(2)
1147 #define REMOTE_FAULT_INT		BIT(1)
1148 #define LINK_UP_INT			BIT(0)
1149 
1150 #define REG_PORT_PHY_DIGITAL_DEBUG_1	0x0138
1151 
1152 #define PORT_REG_CLK_SPEED_25_MHZ	BIT(14)
1153 #define PORT_PHY_FORCE_MDI		BIT(7)
1154 #define PORT_PHY_AUTO_MDIX_DISABLE	BIT(6)
1155 
1156 /* Same as PORT_PHY_LOOPBACK */
1157 #define PORT_PHY_PCS_LOOPBACK		BIT(0)
1158 
1159 #define REG_PORT_PHY_DIGITAL_DEBUG_2	0x013A
1160 
1161 #define REG_PORT_PHY_DIGITAL_DEBUG_3	0x013C
1162 
1163 #define PORT_100BT_FIXED_LATENCY	BIT(15)
1164 
1165 #define REG_PORT_PHY_PHY_CTRL		0x013E
1166 
1167 #define PORT_INT_PIN_HIGH		BIT(14)
1168 #define PORT_ENABLE_JABBER		BIT(9)
1169 #define PORT_STAT_SPEED_1000MBIT	BIT(6)
1170 #define PORT_STAT_SPEED_100MBIT		BIT(5)
1171 #define PORT_STAT_SPEED_10MBIT		BIT(4)
1172 #define PORT_STAT_FULL_DUPLEX		BIT(3)
1173 
1174 /* Same as PORT_PHY_STAT_MASTER */
1175 #define PORT_STAT_MASTER		BIT(2)
1176 #define PORT_RESET			BIT(1)
1177 #define PORT_LINK_STATUS_FAIL		BIT(0)
1178 
1179 /* 3 - xMII */
1180 #define PORT_SGMII_SEL			BIT(7)
1181 #define PORT_GRXC_ENABLE		BIT(0)
1182 
1183 #define PORT_RMII_CLK_SEL		BIT(7)
1184 #define PORT_MII_SEL_EDGE		BIT(5)
1185 
1186 /* 4 - MAC */
1187 #define REG_PORT_MAC_CTRL_0		0x0400
1188 
1189 #define PORT_BROADCAST_STORM		BIT(1)
1190 #define PORT_JUMBO_FRAME		BIT(0)
1191 
1192 #define REG_PORT_MAC_CTRL_1		0x0401
1193 
1194 #define PORT_BACK_PRESSURE		BIT(3)
1195 #define PORT_PASS_ALL			BIT(0)
1196 
1197 #define REG_PORT_MAC_CTRL_2		0x0402
1198 
1199 #define PORT_100BT_EEE_DISABLE		BIT(7)
1200 #define PORT_1000BT_EEE_DISABLE		BIT(6)
1201 
1202 #define REG_PORT_MAC_IN_RATE_LIMIT	0x0403
1203 
1204 #define PORT_IN_PORT_BASED_S		6
1205 #define PORT_RATE_PACKET_BASED_S	5
1206 #define PORT_IN_FLOW_CTRL_S		4
1207 #define PORT_COUNT_IFG_S		1
1208 #define PORT_COUNT_PREAMBLE_S		0
1209 #define PORT_IN_PORT_BASED		BIT(6)
1210 #define PORT_IN_PACKET_BASED		BIT(5)
1211 #define PORT_IN_FLOW_CTRL		BIT(4)
1212 #define PORT_IN_LIMIT_MODE_M		0x3
1213 #define PORT_IN_LIMIT_MODE_S		2
1214 #define PORT_IN_ALL			0
1215 #define PORT_IN_UNICAST			1
1216 #define PORT_IN_MULTICAST		2
1217 #define PORT_IN_BROADCAST		3
1218 #define PORT_COUNT_IFG			BIT(1)
1219 #define PORT_COUNT_PREAMBLE		BIT(0)
1220 
1221 #define REG_PORT_IN_RATE_0		0x0410
1222 #define REG_PORT_IN_RATE_1		0x0411
1223 #define REG_PORT_IN_RATE_2		0x0412
1224 #define REG_PORT_IN_RATE_3		0x0413
1225 #define REG_PORT_IN_RATE_4		0x0414
1226 #define REG_PORT_IN_RATE_5		0x0415
1227 #define REG_PORT_IN_RATE_6		0x0416
1228 #define REG_PORT_IN_RATE_7		0x0417
1229 
1230 #define REG_PORT_OUT_RATE_0		0x0420
1231 #define REG_PORT_OUT_RATE_1		0x0421
1232 #define REG_PORT_OUT_RATE_2		0x0422
1233 #define REG_PORT_OUT_RATE_3		0x0423
1234 
1235 #define PORT_RATE_LIMIT_M		(BIT(7) - 1)
1236 
1237 /* 5 - MIB Counters */
1238 #define REG_PORT_MIB_CTRL_STAT__4	0x0500
1239 
1240 #define MIB_COUNTER_READ		BIT(25)
1241 #define MIB_COUNTER_FLUSH_FREEZE	BIT(24)
1242 #define MIB_COUNTER_INDEX_M		(BIT(8) - 1)
1243 #define MIB_COUNTER_INDEX_S		16
1244 #define MIB_COUNTER_DATA_HI_M		0xF
1245 
1246 #define REG_PORT_MIB_DATA		0x0504
1247 
1248 /* 6 - ACL */
1249 #define REG_PORT_ACL_0			0x0600
1250 
1251 #define ACL_FIRST_RULE_M		0xF
1252 
1253 #define REG_PORT_ACL_1			0x0601
1254 
1255 #define ACL_MODE_M			0x3
1256 #define ACL_MODE_S			4
1257 #define ACL_MODE_DISABLE		0
1258 #define ACL_MODE_LAYER_2		1
1259 #define ACL_MODE_LAYER_3		2
1260 #define ACL_MODE_LAYER_4		3
1261 #define ACL_ENABLE_M			0x3
1262 #define ACL_ENABLE_S			2
1263 #define ACL_ENABLE_2_COUNT		0
1264 #define ACL_ENABLE_2_TYPE		1
1265 #define ACL_ENABLE_2_MAC		2
1266 #define ACL_ENABLE_2_BOTH		3
1267 #define ACL_ENABLE_3_IP			1
1268 #define ACL_ENABLE_3_SRC_DST_COMP	2
1269 #define ACL_ENABLE_4_PROTOCOL		0
1270 #define ACL_ENABLE_4_TCP_PORT_COMP	1
1271 #define ACL_ENABLE_4_UDP_PORT_COMP	2
1272 #define ACL_ENABLE_4_TCP_SEQN_COMP	3
1273 #define ACL_SRC				BIT(1)
1274 #define ACL_EQUAL			BIT(0)
1275 
1276 #define REG_PORT_ACL_2			0x0602
1277 #define REG_PORT_ACL_3			0x0603
1278 
1279 #define ACL_MAX_PORT			0xFFFF
1280 
1281 #define REG_PORT_ACL_4			0x0604
1282 #define REG_PORT_ACL_5			0x0605
1283 
1284 #define ACL_MIN_PORT			0xFFFF
1285 #define ACL_IP_ADDR			0xFFFFFFFF
1286 #define ACL_TCP_SEQNUM			0xFFFFFFFF
1287 
1288 #define REG_PORT_ACL_6			0x0606
1289 
1290 #define ACL_RESERVED			0xF8
1291 #define ACL_PORT_MODE_M			0x3
1292 #define ACL_PORT_MODE_S			1
1293 #define ACL_PORT_MODE_DISABLE		0
1294 #define ACL_PORT_MODE_EITHER		1
1295 #define ACL_PORT_MODE_IN_RANGE		2
1296 #define ACL_PORT_MODE_OUT_OF_RANGE	3
1297 
1298 #define REG_PORT_ACL_7			0x0607
1299 
1300 #define ACL_TCP_FLAG_ENABLE		BIT(0)
1301 
1302 #define REG_PORT_ACL_8			0x0608
1303 
1304 #define ACL_TCP_FLAG_M			0xFF
1305 
1306 #define REG_PORT_ACL_9			0x0609
1307 
1308 #define ACL_TCP_FLAG			0xFF
1309 #define ACL_ETH_TYPE			0xFFFF
1310 #define ACL_IP_M			0xFFFFFFFF
1311 
1312 #define REG_PORT_ACL_A			0x060A
1313 
1314 #define ACL_PRIO_MODE_M			0x3
1315 #define ACL_PRIO_MODE_S			6
1316 #define ACL_PRIO_MODE_DISABLE		0
1317 #define ACL_PRIO_MODE_HIGHER		1
1318 #define ACL_PRIO_MODE_LOWER		2
1319 #define ACL_PRIO_MODE_REPLACE		3
1320 #define ACL_PRIO_M			KS_PRIO_M
1321 #define ACL_PRIO_S			3
1322 #define ACL_VLAN_PRIO_REPLACE		BIT(2)
1323 #define ACL_VLAN_PRIO_M			KS_PRIO_M
1324 #define ACL_VLAN_PRIO_HI_M		0x3
1325 
1326 #define REG_PORT_ACL_B			0x060B
1327 
1328 #define ACL_VLAN_PRIO_LO_M		0x8
1329 #define ACL_VLAN_PRIO_S			7
1330 #define ACL_MAP_MODE_M			0x3
1331 #define ACL_MAP_MODE_S			5
1332 #define ACL_MAP_MODE_DISABLE		0
1333 #define ACL_MAP_MODE_OR			1
1334 #define ACL_MAP_MODE_AND		2
1335 #define ACL_MAP_MODE_REPLACE		3
1336 
1337 #define ACL_CNT_M			(BIT(11) - 1)
1338 #define ACL_CNT_S			5
1339 
1340 #define REG_PORT_ACL_C			0x060C
1341 
1342 #define REG_PORT_ACL_D			0x060D
1343 #define ACL_MSEC_UNIT			BIT(6)
1344 #define ACL_INTR_MODE			BIT(5)
1345 #define ACL_PORT_MAP			0x7F
1346 
1347 #define REG_PORT_ACL_E			0x060E
1348 #define REG_PORT_ACL_F			0x060F
1349 
1350 #define REG_PORT_ACL_BYTE_EN_MSB	0x0610
1351 #define REG_PORT_ACL_BYTE_EN_LSB	0x0611
1352 
1353 #define ACL_ACTION_START		0xA
1354 #define ACL_ACTION_LEN			4
1355 #define ACL_INTR_CNT_START		0xD
1356 #define ACL_RULESET_START		0xE
1357 #define ACL_RULESET_LEN			2
1358 #define ACL_TABLE_LEN			16
1359 
1360 #define ACL_ACTION_ENABLE		0x003C
1361 #define ACL_MATCH_ENABLE		0x7FC3
1362 #define ACL_RULESET_ENABLE		0x8003
1363 #define ACL_BYTE_ENABLE			0xFFFF
1364 
1365 #define REG_PORT_ACL_CTRL_0		0x0612
1366 
1367 #define PORT_ACL_WRITE_DONE		BIT(6)
1368 #define PORT_ACL_READ_DONE		BIT(5)
1369 #define PORT_ACL_WRITE			BIT(4)
1370 #define PORT_ACL_INDEX_M		0xF
1371 
1372 #define REG_PORT_ACL_CTRL_1		0x0613
1373 
1374 /* 8 - Classification and Policing */
1375 #define REG_PORT_MRI_MIRROR_CTRL	0x0800
1376 
1377 #define PORT_MIRROR_RX			BIT(6)
1378 #define PORT_MIRROR_TX			BIT(5)
1379 #define PORT_MIRROR_SNIFFER		BIT(1)
1380 
1381 #define REG_PORT_MRI_PRIO_CTRL		0x0801
1382 
1383 #define PORT_HIGHEST_PRIO		BIT(7)
1384 #define PORT_OR_PRIO			BIT(6)
1385 #define PORT_MAC_PRIO_ENABLE		BIT(4)
1386 #define PORT_VLAN_PRIO_ENABLE		BIT(3)
1387 #define PORT_802_1P_PRIO_ENABLE		BIT(2)
1388 #define PORT_DIFFSERV_PRIO_ENABLE	BIT(1)
1389 #define PORT_ACL_PRIO_ENABLE		BIT(0)
1390 
1391 #define REG_PORT_MRI_MAC_CTRL		0x0802
1392 
1393 #define PORT_USER_PRIO_CEILING		BIT(7)
1394 #define PORT_DROP_NON_VLAN		BIT(4)
1395 #define PORT_DROP_TAG			BIT(3)
1396 #define PORT_BASED_PRIO_M		KS_PRIO_M
1397 #define PORT_BASED_PRIO_S		0
1398 
1399 #define REG_PORT_MRI_AUTHEN_CTRL	0x0803
1400 
1401 #define PORT_ACL_ENABLE			BIT(2)
1402 #define PORT_AUTHEN_MODE		0x3
1403 #define PORT_AUTHEN_PASS		0
1404 #define PORT_AUTHEN_BLOCK		1
1405 #define PORT_AUTHEN_TRAP		2
1406 
1407 #define REG_PORT_MRI_INDEX__4		0x0804
1408 
1409 #define MRI_INDEX_P_M			0x7
1410 #define MRI_INDEX_P_S			16
1411 #define MRI_INDEX_Q_M			0x3
1412 #define MRI_INDEX_Q_S			0
1413 
1414 #define REG_PORT_MRI_TC_MAP__4		0x0808
1415 
1416 #define PORT_TC_MAP_M			0xf
1417 #define PORT_TC_MAP_S			4
1418 
1419 #define REG_PORT_MRI_POLICE_CTRL__4	0x080C
1420 
1421 #define POLICE_DROP_ALL			BIT(10)
1422 #define POLICE_PACKET_TYPE_M		0x3
1423 #define POLICE_PACKET_TYPE_S		8
1424 #define POLICE_PACKET_DROPPED		0
1425 #define POLICE_PACKET_GREEN		1
1426 #define POLICE_PACKET_YELLOW		2
1427 #define POLICE_PACKET_RED		3
1428 #define PORT_BASED_POLICING		BIT(7)
1429 #define NON_DSCP_COLOR_M		0x3
1430 #define NON_DSCP_COLOR_S		5
1431 #define COLOR_MARK_ENABLE		BIT(4)
1432 #define COLOR_REMAP_ENABLE		BIT(3)
1433 #define POLICE_DROP_SRP			BIT(2)
1434 #define POLICE_COLOR_NOT_AWARE		BIT(1)
1435 #define POLICE_ENABLE			BIT(0)
1436 
1437 #define REG_PORT_POLICE_COLOR_0__4	0x0810
1438 #define REG_PORT_POLICE_COLOR_1__4	0x0814
1439 #define REG_PORT_POLICE_COLOR_2__4	0x0818
1440 #define REG_PORT_POLICE_COLOR_3__4	0x081C
1441 
1442 #define POLICE_COLOR_MAP_S		2
1443 #define POLICE_COLOR_MAP_M		(BIT(POLICE_COLOR_MAP_S) - 1)
1444 
1445 #define REG_PORT_POLICE_RATE__4		0x0820
1446 
1447 #define POLICE_CIR_S			16
1448 #define POLICE_PIR_S			0
1449 
1450 #define REG_PORT_POLICE_BURST_SIZE__4	0x0824
1451 
1452 #define POLICE_BURST_SIZE_M		0x3FFF
1453 #define POLICE_CBS_S			16
1454 #define POLICE_PBS_S			0
1455 
1456 #define REG_PORT_WRED_PM_CTRL_0__4	0x0830
1457 
1458 #define WRED_PM_CTRL_M			(BIT(11) - 1)
1459 
1460 #define WRED_PM_MAX_THRESHOLD_S		16
1461 #define WRED_PM_MIN_THRESHOLD_S		0
1462 
1463 #define REG_PORT_WRED_PM_CTRL_1__4	0x0834
1464 
1465 #define WRED_PM_MULTIPLIER_S		16
1466 #define WRED_PM_AVG_QUEUE_SIZE_S	0
1467 
1468 #define REG_PORT_WRED_QUEUE_CTRL_0__4	0x0840
1469 #define REG_PORT_WRED_QUEUE_CTRL_1__4	0x0844
1470 
1471 #define REG_PORT_WRED_QUEUE_PMON__4	0x0848
1472 
1473 #define WRED_RANDOM_DROP_ENABLE		BIT(31)
1474 #define WRED_PMON_FLUSH			BIT(30)
1475 #define WRED_DROP_GYR_DISABLE		BIT(29)
1476 #define WRED_DROP_YR_DISABLE		BIT(28)
1477 #define WRED_DROP_R_DISABLE		BIT(27)
1478 #define WRED_DROP_ALL			BIT(26)
1479 #define WRED_PMON_M			(BIT(24) - 1)
1480 
1481 /* 9 - Shaping */
1482 
1483 #define REG_PORT_MTI_QUEUE_INDEX__4	0x0900
1484 
1485 #define REG_PORT_MTI_QUEUE_CTRL_0__4	0x0904
1486 
1487 #define MTI_PVID_REPLACE		BIT(0)
1488 
1489 #define REG_PORT_MTI_QUEUE_CTRL_0	0x0914
1490 
1491 #define MTI_SCHEDULE_MODE_M		0x3
1492 #define MTI_SCHEDULE_MODE_S		6
1493 #define MTI_SCHEDULE_STRICT_PRIO	0
1494 #define MTI_SCHEDULE_WRR		2
1495 #define MTI_SHAPING_M			0x3
1496 #define MTI_SHAPING_S			4
1497 #define MTI_SHAPING_OFF			0
1498 #define MTI_SHAPING_SRP			1
1499 #define MTI_SHAPING_TIME_AWARE		2
1500 
1501 #define REG_PORT_MTI_QUEUE_CTRL_1	0x0915
1502 
1503 #define MTI_TX_RATIO_M			(BIT(7) - 1)
1504 
1505 #define REG_PORT_MTI_QUEUE_CTRL_2__2	0x0916
1506 #define REG_PORT_MTI_HI_WATER_MARK	0x0916
1507 #define REG_PORT_MTI_QUEUE_CTRL_3__2	0x0918
1508 #define REG_PORT_MTI_LO_WATER_MARK	0x0918
1509 #define REG_PORT_MTI_QUEUE_CTRL_4__2	0x091A
1510 #define REG_PORT_MTI_CREDIT_INCREMENT	0x091A
1511 
1512 /* A - QM */
1513 
1514 #define REG_PORT_QM_CTRL__4		0x0A00
1515 
1516 #define PORT_QM_DROP_PRIO_M		0x3
1517 
1518 #define REG_PORT_VLAN_MEMBERSHIP__4	0x0A04
1519 
1520 #define REG_PORT_QM_QUEUE_INDEX__4	0x0A08
1521 
1522 #define PORT_QM_QUEUE_INDEX_S		24
1523 #define PORT_QM_BURST_SIZE_S		16
1524 #define PORT_QM_MIN_RESV_SPACE_M	(BIT(11) - 1)
1525 
1526 #define REG_PORT_QM_WATER_MARK__4	0x0A0C
1527 
1528 #define PORT_QM_HI_WATER_MARK_S		16
1529 #define PORT_QM_LO_WATER_MARK_S		0
1530 #define PORT_QM_WATER_MARK_M		(BIT(11) - 1)
1531 
1532 #define REG_PORT_QM_TX_CNT_0__4		0x0A10
1533 
1534 #define PORT_QM_TX_CNT_USED_S		0
1535 #define PORT_QM_TX_CNT_M		(BIT(11) - 1)
1536 
1537 #define REG_PORT_QM_TX_CNT_1__4		0x0A14
1538 
1539 #define PORT_QM_TX_CNT_CALCULATED_S	16
1540 #define PORT_QM_TX_CNT_AVAIL_S		0
1541 
1542 /* B - LUE */
1543 #define REG_PORT_LUE_CTRL		0x0B00
1544 
1545 #define PORT_VLAN_LOOKUP_VID_0		BIT(7)
1546 #define PORT_INGRESS_FILTER		BIT(6)
1547 #define PORT_DISCARD_NON_VID		BIT(5)
1548 #define PORT_MAC_BASED_802_1X		BIT(4)
1549 #define PORT_SRC_ADDR_FILTER		BIT(3)
1550 
1551 #define REG_PORT_LUE_MSTP_INDEX		0x0B01
1552 
1553 #define REG_PORT_LUE_MSTP_STATE		0x0B04
1554 
1555 /* C - PTP */
1556 
1557 #define REG_PTP_PORT_RX_DELAY__2	0x0C00
1558 #define REG_PTP_PORT_TX_DELAY__2	0x0C02
1559 #define REG_PTP_PORT_ASYM_DELAY__2	0x0C04
1560 
1561 #define REG_PTP_PORT_XDELAY_TS		0x0C08
1562 #define REG_PTP_PORT_XDELAY_TS_H	0x0C08
1563 #define REG_PTP_PORT_XDELAY_TS_L	0x0C0A
1564 
1565 #define REG_PTP_PORT_SYNC_TS		0x0C0C
1566 #define REG_PTP_PORT_SYNC_TS_H		0x0C0C
1567 #define REG_PTP_PORT_SYNC_TS_L		0x0C0E
1568 
1569 #define REG_PTP_PORT_PDRESP_TS		0x0C10
1570 #define REG_PTP_PORT_PDRESP_TS_H	0x0C10
1571 #define REG_PTP_PORT_PDRESP_TS_L	0x0C12
1572 
1573 #define REG_PTP_PORT_TX_INT_STATUS__2	0x0C14
1574 #define REG_PTP_PORT_TX_INT_ENABLE__2	0x0C16
1575 
1576 #define PTP_PORT_SYNC_INT		BIT(15)
1577 #define PTP_PORT_XDELAY_REQ_INT		BIT(14)
1578 #define PTP_PORT_PDELAY_RESP_INT	BIT(13)
1579 
1580 #define REG_PTP_PORT_LINK_DELAY__4	0x0C18
1581 
1582 #define PRIO_QUEUES			4
1583 #define RX_PRIO_QUEUES			8
1584 
1585 #define KS_PRIO_IN_REG			2
1586 
1587 #define TOTAL_PORT_NUM			7
1588 
1589 #define KSZ9477_COUNTER_NUM		0x20
1590 #define TOTAL_KSZ9477_COUNTER_NUM	(KSZ9477_COUNTER_NUM + 2 + 2)
1591 
1592 #define SWITCH_COUNTER_NUM		KSZ9477_COUNTER_NUM
1593 #define TOTAL_SWITCH_COUNTER_NUM	TOTAL_KSZ9477_COUNTER_NUM
1594 
1595 #define P_BCAST_STORM_CTRL		REG_PORT_MAC_CTRL_0
1596 #define P_PRIO_CTRL			REG_PORT_MRI_PRIO_CTRL
1597 #define P_MIRROR_CTRL			REG_PORT_MRI_MIRROR_CTRL
1598 #define P_PHY_CTRL			REG_PORT_PHY_CTRL
1599 #define P_RATE_LIMIT_CTRL		REG_PORT_MAC_IN_RATE_LIMIT
1600 
1601 #define S_LINK_AGING_CTRL		REG_SW_LUE_CTRL_1
1602 #define S_MIRROR_CTRL			REG_SW_MRI_CTRL_0
1603 #define S_REPLACE_VID_CTRL		REG_SW_MAC_CTRL_2
1604 #define S_802_1P_PRIO_CTRL		REG_SW_MAC_802_1P_MAP_0
1605 #define S_TOS_PRIO_CTRL			REG_SW_MAC_TOS_PRIO_0
1606 #define S_FLUSH_TABLE_CTRL		REG_SW_LUE_CTRL_1
1607 
1608 #define SW_FLUSH_DYN_MAC_TABLE		SW_FLUSH_MSTP_TABLE
1609 
1610 #define MAX_TIMESTAMP_UNIT		2
1611 #define MAX_TRIG_UNIT			3
1612 #define MAX_TIMESTAMP_EVENT_UNIT	8
1613 #define MAX_GPIO			4
1614 
1615 #define PTP_TRIG_UNIT_M			(BIT(MAX_TRIG_UNIT) - 1)
1616 #define PTP_TS_UNIT_M			(BIT(MAX_TIMESTAMP_UNIT) - 1)
1617 
1618 #define KSZ9477_MAX_FRAME_SIZE		9000
1619 
1620 #endif /* KSZ9477_REGS_H */
1621