1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ9477 switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/iopoll.h> 11 #include <linux/platform_data/microchip-ksz.h> 12 #include <linux/phy.h> 13 #include <linux/if_bridge.h> 14 #include <linux/if_vlan.h> 15 #include <net/dsa.h> 16 #include <net/switchdev.h> 17 18 #include "ksz9477_reg.h" 19 #include "ksz_common.h" 20 #include "ksz9477.h" 21 22 /* Used with variable features to indicate capabilities. */ 23 #define GBIT_SUPPORT BIT(0) 24 #define NEW_XMII BIT(1) 25 #define IS_9893 BIT(2) 26 27 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 28 { 29 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0); 30 } 31 32 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 33 bool set) 34 { 35 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset), 36 bits, set ? bits : 0); 37 } 38 39 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set) 40 { 41 regmap_update_bits(dev->regmap[2], addr, bits, set ? bits : 0); 42 } 43 44 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset, 45 u32 bits, bool set) 46 { 47 regmap_update_bits(dev->regmap[2], PORT_CTRL_ADDR(port, offset), 48 bits, set ? bits : 0); 49 } 50 51 int ksz9477_change_mtu(struct ksz_device *dev, int port, int mtu) 52 { 53 u16 frame_size, max_frame = 0; 54 int i; 55 56 frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 57 58 /* Cache the per-port MTU setting */ 59 dev->ports[port].max_frame = frame_size; 60 61 for (i = 0; i < dev->info->port_cnt; i++) 62 max_frame = max(max_frame, dev->ports[i].max_frame); 63 64 return regmap_update_bits(dev->regmap[1], REG_SW_MTU__2, 65 REG_SW_MTU_MASK, max_frame); 66 } 67 68 int ksz9477_max_mtu(struct ksz_device *dev, int port) 69 { 70 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 71 } 72 73 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev) 74 { 75 unsigned int val; 76 77 return regmap_read_poll_timeout(dev->regmap[0], REG_SW_VLAN_CTRL, 78 val, !(val & VLAN_START), 10, 1000); 79 } 80 81 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid, 82 u32 *vlan_table) 83 { 84 int ret; 85 86 mutex_lock(&dev->vlan_mutex); 87 88 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 89 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START); 90 91 /* wait to be cleared */ 92 ret = ksz9477_wait_vlan_ctrl_ready(dev); 93 if (ret) { 94 dev_dbg(dev->dev, "Failed to read vlan table\n"); 95 goto exit; 96 } 97 98 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]); 99 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]); 100 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]); 101 102 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 103 104 exit: 105 mutex_unlock(&dev->vlan_mutex); 106 107 return ret; 108 } 109 110 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid, 111 u32 *vlan_table) 112 { 113 int ret; 114 115 mutex_lock(&dev->vlan_mutex); 116 117 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]); 118 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]); 119 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]); 120 121 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 122 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE); 123 124 /* wait to be cleared */ 125 ret = ksz9477_wait_vlan_ctrl_ready(dev); 126 if (ret) { 127 dev_dbg(dev->dev, "Failed to write vlan table\n"); 128 goto exit; 129 } 130 131 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 132 133 /* update vlan cache table */ 134 dev->vlan_cache[vid].table[0] = vlan_table[0]; 135 dev->vlan_cache[vid].table[1] = vlan_table[1]; 136 dev->vlan_cache[vid].table[2] = vlan_table[2]; 137 138 exit: 139 mutex_unlock(&dev->vlan_mutex); 140 141 return ret; 142 } 143 144 static void ksz9477_read_table(struct ksz_device *dev, u32 *table) 145 { 146 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]); 147 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]); 148 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]); 149 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]); 150 } 151 152 static void ksz9477_write_table(struct ksz_device *dev, u32 *table) 153 { 154 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]); 155 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]); 156 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]); 157 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]); 158 } 159 160 static int ksz9477_wait_alu_ready(struct ksz_device *dev) 161 { 162 unsigned int val; 163 164 return regmap_read_poll_timeout(dev->regmap[2], REG_SW_ALU_CTRL__4, 165 val, !(val & ALU_START), 10, 1000); 166 } 167 168 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev) 169 { 170 unsigned int val; 171 172 return regmap_read_poll_timeout(dev->regmap[2], 173 REG_SW_ALU_STAT_CTRL__4, 174 val, !(val & ALU_STAT_START), 175 10, 1000); 176 } 177 178 int ksz9477_reset_switch(struct ksz_device *dev) 179 { 180 u8 data8; 181 u32 data32; 182 183 /* reset switch */ 184 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 185 186 /* turn off SPI DO Edge select */ 187 regmap_update_bits(dev->regmap[0], REG_SW_GLOBAL_SERIAL_CTRL_0, 188 SPI_AUTO_EDGE_DETECTION, 0); 189 190 /* default configuration */ 191 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8); 192 data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING | 193 SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE; 194 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8); 195 196 /* disable interrupts */ 197 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 198 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F); 199 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 200 201 data8 = SW_ENABLE_REFCLKO; 202 if (dev->synclko_disable) 203 data8 = 0; 204 else if (dev->synclko_125) 205 data8 = SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ; 206 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, data8); 207 208 return 0; 209 } 210 211 void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt) 212 { 213 struct ksz_port *p = &dev->ports[port]; 214 unsigned int val; 215 u32 data; 216 int ret; 217 218 /* retain the flush/freeze bit */ 219 data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 220 data |= MIB_COUNTER_READ; 221 data |= (addr << MIB_COUNTER_INDEX_S); 222 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data); 223 224 ret = regmap_read_poll_timeout(dev->regmap[2], 225 PORT_CTRL_ADDR(port, REG_PORT_MIB_CTRL_STAT__4), 226 val, !(val & MIB_COUNTER_READ), 10, 1000); 227 /* failed to read MIB. get out of loop */ 228 if (ret) { 229 dev_dbg(dev->dev, "Failed to get MIB\n"); 230 return; 231 } 232 233 /* count resets upon read */ 234 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data); 235 *cnt += data; 236 } 237 238 void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 239 u64 *dropped, u64 *cnt) 240 { 241 addr = dev->info->mib_names[addr].index; 242 ksz9477_r_mib_cnt(dev, port, addr, cnt); 243 } 244 245 void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze) 246 { 247 u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 248 struct ksz_port *p = &dev->ports[port]; 249 250 /* enable/disable the port for flush/freeze function */ 251 mutex_lock(&p->mib.cnt_mutex); 252 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val); 253 254 /* used by MIB counter reading code to know freeze is enabled */ 255 p->freeze = freeze; 256 mutex_unlock(&p->mib.cnt_mutex); 257 } 258 259 void ksz9477_port_init_cnt(struct ksz_device *dev, int port) 260 { 261 struct ksz_port_mib *mib = &dev->ports[port].mib; 262 263 /* flush all enabled port MIB counters */ 264 mutex_lock(&mib->cnt_mutex); 265 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 266 MIB_COUNTER_FLUSH_FREEZE); 267 ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH); 268 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0); 269 mutex_unlock(&mib->cnt_mutex); 270 } 271 272 void ksz9477_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data) 273 { 274 u16 val = 0xffff; 275 276 /* No real PHY after this. Simulate the PHY. 277 * A fixed PHY can be setup in the device tree, but this function is 278 * still called for that port during initialization. 279 * For RGMII PHY there is no way to access it so the fixed PHY should 280 * be used. For SGMII PHY the supporting code will be added later. 281 */ 282 if (addr >= dev->phy_port_cnt) { 283 struct ksz_port *p = &dev->ports[addr]; 284 285 switch (reg) { 286 case MII_BMCR: 287 val = 0x1140; 288 break; 289 case MII_BMSR: 290 val = 0x796d; 291 break; 292 case MII_PHYSID1: 293 val = 0x0022; 294 break; 295 case MII_PHYSID2: 296 val = 0x1631; 297 break; 298 case MII_ADVERTISE: 299 val = 0x05e1; 300 break; 301 case MII_LPA: 302 val = 0xc5e1; 303 break; 304 case MII_CTRL1000: 305 val = 0x0700; 306 break; 307 case MII_STAT1000: 308 if (p->phydev.speed == SPEED_1000) 309 val = 0x3800; 310 else 311 val = 0; 312 break; 313 } 314 } else { 315 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val); 316 } 317 318 *data = val; 319 } 320 321 void ksz9477_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val) 322 { 323 /* No real PHY after this. */ 324 if (addr >= dev->phy_port_cnt) 325 return; 326 327 /* No gigabit support. Do not write to this register. */ 328 if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000) 329 return; 330 331 ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val); 332 } 333 334 void ksz9477_cfg_port_member(struct ksz_device *dev, int port, u8 member) 335 { 336 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member); 337 } 338 339 void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port) 340 { 341 const u16 *regs = dev->info->regs; 342 u8 data; 343 344 regmap_update_bits(dev->regmap[0], REG_SW_LUE_CTRL_2, 345 SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S, 346 SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S); 347 348 if (port < dev->info->port_cnt) { 349 /* flush individual port */ 350 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 351 if (!(data & PORT_LEARN_DISABLE)) 352 ksz_pwrite8(dev, port, regs[P_STP_CTRL], 353 data | PORT_LEARN_DISABLE); 354 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 355 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 356 } else { 357 /* flush all */ 358 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true); 359 } 360 } 361 362 int ksz9477_port_vlan_filtering(struct ksz_device *dev, int port, 363 bool flag, struct netlink_ext_ack *extack) 364 { 365 if (flag) { 366 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 367 PORT_VLAN_LOOKUP_VID_0, true); 368 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true); 369 } else { 370 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false); 371 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 372 PORT_VLAN_LOOKUP_VID_0, false); 373 } 374 375 return 0; 376 } 377 378 int ksz9477_port_vlan_add(struct ksz_device *dev, int port, 379 const struct switchdev_obj_port_vlan *vlan, 380 struct netlink_ext_ack *extack) 381 { 382 u32 vlan_table[3]; 383 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 384 int err; 385 386 err = ksz9477_get_vlan_table(dev, vlan->vid, vlan_table); 387 if (err) { 388 NL_SET_ERR_MSG_MOD(extack, "Failed to get vlan table"); 389 return err; 390 } 391 392 vlan_table[0] = VLAN_VALID | (vlan->vid & VLAN_FID_M); 393 if (untagged) 394 vlan_table[1] |= BIT(port); 395 else 396 vlan_table[1] &= ~BIT(port); 397 vlan_table[1] &= ~(BIT(dev->cpu_port)); 398 399 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port); 400 401 err = ksz9477_set_vlan_table(dev, vlan->vid, vlan_table); 402 if (err) { 403 NL_SET_ERR_MSG_MOD(extack, "Failed to set vlan table"); 404 return err; 405 } 406 407 /* change PVID */ 408 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 409 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vlan->vid); 410 411 return 0; 412 } 413 414 int ksz9477_port_vlan_del(struct ksz_device *dev, int port, 415 const struct switchdev_obj_port_vlan *vlan) 416 { 417 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 418 u32 vlan_table[3]; 419 u16 pvid; 420 421 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid); 422 pvid = pvid & 0xFFF; 423 424 if (ksz9477_get_vlan_table(dev, vlan->vid, vlan_table)) { 425 dev_dbg(dev->dev, "Failed to get vlan table\n"); 426 return -ETIMEDOUT; 427 } 428 429 vlan_table[2] &= ~BIT(port); 430 431 if (pvid == vlan->vid) 432 pvid = 1; 433 434 if (untagged) 435 vlan_table[1] &= ~BIT(port); 436 437 if (ksz9477_set_vlan_table(dev, vlan->vid, vlan_table)) { 438 dev_dbg(dev->dev, "Failed to set vlan table\n"); 439 return -ETIMEDOUT; 440 } 441 442 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid); 443 444 return 0; 445 } 446 447 int ksz9477_fdb_add(struct ksz_device *dev, int port, 448 const unsigned char *addr, u16 vid, struct dsa_db db) 449 { 450 u32 alu_table[4]; 451 u32 data; 452 int ret = 0; 453 454 mutex_lock(&dev->alu_mutex); 455 456 /* find any entry with mac & vid */ 457 data = vid << ALU_FID_INDEX_S; 458 data |= ((addr[0] << 8) | addr[1]); 459 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 460 461 data = ((addr[2] << 24) | (addr[3] << 16)); 462 data |= ((addr[4] << 8) | addr[5]); 463 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 464 465 /* start read operation */ 466 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 467 468 /* wait to be finished */ 469 ret = ksz9477_wait_alu_ready(dev); 470 if (ret) { 471 dev_dbg(dev->dev, "Failed to read ALU\n"); 472 goto exit; 473 } 474 475 /* read ALU entry */ 476 ksz9477_read_table(dev, alu_table); 477 478 /* update ALU entry */ 479 alu_table[0] = ALU_V_STATIC_VALID; 480 alu_table[1] |= BIT(port); 481 if (vid) 482 alu_table[1] |= ALU_V_USE_FID; 483 alu_table[2] = (vid << ALU_V_FID_S); 484 alu_table[2] |= ((addr[0] << 8) | addr[1]); 485 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16)); 486 alu_table[3] |= ((addr[4] << 8) | addr[5]); 487 488 ksz9477_write_table(dev, alu_table); 489 490 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 491 492 /* wait to be finished */ 493 ret = ksz9477_wait_alu_ready(dev); 494 if (ret) 495 dev_dbg(dev->dev, "Failed to write ALU\n"); 496 497 exit: 498 mutex_unlock(&dev->alu_mutex); 499 500 return ret; 501 } 502 503 int ksz9477_fdb_del(struct ksz_device *dev, int port, 504 const unsigned char *addr, u16 vid, struct dsa_db db) 505 { 506 u32 alu_table[4]; 507 u32 data; 508 int ret = 0; 509 510 mutex_lock(&dev->alu_mutex); 511 512 /* read any entry with mac & vid */ 513 data = vid << ALU_FID_INDEX_S; 514 data |= ((addr[0] << 8) | addr[1]); 515 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 516 517 data = ((addr[2] << 24) | (addr[3] << 16)); 518 data |= ((addr[4] << 8) | addr[5]); 519 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 520 521 /* start read operation */ 522 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 523 524 /* wait to be finished */ 525 ret = ksz9477_wait_alu_ready(dev); 526 if (ret) { 527 dev_dbg(dev->dev, "Failed to read ALU\n"); 528 goto exit; 529 } 530 531 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]); 532 if (alu_table[0] & ALU_V_STATIC_VALID) { 533 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]); 534 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]); 535 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]); 536 537 /* clear forwarding port */ 538 alu_table[2] &= ~BIT(port); 539 540 /* if there is no port to forward, clear table */ 541 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) { 542 alu_table[0] = 0; 543 alu_table[1] = 0; 544 alu_table[2] = 0; 545 alu_table[3] = 0; 546 } 547 } else { 548 alu_table[0] = 0; 549 alu_table[1] = 0; 550 alu_table[2] = 0; 551 alu_table[3] = 0; 552 } 553 554 ksz9477_write_table(dev, alu_table); 555 556 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 557 558 /* wait to be finished */ 559 ret = ksz9477_wait_alu_ready(dev); 560 if (ret) 561 dev_dbg(dev->dev, "Failed to write ALU\n"); 562 563 exit: 564 mutex_unlock(&dev->alu_mutex); 565 566 return ret; 567 } 568 569 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table) 570 { 571 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID); 572 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER); 573 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER); 574 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) & 575 ALU_V_PRIO_AGE_CNT_M; 576 alu->mstp = alu_table[0] & ALU_V_MSTP_M; 577 578 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE); 579 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID); 580 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP; 581 582 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M; 583 584 alu->mac[0] = (alu_table[2] >> 8) & 0xFF; 585 alu->mac[1] = alu_table[2] & 0xFF; 586 alu->mac[2] = (alu_table[3] >> 24) & 0xFF; 587 alu->mac[3] = (alu_table[3] >> 16) & 0xFF; 588 alu->mac[4] = (alu_table[3] >> 8) & 0xFF; 589 alu->mac[5] = alu_table[3] & 0xFF; 590 } 591 592 int ksz9477_fdb_dump(struct ksz_device *dev, int port, 593 dsa_fdb_dump_cb_t *cb, void *data) 594 { 595 int ret = 0; 596 u32 ksz_data; 597 u32 alu_table[4]; 598 struct alu_struct alu; 599 int timeout; 600 601 mutex_lock(&dev->alu_mutex); 602 603 /* start ALU search */ 604 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH); 605 606 do { 607 timeout = 1000; 608 do { 609 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data); 610 if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START)) 611 break; 612 usleep_range(1, 10); 613 } while (timeout-- > 0); 614 615 if (!timeout) { 616 dev_dbg(dev->dev, "Failed to search ALU\n"); 617 ret = -ETIMEDOUT; 618 goto exit; 619 } 620 621 /* read ALU table */ 622 ksz9477_read_table(dev, alu_table); 623 624 ksz9477_convert_alu(&alu, alu_table); 625 626 if (alu.port_forward & BIT(port)) { 627 ret = cb(alu.mac, alu.fid, alu.is_static, data); 628 if (ret) 629 goto exit; 630 } 631 } while (ksz_data & ALU_START); 632 633 exit: 634 635 /* stop ALU search */ 636 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0); 637 638 mutex_unlock(&dev->alu_mutex); 639 640 return ret; 641 } 642 643 int ksz9477_mdb_add(struct ksz_device *dev, int port, 644 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 645 { 646 u32 static_table[4]; 647 const u8 *shifts; 648 const u32 *masks; 649 u32 data; 650 int index; 651 u32 mac_hi, mac_lo; 652 int err = 0; 653 654 shifts = dev->info->shifts; 655 masks = dev->info->masks; 656 657 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 658 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 659 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 660 661 mutex_lock(&dev->alu_mutex); 662 663 for (index = 0; index < dev->info->num_statics; index++) { 664 /* find empty slot first */ 665 data = (index << shifts[ALU_STAT_INDEX]) | 666 masks[ALU_STAT_READ] | ALU_STAT_START; 667 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 668 669 /* wait to be finished */ 670 err = ksz9477_wait_alu_sta_ready(dev); 671 if (err) { 672 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 673 goto exit; 674 } 675 676 /* read ALU static table */ 677 ksz9477_read_table(dev, static_table); 678 679 if (static_table[0] & ALU_V_STATIC_VALID) { 680 /* check this has same vid & mac address */ 681 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 682 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 683 static_table[3] == mac_lo) { 684 /* found matching one */ 685 break; 686 } 687 } else { 688 /* found empty one */ 689 break; 690 } 691 } 692 693 /* no available entry */ 694 if (index == dev->info->num_statics) { 695 err = -ENOSPC; 696 goto exit; 697 } 698 699 /* add entry */ 700 static_table[0] = ALU_V_STATIC_VALID; 701 static_table[1] |= BIT(port); 702 if (mdb->vid) 703 static_table[1] |= ALU_V_USE_FID; 704 static_table[2] = (mdb->vid << ALU_V_FID_S); 705 static_table[2] |= mac_hi; 706 static_table[3] = mac_lo; 707 708 ksz9477_write_table(dev, static_table); 709 710 data = (index << shifts[ALU_STAT_INDEX]) | ALU_STAT_START; 711 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 712 713 /* wait to be finished */ 714 if (ksz9477_wait_alu_sta_ready(dev)) 715 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 716 717 exit: 718 mutex_unlock(&dev->alu_mutex); 719 return err; 720 } 721 722 int ksz9477_mdb_del(struct ksz_device *dev, int port, 723 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 724 { 725 u32 static_table[4]; 726 const u8 *shifts; 727 const u32 *masks; 728 u32 data; 729 int index; 730 int ret = 0; 731 u32 mac_hi, mac_lo; 732 733 shifts = dev->info->shifts; 734 masks = dev->info->masks; 735 736 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 737 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 738 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 739 740 mutex_lock(&dev->alu_mutex); 741 742 for (index = 0; index < dev->info->num_statics; index++) { 743 /* find empty slot first */ 744 data = (index << shifts[ALU_STAT_INDEX]) | 745 masks[ALU_STAT_READ] | ALU_STAT_START; 746 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 747 748 /* wait to be finished */ 749 ret = ksz9477_wait_alu_sta_ready(dev); 750 if (ret) { 751 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 752 goto exit; 753 } 754 755 /* read ALU static table */ 756 ksz9477_read_table(dev, static_table); 757 758 if (static_table[0] & ALU_V_STATIC_VALID) { 759 /* check this has same vid & mac address */ 760 761 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 762 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 763 static_table[3] == mac_lo) { 764 /* found matching one */ 765 break; 766 } 767 } 768 } 769 770 /* no available entry */ 771 if (index == dev->info->num_statics) 772 goto exit; 773 774 /* clear port */ 775 static_table[1] &= ~BIT(port); 776 777 if ((static_table[1] & ALU_V_PORT_MAP) == 0) { 778 /* delete entry */ 779 static_table[0] = 0; 780 static_table[1] = 0; 781 static_table[2] = 0; 782 static_table[3] = 0; 783 } 784 785 ksz9477_write_table(dev, static_table); 786 787 data = (index << shifts[ALU_STAT_INDEX]) | ALU_STAT_START; 788 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 789 790 /* wait to be finished */ 791 ret = ksz9477_wait_alu_sta_ready(dev); 792 if (ret) 793 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 794 795 exit: 796 mutex_unlock(&dev->alu_mutex); 797 798 return ret; 799 } 800 801 int ksz9477_port_mirror_add(struct ksz_device *dev, int port, 802 struct dsa_mall_mirror_tc_entry *mirror, 803 bool ingress, struct netlink_ext_ack *extack) 804 { 805 u8 data; 806 int p; 807 808 /* Limit to one sniffer port 809 * Check if any of the port is already set for sniffing 810 * If yes, instruct the user to remove the previous entry & exit 811 */ 812 for (p = 0; p < dev->info->port_cnt; p++) { 813 /* Skip the current sniffing port */ 814 if (p == mirror->to_local_port) 815 continue; 816 817 ksz_pread8(dev, p, P_MIRROR_CTRL, &data); 818 819 if (data & PORT_MIRROR_SNIFFER) { 820 NL_SET_ERR_MSG_MOD(extack, 821 "Sniffer port is already configured, delete existing rules & retry"); 822 return -EBUSY; 823 } 824 } 825 826 if (ingress) 827 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 828 else 829 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 830 831 /* configure mirror port */ 832 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 833 PORT_MIRROR_SNIFFER, true); 834 835 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 836 837 return 0; 838 } 839 840 void ksz9477_port_mirror_del(struct ksz_device *dev, int port, 841 struct dsa_mall_mirror_tc_entry *mirror) 842 { 843 bool in_use = false; 844 u8 data; 845 int p; 846 847 if (mirror->ingress) 848 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 849 else 850 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 851 852 853 /* Check if any of the port is still referring to sniffer port */ 854 for (p = 0; p < dev->info->port_cnt; p++) { 855 ksz_pread8(dev, p, P_MIRROR_CTRL, &data); 856 857 if ((data & (PORT_MIRROR_RX | PORT_MIRROR_TX))) { 858 in_use = true; 859 break; 860 } 861 } 862 863 /* delete sniffing if there are no other mirroring rules */ 864 if (!in_use) 865 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 866 PORT_MIRROR_SNIFFER, false); 867 } 868 869 static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data) 870 { 871 bool gbit; 872 873 if (dev->features & NEW_XMII) 874 gbit = !(data & PORT_MII_NOT_1GBIT); 875 else 876 gbit = !!(data & PORT_MII_1000MBIT_S1); 877 return gbit; 878 } 879 880 static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data) 881 { 882 if (dev->features & NEW_XMII) { 883 if (gbit) 884 *data &= ~PORT_MII_NOT_1GBIT; 885 else 886 *data |= PORT_MII_NOT_1GBIT; 887 } else { 888 if (gbit) 889 *data |= PORT_MII_1000MBIT_S1; 890 else 891 *data &= ~PORT_MII_1000MBIT_S1; 892 } 893 } 894 895 static int ksz9477_get_xmii(struct ksz_device *dev, u8 data) 896 { 897 int mode; 898 899 if (dev->features & NEW_XMII) { 900 switch (data & PORT_MII_SEL_M) { 901 case PORT_MII_SEL: 902 mode = 0; 903 break; 904 case PORT_RMII_SEL: 905 mode = 1; 906 break; 907 case PORT_GMII_SEL: 908 mode = 2; 909 break; 910 default: 911 mode = 3; 912 } 913 } else { 914 switch (data & PORT_MII_SEL_M) { 915 case PORT_MII_SEL_S1: 916 mode = 0; 917 break; 918 case PORT_RMII_SEL_S1: 919 mode = 1; 920 break; 921 case PORT_GMII_SEL_S1: 922 mode = 2; 923 break; 924 default: 925 mode = 3; 926 } 927 } 928 return mode; 929 } 930 931 static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data) 932 { 933 u8 xmii; 934 935 if (dev->features & NEW_XMII) { 936 switch (mode) { 937 case 0: 938 xmii = PORT_MII_SEL; 939 break; 940 case 1: 941 xmii = PORT_RMII_SEL; 942 break; 943 case 2: 944 xmii = PORT_GMII_SEL; 945 break; 946 default: 947 xmii = PORT_RGMII_SEL; 948 break; 949 } 950 } else { 951 switch (mode) { 952 case 0: 953 xmii = PORT_MII_SEL_S1; 954 break; 955 case 1: 956 xmii = PORT_RMII_SEL_S1; 957 break; 958 case 2: 959 xmii = PORT_GMII_SEL_S1; 960 break; 961 default: 962 xmii = PORT_RGMII_SEL_S1; 963 break; 964 } 965 } 966 *data &= ~PORT_MII_SEL_M; 967 *data |= xmii; 968 } 969 970 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port) 971 { 972 phy_interface_t interface; 973 bool gbit; 974 int mode; 975 u8 data8; 976 977 if (port < dev->phy_port_cnt) 978 return PHY_INTERFACE_MODE_NA; 979 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 980 gbit = ksz9477_get_gbit(dev, data8); 981 mode = ksz9477_get_xmii(dev, data8); 982 switch (mode) { 983 case 2: 984 interface = PHY_INTERFACE_MODE_GMII; 985 if (gbit) 986 break; 987 fallthrough; 988 case 0: 989 interface = PHY_INTERFACE_MODE_MII; 990 break; 991 case 1: 992 interface = PHY_INTERFACE_MODE_RMII; 993 break; 994 default: 995 interface = PHY_INTERFACE_MODE_RGMII; 996 if (data8 & PORT_RGMII_ID_EG_ENABLE) 997 interface = PHY_INTERFACE_MODE_RGMII_TXID; 998 if (data8 & PORT_RGMII_ID_IG_ENABLE) { 999 interface = PHY_INTERFACE_MODE_RGMII_RXID; 1000 if (data8 & PORT_RGMII_ID_EG_ENABLE) 1001 interface = PHY_INTERFACE_MODE_RGMII_ID; 1002 } 1003 break; 1004 } 1005 return interface; 1006 } 1007 1008 static void ksz9477_port_mmd_write(struct ksz_device *dev, int port, 1009 u8 dev_addr, u16 reg_addr, u16 val) 1010 { 1011 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 1012 MMD_SETUP(PORT_MMD_OP_INDEX, dev_addr)); 1013 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg_addr); 1014 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 1015 MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, dev_addr)); 1016 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val); 1017 } 1018 1019 static void ksz9477_phy_errata_setup(struct ksz_device *dev, int port) 1020 { 1021 /* Apply PHY settings to address errata listed in 1022 * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565 1023 * Silicon Errata and Data Sheet Clarification documents: 1024 * 1025 * Register settings are needed to improve PHY receive performance 1026 */ 1027 ksz9477_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b); 1028 ksz9477_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032); 1029 ksz9477_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c); 1030 ksz9477_port_mmd_write(dev, port, 0x01, 0x75, 0x0060); 1031 ksz9477_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777); 1032 ksz9477_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008); 1033 ksz9477_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001); 1034 1035 /* Transmit waveform amplitude can be improved 1036 * (1000BASE-T, 100BASE-TX, 10BASE-Te) 1037 */ 1038 ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0); 1039 1040 /* Energy Efficient Ethernet (EEE) feature select must 1041 * be manually disabled (except on KSZ8565 which is 100Mbit) 1042 */ 1043 if (dev->features & GBIT_SUPPORT) 1044 ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000); 1045 1046 /* Register settings are required to meet data sheet 1047 * supply current specifications 1048 */ 1049 ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff); 1050 ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff); 1051 ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff); 1052 ksz9477_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff); 1053 ksz9477_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff); 1054 ksz9477_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff); 1055 ksz9477_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff); 1056 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff); 1057 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff); 1058 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff); 1059 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff); 1060 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff); 1061 ksz9477_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee); 1062 } 1063 1064 void ksz9477_get_caps(struct ksz_device *dev, int port, 1065 struct phylink_config *config) 1066 { 1067 config->mac_capabilities = MAC_10 | MAC_100 | MAC_ASYM_PAUSE | 1068 MAC_SYM_PAUSE; 1069 1070 if (dev->features & GBIT_SUPPORT) 1071 config->mac_capabilities |= MAC_1000FD; 1072 } 1073 1074 void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1075 { 1076 struct ksz_port *p = &dev->ports[port]; 1077 struct dsa_switch *ds = dev->ds; 1078 u8 data8, member; 1079 u16 data16; 1080 1081 /* enable tag tail for host port */ 1082 if (cpu_port) 1083 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE, 1084 true); 1085 1086 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false); 1087 1088 /* set back pressure */ 1089 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true); 1090 1091 /* enable broadcast storm limit */ 1092 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 1093 1094 /* disable DiffServ priority */ 1095 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false); 1096 1097 /* replace priority */ 1098 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING, 1099 false); 1100 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4, 1101 MTI_PVID_REPLACE, false); 1102 1103 /* enable 802.1p priority */ 1104 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); 1105 1106 if (port < dev->phy_port_cnt) { 1107 /* do not force flow control */ 1108 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1109 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1110 false); 1111 1112 if (dev->info->phy_errata_9477) 1113 ksz9477_phy_errata_setup(dev, port); 1114 } else { 1115 /* force flow control */ 1116 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1117 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1118 true); 1119 1120 /* configure MAC to 1G & RGMII mode */ 1121 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 1122 switch (p->interface) { 1123 case PHY_INTERFACE_MODE_MII: 1124 ksz9477_set_xmii(dev, 0, &data8); 1125 ksz9477_set_gbit(dev, false, &data8); 1126 p->phydev.speed = SPEED_100; 1127 break; 1128 case PHY_INTERFACE_MODE_RMII: 1129 ksz9477_set_xmii(dev, 1, &data8); 1130 ksz9477_set_gbit(dev, false, &data8); 1131 p->phydev.speed = SPEED_100; 1132 break; 1133 case PHY_INTERFACE_MODE_GMII: 1134 ksz9477_set_xmii(dev, 2, &data8); 1135 ksz9477_set_gbit(dev, true, &data8); 1136 p->phydev.speed = SPEED_1000; 1137 break; 1138 default: 1139 ksz9477_set_xmii(dev, 3, &data8); 1140 ksz9477_set_gbit(dev, true, &data8); 1141 data8 &= ~PORT_RGMII_ID_IG_ENABLE; 1142 data8 &= ~PORT_RGMII_ID_EG_ENABLE; 1143 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1144 p->interface == PHY_INTERFACE_MODE_RGMII_RXID) 1145 data8 |= PORT_RGMII_ID_IG_ENABLE; 1146 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1147 p->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1148 data8 |= PORT_RGMII_ID_EG_ENABLE; 1149 /* On KSZ9893, disable RGMII in-band status support */ 1150 if (dev->features & IS_9893) 1151 data8 &= ~PORT_MII_MAC_MODE; 1152 p->phydev.speed = SPEED_1000; 1153 break; 1154 } 1155 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8); 1156 p->phydev.duplex = 1; 1157 } 1158 1159 if (cpu_port) 1160 member = dsa_user_ports(ds); 1161 else 1162 member = BIT(dsa_upstream_port(ds, port)); 1163 1164 ksz9477_cfg_port_member(dev, port, member); 1165 1166 /* clear pending interrupts */ 1167 if (port < dev->phy_port_cnt) 1168 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16); 1169 } 1170 1171 void ksz9477_config_cpu_port(struct dsa_switch *ds) 1172 { 1173 struct ksz_device *dev = ds->priv; 1174 struct ksz_port *p; 1175 int i; 1176 1177 for (i = 0; i < dev->info->port_cnt; i++) { 1178 if (dsa_is_cpu_port(ds, i) && 1179 (dev->info->cpu_ports & (1 << i))) { 1180 phy_interface_t interface; 1181 const char *prev_msg; 1182 const char *prev_mode; 1183 1184 dev->cpu_port = i; 1185 p = &dev->ports[i]; 1186 1187 /* Read from XMII register to determine host port 1188 * interface. If set specifically in device tree 1189 * note the difference to help debugging. 1190 */ 1191 interface = ksz9477_get_interface(dev, i); 1192 if (!p->interface) { 1193 if (dev->compat_interface) { 1194 dev_warn(dev->dev, 1195 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 1196 "Please update your device tree.\n", 1197 i); 1198 p->interface = dev->compat_interface; 1199 } else { 1200 p->interface = interface; 1201 } 1202 } 1203 if (interface && interface != p->interface) { 1204 prev_msg = " instead of "; 1205 prev_mode = phy_modes(interface); 1206 } else { 1207 prev_msg = ""; 1208 prev_mode = ""; 1209 } 1210 dev_info(dev->dev, 1211 "Port%d: using phy mode %s%s%s\n", 1212 i, 1213 phy_modes(p->interface), 1214 prev_msg, 1215 prev_mode); 1216 1217 /* enable cpu port */ 1218 ksz9477_port_setup(dev, i, true); 1219 p->on = 1; 1220 } 1221 } 1222 1223 for (i = 0; i < dev->info->port_cnt; i++) { 1224 if (i == dev->cpu_port) 1225 continue; 1226 p = &dev->ports[i]; 1227 1228 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1229 p->on = 1; 1230 if (i < dev->phy_port_cnt) 1231 p->phy = 1; 1232 if (dev->chip_id == 0x00947700 && i == 6) { 1233 p->sgmii = 1; 1234 1235 /* SGMII PHY detection code is not implemented yet. */ 1236 p->phy = 0; 1237 } 1238 } 1239 } 1240 1241 int ksz9477_enable_stp_addr(struct ksz_device *dev) 1242 { 1243 const u32 *masks; 1244 u32 data; 1245 int ret; 1246 1247 masks = dev->info->masks; 1248 1249 /* Enable Reserved multicast table */ 1250 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_RESV_MCAST_ENABLE, true); 1251 1252 /* Set the Override bit for forwarding BPDU packet to CPU */ 1253 ret = ksz_write32(dev, REG_SW_ALU_VAL_B, 1254 ALU_V_OVERRIDE | BIT(dev->cpu_port)); 1255 if (ret < 0) 1256 return ret; 1257 1258 data = ALU_STAT_START | ALU_RESV_MCAST_ADDR | masks[ALU_STAT_WRITE]; 1259 1260 ret = ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 1261 if (ret < 0) 1262 return ret; 1263 1264 /* wait to be finished */ 1265 ret = ksz9477_wait_alu_sta_ready(dev); 1266 if (ret < 0) { 1267 dev_err(dev->dev, "Failed to update Reserved Multicast table\n"); 1268 return ret; 1269 } 1270 1271 return 0; 1272 } 1273 1274 int ksz9477_setup(struct dsa_switch *ds) 1275 { 1276 struct ksz_device *dev = ds->priv; 1277 int ret = 0; 1278 1279 /* Required for port partitioning. */ 1280 ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, 1281 true); 1282 1283 /* Do not work correctly with tail tagging. */ 1284 ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false); 1285 1286 /* Enable REG_SW_MTU__2 reg by setting SW_JUMBO_PACKET */ 1287 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_JUMBO_PACKET, true); 1288 1289 /* Now we can configure default MTU value */ 1290 ret = regmap_update_bits(dev->regmap[1], REG_SW_MTU__2, REG_SW_MTU_MASK, 1291 VLAN_ETH_FRAME_LEN + ETH_FCS_LEN); 1292 if (ret) 1293 return ret; 1294 1295 /* queue based egress rate limit */ 1296 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true); 1297 1298 /* enable global MIB counter freeze function */ 1299 ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); 1300 1301 return 0; 1302 } 1303 1304 u32 ksz9477_get_port_addr(int port, int offset) 1305 { 1306 return PORT_CTRL_ADDR(port, offset); 1307 } 1308 1309 int ksz9477_switch_init(struct ksz_device *dev) 1310 { 1311 u8 data8; 1312 int ret; 1313 1314 dev->port_mask = (1 << dev->info->port_cnt) - 1; 1315 1316 /* turn off SPI DO Edge select */ 1317 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 1318 if (ret) 1319 return ret; 1320 1321 data8 &= ~SPI_AUTO_EDGE_DETECTION; 1322 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 1323 if (ret) 1324 return ret; 1325 1326 ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8); 1327 if (ret) 1328 return ret; 1329 1330 /* Number of ports can be reduced depending on chip. */ 1331 dev->phy_port_cnt = 5; 1332 1333 /* Default capability is gigabit capable. */ 1334 dev->features = GBIT_SUPPORT; 1335 1336 if (dev->chip_id == KSZ9893_CHIP_ID) { 1337 dev->features |= IS_9893; 1338 1339 /* Chip does not support gigabit. */ 1340 if (data8 & SW_QW_ABLE) 1341 dev->features &= ~GBIT_SUPPORT; 1342 dev->phy_port_cnt = 2; 1343 } else { 1344 /* Chip uses new XMII register definitions. */ 1345 dev->features |= NEW_XMII; 1346 1347 /* Chip does not support gigabit. */ 1348 if (!(data8 & SW_GIGABIT_ABLE)) 1349 dev->features &= ~GBIT_SUPPORT; 1350 } 1351 1352 return 0; 1353 } 1354 1355 void ksz9477_switch_exit(struct ksz_device *dev) 1356 { 1357 ksz9477_reset_switch(dev); 1358 } 1359 1360 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 1361 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver"); 1362 MODULE_LICENSE("GPL"); 1363