1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ9477 switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/iopoll.h> 11 #include <linux/platform_data/microchip-ksz.h> 12 #include <linux/phy.h> 13 #include <linux/if_bridge.h> 14 #include <linux/if_vlan.h> 15 #include <net/dsa.h> 16 #include <net/switchdev.h> 17 18 #include "ksz9477_reg.h" 19 #include "ksz_common.h" 20 21 /* Used with variable features to indicate capabilities. */ 22 #define GBIT_SUPPORT BIT(0) 23 #define NEW_XMII BIT(1) 24 #define IS_9893 BIT(2) 25 26 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 27 { 28 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0); 29 } 30 31 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 32 bool set) 33 { 34 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset), 35 bits, set ? bits : 0); 36 } 37 38 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set) 39 { 40 regmap_update_bits(dev->regmap[2], addr, bits, set ? bits : 0); 41 } 42 43 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset, 44 u32 bits, bool set) 45 { 46 regmap_update_bits(dev->regmap[2], PORT_CTRL_ADDR(port, offset), 47 bits, set ? bits : 0); 48 } 49 50 static int ksz9477_change_mtu(struct dsa_switch *ds, int port, int mtu) 51 { 52 struct ksz_device *dev = ds->priv; 53 u16 frame_size, max_frame = 0; 54 int i; 55 56 frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 57 58 /* Cache the per-port MTU setting */ 59 dev->ports[port].max_frame = frame_size; 60 61 for (i = 0; i < dev->info->port_cnt; i++) 62 max_frame = max(max_frame, dev->ports[i].max_frame); 63 64 return regmap_update_bits(dev->regmap[1], REG_SW_MTU__2, 65 REG_SW_MTU_MASK, max_frame); 66 } 67 68 static int ksz9477_max_mtu(struct dsa_switch *ds, int port) 69 { 70 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 71 } 72 73 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev) 74 { 75 unsigned int val; 76 77 return regmap_read_poll_timeout(dev->regmap[0], REG_SW_VLAN_CTRL, 78 val, !(val & VLAN_START), 10, 1000); 79 } 80 81 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid, 82 u32 *vlan_table) 83 { 84 int ret; 85 86 mutex_lock(&dev->vlan_mutex); 87 88 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 89 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START); 90 91 /* wait to be cleared */ 92 ret = ksz9477_wait_vlan_ctrl_ready(dev); 93 if (ret) { 94 dev_dbg(dev->dev, "Failed to read vlan table\n"); 95 goto exit; 96 } 97 98 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]); 99 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]); 100 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]); 101 102 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 103 104 exit: 105 mutex_unlock(&dev->vlan_mutex); 106 107 return ret; 108 } 109 110 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid, 111 u32 *vlan_table) 112 { 113 int ret; 114 115 mutex_lock(&dev->vlan_mutex); 116 117 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]); 118 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]); 119 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]); 120 121 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 122 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE); 123 124 /* wait to be cleared */ 125 ret = ksz9477_wait_vlan_ctrl_ready(dev); 126 if (ret) { 127 dev_dbg(dev->dev, "Failed to write vlan table\n"); 128 goto exit; 129 } 130 131 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 132 133 /* update vlan cache table */ 134 dev->vlan_cache[vid].table[0] = vlan_table[0]; 135 dev->vlan_cache[vid].table[1] = vlan_table[1]; 136 dev->vlan_cache[vid].table[2] = vlan_table[2]; 137 138 exit: 139 mutex_unlock(&dev->vlan_mutex); 140 141 return ret; 142 } 143 144 static void ksz9477_read_table(struct ksz_device *dev, u32 *table) 145 { 146 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]); 147 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]); 148 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]); 149 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]); 150 } 151 152 static void ksz9477_write_table(struct ksz_device *dev, u32 *table) 153 { 154 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]); 155 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]); 156 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]); 157 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]); 158 } 159 160 static int ksz9477_wait_alu_ready(struct ksz_device *dev) 161 { 162 unsigned int val; 163 164 return regmap_read_poll_timeout(dev->regmap[2], REG_SW_ALU_CTRL__4, 165 val, !(val & ALU_START), 10, 1000); 166 } 167 168 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev) 169 { 170 unsigned int val; 171 172 return regmap_read_poll_timeout(dev->regmap[2], 173 REG_SW_ALU_STAT_CTRL__4, 174 val, !(val & ALU_STAT_START), 175 10, 1000); 176 } 177 178 static int ksz9477_reset_switch(struct ksz_device *dev) 179 { 180 u8 data8; 181 u32 data32; 182 183 /* reset switch */ 184 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 185 186 /* turn off SPI DO Edge select */ 187 regmap_update_bits(dev->regmap[0], REG_SW_GLOBAL_SERIAL_CTRL_0, 188 SPI_AUTO_EDGE_DETECTION, 0); 189 190 /* default configuration */ 191 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8); 192 data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING | 193 SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE; 194 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8); 195 196 /* disable interrupts */ 197 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 198 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F); 199 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 200 201 /* set broadcast storm protection 10% rate */ 202 regmap_update_bits(dev->regmap[1], REG_SW_MAC_CTRL_2, 203 BROADCAST_STORM_RATE, 204 (BROADCAST_STORM_VALUE * 205 BROADCAST_STORM_PROT_RATE) / 100); 206 207 data8 = SW_ENABLE_REFCLKO; 208 if (dev->synclko_disable) 209 data8 = 0; 210 else if (dev->synclko_125) 211 data8 = SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ; 212 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, data8); 213 214 return 0; 215 } 216 217 static void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, 218 u64 *cnt) 219 { 220 struct ksz_port *p = &dev->ports[port]; 221 unsigned int val; 222 u32 data; 223 int ret; 224 225 /* retain the flush/freeze bit */ 226 data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 227 data |= MIB_COUNTER_READ; 228 data |= (addr << MIB_COUNTER_INDEX_S); 229 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data); 230 231 ret = regmap_read_poll_timeout(dev->regmap[2], 232 PORT_CTRL_ADDR(port, REG_PORT_MIB_CTRL_STAT__4), 233 val, !(val & MIB_COUNTER_READ), 10, 1000); 234 /* failed to read MIB. get out of loop */ 235 if (ret) { 236 dev_dbg(dev->dev, "Failed to get MIB\n"); 237 return; 238 } 239 240 /* count resets upon read */ 241 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data); 242 *cnt += data; 243 } 244 245 static void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 246 u64 *dropped, u64 *cnt) 247 { 248 addr = dev->info->mib_names[addr].index; 249 ksz9477_r_mib_cnt(dev, port, addr, cnt); 250 } 251 252 static void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze) 253 { 254 u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 255 struct ksz_port *p = &dev->ports[port]; 256 257 /* enable/disable the port for flush/freeze function */ 258 mutex_lock(&p->mib.cnt_mutex); 259 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val); 260 261 /* used by MIB counter reading code to know freeze is enabled */ 262 p->freeze = freeze; 263 mutex_unlock(&p->mib.cnt_mutex); 264 } 265 266 static void ksz9477_port_init_cnt(struct ksz_device *dev, int port) 267 { 268 struct ksz_port_mib *mib = &dev->ports[port].mib; 269 270 /* flush all enabled port MIB counters */ 271 mutex_lock(&mib->cnt_mutex); 272 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 273 MIB_COUNTER_FLUSH_FREEZE); 274 ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH); 275 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0); 276 mutex_unlock(&mib->cnt_mutex); 277 } 278 279 static enum dsa_tag_protocol ksz9477_get_tag_protocol(struct dsa_switch *ds, 280 int port, 281 enum dsa_tag_protocol mp) 282 { 283 enum dsa_tag_protocol proto = DSA_TAG_PROTO_KSZ9477; 284 struct ksz_device *dev = ds->priv; 285 286 if (dev->features & IS_9893) 287 proto = DSA_TAG_PROTO_KSZ9893; 288 return proto; 289 } 290 291 static int ksz9477_phy_read16(struct dsa_switch *ds, int addr, int reg) 292 { 293 struct ksz_device *dev = ds->priv; 294 u16 val = 0xffff; 295 296 /* No real PHY after this. Simulate the PHY. 297 * A fixed PHY can be setup in the device tree, but this function is 298 * still called for that port during initialization. 299 * For RGMII PHY there is no way to access it so the fixed PHY should 300 * be used. For SGMII PHY the supporting code will be added later. 301 */ 302 if (addr >= dev->phy_port_cnt) { 303 struct ksz_port *p = &dev->ports[addr]; 304 305 switch (reg) { 306 case MII_BMCR: 307 val = 0x1140; 308 break; 309 case MII_BMSR: 310 val = 0x796d; 311 break; 312 case MII_PHYSID1: 313 val = 0x0022; 314 break; 315 case MII_PHYSID2: 316 val = 0x1631; 317 break; 318 case MII_ADVERTISE: 319 val = 0x05e1; 320 break; 321 case MII_LPA: 322 val = 0xc5e1; 323 break; 324 case MII_CTRL1000: 325 val = 0x0700; 326 break; 327 case MII_STAT1000: 328 if (p->phydev.speed == SPEED_1000) 329 val = 0x3800; 330 else 331 val = 0; 332 break; 333 } 334 } else { 335 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val); 336 } 337 338 return val; 339 } 340 341 static int ksz9477_phy_write16(struct dsa_switch *ds, int addr, int reg, 342 u16 val) 343 { 344 struct ksz_device *dev = ds->priv; 345 346 /* No real PHY after this. */ 347 if (addr >= dev->phy_port_cnt) 348 return 0; 349 350 /* No gigabit support. Do not write to this register. */ 351 if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000) 352 return 0; 353 ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val); 354 355 return 0; 356 } 357 358 static void ksz9477_cfg_port_member(struct ksz_device *dev, int port, 359 u8 member) 360 { 361 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member); 362 } 363 364 static void ksz9477_port_stp_state_set(struct dsa_switch *ds, int port, 365 u8 state) 366 { 367 ksz_port_stp_state_set(ds, port, state, P_STP_CTRL); 368 } 369 370 static void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port) 371 { 372 u8 data; 373 374 regmap_update_bits(dev->regmap[0], REG_SW_LUE_CTRL_2, 375 SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S, 376 SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S); 377 378 if (port < dev->info->port_cnt) { 379 /* flush individual port */ 380 ksz_pread8(dev, port, P_STP_CTRL, &data); 381 if (!(data & PORT_LEARN_DISABLE)) 382 ksz_pwrite8(dev, port, P_STP_CTRL, 383 data | PORT_LEARN_DISABLE); 384 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 385 ksz_pwrite8(dev, port, P_STP_CTRL, data); 386 } else { 387 /* flush all */ 388 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true); 389 } 390 } 391 392 static int ksz9477_port_vlan_filtering(struct dsa_switch *ds, int port, 393 bool flag, 394 struct netlink_ext_ack *extack) 395 { 396 struct ksz_device *dev = ds->priv; 397 398 if (flag) { 399 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 400 PORT_VLAN_LOOKUP_VID_0, true); 401 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true); 402 } else { 403 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false); 404 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 405 PORT_VLAN_LOOKUP_VID_0, false); 406 } 407 408 return 0; 409 } 410 411 static int ksz9477_port_vlan_add(struct dsa_switch *ds, int port, 412 const struct switchdev_obj_port_vlan *vlan, 413 struct netlink_ext_ack *extack) 414 { 415 struct ksz_device *dev = ds->priv; 416 u32 vlan_table[3]; 417 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 418 int err; 419 420 err = ksz9477_get_vlan_table(dev, vlan->vid, vlan_table); 421 if (err) { 422 NL_SET_ERR_MSG_MOD(extack, "Failed to get vlan table"); 423 return err; 424 } 425 426 vlan_table[0] = VLAN_VALID | (vlan->vid & VLAN_FID_M); 427 if (untagged) 428 vlan_table[1] |= BIT(port); 429 else 430 vlan_table[1] &= ~BIT(port); 431 vlan_table[1] &= ~(BIT(dev->cpu_port)); 432 433 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port); 434 435 err = ksz9477_set_vlan_table(dev, vlan->vid, vlan_table); 436 if (err) { 437 NL_SET_ERR_MSG_MOD(extack, "Failed to set vlan table"); 438 return err; 439 } 440 441 /* change PVID */ 442 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 443 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vlan->vid); 444 445 return 0; 446 } 447 448 static int ksz9477_port_vlan_del(struct dsa_switch *ds, int port, 449 const struct switchdev_obj_port_vlan *vlan) 450 { 451 struct ksz_device *dev = ds->priv; 452 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 453 u32 vlan_table[3]; 454 u16 pvid; 455 456 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid); 457 pvid = pvid & 0xFFF; 458 459 if (ksz9477_get_vlan_table(dev, vlan->vid, vlan_table)) { 460 dev_dbg(dev->dev, "Failed to get vlan table\n"); 461 return -ETIMEDOUT; 462 } 463 464 vlan_table[2] &= ~BIT(port); 465 466 if (pvid == vlan->vid) 467 pvid = 1; 468 469 if (untagged) 470 vlan_table[1] &= ~BIT(port); 471 472 if (ksz9477_set_vlan_table(dev, vlan->vid, vlan_table)) { 473 dev_dbg(dev->dev, "Failed to set vlan table\n"); 474 return -ETIMEDOUT; 475 } 476 477 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid); 478 479 return 0; 480 } 481 482 static int ksz9477_port_fdb_add(struct dsa_switch *ds, int port, 483 const unsigned char *addr, u16 vid, 484 struct dsa_db db) 485 { 486 struct ksz_device *dev = ds->priv; 487 u32 alu_table[4]; 488 u32 data; 489 int ret = 0; 490 491 mutex_lock(&dev->alu_mutex); 492 493 /* find any entry with mac & vid */ 494 data = vid << ALU_FID_INDEX_S; 495 data |= ((addr[0] << 8) | addr[1]); 496 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 497 498 data = ((addr[2] << 24) | (addr[3] << 16)); 499 data |= ((addr[4] << 8) | addr[5]); 500 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 501 502 /* start read operation */ 503 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 504 505 /* wait to be finished */ 506 ret = ksz9477_wait_alu_ready(dev); 507 if (ret) { 508 dev_dbg(dev->dev, "Failed to read ALU\n"); 509 goto exit; 510 } 511 512 /* read ALU entry */ 513 ksz9477_read_table(dev, alu_table); 514 515 /* update ALU entry */ 516 alu_table[0] = ALU_V_STATIC_VALID; 517 alu_table[1] |= BIT(port); 518 if (vid) 519 alu_table[1] |= ALU_V_USE_FID; 520 alu_table[2] = (vid << ALU_V_FID_S); 521 alu_table[2] |= ((addr[0] << 8) | addr[1]); 522 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16)); 523 alu_table[3] |= ((addr[4] << 8) | addr[5]); 524 525 ksz9477_write_table(dev, alu_table); 526 527 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 528 529 /* wait to be finished */ 530 ret = ksz9477_wait_alu_ready(dev); 531 if (ret) 532 dev_dbg(dev->dev, "Failed to write ALU\n"); 533 534 exit: 535 mutex_unlock(&dev->alu_mutex); 536 537 return ret; 538 } 539 540 static int ksz9477_port_fdb_del(struct dsa_switch *ds, int port, 541 const unsigned char *addr, u16 vid, 542 struct dsa_db db) 543 { 544 struct ksz_device *dev = ds->priv; 545 u32 alu_table[4]; 546 u32 data; 547 int ret = 0; 548 549 mutex_lock(&dev->alu_mutex); 550 551 /* read any entry with mac & vid */ 552 data = vid << ALU_FID_INDEX_S; 553 data |= ((addr[0] << 8) | addr[1]); 554 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 555 556 data = ((addr[2] << 24) | (addr[3] << 16)); 557 data |= ((addr[4] << 8) | addr[5]); 558 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 559 560 /* start read operation */ 561 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 562 563 /* wait to be finished */ 564 ret = ksz9477_wait_alu_ready(dev); 565 if (ret) { 566 dev_dbg(dev->dev, "Failed to read ALU\n"); 567 goto exit; 568 } 569 570 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]); 571 if (alu_table[0] & ALU_V_STATIC_VALID) { 572 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]); 573 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]); 574 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]); 575 576 /* clear forwarding port */ 577 alu_table[2] &= ~BIT(port); 578 579 /* if there is no port to forward, clear table */ 580 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) { 581 alu_table[0] = 0; 582 alu_table[1] = 0; 583 alu_table[2] = 0; 584 alu_table[3] = 0; 585 } 586 } else { 587 alu_table[0] = 0; 588 alu_table[1] = 0; 589 alu_table[2] = 0; 590 alu_table[3] = 0; 591 } 592 593 ksz9477_write_table(dev, alu_table); 594 595 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 596 597 /* wait to be finished */ 598 ret = ksz9477_wait_alu_ready(dev); 599 if (ret) 600 dev_dbg(dev->dev, "Failed to write ALU\n"); 601 602 exit: 603 mutex_unlock(&dev->alu_mutex); 604 605 return ret; 606 } 607 608 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table) 609 { 610 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID); 611 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER); 612 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER); 613 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) & 614 ALU_V_PRIO_AGE_CNT_M; 615 alu->mstp = alu_table[0] & ALU_V_MSTP_M; 616 617 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE); 618 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID); 619 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP; 620 621 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M; 622 623 alu->mac[0] = (alu_table[2] >> 8) & 0xFF; 624 alu->mac[1] = alu_table[2] & 0xFF; 625 alu->mac[2] = (alu_table[3] >> 24) & 0xFF; 626 alu->mac[3] = (alu_table[3] >> 16) & 0xFF; 627 alu->mac[4] = (alu_table[3] >> 8) & 0xFF; 628 alu->mac[5] = alu_table[3] & 0xFF; 629 } 630 631 static int ksz9477_port_fdb_dump(struct dsa_switch *ds, int port, 632 dsa_fdb_dump_cb_t *cb, void *data) 633 { 634 struct ksz_device *dev = ds->priv; 635 int ret = 0; 636 u32 ksz_data; 637 u32 alu_table[4]; 638 struct alu_struct alu; 639 int timeout; 640 641 mutex_lock(&dev->alu_mutex); 642 643 /* start ALU search */ 644 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH); 645 646 do { 647 timeout = 1000; 648 do { 649 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data); 650 if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START)) 651 break; 652 usleep_range(1, 10); 653 } while (timeout-- > 0); 654 655 if (!timeout) { 656 dev_dbg(dev->dev, "Failed to search ALU\n"); 657 ret = -ETIMEDOUT; 658 goto exit; 659 } 660 661 /* read ALU table */ 662 ksz9477_read_table(dev, alu_table); 663 664 ksz9477_convert_alu(&alu, alu_table); 665 666 if (alu.port_forward & BIT(port)) { 667 ret = cb(alu.mac, alu.fid, alu.is_static, data); 668 if (ret) 669 goto exit; 670 } 671 } while (ksz_data & ALU_START); 672 673 exit: 674 675 /* stop ALU search */ 676 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0); 677 678 mutex_unlock(&dev->alu_mutex); 679 680 return ret; 681 } 682 683 static int ksz9477_port_mdb_add(struct dsa_switch *ds, int port, 684 const struct switchdev_obj_port_mdb *mdb, 685 struct dsa_db db) 686 { 687 struct ksz_device *dev = ds->priv; 688 u32 static_table[4]; 689 u32 data; 690 int index; 691 u32 mac_hi, mac_lo; 692 int err = 0; 693 694 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 695 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 696 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 697 698 mutex_lock(&dev->alu_mutex); 699 700 for (index = 0; index < dev->info->num_statics; index++) { 701 /* find empty slot first */ 702 data = (index << ALU_STAT_INDEX_S) | 703 ALU_STAT_READ | ALU_STAT_START; 704 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 705 706 /* wait to be finished */ 707 err = ksz9477_wait_alu_sta_ready(dev); 708 if (err) { 709 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 710 goto exit; 711 } 712 713 /* read ALU static table */ 714 ksz9477_read_table(dev, static_table); 715 716 if (static_table[0] & ALU_V_STATIC_VALID) { 717 /* check this has same vid & mac address */ 718 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 719 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 720 static_table[3] == mac_lo) { 721 /* found matching one */ 722 break; 723 } 724 } else { 725 /* found empty one */ 726 break; 727 } 728 } 729 730 /* no available entry */ 731 if (index == dev->info->num_statics) { 732 err = -ENOSPC; 733 goto exit; 734 } 735 736 /* add entry */ 737 static_table[0] = ALU_V_STATIC_VALID; 738 static_table[1] |= BIT(port); 739 if (mdb->vid) 740 static_table[1] |= ALU_V_USE_FID; 741 static_table[2] = (mdb->vid << ALU_V_FID_S); 742 static_table[2] |= mac_hi; 743 static_table[3] = mac_lo; 744 745 ksz9477_write_table(dev, static_table); 746 747 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 748 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 749 750 /* wait to be finished */ 751 if (ksz9477_wait_alu_sta_ready(dev)) 752 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 753 754 exit: 755 mutex_unlock(&dev->alu_mutex); 756 return err; 757 } 758 759 static int ksz9477_port_mdb_del(struct dsa_switch *ds, int port, 760 const struct switchdev_obj_port_mdb *mdb, 761 struct dsa_db db) 762 { 763 struct ksz_device *dev = ds->priv; 764 u32 static_table[4]; 765 u32 data; 766 int index; 767 int ret = 0; 768 u32 mac_hi, mac_lo; 769 770 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 771 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 772 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 773 774 mutex_lock(&dev->alu_mutex); 775 776 for (index = 0; index < dev->info->num_statics; index++) { 777 /* find empty slot first */ 778 data = (index << ALU_STAT_INDEX_S) | 779 ALU_STAT_READ | ALU_STAT_START; 780 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 781 782 /* wait to be finished */ 783 ret = ksz9477_wait_alu_sta_ready(dev); 784 if (ret) { 785 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 786 goto exit; 787 } 788 789 /* read ALU static table */ 790 ksz9477_read_table(dev, static_table); 791 792 if (static_table[0] & ALU_V_STATIC_VALID) { 793 /* check this has same vid & mac address */ 794 795 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 796 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 797 static_table[3] == mac_lo) { 798 /* found matching one */ 799 break; 800 } 801 } 802 } 803 804 /* no available entry */ 805 if (index == dev->info->num_statics) 806 goto exit; 807 808 /* clear port */ 809 static_table[1] &= ~BIT(port); 810 811 if ((static_table[1] & ALU_V_PORT_MAP) == 0) { 812 /* delete entry */ 813 static_table[0] = 0; 814 static_table[1] = 0; 815 static_table[2] = 0; 816 static_table[3] = 0; 817 } 818 819 ksz9477_write_table(dev, static_table); 820 821 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 822 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 823 824 /* wait to be finished */ 825 ret = ksz9477_wait_alu_sta_ready(dev); 826 if (ret) 827 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 828 829 exit: 830 mutex_unlock(&dev->alu_mutex); 831 832 return ret; 833 } 834 835 static int ksz9477_port_mirror_add(struct dsa_switch *ds, int port, 836 struct dsa_mall_mirror_tc_entry *mirror, 837 bool ingress, struct netlink_ext_ack *extack) 838 { 839 struct ksz_device *dev = ds->priv; 840 u8 data; 841 int p; 842 843 /* Limit to one sniffer port 844 * Check if any of the port is already set for sniffing 845 * If yes, instruct the user to remove the previous entry & exit 846 */ 847 for (p = 0; p < dev->info->port_cnt; p++) { 848 /* Skip the current sniffing port */ 849 if (p == mirror->to_local_port) 850 continue; 851 852 ksz_pread8(dev, p, P_MIRROR_CTRL, &data); 853 854 if (data & PORT_MIRROR_SNIFFER) { 855 NL_SET_ERR_MSG_MOD(extack, 856 "Sniffer port is already configured, delete existing rules & retry"); 857 return -EBUSY; 858 } 859 } 860 861 if (ingress) 862 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 863 else 864 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 865 866 /* configure mirror port */ 867 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 868 PORT_MIRROR_SNIFFER, true); 869 870 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 871 872 return 0; 873 } 874 875 static void ksz9477_port_mirror_del(struct dsa_switch *ds, int port, 876 struct dsa_mall_mirror_tc_entry *mirror) 877 { 878 struct ksz_device *dev = ds->priv; 879 bool in_use = false; 880 u8 data; 881 int p; 882 883 if (mirror->ingress) 884 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 885 else 886 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 887 888 889 /* Check if any of the port is still referring to sniffer port */ 890 for (p = 0; p < dev->info->port_cnt; p++) { 891 ksz_pread8(dev, p, P_MIRROR_CTRL, &data); 892 893 if ((data & (PORT_MIRROR_RX | PORT_MIRROR_TX))) { 894 in_use = true; 895 break; 896 } 897 } 898 899 /* delete sniffing if there are no other mirroring rules */ 900 if (!in_use) 901 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 902 PORT_MIRROR_SNIFFER, false); 903 } 904 905 static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data) 906 { 907 bool gbit; 908 909 if (dev->features & NEW_XMII) 910 gbit = !(data & PORT_MII_NOT_1GBIT); 911 else 912 gbit = !!(data & PORT_MII_1000MBIT_S1); 913 return gbit; 914 } 915 916 static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data) 917 { 918 if (dev->features & NEW_XMII) { 919 if (gbit) 920 *data &= ~PORT_MII_NOT_1GBIT; 921 else 922 *data |= PORT_MII_NOT_1GBIT; 923 } else { 924 if (gbit) 925 *data |= PORT_MII_1000MBIT_S1; 926 else 927 *data &= ~PORT_MII_1000MBIT_S1; 928 } 929 } 930 931 static int ksz9477_get_xmii(struct ksz_device *dev, u8 data) 932 { 933 int mode; 934 935 if (dev->features & NEW_XMII) { 936 switch (data & PORT_MII_SEL_M) { 937 case PORT_MII_SEL: 938 mode = 0; 939 break; 940 case PORT_RMII_SEL: 941 mode = 1; 942 break; 943 case PORT_GMII_SEL: 944 mode = 2; 945 break; 946 default: 947 mode = 3; 948 } 949 } else { 950 switch (data & PORT_MII_SEL_M) { 951 case PORT_MII_SEL_S1: 952 mode = 0; 953 break; 954 case PORT_RMII_SEL_S1: 955 mode = 1; 956 break; 957 case PORT_GMII_SEL_S1: 958 mode = 2; 959 break; 960 default: 961 mode = 3; 962 } 963 } 964 return mode; 965 } 966 967 static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data) 968 { 969 u8 xmii; 970 971 if (dev->features & NEW_XMII) { 972 switch (mode) { 973 case 0: 974 xmii = PORT_MII_SEL; 975 break; 976 case 1: 977 xmii = PORT_RMII_SEL; 978 break; 979 case 2: 980 xmii = PORT_GMII_SEL; 981 break; 982 default: 983 xmii = PORT_RGMII_SEL; 984 break; 985 } 986 } else { 987 switch (mode) { 988 case 0: 989 xmii = PORT_MII_SEL_S1; 990 break; 991 case 1: 992 xmii = PORT_RMII_SEL_S1; 993 break; 994 case 2: 995 xmii = PORT_GMII_SEL_S1; 996 break; 997 default: 998 xmii = PORT_RGMII_SEL_S1; 999 break; 1000 } 1001 } 1002 *data &= ~PORT_MII_SEL_M; 1003 *data |= xmii; 1004 } 1005 1006 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port) 1007 { 1008 phy_interface_t interface; 1009 bool gbit; 1010 int mode; 1011 u8 data8; 1012 1013 if (port < dev->phy_port_cnt) 1014 return PHY_INTERFACE_MODE_NA; 1015 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 1016 gbit = ksz9477_get_gbit(dev, data8); 1017 mode = ksz9477_get_xmii(dev, data8); 1018 switch (mode) { 1019 case 2: 1020 interface = PHY_INTERFACE_MODE_GMII; 1021 if (gbit) 1022 break; 1023 fallthrough; 1024 case 0: 1025 interface = PHY_INTERFACE_MODE_MII; 1026 break; 1027 case 1: 1028 interface = PHY_INTERFACE_MODE_RMII; 1029 break; 1030 default: 1031 interface = PHY_INTERFACE_MODE_RGMII; 1032 if (data8 & PORT_RGMII_ID_EG_ENABLE) 1033 interface = PHY_INTERFACE_MODE_RGMII_TXID; 1034 if (data8 & PORT_RGMII_ID_IG_ENABLE) { 1035 interface = PHY_INTERFACE_MODE_RGMII_RXID; 1036 if (data8 & PORT_RGMII_ID_EG_ENABLE) 1037 interface = PHY_INTERFACE_MODE_RGMII_ID; 1038 } 1039 break; 1040 } 1041 return interface; 1042 } 1043 1044 static void ksz9477_port_mmd_write(struct ksz_device *dev, int port, 1045 u8 dev_addr, u16 reg_addr, u16 val) 1046 { 1047 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 1048 MMD_SETUP(PORT_MMD_OP_INDEX, dev_addr)); 1049 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg_addr); 1050 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 1051 MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, dev_addr)); 1052 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val); 1053 } 1054 1055 static void ksz9477_phy_errata_setup(struct ksz_device *dev, int port) 1056 { 1057 /* Apply PHY settings to address errata listed in 1058 * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565 1059 * Silicon Errata and Data Sheet Clarification documents: 1060 * 1061 * Register settings are needed to improve PHY receive performance 1062 */ 1063 ksz9477_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b); 1064 ksz9477_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032); 1065 ksz9477_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c); 1066 ksz9477_port_mmd_write(dev, port, 0x01, 0x75, 0x0060); 1067 ksz9477_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777); 1068 ksz9477_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008); 1069 ksz9477_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001); 1070 1071 /* Transmit waveform amplitude can be improved 1072 * (1000BASE-T, 100BASE-TX, 10BASE-Te) 1073 */ 1074 ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0); 1075 1076 /* Energy Efficient Ethernet (EEE) feature select must 1077 * be manually disabled (except on KSZ8565 which is 100Mbit) 1078 */ 1079 if (dev->features & GBIT_SUPPORT) 1080 ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000); 1081 1082 /* Register settings are required to meet data sheet 1083 * supply current specifications 1084 */ 1085 ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff); 1086 ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff); 1087 ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff); 1088 ksz9477_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff); 1089 ksz9477_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff); 1090 ksz9477_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff); 1091 ksz9477_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff); 1092 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff); 1093 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff); 1094 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff); 1095 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff); 1096 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff); 1097 ksz9477_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee); 1098 } 1099 1100 static void ksz9477_get_caps(struct dsa_switch *ds, int port, 1101 struct phylink_config *config) 1102 { 1103 ksz_phylink_get_caps(ds, port, config); 1104 1105 config->mac_capabilities = MAC_10 | MAC_100 | MAC_1000FD | 1106 MAC_ASYM_PAUSE | MAC_SYM_PAUSE; 1107 } 1108 1109 static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1110 { 1111 struct ksz_port *p = &dev->ports[port]; 1112 struct dsa_switch *ds = dev->ds; 1113 u8 data8, member; 1114 u16 data16; 1115 1116 /* enable tag tail for host port */ 1117 if (cpu_port) 1118 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE, 1119 true); 1120 1121 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false); 1122 1123 /* set back pressure */ 1124 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true); 1125 1126 /* enable broadcast storm limit */ 1127 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 1128 1129 /* disable DiffServ priority */ 1130 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false); 1131 1132 /* replace priority */ 1133 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING, 1134 false); 1135 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4, 1136 MTI_PVID_REPLACE, false); 1137 1138 /* enable 802.1p priority */ 1139 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); 1140 1141 if (port < dev->phy_port_cnt) { 1142 /* do not force flow control */ 1143 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1144 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1145 false); 1146 1147 if (dev->info->phy_errata_9477) 1148 ksz9477_phy_errata_setup(dev, port); 1149 } else { 1150 /* force flow control */ 1151 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1152 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1153 true); 1154 1155 /* configure MAC to 1G & RGMII mode */ 1156 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 1157 switch (p->interface) { 1158 case PHY_INTERFACE_MODE_MII: 1159 ksz9477_set_xmii(dev, 0, &data8); 1160 ksz9477_set_gbit(dev, false, &data8); 1161 p->phydev.speed = SPEED_100; 1162 break; 1163 case PHY_INTERFACE_MODE_RMII: 1164 ksz9477_set_xmii(dev, 1, &data8); 1165 ksz9477_set_gbit(dev, false, &data8); 1166 p->phydev.speed = SPEED_100; 1167 break; 1168 case PHY_INTERFACE_MODE_GMII: 1169 ksz9477_set_xmii(dev, 2, &data8); 1170 ksz9477_set_gbit(dev, true, &data8); 1171 p->phydev.speed = SPEED_1000; 1172 break; 1173 default: 1174 ksz9477_set_xmii(dev, 3, &data8); 1175 ksz9477_set_gbit(dev, true, &data8); 1176 data8 &= ~PORT_RGMII_ID_IG_ENABLE; 1177 data8 &= ~PORT_RGMII_ID_EG_ENABLE; 1178 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1179 p->interface == PHY_INTERFACE_MODE_RGMII_RXID) 1180 data8 |= PORT_RGMII_ID_IG_ENABLE; 1181 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1182 p->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1183 data8 |= PORT_RGMII_ID_EG_ENABLE; 1184 /* On KSZ9893, disable RGMII in-band status support */ 1185 if (dev->features & IS_9893) 1186 data8 &= ~PORT_MII_MAC_MODE; 1187 p->phydev.speed = SPEED_1000; 1188 break; 1189 } 1190 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8); 1191 p->phydev.duplex = 1; 1192 } 1193 1194 if (cpu_port) 1195 member = dsa_user_ports(ds); 1196 else 1197 member = BIT(dsa_upstream_port(ds, port)); 1198 1199 ksz9477_cfg_port_member(dev, port, member); 1200 1201 /* clear pending interrupts */ 1202 if (port < dev->phy_port_cnt) 1203 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16); 1204 } 1205 1206 static void ksz9477_config_cpu_port(struct dsa_switch *ds) 1207 { 1208 struct ksz_device *dev = ds->priv; 1209 struct ksz_port *p; 1210 int i; 1211 1212 for (i = 0; i < dev->info->port_cnt; i++) { 1213 if (dsa_is_cpu_port(ds, i) && 1214 (dev->info->cpu_ports & (1 << i))) { 1215 phy_interface_t interface; 1216 const char *prev_msg; 1217 const char *prev_mode; 1218 1219 dev->cpu_port = i; 1220 p = &dev->ports[i]; 1221 1222 /* Read from XMII register to determine host port 1223 * interface. If set specifically in device tree 1224 * note the difference to help debugging. 1225 */ 1226 interface = ksz9477_get_interface(dev, i); 1227 if (!p->interface) { 1228 if (dev->compat_interface) { 1229 dev_warn(dev->dev, 1230 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 1231 "Please update your device tree.\n", 1232 i); 1233 p->interface = dev->compat_interface; 1234 } else { 1235 p->interface = interface; 1236 } 1237 } 1238 if (interface && interface != p->interface) { 1239 prev_msg = " instead of "; 1240 prev_mode = phy_modes(interface); 1241 } else { 1242 prev_msg = ""; 1243 prev_mode = ""; 1244 } 1245 dev_info(dev->dev, 1246 "Port%d: using phy mode %s%s%s\n", 1247 i, 1248 phy_modes(p->interface), 1249 prev_msg, 1250 prev_mode); 1251 1252 /* enable cpu port */ 1253 ksz9477_port_setup(dev, i, true); 1254 p->on = 1; 1255 } 1256 } 1257 1258 for (i = 0; i < dev->info->port_cnt; i++) { 1259 if (i == dev->cpu_port) 1260 continue; 1261 p = &dev->ports[i]; 1262 1263 ksz9477_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1264 p->on = 1; 1265 if (i < dev->phy_port_cnt) 1266 p->phy = 1; 1267 if (dev->chip_id == 0x00947700 && i == 6) { 1268 p->sgmii = 1; 1269 1270 /* SGMII PHY detection code is not implemented yet. */ 1271 p->phy = 0; 1272 } 1273 } 1274 } 1275 1276 static int ksz9477_setup(struct dsa_switch *ds) 1277 { 1278 struct ksz_device *dev = ds->priv; 1279 int ret = 0; 1280 1281 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 1282 dev->info->num_vlans, GFP_KERNEL); 1283 if (!dev->vlan_cache) 1284 return -ENOMEM; 1285 1286 ret = ksz9477_reset_switch(dev); 1287 if (ret) { 1288 dev_err(ds->dev, "failed to reset switch\n"); 1289 return ret; 1290 } 1291 1292 /* Required for port partitioning. */ 1293 ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, 1294 true); 1295 1296 /* Do not work correctly with tail tagging. */ 1297 ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false); 1298 1299 /* Enable REG_SW_MTU__2 reg by setting SW_JUMBO_PACKET */ 1300 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_JUMBO_PACKET, true); 1301 1302 /* Now we can configure default MTU value */ 1303 ret = regmap_update_bits(dev->regmap[1], REG_SW_MTU__2, REG_SW_MTU_MASK, 1304 VLAN_ETH_FRAME_LEN + ETH_FCS_LEN); 1305 if (ret) 1306 return ret; 1307 1308 ksz9477_config_cpu_port(ds); 1309 1310 ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true); 1311 1312 /* queue based egress rate limit */ 1313 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true); 1314 1315 /* enable global MIB counter freeze function */ 1316 ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); 1317 1318 /* start switch */ 1319 ksz_cfg(dev, REG_SW_OPERATION, SW_START, true); 1320 1321 ksz_init_mib_timer(dev); 1322 1323 ds->configure_vlan_while_not_filtering = false; 1324 1325 return 0; 1326 } 1327 1328 static const struct dsa_switch_ops ksz9477_switch_ops = { 1329 .get_tag_protocol = ksz9477_get_tag_protocol, 1330 .setup = ksz9477_setup, 1331 .phy_read = ksz9477_phy_read16, 1332 .phy_write = ksz9477_phy_write16, 1333 .phylink_mac_link_down = ksz_mac_link_down, 1334 .phylink_get_caps = ksz9477_get_caps, 1335 .port_enable = ksz_enable_port, 1336 .get_strings = ksz_get_strings, 1337 .get_ethtool_stats = ksz_get_ethtool_stats, 1338 .get_sset_count = ksz_sset_count, 1339 .port_bridge_join = ksz_port_bridge_join, 1340 .port_bridge_leave = ksz_port_bridge_leave, 1341 .port_stp_state_set = ksz9477_port_stp_state_set, 1342 .port_fast_age = ksz_port_fast_age, 1343 .port_vlan_filtering = ksz9477_port_vlan_filtering, 1344 .port_vlan_add = ksz9477_port_vlan_add, 1345 .port_vlan_del = ksz9477_port_vlan_del, 1346 .port_fdb_dump = ksz9477_port_fdb_dump, 1347 .port_fdb_add = ksz9477_port_fdb_add, 1348 .port_fdb_del = ksz9477_port_fdb_del, 1349 .port_mdb_add = ksz9477_port_mdb_add, 1350 .port_mdb_del = ksz9477_port_mdb_del, 1351 .port_mirror_add = ksz9477_port_mirror_add, 1352 .port_mirror_del = ksz9477_port_mirror_del, 1353 .get_stats64 = ksz_get_stats64, 1354 .port_change_mtu = ksz9477_change_mtu, 1355 .port_max_mtu = ksz9477_max_mtu, 1356 }; 1357 1358 static u32 ksz9477_get_port_addr(int port, int offset) 1359 { 1360 return PORT_CTRL_ADDR(port, offset); 1361 } 1362 1363 static int ksz9477_switch_detect(struct ksz_device *dev) 1364 { 1365 u8 data8; 1366 u8 id_hi; 1367 u8 id_lo; 1368 u32 id32; 1369 int ret; 1370 1371 /* turn off SPI DO Edge select */ 1372 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 1373 if (ret) 1374 return ret; 1375 1376 data8 &= ~SPI_AUTO_EDGE_DETECTION; 1377 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 1378 if (ret) 1379 return ret; 1380 1381 /* read chip id */ 1382 ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32); 1383 if (ret) 1384 return ret; 1385 ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8); 1386 if (ret) 1387 return ret; 1388 1389 /* Number of ports can be reduced depending on chip. */ 1390 dev->phy_port_cnt = 5; 1391 1392 /* Default capability is gigabit capable. */ 1393 dev->features = GBIT_SUPPORT; 1394 1395 dev_dbg(dev->dev, "Switch detect: ID=%08x%02x\n", id32, data8); 1396 id_hi = (u8)(id32 >> 16); 1397 id_lo = (u8)(id32 >> 8); 1398 if ((id_lo & 0xf) == 3) { 1399 /* Chip is from KSZ9893 design. */ 1400 dev_info(dev->dev, "Found KSZ9893\n"); 1401 dev->features |= IS_9893; 1402 1403 /* Chip does not support gigabit. */ 1404 if (data8 & SW_QW_ABLE) 1405 dev->features &= ~GBIT_SUPPORT; 1406 dev->phy_port_cnt = 2; 1407 } else { 1408 dev_info(dev->dev, "Found KSZ9477 or compatible\n"); 1409 /* Chip uses new XMII register definitions. */ 1410 dev->features |= NEW_XMII; 1411 1412 /* Chip does not support gigabit. */ 1413 if (!(data8 & SW_GIGABIT_ABLE)) 1414 dev->features &= ~GBIT_SUPPORT; 1415 } 1416 1417 /* Change chip id to known ones so it can be matched against them. */ 1418 id32 = (id_hi << 16) | (id_lo << 8); 1419 1420 dev->chip_id = id32; 1421 1422 return 0; 1423 } 1424 1425 static int ksz9477_switch_init(struct ksz_device *dev) 1426 { 1427 dev->ds->ops = &ksz9477_switch_ops; 1428 1429 dev->port_mask = (1 << dev->info->port_cnt) - 1; 1430 1431 return 0; 1432 } 1433 1434 static void ksz9477_switch_exit(struct ksz_device *dev) 1435 { 1436 ksz9477_reset_switch(dev); 1437 } 1438 1439 static const struct ksz_dev_ops ksz9477_dev_ops = { 1440 .get_port_addr = ksz9477_get_port_addr, 1441 .cfg_port_member = ksz9477_cfg_port_member, 1442 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 1443 .port_setup = ksz9477_port_setup, 1444 .r_mib_cnt = ksz9477_r_mib_cnt, 1445 .r_mib_pkt = ksz9477_r_mib_pkt, 1446 .r_mib_stat64 = ksz_r_mib_stats64, 1447 .freeze_mib = ksz9477_freeze_mib, 1448 .port_init_cnt = ksz9477_port_init_cnt, 1449 .shutdown = ksz9477_reset_switch, 1450 .detect = ksz9477_switch_detect, 1451 .init = ksz9477_switch_init, 1452 .exit = ksz9477_switch_exit, 1453 }; 1454 1455 int ksz9477_switch_register(struct ksz_device *dev) 1456 { 1457 int ret, i; 1458 struct phy_device *phydev; 1459 1460 ret = ksz_switch_register(dev, &ksz9477_dev_ops); 1461 if (ret) 1462 return ret; 1463 1464 for (i = 0; i < dev->phy_port_cnt; ++i) { 1465 if (!dsa_is_user_port(dev->ds, i)) 1466 continue; 1467 1468 phydev = dsa_to_port(dev->ds, i)->slave->phydev; 1469 1470 /* The MAC actually cannot run in 1000 half-duplex mode. */ 1471 phy_remove_link_mode(phydev, 1472 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1473 1474 /* PHY does not support gigabit. */ 1475 if (!(dev->features & GBIT_SUPPORT)) 1476 phy_remove_link_mode(phydev, 1477 ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 1478 } 1479 return ret; 1480 } 1481 EXPORT_SYMBOL(ksz9477_switch_register); 1482 1483 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 1484 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver"); 1485 MODULE_LICENSE("GPL"); 1486