1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ9477 switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/iopoll.h> 11 #include <linux/platform_data/microchip-ksz.h> 12 #include <linux/phy.h> 13 #include <linux/if_bridge.h> 14 #include <linux/if_vlan.h> 15 #include <net/dsa.h> 16 #include <net/switchdev.h> 17 18 #include "ksz9477_reg.h" 19 #include "ksz_common.h" 20 21 /* Used with variable features to indicate capabilities. */ 22 #define GBIT_SUPPORT BIT(0) 23 #define NEW_XMII BIT(1) 24 #define IS_9893 BIT(2) 25 26 static const struct { 27 int index; 28 char string[ETH_GSTRING_LEN]; 29 } ksz9477_mib_names[TOTAL_SWITCH_COUNTER_NUM] = { 30 { 0x00, "rx_hi" }, 31 { 0x01, "rx_undersize" }, 32 { 0x02, "rx_fragments" }, 33 { 0x03, "rx_oversize" }, 34 { 0x04, "rx_jabbers" }, 35 { 0x05, "rx_symbol_err" }, 36 { 0x06, "rx_crc_err" }, 37 { 0x07, "rx_align_err" }, 38 { 0x08, "rx_mac_ctrl" }, 39 { 0x09, "rx_pause" }, 40 { 0x0A, "rx_bcast" }, 41 { 0x0B, "rx_mcast" }, 42 { 0x0C, "rx_ucast" }, 43 { 0x0D, "rx_64_or_less" }, 44 { 0x0E, "rx_65_127" }, 45 { 0x0F, "rx_128_255" }, 46 { 0x10, "rx_256_511" }, 47 { 0x11, "rx_512_1023" }, 48 { 0x12, "rx_1024_1522" }, 49 { 0x13, "rx_1523_2000" }, 50 { 0x14, "rx_2001" }, 51 { 0x15, "tx_hi" }, 52 { 0x16, "tx_late_col" }, 53 { 0x17, "tx_pause" }, 54 { 0x18, "tx_bcast" }, 55 { 0x19, "tx_mcast" }, 56 { 0x1A, "tx_ucast" }, 57 { 0x1B, "tx_deferred" }, 58 { 0x1C, "tx_total_col" }, 59 { 0x1D, "tx_exc_col" }, 60 { 0x1E, "tx_single_col" }, 61 { 0x1F, "tx_mult_col" }, 62 { 0x80, "rx_total" }, 63 { 0x81, "tx_total" }, 64 { 0x82, "rx_discards" }, 65 { 0x83, "tx_discards" }, 66 }; 67 68 struct ksz9477_stats_raw { 69 u64 rx_hi; 70 u64 rx_undersize; 71 u64 rx_fragments; 72 u64 rx_oversize; 73 u64 rx_jabbers; 74 u64 rx_symbol_err; 75 u64 rx_crc_err; 76 u64 rx_align_err; 77 u64 rx_mac_ctrl; 78 u64 rx_pause; 79 u64 rx_bcast; 80 u64 rx_mcast; 81 u64 rx_ucast; 82 u64 rx_64_or_less; 83 u64 rx_65_127; 84 u64 rx_128_255; 85 u64 rx_256_511; 86 u64 rx_512_1023; 87 u64 rx_1024_1522; 88 u64 rx_1523_2000; 89 u64 rx_2001; 90 u64 tx_hi; 91 u64 tx_late_col; 92 u64 tx_pause; 93 u64 tx_bcast; 94 u64 tx_mcast; 95 u64 tx_ucast; 96 u64 tx_deferred; 97 u64 tx_total_col; 98 u64 tx_exc_col; 99 u64 tx_single_col; 100 u64 tx_mult_col; 101 u64 rx_total; 102 u64 tx_total; 103 u64 rx_discards; 104 u64 tx_discards; 105 }; 106 107 static void ksz9477_r_mib_stats64(struct ksz_device *dev, int port) 108 { 109 struct rtnl_link_stats64 *stats; 110 struct ksz9477_stats_raw *raw; 111 struct ksz_port_mib *mib; 112 113 mib = &dev->ports[port].mib; 114 stats = &mib->stats64; 115 raw = (struct ksz9477_stats_raw *)mib->counters; 116 117 spin_lock(&mib->stats64_lock); 118 119 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast; 120 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast; 121 122 /* HW counters are counting bytes + FCS which is not acceptable 123 * for rtnl_link_stats64 interface 124 */ 125 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 126 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 127 128 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 129 raw->rx_oversize; 130 131 stats->rx_crc_errors = raw->rx_crc_err; 132 stats->rx_frame_errors = raw->rx_align_err; 133 stats->rx_dropped = raw->rx_discards; 134 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 135 stats->rx_frame_errors + stats->rx_dropped; 136 137 stats->tx_window_errors = raw->tx_late_col; 138 stats->tx_fifo_errors = raw->tx_discards; 139 stats->tx_aborted_errors = raw->tx_exc_col; 140 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 141 stats->tx_aborted_errors; 142 143 stats->multicast = raw->rx_mcast; 144 stats->collisions = raw->tx_total_col; 145 146 spin_unlock(&mib->stats64_lock); 147 } 148 149 static void ksz9477_get_stats64(struct dsa_switch *ds, int port, 150 struct rtnl_link_stats64 *s) 151 { 152 struct ksz_device *dev = ds->priv; 153 struct ksz_port_mib *mib; 154 155 mib = &dev->ports[port].mib; 156 157 spin_lock(&mib->stats64_lock); 158 memcpy(s, &mib->stats64, sizeof(*s)); 159 spin_unlock(&mib->stats64_lock); 160 } 161 162 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 163 { 164 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0); 165 } 166 167 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 168 bool set) 169 { 170 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset), 171 bits, set ? bits : 0); 172 } 173 174 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set) 175 { 176 regmap_update_bits(dev->regmap[2], addr, bits, set ? bits : 0); 177 } 178 179 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset, 180 u32 bits, bool set) 181 { 182 regmap_update_bits(dev->regmap[2], PORT_CTRL_ADDR(port, offset), 183 bits, set ? bits : 0); 184 } 185 186 static int ksz9477_change_mtu(struct dsa_switch *ds, int port, int mtu) 187 { 188 struct ksz_device *dev = ds->priv; 189 u16 frame_size, max_frame = 0; 190 int i; 191 192 frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 193 194 /* Cache the per-port MTU setting */ 195 dev->ports[port].max_frame = frame_size; 196 197 for (i = 0; i < dev->port_cnt; i++) 198 max_frame = max(max_frame, dev->ports[i].max_frame); 199 200 return regmap_update_bits(dev->regmap[1], REG_SW_MTU__2, 201 REG_SW_MTU_MASK, max_frame); 202 } 203 204 static int ksz9477_max_mtu(struct dsa_switch *ds, int port) 205 { 206 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 207 } 208 209 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev) 210 { 211 unsigned int val; 212 213 return regmap_read_poll_timeout(dev->regmap[0], REG_SW_VLAN_CTRL, 214 val, !(val & VLAN_START), 10, 1000); 215 } 216 217 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid, 218 u32 *vlan_table) 219 { 220 int ret; 221 222 mutex_lock(&dev->vlan_mutex); 223 224 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 225 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START); 226 227 /* wait to be cleared */ 228 ret = ksz9477_wait_vlan_ctrl_ready(dev); 229 if (ret) { 230 dev_dbg(dev->dev, "Failed to read vlan table\n"); 231 goto exit; 232 } 233 234 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]); 235 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]); 236 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]); 237 238 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 239 240 exit: 241 mutex_unlock(&dev->vlan_mutex); 242 243 return ret; 244 } 245 246 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid, 247 u32 *vlan_table) 248 { 249 int ret; 250 251 mutex_lock(&dev->vlan_mutex); 252 253 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]); 254 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]); 255 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]); 256 257 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 258 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE); 259 260 /* wait to be cleared */ 261 ret = ksz9477_wait_vlan_ctrl_ready(dev); 262 if (ret) { 263 dev_dbg(dev->dev, "Failed to write vlan table\n"); 264 goto exit; 265 } 266 267 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 268 269 /* update vlan cache table */ 270 dev->vlan_cache[vid].table[0] = vlan_table[0]; 271 dev->vlan_cache[vid].table[1] = vlan_table[1]; 272 dev->vlan_cache[vid].table[2] = vlan_table[2]; 273 274 exit: 275 mutex_unlock(&dev->vlan_mutex); 276 277 return ret; 278 } 279 280 static void ksz9477_read_table(struct ksz_device *dev, u32 *table) 281 { 282 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]); 283 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]); 284 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]); 285 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]); 286 } 287 288 static void ksz9477_write_table(struct ksz_device *dev, u32 *table) 289 { 290 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]); 291 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]); 292 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]); 293 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]); 294 } 295 296 static int ksz9477_wait_alu_ready(struct ksz_device *dev) 297 { 298 unsigned int val; 299 300 return regmap_read_poll_timeout(dev->regmap[2], REG_SW_ALU_CTRL__4, 301 val, !(val & ALU_START), 10, 1000); 302 } 303 304 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev) 305 { 306 unsigned int val; 307 308 return regmap_read_poll_timeout(dev->regmap[2], 309 REG_SW_ALU_STAT_CTRL__4, 310 val, !(val & ALU_STAT_START), 311 10, 1000); 312 } 313 314 static int ksz9477_reset_switch(struct ksz_device *dev) 315 { 316 u8 data8; 317 u32 data32; 318 319 /* reset switch */ 320 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 321 322 /* turn off SPI DO Edge select */ 323 regmap_update_bits(dev->regmap[0], REG_SW_GLOBAL_SERIAL_CTRL_0, 324 SPI_AUTO_EDGE_DETECTION, 0); 325 326 /* default configuration */ 327 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8); 328 data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING | 329 SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE; 330 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8); 331 332 /* disable interrupts */ 333 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 334 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F); 335 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 336 337 /* set broadcast storm protection 10% rate */ 338 regmap_update_bits(dev->regmap[1], REG_SW_MAC_CTRL_2, 339 BROADCAST_STORM_RATE, 340 (BROADCAST_STORM_VALUE * 341 BROADCAST_STORM_PROT_RATE) / 100); 342 343 data8 = SW_ENABLE_REFCLKO; 344 if (dev->synclko_disable) 345 data8 = 0; 346 else if (dev->synclko_125) 347 data8 = SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ; 348 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, data8); 349 350 return 0; 351 } 352 353 static void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, 354 u64 *cnt) 355 { 356 struct ksz_port *p = &dev->ports[port]; 357 unsigned int val; 358 u32 data; 359 int ret; 360 361 /* retain the flush/freeze bit */ 362 data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 363 data |= MIB_COUNTER_READ; 364 data |= (addr << MIB_COUNTER_INDEX_S); 365 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data); 366 367 ret = regmap_read_poll_timeout(dev->regmap[2], 368 PORT_CTRL_ADDR(port, REG_PORT_MIB_CTRL_STAT__4), 369 val, !(val & MIB_COUNTER_READ), 10, 1000); 370 /* failed to read MIB. get out of loop */ 371 if (ret) { 372 dev_dbg(dev->dev, "Failed to get MIB\n"); 373 return; 374 } 375 376 /* count resets upon read */ 377 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data); 378 *cnt += data; 379 } 380 381 static void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 382 u64 *dropped, u64 *cnt) 383 { 384 addr = ksz9477_mib_names[addr].index; 385 ksz9477_r_mib_cnt(dev, port, addr, cnt); 386 } 387 388 static void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze) 389 { 390 u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 391 struct ksz_port *p = &dev->ports[port]; 392 393 /* enable/disable the port for flush/freeze function */ 394 mutex_lock(&p->mib.cnt_mutex); 395 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val); 396 397 /* used by MIB counter reading code to know freeze is enabled */ 398 p->freeze = freeze; 399 mutex_unlock(&p->mib.cnt_mutex); 400 } 401 402 static void ksz9477_port_init_cnt(struct ksz_device *dev, int port) 403 { 404 struct ksz_port_mib *mib = &dev->ports[port].mib; 405 406 /* flush all enabled port MIB counters */ 407 mutex_lock(&mib->cnt_mutex); 408 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 409 MIB_COUNTER_FLUSH_FREEZE); 410 ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH); 411 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0); 412 mutex_unlock(&mib->cnt_mutex); 413 414 mib->cnt_ptr = 0; 415 memset(mib->counters, 0, dev->mib_cnt * sizeof(u64)); 416 } 417 418 static enum dsa_tag_protocol ksz9477_get_tag_protocol(struct dsa_switch *ds, 419 int port, 420 enum dsa_tag_protocol mp) 421 { 422 enum dsa_tag_protocol proto = DSA_TAG_PROTO_KSZ9477; 423 struct ksz_device *dev = ds->priv; 424 425 if (dev->features & IS_9893) 426 proto = DSA_TAG_PROTO_KSZ9893; 427 return proto; 428 } 429 430 static int ksz9477_phy_read16(struct dsa_switch *ds, int addr, int reg) 431 { 432 struct ksz_device *dev = ds->priv; 433 u16 val = 0xffff; 434 435 /* No real PHY after this. Simulate the PHY. 436 * A fixed PHY can be setup in the device tree, but this function is 437 * still called for that port during initialization. 438 * For RGMII PHY there is no way to access it so the fixed PHY should 439 * be used. For SGMII PHY the supporting code will be added later. 440 */ 441 if (addr >= dev->phy_port_cnt) { 442 struct ksz_port *p = &dev->ports[addr]; 443 444 switch (reg) { 445 case MII_BMCR: 446 val = 0x1140; 447 break; 448 case MII_BMSR: 449 val = 0x796d; 450 break; 451 case MII_PHYSID1: 452 val = 0x0022; 453 break; 454 case MII_PHYSID2: 455 val = 0x1631; 456 break; 457 case MII_ADVERTISE: 458 val = 0x05e1; 459 break; 460 case MII_LPA: 461 val = 0xc5e1; 462 break; 463 case MII_CTRL1000: 464 val = 0x0700; 465 break; 466 case MII_STAT1000: 467 if (p->phydev.speed == SPEED_1000) 468 val = 0x3800; 469 else 470 val = 0; 471 break; 472 } 473 } else { 474 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val); 475 } 476 477 return val; 478 } 479 480 static int ksz9477_phy_write16(struct dsa_switch *ds, int addr, int reg, 481 u16 val) 482 { 483 struct ksz_device *dev = ds->priv; 484 485 /* No real PHY after this. */ 486 if (addr >= dev->phy_port_cnt) 487 return 0; 488 489 /* No gigabit support. Do not write to this register. */ 490 if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000) 491 return 0; 492 ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val); 493 494 return 0; 495 } 496 497 static void ksz9477_get_strings(struct dsa_switch *ds, int port, 498 u32 stringset, uint8_t *buf) 499 { 500 int i; 501 502 if (stringset != ETH_SS_STATS) 503 return; 504 505 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) { 506 memcpy(buf + i * ETH_GSTRING_LEN, ksz9477_mib_names[i].string, 507 ETH_GSTRING_LEN); 508 } 509 } 510 511 static void ksz9477_cfg_port_member(struct ksz_device *dev, int port, 512 u8 member) 513 { 514 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member); 515 } 516 517 static void ksz9477_port_stp_state_set(struct dsa_switch *ds, int port, 518 u8 state) 519 { 520 struct ksz_device *dev = ds->priv; 521 struct ksz_port *p = &dev->ports[port]; 522 u8 data; 523 524 ksz_pread8(dev, port, P_STP_CTRL, &data); 525 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 526 527 switch (state) { 528 case BR_STATE_DISABLED: 529 data |= PORT_LEARN_DISABLE; 530 break; 531 case BR_STATE_LISTENING: 532 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 533 break; 534 case BR_STATE_LEARNING: 535 data |= PORT_RX_ENABLE; 536 break; 537 case BR_STATE_FORWARDING: 538 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 539 break; 540 case BR_STATE_BLOCKING: 541 data |= PORT_LEARN_DISABLE; 542 break; 543 default: 544 dev_err(ds->dev, "invalid STP state: %d\n", state); 545 return; 546 } 547 548 ksz_pwrite8(dev, port, P_STP_CTRL, data); 549 p->stp_state = state; 550 551 ksz_update_port_member(dev, port); 552 } 553 554 static void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port) 555 { 556 u8 data; 557 558 regmap_update_bits(dev->regmap[0], REG_SW_LUE_CTRL_2, 559 SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S, 560 SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S); 561 562 if (port < dev->port_cnt) { 563 /* flush individual port */ 564 ksz_pread8(dev, port, P_STP_CTRL, &data); 565 if (!(data & PORT_LEARN_DISABLE)) 566 ksz_pwrite8(dev, port, P_STP_CTRL, 567 data | PORT_LEARN_DISABLE); 568 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 569 ksz_pwrite8(dev, port, P_STP_CTRL, data); 570 } else { 571 /* flush all */ 572 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true); 573 } 574 } 575 576 static int ksz9477_port_vlan_filtering(struct dsa_switch *ds, int port, 577 bool flag, 578 struct netlink_ext_ack *extack) 579 { 580 struct ksz_device *dev = ds->priv; 581 582 if (flag) { 583 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 584 PORT_VLAN_LOOKUP_VID_0, true); 585 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true); 586 } else { 587 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false); 588 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 589 PORT_VLAN_LOOKUP_VID_0, false); 590 } 591 592 return 0; 593 } 594 595 static int ksz9477_port_vlan_add(struct dsa_switch *ds, int port, 596 const struct switchdev_obj_port_vlan *vlan, 597 struct netlink_ext_ack *extack) 598 { 599 struct ksz_device *dev = ds->priv; 600 u32 vlan_table[3]; 601 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 602 int err; 603 604 err = ksz9477_get_vlan_table(dev, vlan->vid, vlan_table); 605 if (err) { 606 NL_SET_ERR_MSG_MOD(extack, "Failed to get vlan table"); 607 return err; 608 } 609 610 vlan_table[0] = VLAN_VALID | (vlan->vid & VLAN_FID_M); 611 if (untagged) 612 vlan_table[1] |= BIT(port); 613 else 614 vlan_table[1] &= ~BIT(port); 615 vlan_table[1] &= ~(BIT(dev->cpu_port)); 616 617 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port); 618 619 err = ksz9477_set_vlan_table(dev, vlan->vid, vlan_table); 620 if (err) { 621 NL_SET_ERR_MSG_MOD(extack, "Failed to set vlan table"); 622 return err; 623 } 624 625 /* change PVID */ 626 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 627 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vlan->vid); 628 629 return 0; 630 } 631 632 static int ksz9477_port_vlan_del(struct dsa_switch *ds, int port, 633 const struct switchdev_obj_port_vlan *vlan) 634 { 635 struct ksz_device *dev = ds->priv; 636 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 637 u32 vlan_table[3]; 638 u16 pvid; 639 640 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid); 641 pvid = pvid & 0xFFF; 642 643 if (ksz9477_get_vlan_table(dev, vlan->vid, vlan_table)) { 644 dev_dbg(dev->dev, "Failed to get vlan table\n"); 645 return -ETIMEDOUT; 646 } 647 648 vlan_table[2] &= ~BIT(port); 649 650 if (pvid == vlan->vid) 651 pvid = 1; 652 653 if (untagged) 654 vlan_table[1] &= ~BIT(port); 655 656 if (ksz9477_set_vlan_table(dev, vlan->vid, vlan_table)) { 657 dev_dbg(dev->dev, "Failed to set vlan table\n"); 658 return -ETIMEDOUT; 659 } 660 661 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid); 662 663 return 0; 664 } 665 666 static int ksz9477_port_fdb_add(struct dsa_switch *ds, int port, 667 const unsigned char *addr, u16 vid, 668 struct dsa_db db) 669 { 670 struct ksz_device *dev = ds->priv; 671 u32 alu_table[4]; 672 u32 data; 673 int ret = 0; 674 675 mutex_lock(&dev->alu_mutex); 676 677 /* find any entry with mac & vid */ 678 data = vid << ALU_FID_INDEX_S; 679 data |= ((addr[0] << 8) | addr[1]); 680 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 681 682 data = ((addr[2] << 24) | (addr[3] << 16)); 683 data |= ((addr[4] << 8) | addr[5]); 684 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 685 686 /* start read operation */ 687 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 688 689 /* wait to be finished */ 690 ret = ksz9477_wait_alu_ready(dev); 691 if (ret) { 692 dev_dbg(dev->dev, "Failed to read ALU\n"); 693 goto exit; 694 } 695 696 /* read ALU entry */ 697 ksz9477_read_table(dev, alu_table); 698 699 /* update ALU entry */ 700 alu_table[0] = ALU_V_STATIC_VALID; 701 alu_table[1] |= BIT(port); 702 if (vid) 703 alu_table[1] |= ALU_V_USE_FID; 704 alu_table[2] = (vid << ALU_V_FID_S); 705 alu_table[2] |= ((addr[0] << 8) | addr[1]); 706 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16)); 707 alu_table[3] |= ((addr[4] << 8) | addr[5]); 708 709 ksz9477_write_table(dev, alu_table); 710 711 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 712 713 /* wait to be finished */ 714 ret = ksz9477_wait_alu_ready(dev); 715 if (ret) 716 dev_dbg(dev->dev, "Failed to write ALU\n"); 717 718 exit: 719 mutex_unlock(&dev->alu_mutex); 720 721 return ret; 722 } 723 724 static int ksz9477_port_fdb_del(struct dsa_switch *ds, int port, 725 const unsigned char *addr, u16 vid, 726 struct dsa_db db) 727 { 728 struct ksz_device *dev = ds->priv; 729 u32 alu_table[4]; 730 u32 data; 731 int ret = 0; 732 733 mutex_lock(&dev->alu_mutex); 734 735 /* read any entry with mac & vid */ 736 data = vid << ALU_FID_INDEX_S; 737 data |= ((addr[0] << 8) | addr[1]); 738 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 739 740 data = ((addr[2] << 24) | (addr[3] << 16)); 741 data |= ((addr[4] << 8) | addr[5]); 742 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 743 744 /* start read operation */ 745 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 746 747 /* wait to be finished */ 748 ret = ksz9477_wait_alu_ready(dev); 749 if (ret) { 750 dev_dbg(dev->dev, "Failed to read ALU\n"); 751 goto exit; 752 } 753 754 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]); 755 if (alu_table[0] & ALU_V_STATIC_VALID) { 756 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]); 757 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]); 758 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]); 759 760 /* clear forwarding port */ 761 alu_table[2] &= ~BIT(port); 762 763 /* if there is no port to forward, clear table */ 764 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) { 765 alu_table[0] = 0; 766 alu_table[1] = 0; 767 alu_table[2] = 0; 768 alu_table[3] = 0; 769 } 770 } else { 771 alu_table[0] = 0; 772 alu_table[1] = 0; 773 alu_table[2] = 0; 774 alu_table[3] = 0; 775 } 776 777 ksz9477_write_table(dev, alu_table); 778 779 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 780 781 /* wait to be finished */ 782 ret = ksz9477_wait_alu_ready(dev); 783 if (ret) 784 dev_dbg(dev->dev, "Failed to write ALU\n"); 785 786 exit: 787 mutex_unlock(&dev->alu_mutex); 788 789 return ret; 790 } 791 792 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table) 793 { 794 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID); 795 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER); 796 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER); 797 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) & 798 ALU_V_PRIO_AGE_CNT_M; 799 alu->mstp = alu_table[0] & ALU_V_MSTP_M; 800 801 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE); 802 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID); 803 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP; 804 805 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M; 806 807 alu->mac[0] = (alu_table[2] >> 8) & 0xFF; 808 alu->mac[1] = alu_table[2] & 0xFF; 809 alu->mac[2] = (alu_table[3] >> 24) & 0xFF; 810 alu->mac[3] = (alu_table[3] >> 16) & 0xFF; 811 alu->mac[4] = (alu_table[3] >> 8) & 0xFF; 812 alu->mac[5] = alu_table[3] & 0xFF; 813 } 814 815 static int ksz9477_port_fdb_dump(struct dsa_switch *ds, int port, 816 dsa_fdb_dump_cb_t *cb, void *data) 817 { 818 struct ksz_device *dev = ds->priv; 819 int ret = 0; 820 u32 ksz_data; 821 u32 alu_table[4]; 822 struct alu_struct alu; 823 int timeout; 824 825 mutex_lock(&dev->alu_mutex); 826 827 /* start ALU search */ 828 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH); 829 830 do { 831 timeout = 1000; 832 do { 833 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data); 834 if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START)) 835 break; 836 usleep_range(1, 10); 837 } while (timeout-- > 0); 838 839 if (!timeout) { 840 dev_dbg(dev->dev, "Failed to search ALU\n"); 841 ret = -ETIMEDOUT; 842 goto exit; 843 } 844 845 /* read ALU table */ 846 ksz9477_read_table(dev, alu_table); 847 848 ksz9477_convert_alu(&alu, alu_table); 849 850 if (alu.port_forward & BIT(port)) { 851 ret = cb(alu.mac, alu.fid, alu.is_static, data); 852 if (ret) 853 goto exit; 854 } 855 } while (ksz_data & ALU_START); 856 857 exit: 858 859 /* stop ALU search */ 860 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0); 861 862 mutex_unlock(&dev->alu_mutex); 863 864 return ret; 865 } 866 867 static int ksz9477_port_mdb_add(struct dsa_switch *ds, int port, 868 const struct switchdev_obj_port_mdb *mdb, 869 struct dsa_db db) 870 { 871 struct ksz_device *dev = ds->priv; 872 u32 static_table[4]; 873 u32 data; 874 int index; 875 u32 mac_hi, mac_lo; 876 int err = 0; 877 878 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 879 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 880 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 881 882 mutex_lock(&dev->alu_mutex); 883 884 for (index = 0; index < dev->num_statics; index++) { 885 /* find empty slot first */ 886 data = (index << ALU_STAT_INDEX_S) | 887 ALU_STAT_READ | ALU_STAT_START; 888 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 889 890 /* wait to be finished */ 891 err = ksz9477_wait_alu_sta_ready(dev); 892 if (err) { 893 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 894 goto exit; 895 } 896 897 /* read ALU static table */ 898 ksz9477_read_table(dev, static_table); 899 900 if (static_table[0] & ALU_V_STATIC_VALID) { 901 /* check this has same vid & mac address */ 902 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 903 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 904 static_table[3] == mac_lo) { 905 /* found matching one */ 906 break; 907 } 908 } else { 909 /* found empty one */ 910 break; 911 } 912 } 913 914 /* no available entry */ 915 if (index == dev->num_statics) { 916 err = -ENOSPC; 917 goto exit; 918 } 919 920 /* add entry */ 921 static_table[0] = ALU_V_STATIC_VALID; 922 static_table[1] |= BIT(port); 923 if (mdb->vid) 924 static_table[1] |= ALU_V_USE_FID; 925 static_table[2] = (mdb->vid << ALU_V_FID_S); 926 static_table[2] |= mac_hi; 927 static_table[3] = mac_lo; 928 929 ksz9477_write_table(dev, static_table); 930 931 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 932 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 933 934 /* wait to be finished */ 935 if (ksz9477_wait_alu_sta_ready(dev)) 936 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 937 938 exit: 939 mutex_unlock(&dev->alu_mutex); 940 return err; 941 } 942 943 static int ksz9477_port_mdb_del(struct dsa_switch *ds, int port, 944 const struct switchdev_obj_port_mdb *mdb, 945 struct dsa_db db) 946 { 947 struct ksz_device *dev = ds->priv; 948 u32 static_table[4]; 949 u32 data; 950 int index; 951 int ret = 0; 952 u32 mac_hi, mac_lo; 953 954 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 955 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 956 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 957 958 mutex_lock(&dev->alu_mutex); 959 960 for (index = 0; index < dev->num_statics; index++) { 961 /* find empty slot first */ 962 data = (index << ALU_STAT_INDEX_S) | 963 ALU_STAT_READ | ALU_STAT_START; 964 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 965 966 /* wait to be finished */ 967 ret = ksz9477_wait_alu_sta_ready(dev); 968 if (ret) { 969 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 970 goto exit; 971 } 972 973 /* read ALU static table */ 974 ksz9477_read_table(dev, static_table); 975 976 if (static_table[0] & ALU_V_STATIC_VALID) { 977 /* check this has same vid & mac address */ 978 979 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 980 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 981 static_table[3] == mac_lo) { 982 /* found matching one */ 983 break; 984 } 985 } 986 } 987 988 /* no available entry */ 989 if (index == dev->num_statics) 990 goto exit; 991 992 /* clear port */ 993 static_table[1] &= ~BIT(port); 994 995 if ((static_table[1] & ALU_V_PORT_MAP) == 0) { 996 /* delete entry */ 997 static_table[0] = 0; 998 static_table[1] = 0; 999 static_table[2] = 0; 1000 static_table[3] = 0; 1001 } 1002 1003 ksz9477_write_table(dev, static_table); 1004 1005 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 1006 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 1007 1008 /* wait to be finished */ 1009 ret = ksz9477_wait_alu_sta_ready(dev); 1010 if (ret) 1011 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 1012 1013 exit: 1014 mutex_unlock(&dev->alu_mutex); 1015 1016 return ret; 1017 } 1018 1019 static int ksz9477_port_mirror_add(struct dsa_switch *ds, int port, 1020 struct dsa_mall_mirror_tc_entry *mirror, 1021 bool ingress, struct netlink_ext_ack *extack) 1022 { 1023 struct ksz_device *dev = ds->priv; 1024 1025 if (ingress) 1026 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 1027 else 1028 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 1029 1030 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false); 1031 1032 /* configure mirror port */ 1033 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1034 PORT_MIRROR_SNIFFER, true); 1035 1036 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 1037 1038 return 0; 1039 } 1040 1041 static void ksz9477_port_mirror_del(struct dsa_switch *ds, int port, 1042 struct dsa_mall_mirror_tc_entry *mirror) 1043 { 1044 struct ksz_device *dev = ds->priv; 1045 u8 data; 1046 1047 if (mirror->ingress) 1048 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 1049 else 1050 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 1051 1052 ksz_pread8(dev, port, P_MIRROR_CTRL, &data); 1053 1054 if (!(data & (PORT_MIRROR_RX | PORT_MIRROR_TX))) 1055 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1056 PORT_MIRROR_SNIFFER, false); 1057 } 1058 1059 static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data) 1060 { 1061 bool gbit; 1062 1063 if (dev->features & NEW_XMII) 1064 gbit = !(data & PORT_MII_NOT_1GBIT); 1065 else 1066 gbit = !!(data & PORT_MII_1000MBIT_S1); 1067 return gbit; 1068 } 1069 1070 static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data) 1071 { 1072 if (dev->features & NEW_XMII) { 1073 if (gbit) 1074 *data &= ~PORT_MII_NOT_1GBIT; 1075 else 1076 *data |= PORT_MII_NOT_1GBIT; 1077 } else { 1078 if (gbit) 1079 *data |= PORT_MII_1000MBIT_S1; 1080 else 1081 *data &= ~PORT_MII_1000MBIT_S1; 1082 } 1083 } 1084 1085 static int ksz9477_get_xmii(struct ksz_device *dev, u8 data) 1086 { 1087 int mode; 1088 1089 if (dev->features & NEW_XMII) { 1090 switch (data & PORT_MII_SEL_M) { 1091 case PORT_MII_SEL: 1092 mode = 0; 1093 break; 1094 case PORT_RMII_SEL: 1095 mode = 1; 1096 break; 1097 case PORT_GMII_SEL: 1098 mode = 2; 1099 break; 1100 default: 1101 mode = 3; 1102 } 1103 } else { 1104 switch (data & PORT_MII_SEL_M) { 1105 case PORT_MII_SEL_S1: 1106 mode = 0; 1107 break; 1108 case PORT_RMII_SEL_S1: 1109 mode = 1; 1110 break; 1111 case PORT_GMII_SEL_S1: 1112 mode = 2; 1113 break; 1114 default: 1115 mode = 3; 1116 } 1117 } 1118 return mode; 1119 } 1120 1121 static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data) 1122 { 1123 u8 xmii; 1124 1125 if (dev->features & NEW_XMII) { 1126 switch (mode) { 1127 case 0: 1128 xmii = PORT_MII_SEL; 1129 break; 1130 case 1: 1131 xmii = PORT_RMII_SEL; 1132 break; 1133 case 2: 1134 xmii = PORT_GMII_SEL; 1135 break; 1136 default: 1137 xmii = PORT_RGMII_SEL; 1138 break; 1139 } 1140 } else { 1141 switch (mode) { 1142 case 0: 1143 xmii = PORT_MII_SEL_S1; 1144 break; 1145 case 1: 1146 xmii = PORT_RMII_SEL_S1; 1147 break; 1148 case 2: 1149 xmii = PORT_GMII_SEL_S1; 1150 break; 1151 default: 1152 xmii = PORT_RGMII_SEL_S1; 1153 break; 1154 } 1155 } 1156 *data &= ~PORT_MII_SEL_M; 1157 *data |= xmii; 1158 } 1159 1160 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port) 1161 { 1162 phy_interface_t interface; 1163 bool gbit; 1164 int mode; 1165 u8 data8; 1166 1167 if (port < dev->phy_port_cnt) 1168 return PHY_INTERFACE_MODE_NA; 1169 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 1170 gbit = ksz9477_get_gbit(dev, data8); 1171 mode = ksz9477_get_xmii(dev, data8); 1172 switch (mode) { 1173 case 2: 1174 interface = PHY_INTERFACE_MODE_GMII; 1175 if (gbit) 1176 break; 1177 fallthrough; 1178 case 0: 1179 interface = PHY_INTERFACE_MODE_MII; 1180 break; 1181 case 1: 1182 interface = PHY_INTERFACE_MODE_RMII; 1183 break; 1184 default: 1185 interface = PHY_INTERFACE_MODE_RGMII; 1186 if (data8 & PORT_RGMII_ID_EG_ENABLE) 1187 interface = PHY_INTERFACE_MODE_RGMII_TXID; 1188 if (data8 & PORT_RGMII_ID_IG_ENABLE) { 1189 interface = PHY_INTERFACE_MODE_RGMII_RXID; 1190 if (data8 & PORT_RGMII_ID_EG_ENABLE) 1191 interface = PHY_INTERFACE_MODE_RGMII_ID; 1192 } 1193 break; 1194 } 1195 return interface; 1196 } 1197 1198 static void ksz9477_port_mmd_write(struct ksz_device *dev, int port, 1199 u8 dev_addr, u16 reg_addr, u16 val) 1200 { 1201 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 1202 MMD_SETUP(PORT_MMD_OP_INDEX, dev_addr)); 1203 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg_addr); 1204 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 1205 MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, dev_addr)); 1206 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val); 1207 } 1208 1209 static void ksz9477_phy_errata_setup(struct ksz_device *dev, int port) 1210 { 1211 /* Apply PHY settings to address errata listed in 1212 * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565 1213 * Silicon Errata and Data Sheet Clarification documents: 1214 * 1215 * Register settings are needed to improve PHY receive performance 1216 */ 1217 ksz9477_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b); 1218 ksz9477_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032); 1219 ksz9477_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c); 1220 ksz9477_port_mmd_write(dev, port, 0x01, 0x75, 0x0060); 1221 ksz9477_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777); 1222 ksz9477_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008); 1223 ksz9477_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001); 1224 1225 /* Transmit waveform amplitude can be improved 1226 * (1000BASE-T, 100BASE-TX, 10BASE-Te) 1227 */ 1228 ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0); 1229 1230 /* Energy Efficient Ethernet (EEE) feature select must 1231 * be manually disabled (except on KSZ8565 which is 100Mbit) 1232 */ 1233 if (dev->features & GBIT_SUPPORT) 1234 ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000); 1235 1236 /* Register settings are required to meet data sheet 1237 * supply current specifications 1238 */ 1239 ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff); 1240 ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff); 1241 ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff); 1242 ksz9477_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff); 1243 ksz9477_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff); 1244 ksz9477_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff); 1245 ksz9477_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff); 1246 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff); 1247 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff); 1248 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff); 1249 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff); 1250 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff); 1251 ksz9477_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee); 1252 } 1253 1254 static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1255 { 1256 struct ksz_port *p = &dev->ports[port]; 1257 struct dsa_switch *ds = dev->ds; 1258 u8 data8, member; 1259 u16 data16; 1260 1261 /* enable tag tail for host port */ 1262 if (cpu_port) 1263 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE, 1264 true); 1265 1266 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false); 1267 1268 /* set back pressure */ 1269 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true); 1270 1271 /* enable broadcast storm limit */ 1272 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 1273 1274 /* disable DiffServ priority */ 1275 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false); 1276 1277 /* replace priority */ 1278 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING, 1279 false); 1280 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4, 1281 MTI_PVID_REPLACE, false); 1282 1283 /* enable 802.1p priority */ 1284 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); 1285 1286 if (port < dev->phy_port_cnt) { 1287 /* do not force flow control */ 1288 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1289 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1290 false); 1291 1292 if (dev->phy_errata_9477) 1293 ksz9477_phy_errata_setup(dev, port); 1294 } else { 1295 /* force flow control */ 1296 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1297 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1298 true); 1299 1300 /* configure MAC to 1G & RGMII mode */ 1301 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 1302 switch (p->interface) { 1303 case PHY_INTERFACE_MODE_MII: 1304 ksz9477_set_xmii(dev, 0, &data8); 1305 ksz9477_set_gbit(dev, false, &data8); 1306 p->phydev.speed = SPEED_100; 1307 break; 1308 case PHY_INTERFACE_MODE_RMII: 1309 ksz9477_set_xmii(dev, 1, &data8); 1310 ksz9477_set_gbit(dev, false, &data8); 1311 p->phydev.speed = SPEED_100; 1312 break; 1313 case PHY_INTERFACE_MODE_GMII: 1314 ksz9477_set_xmii(dev, 2, &data8); 1315 ksz9477_set_gbit(dev, true, &data8); 1316 p->phydev.speed = SPEED_1000; 1317 break; 1318 default: 1319 ksz9477_set_xmii(dev, 3, &data8); 1320 ksz9477_set_gbit(dev, true, &data8); 1321 data8 &= ~PORT_RGMII_ID_IG_ENABLE; 1322 data8 &= ~PORT_RGMII_ID_EG_ENABLE; 1323 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1324 p->interface == PHY_INTERFACE_MODE_RGMII_RXID) 1325 data8 |= PORT_RGMII_ID_IG_ENABLE; 1326 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1327 p->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1328 data8 |= PORT_RGMII_ID_EG_ENABLE; 1329 /* On KSZ9893, disable RGMII in-band status support */ 1330 if (dev->features & IS_9893) 1331 data8 &= ~PORT_MII_MAC_MODE; 1332 p->phydev.speed = SPEED_1000; 1333 break; 1334 } 1335 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8); 1336 p->phydev.duplex = 1; 1337 } 1338 1339 if (cpu_port) 1340 member = dsa_user_ports(ds); 1341 else 1342 member = BIT(dsa_upstream_port(ds, port)); 1343 1344 ksz9477_cfg_port_member(dev, port, member); 1345 1346 /* clear pending interrupts */ 1347 if (port < dev->phy_port_cnt) 1348 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16); 1349 } 1350 1351 static void ksz9477_config_cpu_port(struct dsa_switch *ds) 1352 { 1353 struct ksz_device *dev = ds->priv; 1354 struct ksz_port *p; 1355 int i; 1356 1357 for (i = 0; i < dev->port_cnt; i++) { 1358 if (dsa_is_cpu_port(ds, i) && (dev->cpu_ports & (1 << i))) { 1359 phy_interface_t interface; 1360 const char *prev_msg; 1361 const char *prev_mode; 1362 1363 dev->cpu_port = i; 1364 p = &dev->ports[i]; 1365 1366 /* Read from XMII register to determine host port 1367 * interface. If set specifically in device tree 1368 * note the difference to help debugging. 1369 */ 1370 interface = ksz9477_get_interface(dev, i); 1371 if (!p->interface) { 1372 if (dev->compat_interface) { 1373 dev_warn(dev->dev, 1374 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 1375 "Please update your device tree.\n", 1376 i); 1377 p->interface = dev->compat_interface; 1378 } else { 1379 p->interface = interface; 1380 } 1381 } 1382 if (interface && interface != p->interface) { 1383 prev_msg = " instead of "; 1384 prev_mode = phy_modes(interface); 1385 } else { 1386 prev_msg = ""; 1387 prev_mode = ""; 1388 } 1389 dev_info(dev->dev, 1390 "Port%d: using phy mode %s%s%s\n", 1391 i, 1392 phy_modes(p->interface), 1393 prev_msg, 1394 prev_mode); 1395 1396 /* enable cpu port */ 1397 ksz9477_port_setup(dev, i, true); 1398 p->on = 1; 1399 } 1400 } 1401 1402 for (i = 0; i < dev->port_cnt; i++) { 1403 if (i == dev->cpu_port) 1404 continue; 1405 p = &dev->ports[i]; 1406 1407 ksz9477_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1408 p->on = 1; 1409 if (i < dev->phy_port_cnt) 1410 p->phy = 1; 1411 if (dev->chip_id == 0x00947700 && i == 6) { 1412 p->sgmii = 1; 1413 1414 /* SGMII PHY detection code is not implemented yet. */ 1415 p->phy = 0; 1416 } 1417 } 1418 } 1419 1420 static int ksz9477_setup(struct dsa_switch *ds) 1421 { 1422 struct ksz_device *dev = ds->priv; 1423 int ret = 0; 1424 1425 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 1426 dev->num_vlans, GFP_KERNEL); 1427 if (!dev->vlan_cache) 1428 return -ENOMEM; 1429 1430 ret = ksz9477_reset_switch(dev); 1431 if (ret) { 1432 dev_err(ds->dev, "failed to reset switch\n"); 1433 return ret; 1434 } 1435 1436 /* Required for port partitioning. */ 1437 ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, 1438 true); 1439 1440 /* Do not work correctly with tail tagging. */ 1441 ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false); 1442 1443 /* Enable REG_SW_MTU__2 reg by setting SW_JUMBO_PACKET */ 1444 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_JUMBO_PACKET, true); 1445 1446 /* Now we can configure default MTU value */ 1447 ret = regmap_update_bits(dev->regmap[1], REG_SW_MTU__2, REG_SW_MTU_MASK, 1448 VLAN_ETH_FRAME_LEN + ETH_FCS_LEN); 1449 if (ret) 1450 return ret; 1451 1452 ksz9477_config_cpu_port(ds); 1453 1454 ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true); 1455 1456 /* queue based egress rate limit */ 1457 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true); 1458 1459 /* enable global MIB counter freeze function */ 1460 ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); 1461 1462 /* start switch */ 1463 ksz_cfg(dev, REG_SW_OPERATION, SW_START, true); 1464 1465 ksz_init_mib_timer(dev); 1466 1467 ds->configure_vlan_while_not_filtering = false; 1468 1469 return 0; 1470 } 1471 1472 static const struct dsa_switch_ops ksz9477_switch_ops = { 1473 .get_tag_protocol = ksz9477_get_tag_protocol, 1474 .setup = ksz9477_setup, 1475 .phy_read = ksz9477_phy_read16, 1476 .phy_write = ksz9477_phy_write16, 1477 .phylink_mac_link_down = ksz_mac_link_down, 1478 .port_enable = ksz_enable_port, 1479 .get_strings = ksz9477_get_strings, 1480 .get_ethtool_stats = ksz_get_ethtool_stats, 1481 .get_sset_count = ksz_sset_count, 1482 .port_bridge_join = ksz_port_bridge_join, 1483 .port_bridge_leave = ksz_port_bridge_leave, 1484 .port_stp_state_set = ksz9477_port_stp_state_set, 1485 .port_fast_age = ksz_port_fast_age, 1486 .port_vlan_filtering = ksz9477_port_vlan_filtering, 1487 .port_vlan_add = ksz9477_port_vlan_add, 1488 .port_vlan_del = ksz9477_port_vlan_del, 1489 .port_fdb_dump = ksz9477_port_fdb_dump, 1490 .port_fdb_add = ksz9477_port_fdb_add, 1491 .port_fdb_del = ksz9477_port_fdb_del, 1492 .port_mdb_add = ksz9477_port_mdb_add, 1493 .port_mdb_del = ksz9477_port_mdb_del, 1494 .port_mirror_add = ksz9477_port_mirror_add, 1495 .port_mirror_del = ksz9477_port_mirror_del, 1496 .get_stats64 = ksz9477_get_stats64, 1497 .port_change_mtu = ksz9477_change_mtu, 1498 .port_max_mtu = ksz9477_max_mtu, 1499 }; 1500 1501 static u32 ksz9477_get_port_addr(int port, int offset) 1502 { 1503 return PORT_CTRL_ADDR(port, offset); 1504 } 1505 1506 static int ksz9477_switch_detect(struct ksz_device *dev) 1507 { 1508 u8 data8; 1509 u8 id_hi; 1510 u8 id_lo; 1511 u32 id32; 1512 int ret; 1513 1514 /* turn off SPI DO Edge select */ 1515 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 1516 if (ret) 1517 return ret; 1518 1519 data8 &= ~SPI_AUTO_EDGE_DETECTION; 1520 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 1521 if (ret) 1522 return ret; 1523 1524 /* read chip id */ 1525 ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32); 1526 if (ret) 1527 return ret; 1528 ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8); 1529 if (ret) 1530 return ret; 1531 1532 /* Number of ports can be reduced depending on chip. */ 1533 dev->phy_port_cnt = 5; 1534 1535 /* Default capability is gigabit capable. */ 1536 dev->features = GBIT_SUPPORT; 1537 1538 dev_dbg(dev->dev, "Switch detect: ID=%08x%02x\n", id32, data8); 1539 id_hi = (u8)(id32 >> 16); 1540 id_lo = (u8)(id32 >> 8); 1541 if ((id_lo & 0xf) == 3) { 1542 /* Chip is from KSZ9893 design. */ 1543 dev_info(dev->dev, "Found KSZ9893\n"); 1544 dev->features |= IS_9893; 1545 1546 /* Chip does not support gigabit. */ 1547 if (data8 & SW_QW_ABLE) 1548 dev->features &= ~GBIT_SUPPORT; 1549 dev->phy_port_cnt = 2; 1550 } else { 1551 dev_info(dev->dev, "Found KSZ9477 or compatible\n"); 1552 /* Chip uses new XMII register definitions. */ 1553 dev->features |= NEW_XMII; 1554 1555 /* Chip does not support gigabit. */ 1556 if (!(data8 & SW_GIGABIT_ABLE)) 1557 dev->features &= ~GBIT_SUPPORT; 1558 } 1559 1560 /* Change chip id to known ones so it can be matched against them. */ 1561 id32 = (id_hi << 16) | (id_lo << 8); 1562 1563 dev->chip_id = id32; 1564 1565 return 0; 1566 } 1567 1568 struct ksz_chip_data { 1569 u32 chip_id; 1570 const char *dev_name; 1571 int num_vlans; 1572 int num_alus; 1573 int num_statics; 1574 int cpu_ports; 1575 int port_cnt; 1576 bool phy_errata_9477; 1577 }; 1578 1579 static const struct ksz_chip_data ksz9477_switch_chips[] = { 1580 { 1581 .chip_id = 0x00947700, 1582 .dev_name = "KSZ9477", 1583 .num_vlans = 4096, 1584 .num_alus = 4096, 1585 .num_statics = 16, 1586 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1587 .port_cnt = 7, /* total physical port count */ 1588 .phy_errata_9477 = true, 1589 }, 1590 { 1591 .chip_id = 0x00989700, 1592 .dev_name = "KSZ9897", 1593 .num_vlans = 4096, 1594 .num_alus = 4096, 1595 .num_statics = 16, 1596 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1597 .port_cnt = 7, /* total physical port count */ 1598 .phy_errata_9477 = true, 1599 }, 1600 { 1601 .chip_id = 0x00989300, 1602 .dev_name = "KSZ9893", 1603 .num_vlans = 4096, 1604 .num_alus = 4096, 1605 .num_statics = 16, 1606 .cpu_ports = 0x07, /* can be configured as cpu port */ 1607 .port_cnt = 3, /* total port count */ 1608 }, 1609 { 1610 .chip_id = 0x00956700, 1611 .dev_name = "KSZ9567", 1612 .num_vlans = 4096, 1613 .num_alus = 4096, 1614 .num_statics = 16, 1615 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1616 .port_cnt = 7, /* total physical port count */ 1617 .phy_errata_9477 = true, 1618 }, 1619 }; 1620 1621 static int ksz9477_switch_init(struct ksz_device *dev) 1622 { 1623 int i; 1624 1625 dev->ds->ops = &ksz9477_switch_ops; 1626 1627 for (i = 0; i < ARRAY_SIZE(ksz9477_switch_chips); i++) { 1628 const struct ksz_chip_data *chip = &ksz9477_switch_chips[i]; 1629 1630 if (dev->chip_id == chip->chip_id) { 1631 dev->name = chip->dev_name; 1632 dev->num_vlans = chip->num_vlans; 1633 dev->num_alus = chip->num_alus; 1634 dev->num_statics = chip->num_statics; 1635 dev->port_cnt = chip->port_cnt; 1636 dev->cpu_ports = chip->cpu_ports; 1637 dev->phy_errata_9477 = chip->phy_errata_9477; 1638 1639 break; 1640 } 1641 } 1642 1643 /* no switch found */ 1644 if (!dev->port_cnt) 1645 return -ENODEV; 1646 1647 dev->port_mask = (1 << dev->port_cnt) - 1; 1648 1649 dev->reg_mib_cnt = SWITCH_COUNTER_NUM; 1650 dev->mib_cnt = TOTAL_SWITCH_COUNTER_NUM; 1651 1652 dev->ports = devm_kzalloc(dev->dev, 1653 dev->port_cnt * sizeof(struct ksz_port), 1654 GFP_KERNEL); 1655 if (!dev->ports) 1656 return -ENOMEM; 1657 for (i = 0; i < dev->port_cnt; i++) { 1658 spin_lock_init(&dev->ports[i].mib.stats64_lock); 1659 mutex_init(&dev->ports[i].mib.cnt_mutex); 1660 dev->ports[i].mib.counters = 1661 devm_kzalloc(dev->dev, 1662 sizeof(u64) * 1663 (TOTAL_SWITCH_COUNTER_NUM + 1), 1664 GFP_KERNEL); 1665 if (!dev->ports[i].mib.counters) 1666 return -ENOMEM; 1667 } 1668 1669 /* set the real number of ports */ 1670 dev->ds->num_ports = dev->port_cnt; 1671 1672 return 0; 1673 } 1674 1675 static void ksz9477_switch_exit(struct ksz_device *dev) 1676 { 1677 ksz9477_reset_switch(dev); 1678 } 1679 1680 static const struct ksz_dev_ops ksz9477_dev_ops = { 1681 .get_port_addr = ksz9477_get_port_addr, 1682 .cfg_port_member = ksz9477_cfg_port_member, 1683 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 1684 .port_setup = ksz9477_port_setup, 1685 .r_mib_cnt = ksz9477_r_mib_cnt, 1686 .r_mib_pkt = ksz9477_r_mib_pkt, 1687 .r_mib_stat64 = ksz9477_r_mib_stats64, 1688 .freeze_mib = ksz9477_freeze_mib, 1689 .port_init_cnt = ksz9477_port_init_cnt, 1690 .shutdown = ksz9477_reset_switch, 1691 .detect = ksz9477_switch_detect, 1692 .init = ksz9477_switch_init, 1693 .exit = ksz9477_switch_exit, 1694 }; 1695 1696 int ksz9477_switch_register(struct ksz_device *dev) 1697 { 1698 int ret, i; 1699 struct phy_device *phydev; 1700 1701 ret = ksz_switch_register(dev, &ksz9477_dev_ops); 1702 if (ret) 1703 return ret; 1704 1705 for (i = 0; i < dev->phy_port_cnt; ++i) { 1706 if (!dsa_is_user_port(dev->ds, i)) 1707 continue; 1708 1709 phydev = dsa_to_port(dev->ds, i)->slave->phydev; 1710 1711 /* The MAC actually cannot run in 1000 half-duplex mode. */ 1712 phy_remove_link_mode(phydev, 1713 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1714 1715 /* PHY does not support gigabit. */ 1716 if (!(dev->features & GBIT_SUPPORT)) 1717 phy_remove_link_mode(phydev, 1718 ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 1719 } 1720 return ret; 1721 } 1722 EXPORT_SYMBOL(ksz9477_switch_register); 1723 1724 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 1725 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver"); 1726 MODULE_LICENSE("GPL"); 1727