1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ9477 switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/iopoll.h> 11 #include <linux/platform_data/microchip-ksz.h> 12 #include <linux/phy.h> 13 #include <linux/if_bridge.h> 14 #include <net/dsa.h> 15 #include <net/switchdev.h> 16 17 #include "ksz9477_reg.h" 18 #include "ksz_common.h" 19 20 /* Used with variable features to indicate capabilities. */ 21 #define GBIT_SUPPORT BIT(0) 22 #define NEW_XMII BIT(1) 23 #define IS_9893 BIT(2) 24 25 static const struct { 26 int index; 27 char string[ETH_GSTRING_LEN]; 28 } ksz9477_mib_names[TOTAL_SWITCH_COUNTER_NUM] = { 29 { 0x00, "rx_hi" }, 30 { 0x01, "rx_undersize" }, 31 { 0x02, "rx_fragments" }, 32 { 0x03, "rx_oversize" }, 33 { 0x04, "rx_jabbers" }, 34 { 0x05, "rx_symbol_err" }, 35 { 0x06, "rx_crc_err" }, 36 { 0x07, "rx_align_err" }, 37 { 0x08, "rx_mac_ctrl" }, 38 { 0x09, "rx_pause" }, 39 { 0x0A, "rx_bcast" }, 40 { 0x0B, "rx_mcast" }, 41 { 0x0C, "rx_ucast" }, 42 { 0x0D, "rx_64_or_less" }, 43 { 0x0E, "rx_65_127" }, 44 { 0x0F, "rx_128_255" }, 45 { 0x10, "rx_256_511" }, 46 { 0x11, "rx_512_1023" }, 47 { 0x12, "rx_1024_1522" }, 48 { 0x13, "rx_1523_2000" }, 49 { 0x14, "rx_2001" }, 50 { 0x15, "tx_hi" }, 51 { 0x16, "tx_late_col" }, 52 { 0x17, "tx_pause" }, 53 { 0x18, "tx_bcast" }, 54 { 0x19, "tx_mcast" }, 55 { 0x1A, "tx_ucast" }, 56 { 0x1B, "tx_deferred" }, 57 { 0x1C, "tx_total_col" }, 58 { 0x1D, "tx_exc_col" }, 59 { 0x1E, "tx_single_col" }, 60 { 0x1F, "tx_mult_col" }, 61 { 0x80, "rx_total" }, 62 { 0x81, "tx_total" }, 63 { 0x82, "rx_discards" }, 64 { 0x83, "tx_discards" }, 65 }; 66 67 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 68 { 69 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0); 70 } 71 72 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 73 bool set) 74 { 75 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset), 76 bits, set ? bits : 0); 77 } 78 79 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set) 80 { 81 regmap_update_bits(dev->regmap[2], addr, bits, set ? bits : 0); 82 } 83 84 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset, 85 u32 bits, bool set) 86 { 87 regmap_update_bits(dev->regmap[2], PORT_CTRL_ADDR(port, offset), 88 bits, set ? bits : 0); 89 } 90 91 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev) 92 { 93 unsigned int val; 94 95 return regmap_read_poll_timeout(dev->regmap[0], REG_SW_VLAN_CTRL, 96 val, !(val & VLAN_START), 10, 1000); 97 } 98 99 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid, 100 u32 *vlan_table) 101 { 102 int ret; 103 104 mutex_lock(&dev->vlan_mutex); 105 106 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 107 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START); 108 109 /* wait to be cleared */ 110 ret = ksz9477_wait_vlan_ctrl_ready(dev); 111 if (ret) { 112 dev_dbg(dev->dev, "Failed to read vlan table\n"); 113 goto exit; 114 } 115 116 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]); 117 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]); 118 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]); 119 120 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 121 122 exit: 123 mutex_unlock(&dev->vlan_mutex); 124 125 return ret; 126 } 127 128 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid, 129 u32 *vlan_table) 130 { 131 int ret; 132 133 mutex_lock(&dev->vlan_mutex); 134 135 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]); 136 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]); 137 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]); 138 139 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 140 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE); 141 142 /* wait to be cleared */ 143 ret = ksz9477_wait_vlan_ctrl_ready(dev); 144 if (ret) { 145 dev_dbg(dev->dev, "Failed to write vlan table\n"); 146 goto exit; 147 } 148 149 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 150 151 /* update vlan cache table */ 152 dev->vlan_cache[vid].table[0] = vlan_table[0]; 153 dev->vlan_cache[vid].table[1] = vlan_table[1]; 154 dev->vlan_cache[vid].table[2] = vlan_table[2]; 155 156 exit: 157 mutex_unlock(&dev->vlan_mutex); 158 159 return ret; 160 } 161 162 static void ksz9477_read_table(struct ksz_device *dev, u32 *table) 163 { 164 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]); 165 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]); 166 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]); 167 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]); 168 } 169 170 static void ksz9477_write_table(struct ksz_device *dev, u32 *table) 171 { 172 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]); 173 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]); 174 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]); 175 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]); 176 } 177 178 static int ksz9477_wait_alu_ready(struct ksz_device *dev) 179 { 180 unsigned int val; 181 182 return regmap_read_poll_timeout(dev->regmap[2], REG_SW_ALU_CTRL__4, 183 val, !(val & ALU_START), 10, 1000); 184 } 185 186 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev) 187 { 188 unsigned int val; 189 190 return regmap_read_poll_timeout(dev->regmap[2], 191 REG_SW_ALU_STAT_CTRL__4, 192 val, !(val & ALU_STAT_START), 193 10, 1000); 194 } 195 196 static int ksz9477_reset_switch(struct ksz_device *dev) 197 { 198 u8 data8; 199 u32 data32; 200 201 /* reset switch */ 202 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 203 204 /* turn off SPI DO Edge select */ 205 regmap_update_bits(dev->regmap[0], REG_SW_GLOBAL_SERIAL_CTRL_0, 206 SPI_AUTO_EDGE_DETECTION, 0); 207 208 /* default configuration */ 209 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8); 210 data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING | 211 SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE; 212 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8); 213 214 /* disable interrupts */ 215 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 216 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F); 217 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 218 219 /* set broadcast storm protection 10% rate */ 220 regmap_update_bits(dev->regmap[1], REG_SW_MAC_CTRL_2, 221 BROADCAST_STORM_RATE, 222 (BROADCAST_STORM_VALUE * 223 BROADCAST_STORM_PROT_RATE) / 100); 224 225 if (dev->synclko_125) 226 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, 227 SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ); 228 229 return 0; 230 } 231 232 static void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, 233 u64 *cnt) 234 { 235 struct ksz_port *p = &dev->ports[port]; 236 unsigned int val; 237 u32 data; 238 int ret; 239 240 /* retain the flush/freeze bit */ 241 data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 242 data |= MIB_COUNTER_READ; 243 data |= (addr << MIB_COUNTER_INDEX_S); 244 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data); 245 246 ret = regmap_read_poll_timeout(dev->regmap[2], 247 PORT_CTRL_ADDR(port, REG_PORT_MIB_CTRL_STAT__4), 248 val, !(val & MIB_COUNTER_READ), 10, 1000); 249 /* failed to read MIB. get out of loop */ 250 if (ret) { 251 dev_dbg(dev->dev, "Failed to get MIB\n"); 252 return; 253 } 254 255 /* count resets upon read */ 256 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data); 257 *cnt += data; 258 } 259 260 static void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 261 u64 *dropped, u64 *cnt) 262 { 263 addr = ksz9477_mib_names[addr].index; 264 ksz9477_r_mib_cnt(dev, port, addr, cnt); 265 } 266 267 static void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze) 268 { 269 u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 270 struct ksz_port *p = &dev->ports[port]; 271 272 /* enable/disable the port for flush/freeze function */ 273 mutex_lock(&p->mib.cnt_mutex); 274 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val); 275 276 /* used by MIB counter reading code to know freeze is enabled */ 277 p->freeze = freeze; 278 mutex_unlock(&p->mib.cnt_mutex); 279 } 280 281 static void ksz9477_port_init_cnt(struct ksz_device *dev, int port) 282 { 283 struct ksz_port_mib *mib = &dev->ports[port].mib; 284 285 /* flush all enabled port MIB counters */ 286 mutex_lock(&mib->cnt_mutex); 287 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 288 MIB_COUNTER_FLUSH_FREEZE); 289 ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH); 290 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0); 291 mutex_unlock(&mib->cnt_mutex); 292 293 mib->cnt_ptr = 0; 294 memset(mib->counters, 0, dev->mib_cnt * sizeof(u64)); 295 } 296 297 static enum dsa_tag_protocol ksz9477_get_tag_protocol(struct dsa_switch *ds, 298 int port, 299 enum dsa_tag_protocol mp) 300 { 301 enum dsa_tag_protocol proto = DSA_TAG_PROTO_KSZ9477; 302 struct ksz_device *dev = ds->priv; 303 304 if (dev->features & IS_9893) 305 proto = DSA_TAG_PROTO_KSZ9893; 306 return proto; 307 } 308 309 static int ksz9477_phy_read16(struct dsa_switch *ds, int addr, int reg) 310 { 311 struct ksz_device *dev = ds->priv; 312 u16 val = 0xffff; 313 314 /* No real PHY after this. Simulate the PHY. 315 * A fixed PHY can be setup in the device tree, but this function is 316 * still called for that port during initialization. 317 * For RGMII PHY there is no way to access it so the fixed PHY should 318 * be used. For SGMII PHY the supporting code will be added later. 319 */ 320 if (addr >= dev->phy_port_cnt) { 321 struct ksz_port *p = &dev->ports[addr]; 322 323 switch (reg) { 324 case MII_BMCR: 325 val = 0x1140; 326 break; 327 case MII_BMSR: 328 val = 0x796d; 329 break; 330 case MII_PHYSID1: 331 val = 0x0022; 332 break; 333 case MII_PHYSID2: 334 val = 0x1631; 335 break; 336 case MII_ADVERTISE: 337 val = 0x05e1; 338 break; 339 case MII_LPA: 340 val = 0xc5e1; 341 break; 342 case MII_CTRL1000: 343 val = 0x0700; 344 break; 345 case MII_STAT1000: 346 if (p->phydev.speed == SPEED_1000) 347 val = 0x3800; 348 else 349 val = 0; 350 break; 351 } 352 } else { 353 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val); 354 } 355 356 return val; 357 } 358 359 static int ksz9477_phy_write16(struct dsa_switch *ds, int addr, int reg, 360 u16 val) 361 { 362 struct ksz_device *dev = ds->priv; 363 364 /* No real PHY after this. */ 365 if (addr >= dev->phy_port_cnt) 366 return 0; 367 368 /* No gigabit support. Do not write to this register. */ 369 if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000) 370 return 0; 371 ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val); 372 373 return 0; 374 } 375 376 static void ksz9477_get_strings(struct dsa_switch *ds, int port, 377 u32 stringset, uint8_t *buf) 378 { 379 int i; 380 381 if (stringset != ETH_SS_STATS) 382 return; 383 384 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) { 385 memcpy(buf + i * ETH_GSTRING_LEN, ksz9477_mib_names[i].string, 386 ETH_GSTRING_LEN); 387 } 388 } 389 390 static void ksz9477_cfg_port_member(struct ksz_device *dev, int port, 391 u8 member) 392 { 393 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member); 394 dev->ports[port].member = member; 395 } 396 397 static void ksz9477_port_stp_state_set(struct dsa_switch *ds, int port, 398 u8 state) 399 { 400 struct ksz_device *dev = ds->priv; 401 struct ksz_port *p = &dev->ports[port]; 402 u8 data; 403 int member = -1; 404 int forward = dev->member; 405 406 ksz_pread8(dev, port, P_STP_CTRL, &data); 407 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 408 409 switch (state) { 410 case BR_STATE_DISABLED: 411 data |= PORT_LEARN_DISABLE; 412 if (port != dev->cpu_port) 413 member = 0; 414 break; 415 case BR_STATE_LISTENING: 416 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 417 if (port != dev->cpu_port && 418 p->stp_state == BR_STATE_DISABLED) 419 member = dev->host_mask | p->vid_member; 420 break; 421 case BR_STATE_LEARNING: 422 data |= PORT_RX_ENABLE; 423 break; 424 case BR_STATE_FORWARDING: 425 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 426 427 /* This function is also used internally. */ 428 if (port == dev->cpu_port) 429 break; 430 431 member = dev->host_mask | p->vid_member; 432 mutex_lock(&dev->dev_mutex); 433 434 /* Port is a member of a bridge. */ 435 if (dev->br_member & (1 << port)) { 436 dev->member |= (1 << port); 437 member = dev->member; 438 } 439 mutex_unlock(&dev->dev_mutex); 440 break; 441 case BR_STATE_BLOCKING: 442 data |= PORT_LEARN_DISABLE; 443 if (port != dev->cpu_port && 444 p->stp_state == BR_STATE_DISABLED) 445 member = dev->host_mask | p->vid_member; 446 break; 447 default: 448 dev_err(ds->dev, "invalid STP state: %d\n", state); 449 return; 450 } 451 452 ksz_pwrite8(dev, port, P_STP_CTRL, data); 453 p->stp_state = state; 454 mutex_lock(&dev->dev_mutex); 455 if (data & PORT_RX_ENABLE) 456 dev->rx_ports |= (1 << port); 457 else 458 dev->rx_ports &= ~(1 << port); 459 if (data & PORT_TX_ENABLE) 460 dev->tx_ports |= (1 << port); 461 else 462 dev->tx_ports &= ~(1 << port); 463 464 /* Port membership may share register with STP state. */ 465 if (member >= 0 && member != p->member) 466 ksz9477_cfg_port_member(dev, port, (u8)member); 467 468 /* Check if forwarding needs to be updated. */ 469 if (state != BR_STATE_FORWARDING) { 470 if (dev->br_member & (1 << port)) 471 dev->member &= ~(1 << port); 472 } 473 474 /* When topology has changed the function ksz_update_port_member 475 * should be called to modify port forwarding behavior. 476 */ 477 if (forward != dev->member) 478 ksz_update_port_member(dev, port); 479 mutex_unlock(&dev->dev_mutex); 480 } 481 482 static void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port) 483 { 484 u8 data; 485 486 regmap_update_bits(dev->regmap[0], REG_SW_LUE_CTRL_2, 487 SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S, 488 SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S); 489 490 if (port < dev->mib_port_cnt) { 491 /* flush individual port */ 492 ksz_pread8(dev, port, P_STP_CTRL, &data); 493 if (!(data & PORT_LEARN_DISABLE)) 494 ksz_pwrite8(dev, port, P_STP_CTRL, 495 data | PORT_LEARN_DISABLE); 496 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 497 ksz_pwrite8(dev, port, P_STP_CTRL, data); 498 } else { 499 /* flush all */ 500 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true); 501 } 502 } 503 504 static int ksz9477_port_vlan_filtering(struct dsa_switch *ds, int port, 505 bool flag) 506 { 507 struct ksz_device *dev = ds->priv; 508 509 if (flag) { 510 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 511 PORT_VLAN_LOOKUP_VID_0, true); 512 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true); 513 } else { 514 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false); 515 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 516 PORT_VLAN_LOOKUP_VID_0, false); 517 } 518 519 return 0; 520 } 521 522 static void ksz9477_port_vlan_add(struct dsa_switch *ds, int port, 523 const struct switchdev_obj_port_vlan *vlan) 524 { 525 struct ksz_device *dev = ds->priv; 526 u32 vlan_table[3]; 527 u16 vid; 528 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 529 530 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 531 if (ksz9477_get_vlan_table(dev, vid, vlan_table)) { 532 dev_dbg(dev->dev, "Failed to get vlan table\n"); 533 return; 534 } 535 536 vlan_table[0] = VLAN_VALID | (vid & VLAN_FID_M); 537 if (untagged) 538 vlan_table[1] |= BIT(port); 539 else 540 vlan_table[1] &= ~BIT(port); 541 vlan_table[1] &= ~(BIT(dev->cpu_port)); 542 543 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port); 544 545 if (ksz9477_set_vlan_table(dev, vid, vlan_table)) { 546 dev_dbg(dev->dev, "Failed to set vlan table\n"); 547 return; 548 } 549 550 /* change PVID */ 551 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 552 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vid); 553 } 554 } 555 556 static int ksz9477_port_vlan_del(struct dsa_switch *ds, int port, 557 const struct switchdev_obj_port_vlan *vlan) 558 { 559 struct ksz_device *dev = ds->priv; 560 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 561 u32 vlan_table[3]; 562 u16 vid; 563 u16 pvid; 564 565 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid); 566 pvid = pvid & 0xFFF; 567 568 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 569 if (ksz9477_get_vlan_table(dev, vid, vlan_table)) { 570 dev_dbg(dev->dev, "Failed to get vlan table\n"); 571 return -ETIMEDOUT; 572 } 573 574 vlan_table[2] &= ~BIT(port); 575 576 if (pvid == vid) 577 pvid = 1; 578 579 if (untagged) 580 vlan_table[1] &= ~BIT(port); 581 582 if (ksz9477_set_vlan_table(dev, vid, vlan_table)) { 583 dev_dbg(dev->dev, "Failed to set vlan table\n"); 584 return -ETIMEDOUT; 585 } 586 } 587 588 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid); 589 590 return 0; 591 } 592 593 static int ksz9477_port_fdb_add(struct dsa_switch *ds, int port, 594 const unsigned char *addr, u16 vid) 595 { 596 struct ksz_device *dev = ds->priv; 597 u32 alu_table[4]; 598 u32 data; 599 int ret = 0; 600 601 mutex_lock(&dev->alu_mutex); 602 603 /* find any entry with mac & vid */ 604 data = vid << ALU_FID_INDEX_S; 605 data |= ((addr[0] << 8) | addr[1]); 606 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 607 608 data = ((addr[2] << 24) | (addr[3] << 16)); 609 data |= ((addr[4] << 8) | addr[5]); 610 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 611 612 /* start read operation */ 613 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 614 615 /* wait to be finished */ 616 ret = ksz9477_wait_alu_ready(dev); 617 if (ret) { 618 dev_dbg(dev->dev, "Failed to read ALU\n"); 619 goto exit; 620 } 621 622 /* read ALU entry */ 623 ksz9477_read_table(dev, alu_table); 624 625 /* update ALU entry */ 626 alu_table[0] = ALU_V_STATIC_VALID; 627 alu_table[1] |= BIT(port); 628 if (vid) 629 alu_table[1] |= ALU_V_USE_FID; 630 alu_table[2] = (vid << ALU_V_FID_S); 631 alu_table[2] |= ((addr[0] << 8) | addr[1]); 632 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16)); 633 alu_table[3] |= ((addr[4] << 8) | addr[5]); 634 635 ksz9477_write_table(dev, alu_table); 636 637 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 638 639 /* wait to be finished */ 640 ret = ksz9477_wait_alu_ready(dev); 641 if (ret) 642 dev_dbg(dev->dev, "Failed to write ALU\n"); 643 644 exit: 645 mutex_unlock(&dev->alu_mutex); 646 647 return ret; 648 } 649 650 static int ksz9477_port_fdb_del(struct dsa_switch *ds, int port, 651 const unsigned char *addr, u16 vid) 652 { 653 struct ksz_device *dev = ds->priv; 654 u32 alu_table[4]; 655 u32 data; 656 int ret = 0; 657 658 mutex_lock(&dev->alu_mutex); 659 660 /* read any entry with mac & vid */ 661 data = vid << ALU_FID_INDEX_S; 662 data |= ((addr[0] << 8) | addr[1]); 663 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 664 665 data = ((addr[2] << 24) | (addr[3] << 16)); 666 data |= ((addr[4] << 8) | addr[5]); 667 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 668 669 /* start read operation */ 670 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 671 672 /* wait to be finished */ 673 ret = ksz9477_wait_alu_ready(dev); 674 if (ret) { 675 dev_dbg(dev->dev, "Failed to read ALU\n"); 676 goto exit; 677 } 678 679 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]); 680 if (alu_table[0] & ALU_V_STATIC_VALID) { 681 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]); 682 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]); 683 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]); 684 685 /* clear forwarding port */ 686 alu_table[2] &= ~BIT(port); 687 688 /* if there is no port to forward, clear table */ 689 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) { 690 alu_table[0] = 0; 691 alu_table[1] = 0; 692 alu_table[2] = 0; 693 alu_table[3] = 0; 694 } 695 } else { 696 alu_table[0] = 0; 697 alu_table[1] = 0; 698 alu_table[2] = 0; 699 alu_table[3] = 0; 700 } 701 702 ksz9477_write_table(dev, alu_table); 703 704 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 705 706 /* wait to be finished */ 707 ret = ksz9477_wait_alu_ready(dev); 708 if (ret) 709 dev_dbg(dev->dev, "Failed to write ALU\n"); 710 711 exit: 712 mutex_unlock(&dev->alu_mutex); 713 714 return ret; 715 } 716 717 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table) 718 { 719 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID); 720 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER); 721 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER); 722 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) & 723 ALU_V_PRIO_AGE_CNT_M; 724 alu->mstp = alu_table[0] & ALU_V_MSTP_M; 725 726 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE); 727 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID); 728 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP; 729 730 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M; 731 732 alu->mac[0] = (alu_table[2] >> 8) & 0xFF; 733 alu->mac[1] = alu_table[2] & 0xFF; 734 alu->mac[2] = (alu_table[3] >> 24) & 0xFF; 735 alu->mac[3] = (alu_table[3] >> 16) & 0xFF; 736 alu->mac[4] = (alu_table[3] >> 8) & 0xFF; 737 alu->mac[5] = alu_table[3] & 0xFF; 738 } 739 740 static int ksz9477_port_fdb_dump(struct dsa_switch *ds, int port, 741 dsa_fdb_dump_cb_t *cb, void *data) 742 { 743 struct ksz_device *dev = ds->priv; 744 int ret = 0; 745 u32 ksz_data; 746 u32 alu_table[4]; 747 struct alu_struct alu; 748 int timeout; 749 750 mutex_lock(&dev->alu_mutex); 751 752 /* start ALU search */ 753 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH); 754 755 do { 756 timeout = 1000; 757 do { 758 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data); 759 if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START)) 760 break; 761 usleep_range(1, 10); 762 } while (timeout-- > 0); 763 764 if (!timeout) { 765 dev_dbg(dev->dev, "Failed to search ALU\n"); 766 ret = -ETIMEDOUT; 767 goto exit; 768 } 769 770 /* read ALU table */ 771 ksz9477_read_table(dev, alu_table); 772 773 ksz9477_convert_alu(&alu, alu_table); 774 775 if (alu.port_forward & BIT(port)) { 776 ret = cb(alu.mac, alu.fid, alu.is_static, data); 777 if (ret) 778 goto exit; 779 } 780 } while (ksz_data & ALU_START); 781 782 exit: 783 784 /* stop ALU search */ 785 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0); 786 787 mutex_unlock(&dev->alu_mutex); 788 789 return ret; 790 } 791 792 static void ksz9477_port_mdb_add(struct dsa_switch *ds, int port, 793 const struct switchdev_obj_port_mdb *mdb) 794 { 795 struct ksz_device *dev = ds->priv; 796 u32 static_table[4]; 797 u32 data; 798 int index; 799 u32 mac_hi, mac_lo; 800 801 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 802 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 803 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 804 805 mutex_lock(&dev->alu_mutex); 806 807 for (index = 0; index < dev->num_statics; index++) { 808 /* find empty slot first */ 809 data = (index << ALU_STAT_INDEX_S) | 810 ALU_STAT_READ | ALU_STAT_START; 811 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 812 813 /* wait to be finished */ 814 if (ksz9477_wait_alu_sta_ready(dev)) { 815 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 816 goto exit; 817 } 818 819 /* read ALU static table */ 820 ksz9477_read_table(dev, static_table); 821 822 if (static_table[0] & ALU_V_STATIC_VALID) { 823 /* check this has same vid & mac address */ 824 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 825 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 826 static_table[3] == mac_lo) { 827 /* found matching one */ 828 break; 829 } 830 } else { 831 /* found empty one */ 832 break; 833 } 834 } 835 836 /* no available entry */ 837 if (index == dev->num_statics) 838 goto exit; 839 840 /* add entry */ 841 static_table[0] = ALU_V_STATIC_VALID; 842 static_table[1] |= BIT(port); 843 if (mdb->vid) 844 static_table[1] |= ALU_V_USE_FID; 845 static_table[2] = (mdb->vid << ALU_V_FID_S); 846 static_table[2] |= mac_hi; 847 static_table[3] = mac_lo; 848 849 ksz9477_write_table(dev, static_table); 850 851 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 852 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 853 854 /* wait to be finished */ 855 if (ksz9477_wait_alu_sta_ready(dev)) 856 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 857 858 exit: 859 mutex_unlock(&dev->alu_mutex); 860 } 861 862 static int ksz9477_port_mdb_del(struct dsa_switch *ds, int port, 863 const struct switchdev_obj_port_mdb *mdb) 864 { 865 struct ksz_device *dev = ds->priv; 866 u32 static_table[4]; 867 u32 data; 868 int index; 869 int ret = 0; 870 u32 mac_hi, mac_lo; 871 872 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 873 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 874 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 875 876 mutex_lock(&dev->alu_mutex); 877 878 for (index = 0; index < dev->num_statics; index++) { 879 /* find empty slot first */ 880 data = (index << ALU_STAT_INDEX_S) | 881 ALU_STAT_READ | ALU_STAT_START; 882 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 883 884 /* wait to be finished */ 885 ret = ksz9477_wait_alu_sta_ready(dev); 886 if (ret) { 887 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 888 goto exit; 889 } 890 891 /* read ALU static table */ 892 ksz9477_read_table(dev, static_table); 893 894 if (static_table[0] & ALU_V_STATIC_VALID) { 895 /* check this has same vid & mac address */ 896 897 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 898 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 899 static_table[3] == mac_lo) { 900 /* found matching one */ 901 break; 902 } 903 } 904 } 905 906 /* no available entry */ 907 if (index == dev->num_statics) 908 goto exit; 909 910 /* clear port */ 911 static_table[1] &= ~BIT(port); 912 913 if ((static_table[1] & ALU_V_PORT_MAP) == 0) { 914 /* delete entry */ 915 static_table[0] = 0; 916 static_table[1] = 0; 917 static_table[2] = 0; 918 static_table[3] = 0; 919 } 920 921 ksz9477_write_table(dev, static_table); 922 923 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 924 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 925 926 /* wait to be finished */ 927 ret = ksz9477_wait_alu_sta_ready(dev); 928 if (ret) 929 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 930 931 exit: 932 mutex_unlock(&dev->alu_mutex); 933 934 return ret; 935 } 936 937 static int ksz9477_port_mirror_add(struct dsa_switch *ds, int port, 938 struct dsa_mall_mirror_tc_entry *mirror, 939 bool ingress) 940 { 941 struct ksz_device *dev = ds->priv; 942 943 if (ingress) 944 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 945 else 946 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 947 948 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false); 949 950 /* configure mirror port */ 951 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 952 PORT_MIRROR_SNIFFER, true); 953 954 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 955 956 return 0; 957 } 958 959 static void ksz9477_port_mirror_del(struct dsa_switch *ds, int port, 960 struct dsa_mall_mirror_tc_entry *mirror) 961 { 962 struct ksz_device *dev = ds->priv; 963 u8 data; 964 965 if (mirror->ingress) 966 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 967 else 968 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 969 970 ksz_pread8(dev, port, P_MIRROR_CTRL, &data); 971 972 if (!(data & (PORT_MIRROR_RX | PORT_MIRROR_TX))) 973 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 974 PORT_MIRROR_SNIFFER, false); 975 } 976 977 static void ksz9477_phy_setup(struct ksz_device *dev, int port, 978 struct phy_device *phy) 979 { 980 /* Only apply to port with PHY. */ 981 if (port >= dev->phy_port_cnt) 982 return; 983 984 /* The MAC actually cannot run in 1000 half-duplex mode. */ 985 phy_remove_link_mode(phy, 986 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 987 988 /* PHY does not support gigabit. */ 989 if (!(dev->features & GBIT_SUPPORT)) 990 phy_remove_link_mode(phy, 991 ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 992 } 993 994 static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data) 995 { 996 bool gbit; 997 998 if (dev->features & NEW_XMII) 999 gbit = !(data & PORT_MII_NOT_1GBIT); 1000 else 1001 gbit = !!(data & PORT_MII_1000MBIT_S1); 1002 return gbit; 1003 } 1004 1005 static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data) 1006 { 1007 if (dev->features & NEW_XMII) { 1008 if (gbit) 1009 *data &= ~PORT_MII_NOT_1GBIT; 1010 else 1011 *data |= PORT_MII_NOT_1GBIT; 1012 } else { 1013 if (gbit) 1014 *data |= PORT_MII_1000MBIT_S1; 1015 else 1016 *data &= ~PORT_MII_1000MBIT_S1; 1017 } 1018 } 1019 1020 static int ksz9477_get_xmii(struct ksz_device *dev, u8 data) 1021 { 1022 int mode; 1023 1024 if (dev->features & NEW_XMII) { 1025 switch (data & PORT_MII_SEL_M) { 1026 case PORT_MII_SEL: 1027 mode = 0; 1028 break; 1029 case PORT_RMII_SEL: 1030 mode = 1; 1031 break; 1032 case PORT_GMII_SEL: 1033 mode = 2; 1034 break; 1035 default: 1036 mode = 3; 1037 } 1038 } else { 1039 switch (data & PORT_MII_SEL_M) { 1040 case PORT_MII_SEL_S1: 1041 mode = 0; 1042 break; 1043 case PORT_RMII_SEL_S1: 1044 mode = 1; 1045 break; 1046 case PORT_GMII_SEL_S1: 1047 mode = 2; 1048 break; 1049 default: 1050 mode = 3; 1051 } 1052 } 1053 return mode; 1054 } 1055 1056 static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data) 1057 { 1058 u8 xmii; 1059 1060 if (dev->features & NEW_XMII) { 1061 switch (mode) { 1062 case 0: 1063 xmii = PORT_MII_SEL; 1064 break; 1065 case 1: 1066 xmii = PORT_RMII_SEL; 1067 break; 1068 case 2: 1069 xmii = PORT_GMII_SEL; 1070 break; 1071 default: 1072 xmii = PORT_RGMII_SEL; 1073 break; 1074 } 1075 } else { 1076 switch (mode) { 1077 case 0: 1078 xmii = PORT_MII_SEL_S1; 1079 break; 1080 case 1: 1081 xmii = PORT_RMII_SEL_S1; 1082 break; 1083 case 2: 1084 xmii = PORT_GMII_SEL_S1; 1085 break; 1086 default: 1087 xmii = PORT_RGMII_SEL_S1; 1088 break; 1089 } 1090 } 1091 *data &= ~PORT_MII_SEL_M; 1092 *data |= xmii; 1093 } 1094 1095 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port) 1096 { 1097 phy_interface_t interface; 1098 bool gbit; 1099 int mode; 1100 u8 data8; 1101 1102 if (port < dev->phy_port_cnt) 1103 return PHY_INTERFACE_MODE_NA; 1104 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 1105 gbit = ksz9477_get_gbit(dev, data8); 1106 mode = ksz9477_get_xmii(dev, data8); 1107 switch (mode) { 1108 case 2: 1109 interface = PHY_INTERFACE_MODE_GMII; 1110 if (gbit) 1111 break; 1112 /* fall through */ 1113 case 0: 1114 interface = PHY_INTERFACE_MODE_MII; 1115 break; 1116 case 1: 1117 interface = PHY_INTERFACE_MODE_RMII; 1118 break; 1119 default: 1120 interface = PHY_INTERFACE_MODE_RGMII; 1121 if (data8 & PORT_RGMII_ID_EG_ENABLE) 1122 interface = PHY_INTERFACE_MODE_RGMII_TXID; 1123 if (data8 & PORT_RGMII_ID_IG_ENABLE) { 1124 interface = PHY_INTERFACE_MODE_RGMII_RXID; 1125 if (data8 & PORT_RGMII_ID_EG_ENABLE) 1126 interface = PHY_INTERFACE_MODE_RGMII_ID; 1127 } 1128 break; 1129 } 1130 return interface; 1131 } 1132 1133 static void ksz9477_port_mmd_write(struct ksz_device *dev, int port, 1134 u8 dev_addr, u16 reg_addr, u16 val) 1135 { 1136 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 1137 MMD_SETUP(PORT_MMD_OP_INDEX, dev_addr)); 1138 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg_addr); 1139 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 1140 MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, dev_addr)); 1141 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val); 1142 } 1143 1144 static void ksz9477_phy_errata_setup(struct ksz_device *dev, int port) 1145 { 1146 /* Apply PHY settings to address errata listed in 1147 * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565 1148 * Silicon Errata and Data Sheet Clarification documents: 1149 * 1150 * Register settings are needed to improve PHY receive performance 1151 */ 1152 ksz9477_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b); 1153 ksz9477_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032); 1154 ksz9477_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c); 1155 ksz9477_port_mmd_write(dev, port, 0x01, 0x75, 0x0060); 1156 ksz9477_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777); 1157 ksz9477_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008); 1158 ksz9477_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001); 1159 1160 /* Transmit waveform amplitude can be improved 1161 * (1000BASE-T, 100BASE-TX, 10BASE-Te) 1162 */ 1163 ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0); 1164 1165 /* Energy Efficient Ethernet (EEE) feature select must 1166 * be manually disabled (except on KSZ8565 which is 100Mbit) 1167 */ 1168 if (dev->features & GBIT_SUPPORT) 1169 ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000); 1170 1171 /* Register settings are required to meet data sheet 1172 * supply current specifications 1173 */ 1174 ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff); 1175 ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff); 1176 ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff); 1177 ksz9477_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff); 1178 ksz9477_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff); 1179 ksz9477_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff); 1180 ksz9477_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff); 1181 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff); 1182 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff); 1183 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff); 1184 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff); 1185 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff); 1186 ksz9477_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee); 1187 } 1188 1189 static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1190 { 1191 u8 data8; 1192 u8 member; 1193 u16 data16; 1194 struct ksz_port *p = &dev->ports[port]; 1195 1196 /* enable tag tail for host port */ 1197 if (cpu_port) 1198 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE, 1199 true); 1200 1201 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false); 1202 1203 /* set back pressure */ 1204 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true); 1205 1206 /* enable broadcast storm limit */ 1207 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 1208 1209 /* disable DiffServ priority */ 1210 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false); 1211 1212 /* replace priority */ 1213 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING, 1214 false); 1215 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4, 1216 MTI_PVID_REPLACE, false); 1217 1218 /* enable 802.1p priority */ 1219 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); 1220 1221 if (port < dev->phy_port_cnt) { 1222 /* do not force flow control */ 1223 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1224 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1225 false); 1226 1227 if (dev->phy_errata_9477) 1228 ksz9477_phy_errata_setup(dev, port); 1229 } else { 1230 /* force flow control */ 1231 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1232 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1233 true); 1234 1235 /* configure MAC to 1G & RGMII mode */ 1236 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 1237 switch (dev->interface) { 1238 case PHY_INTERFACE_MODE_MII: 1239 ksz9477_set_xmii(dev, 0, &data8); 1240 ksz9477_set_gbit(dev, false, &data8); 1241 p->phydev.speed = SPEED_100; 1242 break; 1243 case PHY_INTERFACE_MODE_RMII: 1244 ksz9477_set_xmii(dev, 1, &data8); 1245 ksz9477_set_gbit(dev, false, &data8); 1246 p->phydev.speed = SPEED_100; 1247 break; 1248 case PHY_INTERFACE_MODE_GMII: 1249 ksz9477_set_xmii(dev, 2, &data8); 1250 ksz9477_set_gbit(dev, true, &data8); 1251 p->phydev.speed = SPEED_1000; 1252 break; 1253 default: 1254 ksz9477_set_xmii(dev, 3, &data8); 1255 ksz9477_set_gbit(dev, true, &data8); 1256 data8 &= ~PORT_RGMII_ID_IG_ENABLE; 1257 data8 &= ~PORT_RGMII_ID_EG_ENABLE; 1258 if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID || 1259 dev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 1260 data8 |= PORT_RGMII_ID_IG_ENABLE; 1261 if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID || 1262 dev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1263 data8 |= PORT_RGMII_ID_EG_ENABLE; 1264 p->phydev.speed = SPEED_1000; 1265 break; 1266 } 1267 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8); 1268 p->phydev.duplex = 1; 1269 } 1270 mutex_lock(&dev->dev_mutex); 1271 if (cpu_port) { 1272 member = dev->port_mask; 1273 dev->on_ports = dev->host_mask; 1274 dev->live_ports = dev->host_mask; 1275 } else { 1276 member = dev->host_mask | p->vid_member; 1277 dev->on_ports |= (1 << port); 1278 1279 /* Link was detected before port is enabled. */ 1280 if (p->phydev.link) 1281 dev->live_ports |= (1 << port); 1282 } 1283 mutex_unlock(&dev->dev_mutex); 1284 ksz9477_cfg_port_member(dev, port, member); 1285 1286 /* clear pending interrupts */ 1287 if (port < dev->phy_port_cnt) 1288 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16); 1289 } 1290 1291 static void ksz9477_config_cpu_port(struct dsa_switch *ds) 1292 { 1293 struct ksz_device *dev = ds->priv; 1294 struct ksz_port *p; 1295 int i; 1296 1297 ds->num_ports = dev->port_cnt; 1298 1299 for (i = 0; i < dev->port_cnt; i++) { 1300 if (dsa_is_cpu_port(ds, i) && (dev->cpu_ports & (1 << i))) { 1301 phy_interface_t interface; 1302 1303 dev->cpu_port = i; 1304 dev->host_mask = (1 << dev->cpu_port); 1305 dev->port_mask |= dev->host_mask; 1306 1307 /* Read from XMII register to determine host port 1308 * interface. If set specifically in device tree 1309 * note the difference to help debugging. 1310 */ 1311 interface = ksz9477_get_interface(dev, i); 1312 if (!dev->interface) 1313 dev->interface = interface; 1314 if (interface && interface != dev->interface) 1315 dev_info(dev->dev, 1316 "use %s instead of %s\n", 1317 phy_modes(dev->interface), 1318 phy_modes(interface)); 1319 1320 /* enable cpu port */ 1321 ksz9477_port_setup(dev, i, true); 1322 p = &dev->ports[dev->cpu_port]; 1323 p->vid_member = dev->port_mask; 1324 p->on = 1; 1325 } 1326 } 1327 1328 dev->member = dev->host_mask; 1329 1330 for (i = 0; i < dev->mib_port_cnt; i++) { 1331 if (i == dev->cpu_port) 1332 continue; 1333 p = &dev->ports[i]; 1334 1335 /* Initialize to non-zero so that ksz_cfg_port_member() will 1336 * be called. 1337 */ 1338 p->vid_member = (1 << i); 1339 p->member = dev->port_mask; 1340 ksz9477_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1341 p->on = 1; 1342 if (i < dev->phy_port_cnt) 1343 p->phy = 1; 1344 if (dev->chip_id == 0x00947700 && i == 6) { 1345 p->sgmii = 1; 1346 1347 /* SGMII PHY detection code is not implemented yet. */ 1348 p->phy = 0; 1349 } 1350 } 1351 } 1352 1353 static int ksz9477_setup(struct dsa_switch *ds) 1354 { 1355 struct ksz_device *dev = ds->priv; 1356 int ret = 0; 1357 1358 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 1359 dev->num_vlans, GFP_KERNEL); 1360 if (!dev->vlan_cache) 1361 return -ENOMEM; 1362 1363 ret = ksz9477_reset_switch(dev); 1364 if (ret) { 1365 dev_err(ds->dev, "failed to reset switch\n"); 1366 return ret; 1367 } 1368 1369 /* Required for port partitioning. */ 1370 ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, 1371 true); 1372 1373 /* Do not work correctly with tail tagging. */ 1374 ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false); 1375 1376 /* accept packet up to 2000bytes */ 1377 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_LEGAL_PACKET_DISABLE, true); 1378 1379 ksz9477_config_cpu_port(ds); 1380 1381 ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true); 1382 1383 /* queue based egress rate limit */ 1384 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true); 1385 1386 /* enable global MIB counter freeze function */ 1387 ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); 1388 1389 /* start switch */ 1390 ksz_cfg(dev, REG_SW_OPERATION, SW_START, true); 1391 1392 ksz_init_mib_timer(dev); 1393 1394 return 0; 1395 } 1396 1397 static const struct dsa_switch_ops ksz9477_switch_ops = { 1398 .get_tag_protocol = ksz9477_get_tag_protocol, 1399 .setup = ksz9477_setup, 1400 .phy_read = ksz9477_phy_read16, 1401 .phy_write = ksz9477_phy_write16, 1402 .adjust_link = ksz_adjust_link, 1403 .port_enable = ksz_enable_port, 1404 .port_disable = ksz_disable_port, 1405 .get_strings = ksz9477_get_strings, 1406 .get_ethtool_stats = ksz_get_ethtool_stats, 1407 .get_sset_count = ksz_sset_count, 1408 .port_bridge_join = ksz_port_bridge_join, 1409 .port_bridge_leave = ksz_port_bridge_leave, 1410 .port_stp_state_set = ksz9477_port_stp_state_set, 1411 .port_fast_age = ksz_port_fast_age, 1412 .port_vlan_filtering = ksz9477_port_vlan_filtering, 1413 .port_vlan_prepare = ksz_port_vlan_prepare, 1414 .port_vlan_add = ksz9477_port_vlan_add, 1415 .port_vlan_del = ksz9477_port_vlan_del, 1416 .port_fdb_dump = ksz9477_port_fdb_dump, 1417 .port_fdb_add = ksz9477_port_fdb_add, 1418 .port_fdb_del = ksz9477_port_fdb_del, 1419 .port_mdb_prepare = ksz_port_mdb_prepare, 1420 .port_mdb_add = ksz9477_port_mdb_add, 1421 .port_mdb_del = ksz9477_port_mdb_del, 1422 .port_mirror_add = ksz9477_port_mirror_add, 1423 .port_mirror_del = ksz9477_port_mirror_del, 1424 }; 1425 1426 static u32 ksz9477_get_port_addr(int port, int offset) 1427 { 1428 return PORT_CTRL_ADDR(port, offset); 1429 } 1430 1431 static int ksz9477_switch_detect(struct ksz_device *dev) 1432 { 1433 u8 data8; 1434 u8 id_hi; 1435 u8 id_lo; 1436 u32 id32; 1437 int ret; 1438 1439 /* turn off SPI DO Edge select */ 1440 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 1441 if (ret) 1442 return ret; 1443 1444 data8 &= ~SPI_AUTO_EDGE_DETECTION; 1445 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 1446 if (ret) 1447 return ret; 1448 1449 /* read chip id */ 1450 ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32); 1451 if (ret) 1452 return ret; 1453 ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8); 1454 if (ret) 1455 return ret; 1456 1457 /* Number of ports can be reduced depending on chip. */ 1458 dev->mib_port_cnt = TOTAL_PORT_NUM; 1459 dev->phy_port_cnt = 5; 1460 1461 /* Default capability is gigabit capable. */ 1462 dev->features = GBIT_SUPPORT; 1463 1464 id_hi = (u8)(id32 >> 16); 1465 id_lo = (u8)(id32 >> 8); 1466 if ((id_lo & 0xf) == 3) { 1467 /* Chip is from KSZ9893 design. */ 1468 dev->features |= IS_9893; 1469 1470 /* Chip does not support gigabit. */ 1471 if (data8 & SW_QW_ABLE) 1472 dev->features &= ~GBIT_SUPPORT; 1473 dev->mib_port_cnt = 3; 1474 dev->phy_port_cnt = 2; 1475 } else { 1476 /* Chip uses new XMII register definitions. */ 1477 dev->features |= NEW_XMII; 1478 1479 /* Chip does not support gigabit. */ 1480 if (!(data8 & SW_GIGABIT_ABLE)) 1481 dev->features &= ~GBIT_SUPPORT; 1482 } 1483 1484 /* Change chip id to known ones so it can be matched against them. */ 1485 id32 = (id_hi << 16) | (id_lo << 8); 1486 1487 dev->chip_id = id32; 1488 1489 return 0; 1490 } 1491 1492 struct ksz_chip_data { 1493 u32 chip_id; 1494 const char *dev_name; 1495 int num_vlans; 1496 int num_alus; 1497 int num_statics; 1498 int cpu_ports; 1499 int port_cnt; 1500 bool phy_errata_9477; 1501 }; 1502 1503 static const struct ksz_chip_data ksz9477_switch_chips[] = { 1504 { 1505 .chip_id = 0x00947700, 1506 .dev_name = "KSZ9477", 1507 .num_vlans = 4096, 1508 .num_alus = 4096, 1509 .num_statics = 16, 1510 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1511 .port_cnt = 7, /* total physical port count */ 1512 .phy_errata_9477 = true, 1513 }, 1514 { 1515 .chip_id = 0x00989700, 1516 .dev_name = "KSZ9897", 1517 .num_vlans = 4096, 1518 .num_alus = 4096, 1519 .num_statics = 16, 1520 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1521 .port_cnt = 7, /* total physical port count */ 1522 .phy_errata_9477 = true, 1523 }, 1524 { 1525 .chip_id = 0x00989300, 1526 .dev_name = "KSZ9893", 1527 .num_vlans = 4096, 1528 .num_alus = 4096, 1529 .num_statics = 16, 1530 .cpu_ports = 0x07, /* can be configured as cpu port */ 1531 .port_cnt = 3, /* total port count */ 1532 }, 1533 { 1534 .chip_id = 0x00956700, 1535 .dev_name = "KSZ9567", 1536 .num_vlans = 4096, 1537 .num_alus = 4096, 1538 .num_statics = 16, 1539 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1540 .port_cnt = 7, /* total physical port count */ 1541 }, 1542 }; 1543 1544 static int ksz9477_switch_init(struct ksz_device *dev) 1545 { 1546 int i; 1547 1548 dev->ds->ops = &ksz9477_switch_ops; 1549 1550 for (i = 0; i < ARRAY_SIZE(ksz9477_switch_chips); i++) { 1551 const struct ksz_chip_data *chip = &ksz9477_switch_chips[i]; 1552 1553 if (dev->chip_id == chip->chip_id) { 1554 dev->name = chip->dev_name; 1555 dev->num_vlans = chip->num_vlans; 1556 dev->num_alus = chip->num_alus; 1557 dev->num_statics = chip->num_statics; 1558 dev->port_cnt = chip->port_cnt; 1559 dev->cpu_ports = chip->cpu_ports; 1560 dev->phy_errata_9477 = chip->phy_errata_9477; 1561 1562 break; 1563 } 1564 } 1565 1566 /* no switch found */ 1567 if (!dev->port_cnt) 1568 return -ENODEV; 1569 1570 dev->port_mask = (1 << dev->port_cnt) - 1; 1571 1572 dev->reg_mib_cnt = SWITCH_COUNTER_NUM; 1573 dev->mib_cnt = TOTAL_SWITCH_COUNTER_NUM; 1574 1575 i = dev->mib_port_cnt; 1576 dev->ports = devm_kzalloc(dev->dev, sizeof(struct ksz_port) * i, 1577 GFP_KERNEL); 1578 if (!dev->ports) 1579 return -ENOMEM; 1580 for (i = 0; i < dev->mib_port_cnt; i++) { 1581 mutex_init(&dev->ports[i].mib.cnt_mutex); 1582 dev->ports[i].mib.counters = 1583 devm_kzalloc(dev->dev, 1584 sizeof(u64) * 1585 (TOTAL_SWITCH_COUNTER_NUM + 1), 1586 GFP_KERNEL); 1587 if (!dev->ports[i].mib.counters) 1588 return -ENOMEM; 1589 } 1590 1591 return 0; 1592 } 1593 1594 static void ksz9477_switch_exit(struct ksz_device *dev) 1595 { 1596 ksz9477_reset_switch(dev); 1597 } 1598 1599 static const struct ksz_dev_ops ksz9477_dev_ops = { 1600 .get_port_addr = ksz9477_get_port_addr, 1601 .cfg_port_member = ksz9477_cfg_port_member, 1602 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 1603 .phy_setup = ksz9477_phy_setup, 1604 .port_setup = ksz9477_port_setup, 1605 .r_mib_cnt = ksz9477_r_mib_cnt, 1606 .r_mib_pkt = ksz9477_r_mib_pkt, 1607 .freeze_mib = ksz9477_freeze_mib, 1608 .port_init_cnt = ksz9477_port_init_cnt, 1609 .shutdown = ksz9477_reset_switch, 1610 .detect = ksz9477_switch_detect, 1611 .init = ksz9477_switch_init, 1612 .exit = ksz9477_switch_exit, 1613 }; 1614 1615 int ksz9477_switch_register(struct ksz_device *dev) 1616 { 1617 return ksz_switch_register(dev, &ksz9477_dev_ops); 1618 } 1619 EXPORT_SYMBOL(ksz9477_switch_register); 1620 1621 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 1622 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver"); 1623 MODULE_LICENSE("GPL"); 1624