1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ9477 switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/iopoll.h> 11 #include <linux/platform_data/microchip-ksz.h> 12 #include <linux/phy.h> 13 #include <linux/if_bridge.h> 14 #include <net/dsa.h> 15 #include <net/switchdev.h> 16 17 #include "ksz_priv.h" 18 #include "ksz9477_reg.h" 19 #include "ksz_common.h" 20 21 /* Used with variable features to indicate capabilities. */ 22 #define GBIT_SUPPORT BIT(0) 23 #define NEW_XMII BIT(1) 24 #define IS_9893 BIT(2) 25 26 static const struct { 27 int index; 28 char string[ETH_GSTRING_LEN]; 29 } ksz9477_mib_names[TOTAL_SWITCH_COUNTER_NUM] = { 30 { 0x00, "rx_hi" }, 31 { 0x01, "rx_undersize" }, 32 { 0x02, "rx_fragments" }, 33 { 0x03, "rx_oversize" }, 34 { 0x04, "rx_jabbers" }, 35 { 0x05, "rx_symbol_err" }, 36 { 0x06, "rx_crc_err" }, 37 { 0x07, "rx_align_err" }, 38 { 0x08, "rx_mac_ctrl" }, 39 { 0x09, "rx_pause" }, 40 { 0x0A, "rx_bcast" }, 41 { 0x0B, "rx_mcast" }, 42 { 0x0C, "rx_ucast" }, 43 { 0x0D, "rx_64_or_less" }, 44 { 0x0E, "rx_65_127" }, 45 { 0x0F, "rx_128_255" }, 46 { 0x10, "rx_256_511" }, 47 { 0x11, "rx_512_1023" }, 48 { 0x12, "rx_1024_1522" }, 49 { 0x13, "rx_1523_2000" }, 50 { 0x14, "rx_2001" }, 51 { 0x15, "tx_hi" }, 52 { 0x16, "tx_late_col" }, 53 { 0x17, "tx_pause" }, 54 { 0x18, "tx_bcast" }, 55 { 0x19, "tx_mcast" }, 56 { 0x1A, "tx_ucast" }, 57 { 0x1B, "tx_deferred" }, 58 { 0x1C, "tx_total_col" }, 59 { 0x1D, "tx_exc_col" }, 60 { 0x1E, "tx_single_col" }, 61 { 0x1F, "tx_mult_col" }, 62 { 0x80, "rx_total" }, 63 { 0x81, "tx_total" }, 64 { 0x82, "rx_discards" }, 65 { 0x83, "tx_discards" }, 66 }; 67 68 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set) 69 { 70 u32 data; 71 72 ksz_read32(dev, addr, &data); 73 if (set) 74 data |= bits; 75 else 76 data &= ~bits; 77 ksz_write32(dev, addr, data); 78 } 79 80 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset, 81 u32 bits, bool set) 82 { 83 u32 addr; 84 u32 data; 85 86 addr = PORT_CTRL_ADDR(port, offset); 87 ksz_read32(dev, addr, &data); 88 89 if (set) 90 data |= bits; 91 else 92 data &= ~bits; 93 94 ksz_write32(dev, addr, data); 95 } 96 97 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev, u32 waiton, 98 int timeout) 99 { 100 u8 data; 101 102 do { 103 ksz_read8(dev, REG_SW_VLAN_CTRL, &data); 104 if (!(data & waiton)) 105 break; 106 usleep_range(1, 10); 107 } while (timeout-- > 0); 108 109 if (timeout <= 0) 110 return -ETIMEDOUT; 111 112 return 0; 113 } 114 115 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid, 116 u32 *vlan_table) 117 { 118 int ret; 119 120 mutex_lock(&dev->vlan_mutex); 121 122 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 123 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START); 124 125 /* wait to be cleared */ 126 ret = ksz9477_wait_vlan_ctrl_ready(dev, VLAN_START, 1000); 127 if (ret < 0) { 128 dev_dbg(dev->dev, "Failed to read vlan table\n"); 129 goto exit; 130 } 131 132 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]); 133 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]); 134 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]); 135 136 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 137 138 exit: 139 mutex_unlock(&dev->vlan_mutex); 140 141 return ret; 142 } 143 144 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid, 145 u32 *vlan_table) 146 { 147 int ret; 148 149 mutex_lock(&dev->vlan_mutex); 150 151 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]); 152 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]); 153 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]); 154 155 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 156 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE); 157 158 /* wait to be cleared */ 159 ret = ksz9477_wait_vlan_ctrl_ready(dev, VLAN_START, 1000); 160 if (ret < 0) { 161 dev_dbg(dev->dev, "Failed to write vlan table\n"); 162 goto exit; 163 } 164 165 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 166 167 /* update vlan cache table */ 168 dev->vlan_cache[vid].table[0] = vlan_table[0]; 169 dev->vlan_cache[vid].table[1] = vlan_table[1]; 170 dev->vlan_cache[vid].table[2] = vlan_table[2]; 171 172 exit: 173 mutex_unlock(&dev->vlan_mutex); 174 175 return ret; 176 } 177 178 static void ksz9477_read_table(struct ksz_device *dev, u32 *table) 179 { 180 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]); 181 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]); 182 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]); 183 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]); 184 } 185 186 static void ksz9477_write_table(struct ksz_device *dev, u32 *table) 187 { 188 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]); 189 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]); 190 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]); 191 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]); 192 } 193 194 static int ksz9477_wait_alu_ready(struct ksz_device *dev, u32 waiton, 195 int timeout) 196 { 197 u32 data; 198 199 do { 200 ksz_read32(dev, REG_SW_ALU_CTRL__4, &data); 201 if (!(data & waiton)) 202 break; 203 usleep_range(1, 10); 204 } while (timeout-- > 0); 205 206 if (timeout <= 0) 207 return -ETIMEDOUT; 208 209 return 0; 210 } 211 212 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev, u32 waiton, 213 int timeout) 214 { 215 u32 data; 216 217 do { 218 ksz_read32(dev, REG_SW_ALU_STAT_CTRL__4, &data); 219 if (!(data & waiton)) 220 break; 221 usleep_range(1, 10); 222 } while (timeout-- > 0); 223 224 if (timeout <= 0) 225 return -ETIMEDOUT; 226 227 return 0; 228 } 229 230 static int ksz9477_reset_switch(struct ksz_device *dev) 231 { 232 u8 data8; 233 u16 data16; 234 u32 data32; 235 236 /* reset switch */ 237 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 238 239 /* turn off SPI DO Edge select */ 240 ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 241 data8 &= ~SPI_AUTO_EDGE_DETECTION; 242 ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 243 244 /* default configuration */ 245 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8); 246 data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING | 247 SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE; 248 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8); 249 250 /* disable interrupts */ 251 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 252 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F); 253 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 254 255 /* set broadcast storm protection 10% rate */ 256 ksz_read16(dev, REG_SW_MAC_CTRL_2, &data16); 257 data16 &= ~BROADCAST_STORM_RATE; 258 data16 |= (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100; 259 ksz_write16(dev, REG_SW_MAC_CTRL_2, data16); 260 261 return 0; 262 } 263 264 static void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, 265 u64 *cnt) 266 { 267 struct ksz_poll_ctx ctx = { 268 .dev = dev, 269 .port = port, 270 .offset = REG_PORT_MIB_CTRL_STAT__4, 271 }; 272 struct ksz_port *p = &dev->ports[port]; 273 u32 data; 274 int ret; 275 276 /* retain the flush/freeze bit */ 277 data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 278 data |= MIB_COUNTER_READ; 279 data |= (addr << MIB_COUNTER_INDEX_S); 280 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data); 281 282 ret = readx_poll_timeout(ksz_pread32_poll, &ctx, data, 283 !(data & MIB_COUNTER_READ), 10, 1000); 284 285 /* failed to read MIB. get out of loop */ 286 if (ret < 0) { 287 dev_dbg(dev->dev, "Failed to get MIB\n"); 288 return; 289 } 290 291 /* count resets upon read */ 292 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data); 293 *cnt += data; 294 } 295 296 static void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 297 u64 *dropped, u64 *cnt) 298 { 299 addr = ksz9477_mib_names[addr].index; 300 ksz9477_r_mib_cnt(dev, port, addr, cnt); 301 } 302 303 static void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze) 304 { 305 u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 306 struct ksz_port *p = &dev->ports[port]; 307 308 /* enable/disable the port for flush/freeze function */ 309 mutex_lock(&p->mib.cnt_mutex); 310 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val); 311 312 /* used by MIB counter reading code to know freeze is enabled */ 313 p->freeze = freeze; 314 mutex_unlock(&p->mib.cnt_mutex); 315 } 316 317 static void ksz9477_port_init_cnt(struct ksz_device *dev, int port) 318 { 319 struct ksz_port_mib *mib = &dev->ports[port].mib; 320 321 /* flush all enabled port MIB counters */ 322 mutex_lock(&mib->cnt_mutex); 323 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 324 MIB_COUNTER_FLUSH_FREEZE); 325 ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH); 326 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0); 327 mutex_unlock(&mib->cnt_mutex); 328 329 mib->cnt_ptr = 0; 330 memset(mib->counters, 0, dev->mib_cnt * sizeof(u64)); 331 } 332 333 static enum dsa_tag_protocol ksz9477_get_tag_protocol(struct dsa_switch *ds, 334 int port) 335 { 336 enum dsa_tag_protocol proto = DSA_TAG_PROTO_KSZ9477; 337 struct ksz_device *dev = ds->priv; 338 339 if (dev->features & IS_9893) 340 proto = DSA_TAG_PROTO_KSZ9893; 341 return proto; 342 } 343 344 static int ksz9477_phy_read16(struct dsa_switch *ds, int addr, int reg) 345 { 346 struct ksz_device *dev = ds->priv; 347 u16 val = 0xffff; 348 349 /* No real PHY after this. Simulate the PHY. 350 * A fixed PHY can be setup in the device tree, but this function is 351 * still called for that port during initialization. 352 * For RGMII PHY there is no way to access it so the fixed PHY should 353 * be used. For SGMII PHY the supporting code will be added later. 354 */ 355 if (addr >= dev->phy_port_cnt) { 356 struct ksz_port *p = &dev->ports[addr]; 357 358 switch (reg) { 359 case MII_BMCR: 360 val = 0x1140; 361 break; 362 case MII_BMSR: 363 val = 0x796d; 364 break; 365 case MII_PHYSID1: 366 val = 0x0022; 367 break; 368 case MII_PHYSID2: 369 val = 0x1631; 370 break; 371 case MII_ADVERTISE: 372 val = 0x05e1; 373 break; 374 case MII_LPA: 375 val = 0xc5e1; 376 break; 377 case MII_CTRL1000: 378 val = 0x0700; 379 break; 380 case MII_STAT1000: 381 if (p->phydev.speed == SPEED_1000) 382 val = 0x3800; 383 else 384 val = 0; 385 break; 386 } 387 } else { 388 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val); 389 } 390 391 return val; 392 } 393 394 static int ksz9477_phy_write16(struct dsa_switch *ds, int addr, int reg, 395 u16 val) 396 { 397 struct ksz_device *dev = ds->priv; 398 399 /* No real PHY after this. */ 400 if (addr >= dev->phy_port_cnt) 401 return 0; 402 403 /* No gigabit support. Do not write to this register. */ 404 if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000) 405 return 0; 406 ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val); 407 408 return 0; 409 } 410 411 static void ksz9477_get_strings(struct dsa_switch *ds, int port, 412 u32 stringset, uint8_t *buf) 413 { 414 int i; 415 416 if (stringset != ETH_SS_STATS) 417 return; 418 419 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) { 420 memcpy(buf + i * ETH_GSTRING_LEN, ksz9477_mib_names[i].string, 421 ETH_GSTRING_LEN); 422 } 423 } 424 425 static void ksz9477_cfg_port_member(struct ksz_device *dev, int port, 426 u8 member) 427 { 428 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member); 429 dev->ports[port].member = member; 430 } 431 432 static void ksz9477_port_stp_state_set(struct dsa_switch *ds, int port, 433 u8 state) 434 { 435 struct ksz_device *dev = ds->priv; 436 struct ksz_port *p = &dev->ports[port]; 437 u8 data; 438 int member = -1; 439 int forward = dev->member; 440 441 ksz_pread8(dev, port, P_STP_CTRL, &data); 442 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 443 444 switch (state) { 445 case BR_STATE_DISABLED: 446 data |= PORT_LEARN_DISABLE; 447 if (port != dev->cpu_port) 448 member = 0; 449 break; 450 case BR_STATE_LISTENING: 451 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 452 if (port != dev->cpu_port && 453 p->stp_state == BR_STATE_DISABLED) 454 member = dev->host_mask | p->vid_member; 455 break; 456 case BR_STATE_LEARNING: 457 data |= PORT_RX_ENABLE; 458 break; 459 case BR_STATE_FORWARDING: 460 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 461 462 /* This function is also used internally. */ 463 if (port == dev->cpu_port) 464 break; 465 466 member = dev->host_mask | p->vid_member; 467 mutex_lock(&dev->dev_mutex); 468 469 /* Port is a member of a bridge. */ 470 if (dev->br_member & (1 << port)) { 471 dev->member |= (1 << port); 472 member = dev->member; 473 } 474 mutex_unlock(&dev->dev_mutex); 475 break; 476 case BR_STATE_BLOCKING: 477 data |= PORT_LEARN_DISABLE; 478 if (port != dev->cpu_port && 479 p->stp_state == BR_STATE_DISABLED) 480 member = dev->host_mask | p->vid_member; 481 break; 482 default: 483 dev_err(ds->dev, "invalid STP state: %d\n", state); 484 return; 485 } 486 487 ksz_pwrite8(dev, port, P_STP_CTRL, data); 488 p->stp_state = state; 489 mutex_lock(&dev->dev_mutex); 490 if (data & PORT_RX_ENABLE) 491 dev->rx_ports |= (1 << port); 492 else 493 dev->rx_ports &= ~(1 << port); 494 if (data & PORT_TX_ENABLE) 495 dev->tx_ports |= (1 << port); 496 else 497 dev->tx_ports &= ~(1 << port); 498 499 /* Port membership may share register with STP state. */ 500 if (member >= 0 && member != p->member) 501 ksz9477_cfg_port_member(dev, port, (u8)member); 502 503 /* Check if forwarding needs to be updated. */ 504 if (state != BR_STATE_FORWARDING) { 505 if (dev->br_member & (1 << port)) 506 dev->member &= ~(1 << port); 507 } 508 509 /* When topology has changed the function ksz_update_port_member 510 * should be called to modify port forwarding behavior. 511 */ 512 if (forward != dev->member) 513 ksz_update_port_member(dev, port); 514 mutex_unlock(&dev->dev_mutex); 515 } 516 517 static void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port) 518 { 519 u8 data; 520 521 ksz_read8(dev, REG_SW_LUE_CTRL_2, &data); 522 data &= ~(SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S); 523 data |= (SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S); 524 ksz_write8(dev, REG_SW_LUE_CTRL_2, data); 525 if (port < dev->mib_port_cnt) { 526 /* flush individual port */ 527 ksz_pread8(dev, port, P_STP_CTRL, &data); 528 if (!(data & PORT_LEARN_DISABLE)) 529 ksz_pwrite8(dev, port, P_STP_CTRL, 530 data | PORT_LEARN_DISABLE); 531 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 532 ksz_pwrite8(dev, port, P_STP_CTRL, data); 533 } else { 534 /* flush all */ 535 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true); 536 } 537 } 538 539 static int ksz9477_port_vlan_filtering(struct dsa_switch *ds, int port, 540 bool flag) 541 { 542 struct ksz_device *dev = ds->priv; 543 544 if (flag) { 545 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 546 PORT_VLAN_LOOKUP_VID_0, true); 547 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true); 548 } else { 549 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false); 550 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 551 PORT_VLAN_LOOKUP_VID_0, false); 552 } 553 554 return 0; 555 } 556 557 static void ksz9477_port_vlan_add(struct dsa_switch *ds, int port, 558 const struct switchdev_obj_port_vlan *vlan) 559 { 560 struct ksz_device *dev = ds->priv; 561 u32 vlan_table[3]; 562 u16 vid; 563 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 564 565 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 566 if (ksz9477_get_vlan_table(dev, vid, vlan_table)) { 567 dev_dbg(dev->dev, "Failed to get vlan table\n"); 568 return; 569 } 570 571 vlan_table[0] = VLAN_VALID | (vid & VLAN_FID_M); 572 if (untagged) 573 vlan_table[1] |= BIT(port); 574 else 575 vlan_table[1] &= ~BIT(port); 576 vlan_table[1] &= ~(BIT(dev->cpu_port)); 577 578 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port); 579 580 if (ksz9477_set_vlan_table(dev, vid, vlan_table)) { 581 dev_dbg(dev->dev, "Failed to set vlan table\n"); 582 return; 583 } 584 585 /* change PVID */ 586 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 587 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vid); 588 } 589 } 590 591 static int ksz9477_port_vlan_del(struct dsa_switch *ds, int port, 592 const struct switchdev_obj_port_vlan *vlan) 593 { 594 struct ksz_device *dev = ds->priv; 595 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 596 u32 vlan_table[3]; 597 u16 vid; 598 u16 pvid; 599 600 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid); 601 pvid = pvid & 0xFFF; 602 603 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 604 if (ksz9477_get_vlan_table(dev, vid, vlan_table)) { 605 dev_dbg(dev->dev, "Failed to get vlan table\n"); 606 return -ETIMEDOUT; 607 } 608 609 vlan_table[2] &= ~BIT(port); 610 611 if (pvid == vid) 612 pvid = 1; 613 614 if (untagged) 615 vlan_table[1] &= ~BIT(port); 616 617 if (ksz9477_set_vlan_table(dev, vid, vlan_table)) { 618 dev_dbg(dev->dev, "Failed to set vlan table\n"); 619 return -ETIMEDOUT; 620 } 621 } 622 623 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid); 624 625 return 0; 626 } 627 628 static int ksz9477_port_fdb_add(struct dsa_switch *ds, int port, 629 const unsigned char *addr, u16 vid) 630 { 631 struct ksz_device *dev = ds->priv; 632 u32 alu_table[4]; 633 u32 data; 634 int ret = 0; 635 636 mutex_lock(&dev->alu_mutex); 637 638 /* find any entry with mac & vid */ 639 data = vid << ALU_FID_INDEX_S; 640 data |= ((addr[0] << 8) | addr[1]); 641 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 642 643 data = ((addr[2] << 24) | (addr[3] << 16)); 644 data |= ((addr[4] << 8) | addr[5]); 645 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 646 647 /* start read operation */ 648 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 649 650 /* wait to be finished */ 651 ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000); 652 if (ret < 0) { 653 dev_dbg(dev->dev, "Failed to read ALU\n"); 654 goto exit; 655 } 656 657 /* read ALU entry */ 658 ksz9477_read_table(dev, alu_table); 659 660 /* update ALU entry */ 661 alu_table[0] = ALU_V_STATIC_VALID; 662 alu_table[1] |= BIT(port); 663 if (vid) 664 alu_table[1] |= ALU_V_USE_FID; 665 alu_table[2] = (vid << ALU_V_FID_S); 666 alu_table[2] |= ((addr[0] << 8) | addr[1]); 667 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16)); 668 alu_table[3] |= ((addr[4] << 8) | addr[5]); 669 670 ksz9477_write_table(dev, alu_table); 671 672 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 673 674 /* wait to be finished */ 675 ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000); 676 if (ret < 0) 677 dev_dbg(dev->dev, "Failed to write ALU\n"); 678 679 exit: 680 mutex_unlock(&dev->alu_mutex); 681 682 return ret; 683 } 684 685 static int ksz9477_port_fdb_del(struct dsa_switch *ds, int port, 686 const unsigned char *addr, u16 vid) 687 { 688 struct ksz_device *dev = ds->priv; 689 u32 alu_table[4]; 690 u32 data; 691 int ret = 0; 692 693 mutex_lock(&dev->alu_mutex); 694 695 /* read any entry with mac & vid */ 696 data = vid << ALU_FID_INDEX_S; 697 data |= ((addr[0] << 8) | addr[1]); 698 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 699 700 data = ((addr[2] << 24) | (addr[3] << 16)); 701 data |= ((addr[4] << 8) | addr[5]); 702 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 703 704 /* start read operation */ 705 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 706 707 /* wait to be finished */ 708 ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000); 709 if (ret < 0) { 710 dev_dbg(dev->dev, "Failed to read ALU\n"); 711 goto exit; 712 } 713 714 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]); 715 if (alu_table[0] & ALU_V_STATIC_VALID) { 716 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]); 717 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]); 718 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]); 719 720 /* clear forwarding port */ 721 alu_table[2] &= ~BIT(port); 722 723 /* if there is no port to forward, clear table */ 724 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) { 725 alu_table[0] = 0; 726 alu_table[1] = 0; 727 alu_table[2] = 0; 728 alu_table[3] = 0; 729 } 730 } else { 731 alu_table[0] = 0; 732 alu_table[1] = 0; 733 alu_table[2] = 0; 734 alu_table[3] = 0; 735 } 736 737 ksz9477_write_table(dev, alu_table); 738 739 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 740 741 /* wait to be finished */ 742 ret = ksz9477_wait_alu_ready(dev, ALU_START, 1000); 743 if (ret < 0) 744 dev_dbg(dev->dev, "Failed to write ALU\n"); 745 746 exit: 747 mutex_unlock(&dev->alu_mutex); 748 749 return ret; 750 } 751 752 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table) 753 { 754 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID); 755 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER); 756 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER); 757 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) & 758 ALU_V_PRIO_AGE_CNT_M; 759 alu->mstp = alu_table[0] & ALU_V_MSTP_M; 760 761 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE); 762 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID); 763 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP; 764 765 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M; 766 767 alu->mac[0] = (alu_table[2] >> 8) & 0xFF; 768 alu->mac[1] = alu_table[2] & 0xFF; 769 alu->mac[2] = (alu_table[3] >> 24) & 0xFF; 770 alu->mac[3] = (alu_table[3] >> 16) & 0xFF; 771 alu->mac[4] = (alu_table[3] >> 8) & 0xFF; 772 alu->mac[5] = alu_table[3] & 0xFF; 773 } 774 775 static int ksz9477_port_fdb_dump(struct dsa_switch *ds, int port, 776 dsa_fdb_dump_cb_t *cb, void *data) 777 { 778 struct ksz_device *dev = ds->priv; 779 int ret = 0; 780 u32 ksz_data; 781 u32 alu_table[4]; 782 struct alu_struct alu; 783 int timeout; 784 785 mutex_lock(&dev->alu_mutex); 786 787 /* start ALU search */ 788 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH); 789 790 do { 791 timeout = 1000; 792 do { 793 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data); 794 if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START)) 795 break; 796 usleep_range(1, 10); 797 } while (timeout-- > 0); 798 799 if (!timeout) { 800 dev_dbg(dev->dev, "Failed to search ALU\n"); 801 ret = -ETIMEDOUT; 802 goto exit; 803 } 804 805 /* read ALU table */ 806 ksz9477_read_table(dev, alu_table); 807 808 ksz9477_convert_alu(&alu, alu_table); 809 810 if (alu.port_forward & BIT(port)) { 811 ret = cb(alu.mac, alu.fid, alu.is_static, data); 812 if (ret) 813 goto exit; 814 } 815 } while (ksz_data & ALU_START); 816 817 exit: 818 819 /* stop ALU search */ 820 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0); 821 822 mutex_unlock(&dev->alu_mutex); 823 824 return ret; 825 } 826 827 static void ksz9477_port_mdb_add(struct dsa_switch *ds, int port, 828 const struct switchdev_obj_port_mdb *mdb) 829 { 830 struct ksz_device *dev = ds->priv; 831 u32 static_table[4]; 832 u32 data; 833 int index; 834 u32 mac_hi, mac_lo; 835 836 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 837 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 838 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 839 840 mutex_lock(&dev->alu_mutex); 841 842 for (index = 0; index < dev->num_statics; index++) { 843 /* find empty slot first */ 844 data = (index << ALU_STAT_INDEX_S) | 845 ALU_STAT_READ | ALU_STAT_START; 846 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 847 848 /* wait to be finished */ 849 if (ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000) < 0) { 850 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 851 goto exit; 852 } 853 854 /* read ALU static table */ 855 ksz9477_read_table(dev, static_table); 856 857 if (static_table[0] & ALU_V_STATIC_VALID) { 858 /* check this has same vid & mac address */ 859 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 860 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 861 static_table[3] == mac_lo) { 862 /* found matching one */ 863 break; 864 } 865 } else { 866 /* found empty one */ 867 break; 868 } 869 } 870 871 /* no available entry */ 872 if (index == dev->num_statics) 873 goto exit; 874 875 /* add entry */ 876 static_table[0] = ALU_V_STATIC_VALID; 877 static_table[1] |= BIT(port); 878 if (mdb->vid) 879 static_table[1] |= ALU_V_USE_FID; 880 static_table[2] = (mdb->vid << ALU_V_FID_S); 881 static_table[2] |= mac_hi; 882 static_table[3] = mac_lo; 883 884 ksz9477_write_table(dev, static_table); 885 886 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 887 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 888 889 /* wait to be finished */ 890 if (ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000) < 0) 891 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 892 893 exit: 894 mutex_unlock(&dev->alu_mutex); 895 } 896 897 static int ksz9477_port_mdb_del(struct dsa_switch *ds, int port, 898 const struct switchdev_obj_port_mdb *mdb) 899 { 900 struct ksz_device *dev = ds->priv; 901 u32 static_table[4]; 902 u32 data; 903 int index; 904 int ret = 0; 905 u32 mac_hi, mac_lo; 906 907 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 908 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 909 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 910 911 mutex_lock(&dev->alu_mutex); 912 913 for (index = 0; index < dev->num_statics; index++) { 914 /* find empty slot first */ 915 data = (index << ALU_STAT_INDEX_S) | 916 ALU_STAT_READ | ALU_STAT_START; 917 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 918 919 /* wait to be finished */ 920 ret = ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000); 921 if (ret < 0) { 922 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 923 goto exit; 924 } 925 926 /* read ALU static table */ 927 ksz9477_read_table(dev, static_table); 928 929 if (static_table[0] & ALU_V_STATIC_VALID) { 930 /* check this has same vid & mac address */ 931 932 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 933 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 934 static_table[3] == mac_lo) { 935 /* found matching one */ 936 break; 937 } 938 } 939 } 940 941 /* no available entry */ 942 if (index == dev->num_statics) 943 goto exit; 944 945 /* clear port */ 946 static_table[1] &= ~BIT(port); 947 948 if ((static_table[1] & ALU_V_PORT_MAP) == 0) { 949 /* delete entry */ 950 static_table[0] = 0; 951 static_table[1] = 0; 952 static_table[2] = 0; 953 static_table[3] = 0; 954 } 955 956 ksz9477_write_table(dev, static_table); 957 958 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START; 959 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 960 961 /* wait to be finished */ 962 ret = ksz9477_wait_alu_sta_ready(dev, ALU_STAT_START, 1000); 963 if (ret < 0) 964 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 965 966 exit: 967 mutex_unlock(&dev->alu_mutex); 968 969 return ret; 970 } 971 972 static int ksz9477_port_mirror_add(struct dsa_switch *ds, int port, 973 struct dsa_mall_mirror_tc_entry *mirror, 974 bool ingress) 975 { 976 struct ksz_device *dev = ds->priv; 977 978 if (ingress) 979 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 980 else 981 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 982 983 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false); 984 985 /* configure mirror port */ 986 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 987 PORT_MIRROR_SNIFFER, true); 988 989 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 990 991 return 0; 992 } 993 994 static void ksz9477_port_mirror_del(struct dsa_switch *ds, int port, 995 struct dsa_mall_mirror_tc_entry *mirror) 996 { 997 struct ksz_device *dev = ds->priv; 998 u8 data; 999 1000 if (mirror->ingress) 1001 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 1002 else 1003 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 1004 1005 ksz_pread8(dev, port, P_MIRROR_CTRL, &data); 1006 1007 if (!(data & (PORT_MIRROR_RX | PORT_MIRROR_TX))) 1008 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1009 PORT_MIRROR_SNIFFER, false); 1010 } 1011 1012 static void ksz9477_phy_setup(struct ksz_device *dev, int port, 1013 struct phy_device *phy) 1014 { 1015 /* Only apply to port with PHY. */ 1016 if (port >= dev->phy_port_cnt) 1017 return; 1018 1019 /* The MAC actually cannot run in 1000 half-duplex mode. */ 1020 phy_remove_link_mode(phy, 1021 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1022 1023 /* PHY does not support gigabit. */ 1024 if (!(dev->features & GBIT_SUPPORT)) 1025 phy_remove_link_mode(phy, 1026 ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 1027 } 1028 1029 static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data) 1030 { 1031 bool gbit; 1032 1033 if (dev->features & NEW_XMII) 1034 gbit = !(data & PORT_MII_NOT_1GBIT); 1035 else 1036 gbit = !!(data & PORT_MII_1000MBIT_S1); 1037 return gbit; 1038 } 1039 1040 static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data) 1041 { 1042 if (dev->features & NEW_XMII) { 1043 if (gbit) 1044 *data &= ~PORT_MII_NOT_1GBIT; 1045 else 1046 *data |= PORT_MII_NOT_1GBIT; 1047 } else { 1048 if (gbit) 1049 *data |= PORT_MII_1000MBIT_S1; 1050 else 1051 *data &= ~PORT_MII_1000MBIT_S1; 1052 } 1053 } 1054 1055 static int ksz9477_get_xmii(struct ksz_device *dev, u8 data) 1056 { 1057 int mode; 1058 1059 if (dev->features & NEW_XMII) { 1060 switch (data & PORT_MII_SEL_M) { 1061 case PORT_MII_SEL: 1062 mode = 0; 1063 break; 1064 case PORT_RMII_SEL: 1065 mode = 1; 1066 break; 1067 case PORT_GMII_SEL: 1068 mode = 2; 1069 break; 1070 default: 1071 mode = 3; 1072 } 1073 } else { 1074 switch (data & PORT_MII_SEL_M) { 1075 case PORT_MII_SEL_S1: 1076 mode = 0; 1077 break; 1078 case PORT_RMII_SEL_S1: 1079 mode = 1; 1080 break; 1081 case PORT_GMII_SEL_S1: 1082 mode = 2; 1083 break; 1084 default: 1085 mode = 3; 1086 } 1087 } 1088 return mode; 1089 } 1090 1091 static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data) 1092 { 1093 u8 xmii; 1094 1095 if (dev->features & NEW_XMII) { 1096 switch (mode) { 1097 case 0: 1098 xmii = PORT_MII_SEL; 1099 break; 1100 case 1: 1101 xmii = PORT_RMII_SEL; 1102 break; 1103 case 2: 1104 xmii = PORT_GMII_SEL; 1105 break; 1106 default: 1107 xmii = PORT_RGMII_SEL; 1108 break; 1109 } 1110 } else { 1111 switch (mode) { 1112 case 0: 1113 xmii = PORT_MII_SEL_S1; 1114 break; 1115 case 1: 1116 xmii = PORT_RMII_SEL_S1; 1117 break; 1118 case 2: 1119 xmii = PORT_GMII_SEL_S1; 1120 break; 1121 default: 1122 xmii = PORT_RGMII_SEL_S1; 1123 break; 1124 } 1125 } 1126 *data &= ~PORT_MII_SEL_M; 1127 *data |= xmii; 1128 } 1129 1130 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port) 1131 { 1132 phy_interface_t interface; 1133 bool gbit; 1134 int mode; 1135 u8 data8; 1136 1137 if (port < dev->phy_port_cnt) 1138 return PHY_INTERFACE_MODE_NA; 1139 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 1140 gbit = ksz9477_get_gbit(dev, data8); 1141 mode = ksz9477_get_xmii(dev, data8); 1142 switch (mode) { 1143 case 2: 1144 interface = PHY_INTERFACE_MODE_GMII; 1145 if (gbit) 1146 break; 1147 /* fall through */ 1148 case 0: 1149 interface = PHY_INTERFACE_MODE_MII; 1150 break; 1151 case 1: 1152 interface = PHY_INTERFACE_MODE_RMII; 1153 break; 1154 default: 1155 interface = PHY_INTERFACE_MODE_RGMII; 1156 if (data8 & PORT_RGMII_ID_EG_ENABLE) 1157 interface = PHY_INTERFACE_MODE_RGMII_TXID; 1158 if (data8 & PORT_RGMII_ID_IG_ENABLE) { 1159 interface = PHY_INTERFACE_MODE_RGMII_RXID; 1160 if (data8 & PORT_RGMII_ID_EG_ENABLE) 1161 interface = PHY_INTERFACE_MODE_RGMII_ID; 1162 } 1163 break; 1164 } 1165 return interface; 1166 } 1167 1168 static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1169 { 1170 u8 data8; 1171 u8 member; 1172 u16 data16; 1173 struct ksz_port *p = &dev->ports[port]; 1174 1175 /* enable tag tail for host port */ 1176 if (cpu_port) 1177 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE, 1178 true); 1179 1180 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false); 1181 1182 /* set back pressure */ 1183 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true); 1184 1185 /* enable broadcast storm limit */ 1186 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 1187 1188 /* disable DiffServ priority */ 1189 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false); 1190 1191 /* replace priority */ 1192 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING, 1193 false); 1194 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4, 1195 MTI_PVID_REPLACE, false); 1196 1197 /* enable 802.1p priority */ 1198 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); 1199 1200 if (port < dev->phy_port_cnt) { 1201 /* do not force flow control */ 1202 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1203 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1204 false); 1205 1206 } else { 1207 /* force flow control */ 1208 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 1209 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 1210 true); 1211 1212 /* configure MAC to 1G & RGMII mode */ 1213 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); 1214 switch (dev->interface) { 1215 case PHY_INTERFACE_MODE_MII: 1216 ksz9477_set_xmii(dev, 0, &data8); 1217 ksz9477_set_gbit(dev, false, &data8); 1218 p->phydev.speed = SPEED_100; 1219 break; 1220 case PHY_INTERFACE_MODE_RMII: 1221 ksz9477_set_xmii(dev, 1, &data8); 1222 ksz9477_set_gbit(dev, false, &data8); 1223 p->phydev.speed = SPEED_100; 1224 break; 1225 case PHY_INTERFACE_MODE_GMII: 1226 ksz9477_set_xmii(dev, 2, &data8); 1227 ksz9477_set_gbit(dev, true, &data8); 1228 p->phydev.speed = SPEED_1000; 1229 break; 1230 default: 1231 ksz9477_set_xmii(dev, 3, &data8); 1232 ksz9477_set_gbit(dev, true, &data8); 1233 data8 &= ~PORT_RGMII_ID_IG_ENABLE; 1234 data8 &= ~PORT_RGMII_ID_EG_ENABLE; 1235 if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID || 1236 dev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 1237 data8 |= PORT_RGMII_ID_IG_ENABLE; 1238 if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID || 1239 dev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1240 data8 |= PORT_RGMII_ID_EG_ENABLE; 1241 p->phydev.speed = SPEED_1000; 1242 break; 1243 } 1244 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8); 1245 p->phydev.duplex = 1; 1246 } 1247 mutex_lock(&dev->dev_mutex); 1248 if (cpu_port) { 1249 member = dev->port_mask; 1250 dev->on_ports = dev->host_mask; 1251 dev->live_ports = dev->host_mask; 1252 } else { 1253 member = dev->host_mask | p->vid_member; 1254 dev->on_ports |= (1 << port); 1255 1256 /* Link was detected before port is enabled. */ 1257 if (p->phydev.link) 1258 dev->live_ports |= (1 << port); 1259 } 1260 mutex_unlock(&dev->dev_mutex); 1261 ksz9477_cfg_port_member(dev, port, member); 1262 1263 /* clear pending interrupts */ 1264 if (port < dev->phy_port_cnt) 1265 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16); 1266 } 1267 1268 static void ksz9477_config_cpu_port(struct dsa_switch *ds) 1269 { 1270 struct ksz_device *dev = ds->priv; 1271 struct ksz_port *p; 1272 int i; 1273 1274 ds->num_ports = dev->port_cnt; 1275 1276 for (i = 0; i < dev->port_cnt; i++) { 1277 if (dsa_is_cpu_port(ds, i) && (dev->cpu_ports & (1 << i))) { 1278 phy_interface_t interface; 1279 1280 dev->cpu_port = i; 1281 dev->host_mask = (1 << dev->cpu_port); 1282 dev->port_mask |= dev->host_mask; 1283 1284 /* Read from XMII register to determine host port 1285 * interface. If set specifically in device tree 1286 * note the difference to help debugging. 1287 */ 1288 interface = ksz9477_get_interface(dev, i); 1289 if (!dev->interface) 1290 dev->interface = interface; 1291 if (interface && interface != dev->interface) 1292 dev_info(dev->dev, 1293 "use %s instead of %s\n", 1294 phy_modes(dev->interface), 1295 phy_modes(interface)); 1296 1297 /* enable cpu port */ 1298 ksz9477_port_setup(dev, i, true); 1299 p = &dev->ports[dev->cpu_port]; 1300 p->vid_member = dev->port_mask; 1301 p->on = 1; 1302 } 1303 } 1304 1305 dev->member = dev->host_mask; 1306 1307 for (i = 0; i < dev->mib_port_cnt; i++) { 1308 if (i == dev->cpu_port) 1309 continue; 1310 p = &dev->ports[i]; 1311 1312 /* Initialize to non-zero so that ksz_cfg_port_member() will 1313 * be called. 1314 */ 1315 p->vid_member = (1 << i); 1316 p->member = dev->port_mask; 1317 ksz9477_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1318 p->on = 1; 1319 if (i < dev->phy_port_cnt) 1320 p->phy = 1; 1321 if (dev->chip_id == 0x00947700 && i == 6) { 1322 p->sgmii = 1; 1323 1324 /* SGMII PHY detection code is not implemented yet. */ 1325 p->phy = 0; 1326 } 1327 } 1328 } 1329 1330 static int ksz9477_setup(struct dsa_switch *ds) 1331 { 1332 struct ksz_device *dev = ds->priv; 1333 int ret = 0; 1334 1335 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 1336 dev->num_vlans, GFP_KERNEL); 1337 if (!dev->vlan_cache) 1338 return -ENOMEM; 1339 1340 ret = ksz9477_reset_switch(dev); 1341 if (ret) { 1342 dev_err(ds->dev, "failed to reset switch\n"); 1343 return ret; 1344 } 1345 1346 /* Required for port partitioning. */ 1347 ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, 1348 true); 1349 1350 /* Do not work correctly with tail tagging. */ 1351 ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false); 1352 1353 /* accept packet up to 2000bytes */ 1354 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_LEGAL_PACKET_DISABLE, true); 1355 1356 ksz9477_config_cpu_port(ds); 1357 1358 ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true); 1359 1360 /* queue based egress rate limit */ 1361 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true); 1362 1363 /* enable global MIB counter freeze function */ 1364 ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); 1365 1366 /* start switch */ 1367 ksz_cfg(dev, REG_SW_OPERATION, SW_START, true); 1368 1369 ksz_init_mib_timer(dev); 1370 1371 return 0; 1372 } 1373 1374 static const struct dsa_switch_ops ksz9477_switch_ops = { 1375 .get_tag_protocol = ksz9477_get_tag_protocol, 1376 .setup = ksz9477_setup, 1377 .phy_read = ksz9477_phy_read16, 1378 .phy_write = ksz9477_phy_write16, 1379 .adjust_link = ksz_adjust_link, 1380 .port_enable = ksz_enable_port, 1381 .port_disable = ksz_disable_port, 1382 .get_strings = ksz9477_get_strings, 1383 .get_ethtool_stats = ksz_get_ethtool_stats, 1384 .get_sset_count = ksz_sset_count, 1385 .port_bridge_join = ksz_port_bridge_join, 1386 .port_bridge_leave = ksz_port_bridge_leave, 1387 .port_stp_state_set = ksz9477_port_stp_state_set, 1388 .port_fast_age = ksz_port_fast_age, 1389 .port_vlan_filtering = ksz9477_port_vlan_filtering, 1390 .port_vlan_prepare = ksz_port_vlan_prepare, 1391 .port_vlan_add = ksz9477_port_vlan_add, 1392 .port_vlan_del = ksz9477_port_vlan_del, 1393 .port_fdb_dump = ksz9477_port_fdb_dump, 1394 .port_fdb_add = ksz9477_port_fdb_add, 1395 .port_fdb_del = ksz9477_port_fdb_del, 1396 .port_mdb_prepare = ksz_port_mdb_prepare, 1397 .port_mdb_add = ksz9477_port_mdb_add, 1398 .port_mdb_del = ksz9477_port_mdb_del, 1399 .port_mirror_add = ksz9477_port_mirror_add, 1400 .port_mirror_del = ksz9477_port_mirror_del, 1401 }; 1402 1403 static u32 ksz9477_get_port_addr(int port, int offset) 1404 { 1405 return PORT_CTRL_ADDR(port, offset); 1406 } 1407 1408 static int ksz9477_switch_detect(struct ksz_device *dev) 1409 { 1410 u8 data8; 1411 u8 id_hi; 1412 u8 id_lo; 1413 u32 id32; 1414 int ret; 1415 1416 /* turn off SPI DO Edge select */ 1417 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 1418 if (ret) 1419 return ret; 1420 1421 data8 &= ~SPI_AUTO_EDGE_DETECTION; 1422 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 1423 if (ret) 1424 return ret; 1425 1426 /* read chip id */ 1427 ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32); 1428 if (ret) 1429 return ret; 1430 ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8); 1431 if (ret) 1432 return ret; 1433 1434 /* Number of ports can be reduced depending on chip. */ 1435 dev->mib_port_cnt = TOTAL_PORT_NUM; 1436 dev->phy_port_cnt = 5; 1437 1438 /* Default capability is gigabit capable. */ 1439 dev->features = GBIT_SUPPORT; 1440 1441 id_hi = (u8)(id32 >> 16); 1442 id_lo = (u8)(id32 >> 8); 1443 if ((id_lo & 0xf) == 3) { 1444 /* Chip is from KSZ9893 design. */ 1445 dev->features |= IS_9893; 1446 1447 /* Chip does not support gigabit. */ 1448 if (data8 & SW_QW_ABLE) 1449 dev->features &= ~GBIT_SUPPORT; 1450 dev->mib_port_cnt = 3; 1451 dev->phy_port_cnt = 2; 1452 } else { 1453 /* Chip uses new XMII register definitions. */ 1454 dev->features |= NEW_XMII; 1455 1456 /* Chip does not support gigabit. */ 1457 if (!(data8 & SW_GIGABIT_ABLE)) 1458 dev->features &= ~GBIT_SUPPORT; 1459 } 1460 1461 /* Change chip id to known ones so it can be matched against them. */ 1462 id32 = (id_hi << 16) | (id_lo << 8); 1463 1464 dev->chip_id = id32; 1465 1466 return 0; 1467 } 1468 1469 struct ksz_chip_data { 1470 u32 chip_id; 1471 const char *dev_name; 1472 int num_vlans; 1473 int num_alus; 1474 int num_statics; 1475 int cpu_ports; 1476 int port_cnt; 1477 }; 1478 1479 static const struct ksz_chip_data ksz9477_switch_chips[] = { 1480 { 1481 .chip_id = 0x00947700, 1482 .dev_name = "KSZ9477", 1483 .num_vlans = 4096, 1484 .num_alus = 4096, 1485 .num_statics = 16, 1486 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1487 .port_cnt = 7, /* total physical port count */ 1488 }, 1489 { 1490 .chip_id = 0x00989700, 1491 .dev_name = "KSZ9897", 1492 .num_vlans = 4096, 1493 .num_alus = 4096, 1494 .num_statics = 16, 1495 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1496 .port_cnt = 7, /* total physical port count */ 1497 }, 1498 { 1499 .chip_id = 0x00989300, 1500 .dev_name = "KSZ9893", 1501 .num_vlans = 4096, 1502 .num_alus = 4096, 1503 .num_statics = 16, 1504 .cpu_ports = 0x07, /* can be configured as cpu port */ 1505 .port_cnt = 3, /* total port count */ 1506 }, 1507 }; 1508 1509 static int ksz9477_switch_init(struct ksz_device *dev) 1510 { 1511 int i; 1512 1513 dev->ds->ops = &ksz9477_switch_ops; 1514 1515 for (i = 0; i < ARRAY_SIZE(ksz9477_switch_chips); i++) { 1516 const struct ksz_chip_data *chip = &ksz9477_switch_chips[i]; 1517 1518 if (dev->chip_id == chip->chip_id) { 1519 dev->name = chip->dev_name; 1520 dev->num_vlans = chip->num_vlans; 1521 dev->num_alus = chip->num_alus; 1522 dev->num_statics = chip->num_statics; 1523 dev->port_cnt = chip->port_cnt; 1524 dev->cpu_ports = chip->cpu_ports; 1525 1526 break; 1527 } 1528 } 1529 1530 /* no switch found */ 1531 if (!dev->port_cnt) 1532 return -ENODEV; 1533 1534 dev->port_mask = (1 << dev->port_cnt) - 1; 1535 1536 dev->reg_mib_cnt = SWITCH_COUNTER_NUM; 1537 dev->mib_cnt = TOTAL_SWITCH_COUNTER_NUM; 1538 1539 i = dev->mib_port_cnt; 1540 dev->ports = devm_kzalloc(dev->dev, sizeof(struct ksz_port) * i, 1541 GFP_KERNEL); 1542 if (!dev->ports) 1543 return -ENOMEM; 1544 for (i = 0; i < dev->mib_port_cnt; i++) { 1545 mutex_init(&dev->ports[i].mib.cnt_mutex); 1546 dev->ports[i].mib.counters = 1547 devm_kzalloc(dev->dev, 1548 sizeof(u64) * 1549 (TOTAL_SWITCH_COUNTER_NUM + 1), 1550 GFP_KERNEL); 1551 if (!dev->ports[i].mib.counters) 1552 return -ENOMEM; 1553 } 1554 1555 return 0; 1556 } 1557 1558 static void ksz9477_switch_exit(struct ksz_device *dev) 1559 { 1560 ksz9477_reset_switch(dev); 1561 } 1562 1563 static const struct ksz_dev_ops ksz9477_dev_ops = { 1564 .get_port_addr = ksz9477_get_port_addr, 1565 .cfg_port_member = ksz9477_cfg_port_member, 1566 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 1567 .phy_setup = ksz9477_phy_setup, 1568 .port_setup = ksz9477_port_setup, 1569 .r_mib_cnt = ksz9477_r_mib_cnt, 1570 .r_mib_pkt = ksz9477_r_mib_pkt, 1571 .freeze_mib = ksz9477_freeze_mib, 1572 .port_init_cnt = ksz9477_port_init_cnt, 1573 .shutdown = ksz9477_reset_switch, 1574 .detect = ksz9477_switch_detect, 1575 .init = ksz9477_switch_init, 1576 .exit = ksz9477_switch_exit, 1577 }; 1578 1579 int ksz9477_switch_register(struct ksz_device *dev) 1580 { 1581 return ksz_switch_register(dev, &ksz9477_dev_ops); 1582 } 1583 EXPORT_SYMBOL(ksz9477_switch_register); 1584 1585 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 1586 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver"); 1587 MODULE_LICENSE("GPL"); 1588