1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ9477 switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/iopoll.h> 11 #include <linux/platform_data/microchip-ksz.h> 12 #include <linux/phy.h> 13 #include <linux/if_bridge.h> 14 #include <linux/if_vlan.h> 15 #include <net/dsa.h> 16 #include <net/switchdev.h> 17 18 #include "ksz9477_reg.h" 19 #include "ksz_common.h" 20 #include "ksz9477.h" 21 22 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 23 { 24 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0); 25 } 26 27 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 28 bool set) 29 { 30 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset), 31 bits, set ? bits : 0); 32 } 33 34 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set) 35 { 36 regmap_update_bits(dev->regmap[2], addr, bits, set ? bits : 0); 37 } 38 39 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset, 40 u32 bits, bool set) 41 { 42 regmap_update_bits(dev->regmap[2], PORT_CTRL_ADDR(port, offset), 43 bits, set ? bits : 0); 44 } 45 46 int ksz9477_change_mtu(struct ksz_device *dev, int port, int mtu) 47 { 48 u16 frame_size, max_frame = 0; 49 int i; 50 51 frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 52 53 /* Cache the per-port MTU setting */ 54 dev->ports[port].max_frame = frame_size; 55 56 for (i = 0; i < dev->info->port_cnt; i++) 57 max_frame = max(max_frame, dev->ports[i].max_frame); 58 59 return regmap_update_bits(dev->regmap[1], REG_SW_MTU__2, 60 REG_SW_MTU_MASK, max_frame); 61 } 62 63 int ksz9477_max_mtu(struct ksz_device *dev, int port) 64 { 65 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 66 } 67 68 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev) 69 { 70 unsigned int val; 71 72 return regmap_read_poll_timeout(dev->regmap[0], REG_SW_VLAN_CTRL, 73 val, !(val & VLAN_START), 10, 1000); 74 } 75 76 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid, 77 u32 *vlan_table) 78 { 79 int ret; 80 81 mutex_lock(&dev->vlan_mutex); 82 83 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 84 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START); 85 86 /* wait to be cleared */ 87 ret = ksz9477_wait_vlan_ctrl_ready(dev); 88 if (ret) { 89 dev_dbg(dev->dev, "Failed to read vlan table\n"); 90 goto exit; 91 } 92 93 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]); 94 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]); 95 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]); 96 97 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 98 99 exit: 100 mutex_unlock(&dev->vlan_mutex); 101 102 return ret; 103 } 104 105 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid, 106 u32 *vlan_table) 107 { 108 int ret; 109 110 mutex_lock(&dev->vlan_mutex); 111 112 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]); 113 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]); 114 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]); 115 116 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 117 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE); 118 119 /* wait to be cleared */ 120 ret = ksz9477_wait_vlan_ctrl_ready(dev); 121 if (ret) { 122 dev_dbg(dev->dev, "Failed to write vlan table\n"); 123 goto exit; 124 } 125 126 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 127 128 /* update vlan cache table */ 129 dev->vlan_cache[vid].table[0] = vlan_table[0]; 130 dev->vlan_cache[vid].table[1] = vlan_table[1]; 131 dev->vlan_cache[vid].table[2] = vlan_table[2]; 132 133 exit: 134 mutex_unlock(&dev->vlan_mutex); 135 136 return ret; 137 } 138 139 static void ksz9477_read_table(struct ksz_device *dev, u32 *table) 140 { 141 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]); 142 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]); 143 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]); 144 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]); 145 } 146 147 static void ksz9477_write_table(struct ksz_device *dev, u32 *table) 148 { 149 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]); 150 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]); 151 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]); 152 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]); 153 } 154 155 static int ksz9477_wait_alu_ready(struct ksz_device *dev) 156 { 157 unsigned int val; 158 159 return regmap_read_poll_timeout(dev->regmap[2], REG_SW_ALU_CTRL__4, 160 val, !(val & ALU_START), 10, 1000); 161 } 162 163 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev) 164 { 165 unsigned int val; 166 167 return regmap_read_poll_timeout(dev->regmap[2], 168 REG_SW_ALU_STAT_CTRL__4, 169 val, !(val & ALU_STAT_START), 170 10, 1000); 171 } 172 173 int ksz9477_reset_switch(struct ksz_device *dev) 174 { 175 u8 data8; 176 u32 data32; 177 178 /* reset switch */ 179 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 180 181 /* turn off SPI DO Edge select */ 182 regmap_update_bits(dev->regmap[0], REG_SW_GLOBAL_SERIAL_CTRL_0, 183 SPI_AUTO_EDGE_DETECTION, 0); 184 185 /* default configuration */ 186 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8); 187 data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING | 188 SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE; 189 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8); 190 191 /* disable interrupts */ 192 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 193 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F); 194 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 195 196 data8 = SW_ENABLE_REFCLKO; 197 if (dev->synclko_disable) 198 data8 = 0; 199 else if (dev->synclko_125) 200 data8 = SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ; 201 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, data8); 202 203 return 0; 204 } 205 206 void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt) 207 { 208 struct ksz_port *p = &dev->ports[port]; 209 unsigned int val; 210 u32 data; 211 int ret; 212 213 /* retain the flush/freeze bit */ 214 data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 215 data |= MIB_COUNTER_READ; 216 data |= (addr << MIB_COUNTER_INDEX_S); 217 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data); 218 219 ret = regmap_read_poll_timeout(dev->regmap[2], 220 PORT_CTRL_ADDR(port, REG_PORT_MIB_CTRL_STAT__4), 221 val, !(val & MIB_COUNTER_READ), 10, 1000); 222 /* failed to read MIB. get out of loop */ 223 if (ret) { 224 dev_dbg(dev->dev, "Failed to get MIB\n"); 225 return; 226 } 227 228 /* count resets upon read */ 229 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data); 230 *cnt += data; 231 } 232 233 void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 234 u64 *dropped, u64 *cnt) 235 { 236 addr = dev->info->mib_names[addr].index; 237 ksz9477_r_mib_cnt(dev, port, addr, cnt); 238 } 239 240 void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze) 241 { 242 u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 243 struct ksz_port *p = &dev->ports[port]; 244 245 /* enable/disable the port for flush/freeze function */ 246 mutex_lock(&p->mib.cnt_mutex); 247 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val); 248 249 /* used by MIB counter reading code to know freeze is enabled */ 250 p->freeze = freeze; 251 mutex_unlock(&p->mib.cnt_mutex); 252 } 253 254 void ksz9477_port_init_cnt(struct ksz_device *dev, int port) 255 { 256 struct ksz_port_mib *mib = &dev->ports[port].mib; 257 258 /* flush all enabled port MIB counters */ 259 mutex_lock(&mib->cnt_mutex); 260 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 261 MIB_COUNTER_FLUSH_FREEZE); 262 ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH); 263 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0); 264 mutex_unlock(&mib->cnt_mutex); 265 } 266 267 void ksz9477_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data) 268 { 269 u16 val = 0xffff; 270 271 /* No real PHY after this. Simulate the PHY. 272 * A fixed PHY can be setup in the device tree, but this function is 273 * still called for that port during initialization. 274 * For RGMII PHY there is no way to access it so the fixed PHY should 275 * be used. For SGMII PHY the supporting code will be added later. 276 */ 277 if (addr >= dev->phy_port_cnt) { 278 struct ksz_port *p = &dev->ports[addr]; 279 280 switch (reg) { 281 case MII_BMCR: 282 val = 0x1140; 283 break; 284 case MII_BMSR: 285 val = 0x796d; 286 break; 287 case MII_PHYSID1: 288 val = 0x0022; 289 break; 290 case MII_PHYSID2: 291 val = 0x1631; 292 break; 293 case MII_ADVERTISE: 294 val = 0x05e1; 295 break; 296 case MII_LPA: 297 val = 0xc5e1; 298 break; 299 case MII_CTRL1000: 300 val = 0x0700; 301 break; 302 case MII_STAT1000: 303 if (p->phydev.speed == SPEED_1000) 304 val = 0x3800; 305 else 306 val = 0; 307 break; 308 } 309 } else { 310 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val); 311 } 312 313 *data = val; 314 } 315 316 void ksz9477_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val) 317 { 318 /* No real PHY after this. */ 319 if (addr >= dev->phy_port_cnt) 320 return; 321 322 /* No gigabit support. Do not write to this register. */ 323 if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000) 324 return; 325 326 ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val); 327 } 328 329 void ksz9477_cfg_port_member(struct ksz_device *dev, int port, u8 member) 330 { 331 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member); 332 } 333 334 void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port) 335 { 336 const u16 *regs = dev->info->regs; 337 u8 data; 338 339 regmap_update_bits(dev->regmap[0], REG_SW_LUE_CTRL_2, 340 SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S, 341 SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S); 342 343 if (port < dev->info->port_cnt) { 344 /* flush individual port */ 345 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 346 if (!(data & PORT_LEARN_DISABLE)) 347 ksz_pwrite8(dev, port, regs[P_STP_CTRL], 348 data | PORT_LEARN_DISABLE); 349 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 350 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 351 } else { 352 /* flush all */ 353 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true); 354 } 355 } 356 357 int ksz9477_port_vlan_filtering(struct ksz_device *dev, int port, 358 bool flag, struct netlink_ext_ack *extack) 359 { 360 if (flag) { 361 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 362 PORT_VLAN_LOOKUP_VID_0, true); 363 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true); 364 } else { 365 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false); 366 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 367 PORT_VLAN_LOOKUP_VID_0, false); 368 } 369 370 return 0; 371 } 372 373 int ksz9477_port_vlan_add(struct ksz_device *dev, int port, 374 const struct switchdev_obj_port_vlan *vlan, 375 struct netlink_ext_ack *extack) 376 { 377 u32 vlan_table[3]; 378 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 379 int err; 380 381 err = ksz9477_get_vlan_table(dev, vlan->vid, vlan_table); 382 if (err) { 383 NL_SET_ERR_MSG_MOD(extack, "Failed to get vlan table"); 384 return err; 385 } 386 387 vlan_table[0] = VLAN_VALID | (vlan->vid & VLAN_FID_M); 388 if (untagged) 389 vlan_table[1] |= BIT(port); 390 else 391 vlan_table[1] &= ~BIT(port); 392 vlan_table[1] &= ~(BIT(dev->cpu_port)); 393 394 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port); 395 396 err = ksz9477_set_vlan_table(dev, vlan->vid, vlan_table); 397 if (err) { 398 NL_SET_ERR_MSG_MOD(extack, "Failed to set vlan table"); 399 return err; 400 } 401 402 /* change PVID */ 403 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 404 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vlan->vid); 405 406 return 0; 407 } 408 409 int ksz9477_port_vlan_del(struct ksz_device *dev, int port, 410 const struct switchdev_obj_port_vlan *vlan) 411 { 412 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 413 u32 vlan_table[3]; 414 u16 pvid; 415 416 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid); 417 pvid = pvid & 0xFFF; 418 419 if (ksz9477_get_vlan_table(dev, vlan->vid, vlan_table)) { 420 dev_dbg(dev->dev, "Failed to get vlan table\n"); 421 return -ETIMEDOUT; 422 } 423 424 vlan_table[2] &= ~BIT(port); 425 426 if (pvid == vlan->vid) 427 pvid = 1; 428 429 if (untagged) 430 vlan_table[1] &= ~BIT(port); 431 432 if (ksz9477_set_vlan_table(dev, vlan->vid, vlan_table)) { 433 dev_dbg(dev->dev, "Failed to set vlan table\n"); 434 return -ETIMEDOUT; 435 } 436 437 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid); 438 439 return 0; 440 } 441 442 int ksz9477_fdb_add(struct ksz_device *dev, int port, 443 const unsigned char *addr, u16 vid, struct dsa_db db) 444 { 445 u32 alu_table[4]; 446 u32 data; 447 int ret = 0; 448 449 mutex_lock(&dev->alu_mutex); 450 451 /* find any entry with mac & vid */ 452 data = vid << ALU_FID_INDEX_S; 453 data |= ((addr[0] << 8) | addr[1]); 454 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 455 456 data = ((addr[2] << 24) | (addr[3] << 16)); 457 data |= ((addr[4] << 8) | addr[5]); 458 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 459 460 /* start read operation */ 461 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 462 463 /* wait to be finished */ 464 ret = ksz9477_wait_alu_ready(dev); 465 if (ret) { 466 dev_dbg(dev->dev, "Failed to read ALU\n"); 467 goto exit; 468 } 469 470 /* read ALU entry */ 471 ksz9477_read_table(dev, alu_table); 472 473 /* update ALU entry */ 474 alu_table[0] = ALU_V_STATIC_VALID; 475 alu_table[1] |= BIT(port); 476 if (vid) 477 alu_table[1] |= ALU_V_USE_FID; 478 alu_table[2] = (vid << ALU_V_FID_S); 479 alu_table[2] |= ((addr[0] << 8) | addr[1]); 480 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16)); 481 alu_table[3] |= ((addr[4] << 8) | addr[5]); 482 483 ksz9477_write_table(dev, alu_table); 484 485 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 486 487 /* wait to be finished */ 488 ret = ksz9477_wait_alu_ready(dev); 489 if (ret) 490 dev_dbg(dev->dev, "Failed to write ALU\n"); 491 492 exit: 493 mutex_unlock(&dev->alu_mutex); 494 495 return ret; 496 } 497 498 int ksz9477_fdb_del(struct ksz_device *dev, int port, 499 const unsigned char *addr, u16 vid, struct dsa_db db) 500 { 501 u32 alu_table[4]; 502 u32 data; 503 int ret = 0; 504 505 mutex_lock(&dev->alu_mutex); 506 507 /* read any entry with mac & vid */ 508 data = vid << ALU_FID_INDEX_S; 509 data |= ((addr[0] << 8) | addr[1]); 510 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 511 512 data = ((addr[2] << 24) | (addr[3] << 16)); 513 data |= ((addr[4] << 8) | addr[5]); 514 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 515 516 /* start read operation */ 517 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 518 519 /* wait to be finished */ 520 ret = ksz9477_wait_alu_ready(dev); 521 if (ret) { 522 dev_dbg(dev->dev, "Failed to read ALU\n"); 523 goto exit; 524 } 525 526 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]); 527 if (alu_table[0] & ALU_V_STATIC_VALID) { 528 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]); 529 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]); 530 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]); 531 532 /* clear forwarding port */ 533 alu_table[2] &= ~BIT(port); 534 535 /* if there is no port to forward, clear table */ 536 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) { 537 alu_table[0] = 0; 538 alu_table[1] = 0; 539 alu_table[2] = 0; 540 alu_table[3] = 0; 541 } 542 } else { 543 alu_table[0] = 0; 544 alu_table[1] = 0; 545 alu_table[2] = 0; 546 alu_table[3] = 0; 547 } 548 549 ksz9477_write_table(dev, alu_table); 550 551 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 552 553 /* wait to be finished */ 554 ret = ksz9477_wait_alu_ready(dev); 555 if (ret) 556 dev_dbg(dev->dev, "Failed to write ALU\n"); 557 558 exit: 559 mutex_unlock(&dev->alu_mutex); 560 561 return ret; 562 } 563 564 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table) 565 { 566 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID); 567 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER); 568 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER); 569 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) & 570 ALU_V_PRIO_AGE_CNT_M; 571 alu->mstp = alu_table[0] & ALU_V_MSTP_M; 572 573 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE); 574 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID); 575 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP; 576 577 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M; 578 579 alu->mac[0] = (alu_table[2] >> 8) & 0xFF; 580 alu->mac[1] = alu_table[2] & 0xFF; 581 alu->mac[2] = (alu_table[3] >> 24) & 0xFF; 582 alu->mac[3] = (alu_table[3] >> 16) & 0xFF; 583 alu->mac[4] = (alu_table[3] >> 8) & 0xFF; 584 alu->mac[5] = alu_table[3] & 0xFF; 585 } 586 587 int ksz9477_fdb_dump(struct ksz_device *dev, int port, 588 dsa_fdb_dump_cb_t *cb, void *data) 589 { 590 int ret = 0; 591 u32 ksz_data; 592 u32 alu_table[4]; 593 struct alu_struct alu; 594 int timeout; 595 596 mutex_lock(&dev->alu_mutex); 597 598 /* start ALU search */ 599 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH); 600 601 do { 602 timeout = 1000; 603 do { 604 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data); 605 if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START)) 606 break; 607 usleep_range(1, 10); 608 } while (timeout-- > 0); 609 610 if (!timeout) { 611 dev_dbg(dev->dev, "Failed to search ALU\n"); 612 ret = -ETIMEDOUT; 613 goto exit; 614 } 615 616 if (!(ksz_data & ALU_VALID)) 617 continue; 618 619 /* read ALU table */ 620 ksz9477_read_table(dev, alu_table); 621 622 ksz9477_convert_alu(&alu, alu_table); 623 624 if (alu.port_forward & BIT(port)) { 625 ret = cb(alu.mac, alu.fid, alu.is_static, data); 626 if (ret) 627 goto exit; 628 } 629 } while (ksz_data & ALU_START); 630 631 exit: 632 633 /* stop ALU search */ 634 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0); 635 636 mutex_unlock(&dev->alu_mutex); 637 638 return ret; 639 } 640 641 int ksz9477_mdb_add(struct ksz_device *dev, int port, 642 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 643 { 644 u32 static_table[4]; 645 const u8 *shifts; 646 const u32 *masks; 647 u32 data; 648 int index; 649 u32 mac_hi, mac_lo; 650 int err = 0; 651 652 shifts = dev->info->shifts; 653 masks = dev->info->masks; 654 655 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 656 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 657 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 658 659 mutex_lock(&dev->alu_mutex); 660 661 for (index = 0; index < dev->info->num_statics; index++) { 662 /* find empty slot first */ 663 data = (index << shifts[ALU_STAT_INDEX]) | 664 masks[ALU_STAT_READ] | ALU_STAT_START; 665 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 666 667 /* wait to be finished */ 668 err = ksz9477_wait_alu_sta_ready(dev); 669 if (err) { 670 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 671 goto exit; 672 } 673 674 /* read ALU static table */ 675 ksz9477_read_table(dev, static_table); 676 677 if (static_table[0] & ALU_V_STATIC_VALID) { 678 /* check this has same vid & mac address */ 679 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 680 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 681 static_table[3] == mac_lo) { 682 /* found matching one */ 683 break; 684 } 685 } else { 686 /* found empty one */ 687 break; 688 } 689 } 690 691 /* no available entry */ 692 if (index == dev->info->num_statics) { 693 err = -ENOSPC; 694 goto exit; 695 } 696 697 /* add entry */ 698 static_table[0] = ALU_V_STATIC_VALID; 699 static_table[1] |= BIT(port); 700 if (mdb->vid) 701 static_table[1] |= ALU_V_USE_FID; 702 static_table[2] = (mdb->vid << ALU_V_FID_S); 703 static_table[2] |= mac_hi; 704 static_table[3] = mac_lo; 705 706 ksz9477_write_table(dev, static_table); 707 708 data = (index << shifts[ALU_STAT_INDEX]) | ALU_STAT_START; 709 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 710 711 /* wait to be finished */ 712 if (ksz9477_wait_alu_sta_ready(dev)) 713 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 714 715 exit: 716 mutex_unlock(&dev->alu_mutex); 717 return err; 718 } 719 720 int ksz9477_mdb_del(struct ksz_device *dev, int port, 721 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 722 { 723 u32 static_table[4]; 724 const u8 *shifts; 725 const u32 *masks; 726 u32 data; 727 int index; 728 int ret = 0; 729 u32 mac_hi, mac_lo; 730 731 shifts = dev->info->shifts; 732 masks = dev->info->masks; 733 734 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 735 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 736 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 737 738 mutex_lock(&dev->alu_mutex); 739 740 for (index = 0; index < dev->info->num_statics; index++) { 741 /* find empty slot first */ 742 data = (index << shifts[ALU_STAT_INDEX]) | 743 masks[ALU_STAT_READ] | ALU_STAT_START; 744 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 745 746 /* wait to be finished */ 747 ret = ksz9477_wait_alu_sta_ready(dev); 748 if (ret) { 749 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 750 goto exit; 751 } 752 753 /* read ALU static table */ 754 ksz9477_read_table(dev, static_table); 755 756 if (static_table[0] & ALU_V_STATIC_VALID) { 757 /* check this has same vid & mac address */ 758 759 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 760 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 761 static_table[3] == mac_lo) { 762 /* found matching one */ 763 break; 764 } 765 } 766 } 767 768 /* no available entry */ 769 if (index == dev->info->num_statics) 770 goto exit; 771 772 /* clear port */ 773 static_table[1] &= ~BIT(port); 774 775 if ((static_table[1] & ALU_V_PORT_MAP) == 0) { 776 /* delete entry */ 777 static_table[0] = 0; 778 static_table[1] = 0; 779 static_table[2] = 0; 780 static_table[3] = 0; 781 } 782 783 ksz9477_write_table(dev, static_table); 784 785 data = (index << shifts[ALU_STAT_INDEX]) | ALU_STAT_START; 786 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 787 788 /* wait to be finished */ 789 ret = ksz9477_wait_alu_sta_ready(dev); 790 if (ret) 791 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 792 793 exit: 794 mutex_unlock(&dev->alu_mutex); 795 796 return ret; 797 } 798 799 int ksz9477_port_mirror_add(struct ksz_device *dev, int port, 800 struct dsa_mall_mirror_tc_entry *mirror, 801 bool ingress, struct netlink_ext_ack *extack) 802 { 803 u8 data; 804 int p; 805 806 /* Limit to one sniffer port 807 * Check if any of the port is already set for sniffing 808 * If yes, instruct the user to remove the previous entry & exit 809 */ 810 for (p = 0; p < dev->info->port_cnt; p++) { 811 /* Skip the current sniffing port */ 812 if (p == mirror->to_local_port) 813 continue; 814 815 ksz_pread8(dev, p, P_MIRROR_CTRL, &data); 816 817 if (data & PORT_MIRROR_SNIFFER) { 818 NL_SET_ERR_MSG_MOD(extack, 819 "Sniffer port is already configured, delete existing rules & retry"); 820 return -EBUSY; 821 } 822 } 823 824 if (ingress) 825 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 826 else 827 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 828 829 /* configure mirror port */ 830 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 831 PORT_MIRROR_SNIFFER, true); 832 833 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 834 835 return 0; 836 } 837 838 void ksz9477_port_mirror_del(struct ksz_device *dev, int port, 839 struct dsa_mall_mirror_tc_entry *mirror) 840 { 841 bool in_use = false; 842 u8 data; 843 int p; 844 845 if (mirror->ingress) 846 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 847 else 848 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 849 850 851 /* Check if any of the port is still referring to sniffer port */ 852 for (p = 0; p < dev->info->port_cnt; p++) { 853 ksz_pread8(dev, p, P_MIRROR_CTRL, &data); 854 855 if ((data & (PORT_MIRROR_RX | PORT_MIRROR_TX))) { 856 in_use = true; 857 break; 858 } 859 } 860 861 /* delete sniffing if there are no other mirroring rules */ 862 if (!in_use) 863 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 864 PORT_MIRROR_SNIFFER, false); 865 } 866 867 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port) 868 { 869 phy_interface_t interface; 870 bool gbit; 871 872 if (port < dev->phy_port_cnt) 873 return PHY_INTERFACE_MODE_NA; 874 875 gbit = ksz_get_gbit(dev, port); 876 877 interface = ksz_get_xmii(dev, port, gbit); 878 879 return interface; 880 } 881 882 static void ksz9477_port_mmd_write(struct ksz_device *dev, int port, 883 u8 dev_addr, u16 reg_addr, u16 val) 884 { 885 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 886 MMD_SETUP(PORT_MMD_OP_INDEX, dev_addr)); 887 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg_addr); 888 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 889 MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, dev_addr)); 890 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val); 891 } 892 893 static void ksz9477_phy_errata_setup(struct ksz_device *dev, int port) 894 { 895 /* Apply PHY settings to address errata listed in 896 * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565 897 * Silicon Errata and Data Sheet Clarification documents: 898 * 899 * Register settings are needed to improve PHY receive performance 900 */ 901 ksz9477_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b); 902 ksz9477_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032); 903 ksz9477_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c); 904 ksz9477_port_mmd_write(dev, port, 0x01, 0x75, 0x0060); 905 ksz9477_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777); 906 ksz9477_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008); 907 ksz9477_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001); 908 909 /* Transmit waveform amplitude can be improved 910 * (1000BASE-T, 100BASE-TX, 10BASE-Te) 911 */ 912 ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0); 913 914 /* Energy Efficient Ethernet (EEE) feature select must 915 * be manually disabled (except on KSZ8565 which is 100Mbit) 916 */ 917 if (dev->features & GBIT_SUPPORT) 918 ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000); 919 920 /* Register settings are required to meet data sheet 921 * supply current specifications 922 */ 923 ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff); 924 ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff); 925 ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff); 926 ksz9477_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff); 927 ksz9477_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff); 928 ksz9477_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff); 929 ksz9477_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff); 930 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff); 931 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff); 932 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff); 933 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff); 934 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff); 935 ksz9477_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee); 936 } 937 938 void ksz9477_get_caps(struct ksz_device *dev, int port, 939 struct phylink_config *config) 940 { 941 config->mac_capabilities = MAC_10 | MAC_100 | MAC_ASYM_PAUSE | 942 MAC_SYM_PAUSE; 943 944 if (dev->features & GBIT_SUPPORT) 945 config->mac_capabilities |= MAC_1000FD; 946 } 947 948 void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port) 949 { 950 struct dsa_switch *ds = dev->ds; 951 u16 data16; 952 u8 member; 953 954 /* enable tag tail for host port */ 955 if (cpu_port) 956 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE, 957 true); 958 959 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false); 960 961 /* set back pressure */ 962 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true); 963 964 /* enable broadcast storm limit */ 965 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 966 967 /* disable DiffServ priority */ 968 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false); 969 970 /* replace priority */ 971 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING, 972 false); 973 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4, 974 MTI_PVID_REPLACE, false); 975 976 /* enable 802.1p priority */ 977 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); 978 979 if (port < dev->phy_port_cnt) { 980 /* do not force flow control */ 981 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 982 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 983 false); 984 985 if (dev->info->phy_errata_9477) 986 ksz9477_phy_errata_setup(dev, port); 987 } else { 988 /* force flow control */ 989 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 990 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 991 true); 992 } 993 994 if (cpu_port) 995 member = dsa_user_ports(ds); 996 else 997 member = BIT(dsa_upstream_port(ds, port)); 998 999 ksz9477_cfg_port_member(dev, port, member); 1000 1001 /* clear pending interrupts */ 1002 if (port < dev->phy_port_cnt) 1003 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16); 1004 } 1005 1006 void ksz9477_config_cpu_port(struct dsa_switch *ds) 1007 { 1008 struct ksz_device *dev = ds->priv; 1009 struct ksz_port *p; 1010 int i; 1011 1012 for (i = 0; i < dev->info->port_cnt; i++) { 1013 if (dsa_is_cpu_port(ds, i) && 1014 (dev->info->cpu_ports & (1 << i))) { 1015 phy_interface_t interface; 1016 const char *prev_msg; 1017 const char *prev_mode; 1018 1019 dev->cpu_port = i; 1020 p = &dev->ports[i]; 1021 1022 /* Read from XMII register to determine host port 1023 * interface. If set specifically in device tree 1024 * note the difference to help debugging. 1025 */ 1026 interface = ksz9477_get_interface(dev, i); 1027 if (!p->interface) { 1028 if (dev->compat_interface) { 1029 dev_warn(dev->dev, 1030 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 1031 "Please update your device tree.\n", 1032 i); 1033 p->interface = dev->compat_interface; 1034 } else { 1035 p->interface = interface; 1036 } 1037 } 1038 if (interface && interface != p->interface) { 1039 prev_msg = " instead of "; 1040 prev_mode = phy_modes(interface); 1041 } else { 1042 prev_msg = ""; 1043 prev_mode = ""; 1044 } 1045 dev_info(dev->dev, 1046 "Port%d: using phy mode %s%s%s\n", 1047 i, 1048 phy_modes(p->interface), 1049 prev_msg, 1050 prev_mode); 1051 1052 /* enable cpu port */ 1053 ksz9477_port_setup(dev, i, true); 1054 p->on = 1; 1055 } 1056 } 1057 1058 for (i = 0; i < dev->info->port_cnt; i++) { 1059 if (i == dev->cpu_port) 1060 continue; 1061 p = &dev->ports[i]; 1062 1063 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1064 p->on = 1; 1065 if (i < dev->phy_port_cnt) 1066 p->phy = 1; 1067 if (dev->chip_id == 0x00947700 && i == 6) { 1068 p->sgmii = 1; 1069 1070 /* SGMII PHY detection code is not implemented yet. */ 1071 p->phy = 0; 1072 } 1073 } 1074 } 1075 1076 int ksz9477_enable_stp_addr(struct ksz_device *dev) 1077 { 1078 const u32 *masks; 1079 u32 data; 1080 int ret; 1081 1082 masks = dev->info->masks; 1083 1084 /* Enable Reserved multicast table */ 1085 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_RESV_MCAST_ENABLE, true); 1086 1087 /* Set the Override bit for forwarding BPDU packet to CPU */ 1088 ret = ksz_write32(dev, REG_SW_ALU_VAL_B, 1089 ALU_V_OVERRIDE | BIT(dev->cpu_port)); 1090 if (ret < 0) 1091 return ret; 1092 1093 data = ALU_STAT_START | ALU_RESV_MCAST_ADDR | masks[ALU_STAT_WRITE]; 1094 1095 ret = ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 1096 if (ret < 0) 1097 return ret; 1098 1099 /* wait to be finished */ 1100 ret = ksz9477_wait_alu_sta_ready(dev); 1101 if (ret < 0) { 1102 dev_err(dev->dev, "Failed to update Reserved Multicast table\n"); 1103 return ret; 1104 } 1105 1106 return 0; 1107 } 1108 1109 int ksz9477_setup(struct dsa_switch *ds) 1110 { 1111 struct ksz_device *dev = ds->priv; 1112 int ret = 0; 1113 1114 /* Required for port partitioning. */ 1115 ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, 1116 true); 1117 1118 /* Do not work correctly with tail tagging. */ 1119 ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false); 1120 1121 /* Enable REG_SW_MTU__2 reg by setting SW_JUMBO_PACKET */ 1122 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_JUMBO_PACKET, true); 1123 1124 /* Now we can configure default MTU value */ 1125 ret = regmap_update_bits(dev->regmap[1], REG_SW_MTU__2, REG_SW_MTU_MASK, 1126 VLAN_ETH_FRAME_LEN + ETH_FCS_LEN); 1127 if (ret) 1128 return ret; 1129 1130 /* queue based egress rate limit */ 1131 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true); 1132 1133 /* enable global MIB counter freeze function */ 1134 ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); 1135 1136 return 0; 1137 } 1138 1139 u32 ksz9477_get_port_addr(int port, int offset) 1140 { 1141 return PORT_CTRL_ADDR(port, offset); 1142 } 1143 1144 int ksz9477_switch_init(struct ksz_device *dev) 1145 { 1146 u8 data8; 1147 int ret; 1148 1149 dev->port_mask = (1 << dev->info->port_cnt) - 1; 1150 1151 /* turn off SPI DO Edge select */ 1152 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 1153 if (ret) 1154 return ret; 1155 1156 data8 &= ~SPI_AUTO_EDGE_DETECTION; 1157 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 1158 if (ret) 1159 return ret; 1160 1161 ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8); 1162 if (ret) 1163 return ret; 1164 1165 /* Number of ports can be reduced depending on chip. */ 1166 dev->phy_port_cnt = 5; 1167 1168 /* Default capability is gigabit capable. */ 1169 dev->features = GBIT_SUPPORT; 1170 1171 if (dev->chip_id == KSZ9893_CHIP_ID) { 1172 dev->features |= IS_9893; 1173 1174 /* Chip does not support gigabit. */ 1175 if (data8 & SW_QW_ABLE) 1176 dev->features &= ~GBIT_SUPPORT; 1177 dev->phy_port_cnt = 2; 1178 } else { 1179 /* Chip does not support gigabit. */ 1180 if (!(data8 & SW_GIGABIT_ABLE)) 1181 dev->features &= ~GBIT_SUPPORT; 1182 } 1183 1184 return 0; 1185 } 1186 1187 void ksz9477_switch_exit(struct ksz_device *dev) 1188 { 1189 ksz9477_reset_switch(dev); 1190 } 1191 1192 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 1193 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver"); 1194 MODULE_LICENSE("GPL"); 1195