1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ9477 switch driver main logic 4 * 5 * Copyright (C) 2017-2019 Microchip Technology Inc. 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/iopoll.h> 11 #include <linux/platform_data/microchip-ksz.h> 12 #include <linux/phy.h> 13 #include <linux/if_bridge.h> 14 #include <linux/if_vlan.h> 15 #include <net/dsa.h> 16 #include <net/switchdev.h> 17 18 #include "ksz9477_reg.h" 19 #include "ksz_common.h" 20 #include "ksz9477.h" 21 22 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 23 { 24 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0); 25 } 26 27 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 28 bool set) 29 { 30 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset), 31 bits, set ? bits : 0); 32 } 33 34 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set) 35 { 36 regmap_update_bits(dev->regmap[2], addr, bits, set ? bits : 0); 37 } 38 39 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset, 40 u32 bits, bool set) 41 { 42 regmap_update_bits(dev->regmap[2], PORT_CTRL_ADDR(port, offset), 43 bits, set ? bits : 0); 44 } 45 46 int ksz9477_change_mtu(struct ksz_device *dev, int port, int mtu) 47 { 48 u16 frame_size, max_frame = 0; 49 int i; 50 51 frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 52 53 /* Cache the per-port MTU setting */ 54 dev->ports[port].max_frame = frame_size; 55 56 for (i = 0; i < dev->info->port_cnt; i++) 57 max_frame = max(max_frame, dev->ports[i].max_frame); 58 59 return regmap_update_bits(dev->regmap[1], REG_SW_MTU__2, 60 REG_SW_MTU_MASK, max_frame); 61 } 62 63 int ksz9477_max_mtu(struct ksz_device *dev, int port) 64 { 65 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 66 } 67 68 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev) 69 { 70 unsigned int val; 71 72 return regmap_read_poll_timeout(dev->regmap[0], REG_SW_VLAN_CTRL, 73 val, !(val & VLAN_START), 10, 1000); 74 } 75 76 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid, 77 u32 *vlan_table) 78 { 79 int ret; 80 81 mutex_lock(&dev->vlan_mutex); 82 83 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 84 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START); 85 86 /* wait to be cleared */ 87 ret = ksz9477_wait_vlan_ctrl_ready(dev); 88 if (ret) { 89 dev_dbg(dev->dev, "Failed to read vlan table\n"); 90 goto exit; 91 } 92 93 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]); 94 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]); 95 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]); 96 97 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 98 99 exit: 100 mutex_unlock(&dev->vlan_mutex); 101 102 return ret; 103 } 104 105 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid, 106 u32 *vlan_table) 107 { 108 int ret; 109 110 mutex_lock(&dev->vlan_mutex); 111 112 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]); 113 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]); 114 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]); 115 116 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M); 117 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE); 118 119 /* wait to be cleared */ 120 ret = ksz9477_wait_vlan_ctrl_ready(dev); 121 if (ret) { 122 dev_dbg(dev->dev, "Failed to write vlan table\n"); 123 goto exit; 124 } 125 126 ksz_write8(dev, REG_SW_VLAN_CTRL, 0); 127 128 /* update vlan cache table */ 129 dev->vlan_cache[vid].table[0] = vlan_table[0]; 130 dev->vlan_cache[vid].table[1] = vlan_table[1]; 131 dev->vlan_cache[vid].table[2] = vlan_table[2]; 132 133 exit: 134 mutex_unlock(&dev->vlan_mutex); 135 136 return ret; 137 } 138 139 static void ksz9477_read_table(struct ksz_device *dev, u32 *table) 140 { 141 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]); 142 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]); 143 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]); 144 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]); 145 } 146 147 static void ksz9477_write_table(struct ksz_device *dev, u32 *table) 148 { 149 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]); 150 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]); 151 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]); 152 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]); 153 } 154 155 static int ksz9477_wait_alu_ready(struct ksz_device *dev) 156 { 157 unsigned int val; 158 159 return regmap_read_poll_timeout(dev->regmap[2], REG_SW_ALU_CTRL__4, 160 val, !(val & ALU_START), 10, 1000); 161 } 162 163 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev) 164 { 165 unsigned int val; 166 167 return regmap_read_poll_timeout(dev->regmap[2], 168 REG_SW_ALU_STAT_CTRL__4, 169 val, !(val & ALU_STAT_START), 170 10, 1000); 171 } 172 173 int ksz9477_reset_switch(struct ksz_device *dev) 174 { 175 u8 data8; 176 u32 data32; 177 178 /* reset switch */ 179 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 180 181 /* turn off SPI DO Edge select */ 182 regmap_update_bits(dev->regmap[0], REG_SW_GLOBAL_SERIAL_CTRL_0, 183 SPI_AUTO_EDGE_DETECTION, 0); 184 185 /* default configuration */ 186 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8); 187 data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING | 188 SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE; 189 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8); 190 191 /* disable interrupts */ 192 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 193 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F); 194 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 195 196 data8 = SW_ENABLE_REFCLKO; 197 if (dev->synclko_disable) 198 data8 = 0; 199 else if (dev->synclko_125) 200 data8 = SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ; 201 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, data8); 202 203 return 0; 204 } 205 206 void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt) 207 { 208 struct ksz_port *p = &dev->ports[port]; 209 unsigned int val; 210 u32 data; 211 int ret; 212 213 /* retain the flush/freeze bit */ 214 data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 215 data |= MIB_COUNTER_READ; 216 data |= (addr << MIB_COUNTER_INDEX_S); 217 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data); 218 219 ret = regmap_read_poll_timeout(dev->regmap[2], 220 PORT_CTRL_ADDR(port, REG_PORT_MIB_CTRL_STAT__4), 221 val, !(val & MIB_COUNTER_READ), 10, 1000); 222 /* failed to read MIB. get out of loop */ 223 if (ret) { 224 dev_dbg(dev->dev, "Failed to get MIB\n"); 225 return; 226 } 227 228 /* count resets upon read */ 229 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data); 230 *cnt += data; 231 } 232 233 void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 234 u64 *dropped, u64 *cnt) 235 { 236 addr = dev->info->mib_names[addr].index; 237 ksz9477_r_mib_cnt(dev, port, addr, cnt); 238 } 239 240 void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze) 241 { 242 u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0; 243 struct ksz_port *p = &dev->ports[port]; 244 245 /* enable/disable the port for flush/freeze function */ 246 mutex_lock(&p->mib.cnt_mutex); 247 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val); 248 249 /* used by MIB counter reading code to know freeze is enabled */ 250 p->freeze = freeze; 251 mutex_unlock(&p->mib.cnt_mutex); 252 } 253 254 void ksz9477_port_init_cnt(struct ksz_device *dev, int port) 255 { 256 struct ksz_port_mib *mib = &dev->ports[port].mib; 257 258 /* flush all enabled port MIB counters */ 259 mutex_lock(&mib->cnt_mutex); 260 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 261 MIB_COUNTER_FLUSH_FREEZE); 262 ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH); 263 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0); 264 mutex_unlock(&mib->cnt_mutex); 265 } 266 267 void ksz9477_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data) 268 { 269 u16 val = 0xffff; 270 271 /* No real PHY after this. Simulate the PHY. 272 * A fixed PHY can be setup in the device tree, but this function is 273 * still called for that port during initialization. 274 * For RGMII PHY there is no way to access it so the fixed PHY should 275 * be used. For SGMII PHY the supporting code will be added later. 276 */ 277 if (addr >= dev->phy_port_cnt) { 278 struct ksz_port *p = &dev->ports[addr]; 279 280 switch (reg) { 281 case MII_BMCR: 282 val = 0x1140; 283 break; 284 case MII_BMSR: 285 val = 0x796d; 286 break; 287 case MII_PHYSID1: 288 val = 0x0022; 289 break; 290 case MII_PHYSID2: 291 val = 0x1631; 292 break; 293 case MII_ADVERTISE: 294 val = 0x05e1; 295 break; 296 case MII_LPA: 297 val = 0xc5e1; 298 break; 299 case MII_CTRL1000: 300 val = 0x0700; 301 break; 302 case MII_STAT1000: 303 if (p->phydev.speed == SPEED_1000) 304 val = 0x3800; 305 else 306 val = 0; 307 break; 308 } 309 } else { 310 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val); 311 } 312 313 *data = val; 314 } 315 316 void ksz9477_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val) 317 { 318 /* No real PHY after this. */ 319 if (addr >= dev->phy_port_cnt) 320 return; 321 322 /* No gigabit support. Do not write to this register. */ 323 if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000) 324 return; 325 326 ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val); 327 } 328 329 void ksz9477_cfg_port_member(struct ksz_device *dev, int port, u8 member) 330 { 331 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member); 332 } 333 334 void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port) 335 { 336 const u16 *regs = dev->info->regs; 337 u8 data; 338 339 regmap_update_bits(dev->regmap[0], REG_SW_LUE_CTRL_2, 340 SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S, 341 SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S); 342 343 if (port < dev->info->port_cnt) { 344 /* flush individual port */ 345 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 346 if (!(data & PORT_LEARN_DISABLE)) 347 ksz_pwrite8(dev, port, regs[P_STP_CTRL], 348 data | PORT_LEARN_DISABLE); 349 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 350 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 351 } else { 352 /* flush all */ 353 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true); 354 } 355 } 356 357 int ksz9477_port_vlan_filtering(struct ksz_device *dev, int port, 358 bool flag, struct netlink_ext_ack *extack) 359 { 360 if (flag) { 361 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 362 PORT_VLAN_LOOKUP_VID_0, true); 363 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true); 364 } else { 365 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false); 366 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL, 367 PORT_VLAN_LOOKUP_VID_0, false); 368 } 369 370 return 0; 371 } 372 373 int ksz9477_port_vlan_add(struct ksz_device *dev, int port, 374 const struct switchdev_obj_port_vlan *vlan, 375 struct netlink_ext_ack *extack) 376 { 377 u32 vlan_table[3]; 378 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 379 int err; 380 381 err = ksz9477_get_vlan_table(dev, vlan->vid, vlan_table); 382 if (err) { 383 NL_SET_ERR_MSG_MOD(extack, "Failed to get vlan table"); 384 return err; 385 } 386 387 vlan_table[0] = VLAN_VALID | (vlan->vid & VLAN_FID_M); 388 if (untagged) 389 vlan_table[1] |= BIT(port); 390 else 391 vlan_table[1] &= ~BIT(port); 392 vlan_table[1] &= ~(BIT(dev->cpu_port)); 393 394 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port); 395 396 err = ksz9477_set_vlan_table(dev, vlan->vid, vlan_table); 397 if (err) { 398 NL_SET_ERR_MSG_MOD(extack, "Failed to set vlan table"); 399 return err; 400 } 401 402 /* change PVID */ 403 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 404 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vlan->vid); 405 406 return 0; 407 } 408 409 int ksz9477_port_vlan_del(struct ksz_device *dev, int port, 410 const struct switchdev_obj_port_vlan *vlan) 411 { 412 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 413 u32 vlan_table[3]; 414 u16 pvid; 415 416 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid); 417 pvid = pvid & 0xFFF; 418 419 if (ksz9477_get_vlan_table(dev, vlan->vid, vlan_table)) { 420 dev_dbg(dev->dev, "Failed to get vlan table\n"); 421 return -ETIMEDOUT; 422 } 423 424 vlan_table[2] &= ~BIT(port); 425 426 if (pvid == vlan->vid) 427 pvid = 1; 428 429 if (untagged) 430 vlan_table[1] &= ~BIT(port); 431 432 if (ksz9477_set_vlan_table(dev, vlan->vid, vlan_table)) { 433 dev_dbg(dev->dev, "Failed to set vlan table\n"); 434 return -ETIMEDOUT; 435 } 436 437 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid); 438 439 return 0; 440 } 441 442 int ksz9477_fdb_add(struct ksz_device *dev, int port, 443 const unsigned char *addr, u16 vid, struct dsa_db db) 444 { 445 u32 alu_table[4]; 446 u32 data; 447 int ret = 0; 448 449 mutex_lock(&dev->alu_mutex); 450 451 /* find any entry with mac & vid */ 452 data = vid << ALU_FID_INDEX_S; 453 data |= ((addr[0] << 8) | addr[1]); 454 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 455 456 data = ((addr[2] << 24) | (addr[3] << 16)); 457 data |= ((addr[4] << 8) | addr[5]); 458 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 459 460 /* start read operation */ 461 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 462 463 /* wait to be finished */ 464 ret = ksz9477_wait_alu_ready(dev); 465 if (ret) { 466 dev_dbg(dev->dev, "Failed to read ALU\n"); 467 goto exit; 468 } 469 470 /* read ALU entry */ 471 ksz9477_read_table(dev, alu_table); 472 473 /* update ALU entry */ 474 alu_table[0] = ALU_V_STATIC_VALID; 475 alu_table[1] |= BIT(port); 476 if (vid) 477 alu_table[1] |= ALU_V_USE_FID; 478 alu_table[2] = (vid << ALU_V_FID_S); 479 alu_table[2] |= ((addr[0] << 8) | addr[1]); 480 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16)); 481 alu_table[3] |= ((addr[4] << 8) | addr[5]); 482 483 ksz9477_write_table(dev, alu_table); 484 485 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 486 487 /* wait to be finished */ 488 ret = ksz9477_wait_alu_ready(dev); 489 if (ret) 490 dev_dbg(dev->dev, "Failed to write ALU\n"); 491 492 exit: 493 mutex_unlock(&dev->alu_mutex); 494 495 return ret; 496 } 497 498 int ksz9477_fdb_del(struct ksz_device *dev, int port, 499 const unsigned char *addr, u16 vid, struct dsa_db db) 500 { 501 u32 alu_table[4]; 502 u32 data; 503 int ret = 0; 504 505 mutex_lock(&dev->alu_mutex); 506 507 /* read any entry with mac & vid */ 508 data = vid << ALU_FID_INDEX_S; 509 data |= ((addr[0] << 8) | addr[1]); 510 ksz_write32(dev, REG_SW_ALU_INDEX_0, data); 511 512 data = ((addr[2] << 24) | (addr[3] << 16)); 513 data |= ((addr[4] << 8) | addr[5]); 514 ksz_write32(dev, REG_SW_ALU_INDEX_1, data); 515 516 /* start read operation */ 517 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START); 518 519 /* wait to be finished */ 520 ret = ksz9477_wait_alu_ready(dev); 521 if (ret) { 522 dev_dbg(dev->dev, "Failed to read ALU\n"); 523 goto exit; 524 } 525 526 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]); 527 if (alu_table[0] & ALU_V_STATIC_VALID) { 528 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]); 529 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]); 530 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]); 531 532 /* clear forwarding port */ 533 alu_table[2] &= ~BIT(port); 534 535 /* if there is no port to forward, clear table */ 536 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) { 537 alu_table[0] = 0; 538 alu_table[1] = 0; 539 alu_table[2] = 0; 540 alu_table[3] = 0; 541 } 542 } else { 543 alu_table[0] = 0; 544 alu_table[1] = 0; 545 alu_table[2] = 0; 546 alu_table[3] = 0; 547 } 548 549 ksz9477_write_table(dev, alu_table); 550 551 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START); 552 553 /* wait to be finished */ 554 ret = ksz9477_wait_alu_ready(dev); 555 if (ret) 556 dev_dbg(dev->dev, "Failed to write ALU\n"); 557 558 exit: 559 mutex_unlock(&dev->alu_mutex); 560 561 return ret; 562 } 563 564 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table) 565 { 566 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID); 567 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER); 568 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER); 569 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) & 570 ALU_V_PRIO_AGE_CNT_M; 571 alu->mstp = alu_table[0] & ALU_V_MSTP_M; 572 573 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE); 574 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID); 575 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP; 576 577 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M; 578 579 alu->mac[0] = (alu_table[2] >> 8) & 0xFF; 580 alu->mac[1] = alu_table[2] & 0xFF; 581 alu->mac[2] = (alu_table[3] >> 24) & 0xFF; 582 alu->mac[3] = (alu_table[3] >> 16) & 0xFF; 583 alu->mac[4] = (alu_table[3] >> 8) & 0xFF; 584 alu->mac[5] = alu_table[3] & 0xFF; 585 } 586 587 int ksz9477_fdb_dump(struct ksz_device *dev, int port, 588 dsa_fdb_dump_cb_t *cb, void *data) 589 { 590 int ret = 0; 591 u32 ksz_data; 592 u32 alu_table[4]; 593 struct alu_struct alu; 594 int timeout; 595 596 mutex_lock(&dev->alu_mutex); 597 598 /* start ALU search */ 599 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH); 600 601 do { 602 timeout = 1000; 603 do { 604 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data); 605 if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START)) 606 break; 607 usleep_range(1, 10); 608 } while (timeout-- > 0); 609 610 if (!timeout) { 611 dev_dbg(dev->dev, "Failed to search ALU\n"); 612 ret = -ETIMEDOUT; 613 goto exit; 614 } 615 616 /* read ALU table */ 617 ksz9477_read_table(dev, alu_table); 618 619 ksz9477_convert_alu(&alu, alu_table); 620 621 if (alu.port_forward & BIT(port)) { 622 ret = cb(alu.mac, alu.fid, alu.is_static, data); 623 if (ret) 624 goto exit; 625 } 626 } while (ksz_data & ALU_START); 627 628 exit: 629 630 /* stop ALU search */ 631 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0); 632 633 mutex_unlock(&dev->alu_mutex); 634 635 return ret; 636 } 637 638 int ksz9477_mdb_add(struct ksz_device *dev, int port, 639 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 640 { 641 u32 static_table[4]; 642 const u8 *shifts; 643 const u32 *masks; 644 u32 data; 645 int index; 646 u32 mac_hi, mac_lo; 647 int err = 0; 648 649 shifts = dev->info->shifts; 650 masks = dev->info->masks; 651 652 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 653 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 654 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 655 656 mutex_lock(&dev->alu_mutex); 657 658 for (index = 0; index < dev->info->num_statics; index++) { 659 /* find empty slot first */ 660 data = (index << shifts[ALU_STAT_INDEX]) | 661 masks[ALU_STAT_READ] | ALU_STAT_START; 662 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 663 664 /* wait to be finished */ 665 err = ksz9477_wait_alu_sta_ready(dev); 666 if (err) { 667 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 668 goto exit; 669 } 670 671 /* read ALU static table */ 672 ksz9477_read_table(dev, static_table); 673 674 if (static_table[0] & ALU_V_STATIC_VALID) { 675 /* check this has same vid & mac address */ 676 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 677 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 678 static_table[3] == mac_lo) { 679 /* found matching one */ 680 break; 681 } 682 } else { 683 /* found empty one */ 684 break; 685 } 686 } 687 688 /* no available entry */ 689 if (index == dev->info->num_statics) { 690 err = -ENOSPC; 691 goto exit; 692 } 693 694 /* add entry */ 695 static_table[0] = ALU_V_STATIC_VALID; 696 static_table[1] |= BIT(port); 697 if (mdb->vid) 698 static_table[1] |= ALU_V_USE_FID; 699 static_table[2] = (mdb->vid << ALU_V_FID_S); 700 static_table[2] |= mac_hi; 701 static_table[3] = mac_lo; 702 703 ksz9477_write_table(dev, static_table); 704 705 data = (index << shifts[ALU_STAT_INDEX]) | ALU_STAT_START; 706 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 707 708 /* wait to be finished */ 709 if (ksz9477_wait_alu_sta_ready(dev)) 710 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 711 712 exit: 713 mutex_unlock(&dev->alu_mutex); 714 return err; 715 } 716 717 int ksz9477_mdb_del(struct ksz_device *dev, int port, 718 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 719 { 720 u32 static_table[4]; 721 const u8 *shifts; 722 const u32 *masks; 723 u32 data; 724 int index; 725 int ret = 0; 726 u32 mac_hi, mac_lo; 727 728 shifts = dev->info->shifts; 729 masks = dev->info->masks; 730 731 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]); 732 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16)); 733 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]); 734 735 mutex_lock(&dev->alu_mutex); 736 737 for (index = 0; index < dev->info->num_statics; index++) { 738 /* find empty slot first */ 739 data = (index << shifts[ALU_STAT_INDEX]) | 740 masks[ALU_STAT_READ] | ALU_STAT_START; 741 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 742 743 /* wait to be finished */ 744 ret = ksz9477_wait_alu_sta_ready(dev); 745 if (ret) { 746 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 747 goto exit; 748 } 749 750 /* read ALU static table */ 751 ksz9477_read_table(dev, static_table); 752 753 if (static_table[0] & ALU_V_STATIC_VALID) { 754 /* check this has same vid & mac address */ 755 756 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) && 757 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) && 758 static_table[3] == mac_lo) { 759 /* found matching one */ 760 break; 761 } 762 } 763 } 764 765 /* no available entry */ 766 if (index == dev->info->num_statics) 767 goto exit; 768 769 /* clear port */ 770 static_table[1] &= ~BIT(port); 771 772 if ((static_table[1] & ALU_V_PORT_MAP) == 0) { 773 /* delete entry */ 774 static_table[0] = 0; 775 static_table[1] = 0; 776 static_table[2] = 0; 777 static_table[3] = 0; 778 } 779 780 ksz9477_write_table(dev, static_table); 781 782 data = (index << shifts[ALU_STAT_INDEX]) | ALU_STAT_START; 783 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 784 785 /* wait to be finished */ 786 ret = ksz9477_wait_alu_sta_ready(dev); 787 if (ret) 788 dev_dbg(dev->dev, "Failed to read ALU STATIC\n"); 789 790 exit: 791 mutex_unlock(&dev->alu_mutex); 792 793 return ret; 794 } 795 796 int ksz9477_port_mirror_add(struct ksz_device *dev, int port, 797 struct dsa_mall_mirror_tc_entry *mirror, 798 bool ingress, struct netlink_ext_ack *extack) 799 { 800 u8 data; 801 int p; 802 803 /* Limit to one sniffer port 804 * Check if any of the port is already set for sniffing 805 * If yes, instruct the user to remove the previous entry & exit 806 */ 807 for (p = 0; p < dev->info->port_cnt; p++) { 808 /* Skip the current sniffing port */ 809 if (p == mirror->to_local_port) 810 continue; 811 812 ksz_pread8(dev, p, P_MIRROR_CTRL, &data); 813 814 if (data & PORT_MIRROR_SNIFFER) { 815 NL_SET_ERR_MSG_MOD(extack, 816 "Sniffer port is already configured, delete existing rules & retry"); 817 return -EBUSY; 818 } 819 } 820 821 if (ingress) 822 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 823 else 824 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 825 826 /* configure mirror port */ 827 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 828 PORT_MIRROR_SNIFFER, true); 829 830 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 831 832 return 0; 833 } 834 835 void ksz9477_port_mirror_del(struct ksz_device *dev, int port, 836 struct dsa_mall_mirror_tc_entry *mirror) 837 { 838 bool in_use = false; 839 u8 data; 840 int p; 841 842 if (mirror->ingress) 843 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 844 else 845 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 846 847 848 /* Check if any of the port is still referring to sniffer port */ 849 for (p = 0; p < dev->info->port_cnt; p++) { 850 ksz_pread8(dev, p, P_MIRROR_CTRL, &data); 851 852 if ((data & (PORT_MIRROR_RX | PORT_MIRROR_TX))) { 853 in_use = true; 854 break; 855 } 856 } 857 858 /* delete sniffing if there are no other mirroring rules */ 859 if (!in_use) 860 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 861 PORT_MIRROR_SNIFFER, false); 862 } 863 864 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port) 865 { 866 phy_interface_t interface; 867 bool gbit; 868 869 if (port < dev->phy_port_cnt) 870 return PHY_INTERFACE_MODE_NA; 871 872 gbit = ksz_get_gbit(dev, port); 873 874 interface = ksz_get_xmii(dev, port, gbit); 875 876 return interface; 877 } 878 879 static void ksz9477_port_mmd_write(struct ksz_device *dev, int port, 880 u8 dev_addr, u16 reg_addr, u16 val) 881 { 882 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 883 MMD_SETUP(PORT_MMD_OP_INDEX, dev_addr)); 884 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg_addr); 885 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, 886 MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, dev_addr)); 887 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val); 888 } 889 890 static void ksz9477_phy_errata_setup(struct ksz_device *dev, int port) 891 { 892 /* Apply PHY settings to address errata listed in 893 * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565 894 * Silicon Errata and Data Sheet Clarification documents: 895 * 896 * Register settings are needed to improve PHY receive performance 897 */ 898 ksz9477_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b); 899 ksz9477_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032); 900 ksz9477_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c); 901 ksz9477_port_mmd_write(dev, port, 0x01, 0x75, 0x0060); 902 ksz9477_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777); 903 ksz9477_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008); 904 ksz9477_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001); 905 906 /* Transmit waveform amplitude can be improved 907 * (1000BASE-T, 100BASE-TX, 10BASE-Te) 908 */ 909 ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0); 910 911 /* Energy Efficient Ethernet (EEE) feature select must 912 * be manually disabled (except on KSZ8565 which is 100Mbit) 913 */ 914 if (dev->features & GBIT_SUPPORT) 915 ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000); 916 917 /* Register settings are required to meet data sheet 918 * supply current specifications 919 */ 920 ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff); 921 ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff); 922 ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff); 923 ksz9477_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff); 924 ksz9477_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff); 925 ksz9477_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff); 926 ksz9477_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff); 927 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff); 928 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff); 929 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff); 930 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff); 931 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff); 932 ksz9477_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee); 933 } 934 935 void ksz9477_get_caps(struct ksz_device *dev, int port, 936 struct phylink_config *config) 937 { 938 config->mac_capabilities = MAC_10 | MAC_100 | MAC_ASYM_PAUSE | 939 MAC_SYM_PAUSE; 940 941 if (dev->features & GBIT_SUPPORT) 942 config->mac_capabilities |= MAC_1000FD; 943 } 944 945 void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port) 946 { 947 struct dsa_switch *ds = dev->ds; 948 u16 data16; 949 u8 member; 950 951 /* enable tag tail for host port */ 952 if (cpu_port) 953 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE, 954 true); 955 956 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false); 957 958 /* set back pressure */ 959 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true); 960 961 /* enable broadcast storm limit */ 962 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 963 964 /* disable DiffServ priority */ 965 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false); 966 967 /* replace priority */ 968 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING, 969 false); 970 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4, 971 MTI_PVID_REPLACE, false); 972 973 /* enable 802.1p priority */ 974 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); 975 976 if (port < dev->phy_port_cnt) { 977 /* do not force flow control */ 978 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 979 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 980 false); 981 982 if (dev->info->phy_errata_9477) 983 ksz9477_phy_errata_setup(dev, port); 984 } else { 985 /* force flow control */ 986 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, 987 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, 988 true); 989 } 990 991 if (cpu_port) 992 member = dsa_user_ports(ds); 993 else 994 member = BIT(dsa_upstream_port(ds, port)); 995 996 ksz9477_cfg_port_member(dev, port, member); 997 998 /* clear pending interrupts */ 999 if (port < dev->phy_port_cnt) 1000 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16); 1001 } 1002 1003 void ksz9477_config_cpu_port(struct dsa_switch *ds) 1004 { 1005 struct ksz_device *dev = ds->priv; 1006 struct ksz_port *p; 1007 int i; 1008 1009 for (i = 0; i < dev->info->port_cnt; i++) { 1010 if (dsa_is_cpu_port(ds, i) && 1011 (dev->info->cpu_ports & (1 << i))) { 1012 phy_interface_t interface; 1013 const char *prev_msg; 1014 const char *prev_mode; 1015 1016 dev->cpu_port = i; 1017 p = &dev->ports[i]; 1018 1019 /* Read from XMII register to determine host port 1020 * interface. If set specifically in device tree 1021 * note the difference to help debugging. 1022 */ 1023 interface = ksz9477_get_interface(dev, i); 1024 if (!p->interface) { 1025 if (dev->compat_interface) { 1026 dev_warn(dev->dev, 1027 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 1028 "Please update your device tree.\n", 1029 i); 1030 p->interface = dev->compat_interface; 1031 } else { 1032 p->interface = interface; 1033 } 1034 } 1035 if (interface && interface != p->interface) { 1036 prev_msg = " instead of "; 1037 prev_mode = phy_modes(interface); 1038 } else { 1039 prev_msg = ""; 1040 prev_mode = ""; 1041 } 1042 dev_info(dev->dev, 1043 "Port%d: using phy mode %s%s%s\n", 1044 i, 1045 phy_modes(p->interface), 1046 prev_msg, 1047 prev_mode); 1048 1049 /* enable cpu port */ 1050 ksz9477_port_setup(dev, i, true); 1051 p->on = 1; 1052 } 1053 } 1054 1055 for (i = 0; i < dev->info->port_cnt; i++) { 1056 if (i == dev->cpu_port) 1057 continue; 1058 p = &dev->ports[i]; 1059 1060 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1061 p->on = 1; 1062 if (i < dev->phy_port_cnt) 1063 p->phy = 1; 1064 if (dev->chip_id == 0x00947700 && i == 6) { 1065 p->sgmii = 1; 1066 1067 /* SGMII PHY detection code is not implemented yet. */ 1068 p->phy = 0; 1069 } 1070 } 1071 } 1072 1073 int ksz9477_enable_stp_addr(struct ksz_device *dev) 1074 { 1075 const u32 *masks; 1076 u32 data; 1077 int ret; 1078 1079 masks = dev->info->masks; 1080 1081 /* Enable Reserved multicast table */ 1082 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_RESV_MCAST_ENABLE, true); 1083 1084 /* Set the Override bit for forwarding BPDU packet to CPU */ 1085 ret = ksz_write32(dev, REG_SW_ALU_VAL_B, 1086 ALU_V_OVERRIDE | BIT(dev->cpu_port)); 1087 if (ret < 0) 1088 return ret; 1089 1090 data = ALU_STAT_START | ALU_RESV_MCAST_ADDR | masks[ALU_STAT_WRITE]; 1091 1092 ret = ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data); 1093 if (ret < 0) 1094 return ret; 1095 1096 /* wait to be finished */ 1097 ret = ksz9477_wait_alu_sta_ready(dev); 1098 if (ret < 0) { 1099 dev_err(dev->dev, "Failed to update Reserved Multicast table\n"); 1100 return ret; 1101 } 1102 1103 return 0; 1104 } 1105 1106 int ksz9477_setup(struct dsa_switch *ds) 1107 { 1108 struct ksz_device *dev = ds->priv; 1109 int ret = 0; 1110 1111 /* Required for port partitioning. */ 1112 ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY, 1113 true); 1114 1115 /* Do not work correctly with tail tagging. */ 1116 ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false); 1117 1118 /* Enable REG_SW_MTU__2 reg by setting SW_JUMBO_PACKET */ 1119 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_JUMBO_PACKET, true); 1120 1121 /* Now we can configure default MTU value */ 1122 ret = regmap_update_bits(dev->regmap[1], REG_SW_MTU__2, REG_SW_MTU_MASK, 1123 VLAN_ETH_FRAME_LEN + ETH_FCS_LEN); 1124 if (ret) 1125 return ret; 1126 1127 /* queue based egress rate limit */ 1128 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true); 1129 1130 /* enable global MIB counter freeze function */ 1131 ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); 1132 1133 return 0; 1134 } 1135 1136 u32 ksz9477_get_port_addr(int port, int offset) 1137 { 1138 return PORT_CTRL_ADDR(port, offset); 1139 } 1140 1141 int ksz9477_switch_init(struct ksz_device *dev) 1142 { 1143 u8 data8; 1144 int ret; 1145 1146 dev->port_mask = (1 << dev->info->port_cnt) - 1; 1147 1148 /* turn off SPI DO Edge select */ 1149 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8); 1150 if (ret) 1151 return ret; 1152 1153 data8 &= ~SPI_AUTO_EDGE_DETECTION; 1154 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8); 1155 if (ret) 1156 return ret; 1157 1158 ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8); 1159 if (ret) 1160 return ret; 1161 1162 /* Number of ports can be reduced depending on chip. */ 1163 dev->phy_port_cnt = 5; 1164 1165 /* Default capability is gigabit capable. */ 1166 dev->features = GBIT_SUPPORT; 1167 1168 if (dev->chip_id == KSZ9893_CHIP_ID) { 1169 dev->features |= IS_9893; 1170 1171 /* Chip does not support gigabit. */ 1172 if (data8 & SW_QW_ABLE) 1173 dev->features &= ~GBIT_SUPPORT; 1174 dev->phy_port_cnt = 2; 1175 } else { 1176 /* Chip does not support gigabit. */ 1177 if (!(data8 & SW_GIGABIT_ABLE)) 1178 dev->features &= ~GBIT_SUPPORT; 1179 } 1180 1181 return 0; 1182 } 1183 1184 void ksz9477_switch_exit(struct ksz_device *dev) 1185 { 1186 ksz9477_reset_switch(dev); 1187 } 1188 1189 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 1190 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver"); 1191 MODULE_LICENSE("GPL"); 1192