1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Microchip KSZ8795 register definitions
4  *
5  * Copyright (c) 2017 Microchip Technology Inc.
6  *	Tristram Ha <Tristram.Ha@microchip.com>
7  */
8 
9 #ifndef __KSZ8795_REG_H
10 #define __KSZ8795_REG_H
11 
12 #define KS_PORT_M			0x1F
13 
14 #define KS_PRIO_M			0x3
15 #define KS_PRIO_S			2
16 
17 #define REG_CHIP_ID0			0x00
18 
19 #define KSZ87_FAMILY_ID			0x87
20 #define KSZ88_FAMILY_ID			0x88
21 
22 #define REG_CHIP_ID1			0x01
23 
24 #define SW_CHIP_ID_M			0xF0
25 #define SW_CHIP_ID_S			4
26 #define SW_REVISION_M			0x0E
27 #define SW_REVISION_S			1
28 #define SW_START			0x01
29 
30 #define CHIP_ID_94			0x60
31 #define CHIP_ID_95			0x90
32 #define CHIP_ID_63			0x30
33 
34 #define KSZ8863_REG_SW_RESET		0x43
35 
36 #define KSZ8863_GLOBAL_SOFTWARE_RESET	BIT(4)
37 #define KSZ8863_PCS_RESET		BIT(0)
38 
39 #define REG_SW_CTRL_0			0x02
40 
41 #define SW_NEW_BACKOFF			BIT(7)
42 #define SW_GLOBAL_RESET			BIT(6)
43 #define SW_FLUSH_DYN_MAC_TABLE		BIT(5)
44 #define SW_FLUSH_STA_MAC_TABLE		BIT(4)
45 #define SW_LINK_AUTO_AGING		BIT(0)
46 
47 #define REG_SW_CTRL_1			0x03
48 
49 #define SW_HUGE_PACKET			BIT(6)
50 #define SW_TX_FLOW_CTRL_DISABLE		BIT(5)
51 #define SW_RX_FLOW_CTRL_DISABLE		BIT(4)
52 #define SW_CHECK_LENGTH			BIT(3)
53 #define SW_AGING_ENABLE			BIT(2)
54 #define SW_FAST_AGING			BIT(1)
55 #define SW_AGGR_BACKOFF			BIT(0)
56 
57 #define REG_SW_CTRL_2			0x04
58 
59 #define UNICAST_VLAN_BOUNDARY		BIT(7)
60 #define MULTICAST_STORM_DISABLE		BIT(6)
61 #define SW_BACK_PRESSURE		BIT(5)
62 #define FAIR_FLOW_CTRL			BIT(4)
63 #define NO_EXC_COLLISION_DROP		BIT(3)
64 #define SW_LEGAL_PACKET_DISABLE		BIT(1)
65 
66 #define REG_SW_CTRL_3			0x05
67  #define WEIGHTED_FAIR_QUEUE_ENABLE	BIT(3)
68 
69 #define SW_VLAN_ENABLE			BIT(7)
70 #define SW_IGMP_SNOOP			BIT(6)
71 #define SW_MIRROR_RX_TX			BIT(0)
72 
73 #define REG_SW_CTRL_4			0x06
74 
75 #define SW_HALF_DUPLEX_FLOW_CTRL	BIT(7)
76 #define SW_HALF_DUPLEX			BIT(6)
77 #define SW_FLOW_CTRL			BIT(5)
78 #define SW_10_MBIT			BIT(4)
79 #define SW_REPLACE_VID			BIT(3)
80 #define BROADCAST_STORM_RATE_HI		0x07
81 
82 #define REG_SW_CTRL_5			0x07
83 
84 #define BROADCAST_STORM_RATE_LO		0xFF
85 #define BROADCAST_STORM_RATE		0x07FF
86 
87 #define REG_SW_CTRL_6			0x08
88 
89 #define SW_MIB_COUNTER_FLUSH		BIT(7)
90 #define SW_MIB_COUNTER_FREEZE		BIT(6)
91 #define SW_MIB_COUNTER_CTRL_ENABLE	KS_PORT_M
92 
93 #define REG_SW_CTRL_9			0x0B
94 
95 #define SPI_CLK_125_MHZ			0x80
96 #define SPI_CLK_62_5_MHZ		0x40
97 #define SPI_CLK_31_25_MHZ		0x00
98 
99 #define SW_LED_MODE_M			0x3
100 #define SW_LED_MODE_S			4
101 #define SW_LED_LINK_ACT_SPEED		0
102 #define SW_LED_LINK_ACT			1
103 #define SW_LED_LINK_ACT_DUPLEX		2
104 #define SW_LED_LINK_DUPLEX		3
105 
106 #define REG_SW_CTRL_10			0x0C
107 
108 #define SW_PASS_PAUSE			BIT(0)
109 
110 #define REG_SW_CTRL_11			0x0D
111 
112 #define REG_POWER_MANAGEMENT_1		0x0E
113 
114 #define SW_PLL_POWER_DOWN		BIT(5)
115 #define SW_POWER_MANAGEMENT_MODE_M	0x3
116 #define SW_POWER_MANAGEMENT_MODE_S	3
117 #define SW_POWER_NORMAL			0
118 #define SW_ENERGY_DETECTION		1
119 #define SW_SOFTWARE_POWER_DOWN		2
120 
121 #define REG_POWER_MANAGEMENT_2		0x0F
122 
123 #define REG_PORT_1_CTRL_0		0x10
124 #define REG_PORT_2_CTRL_0		0x20
125 #define REG_PORT_3_CTRL_0		0x30
126 #define REG_PORT_4_CTRL_0		0x40
127 #define REG_PORT_5_CTRL_0		0x50
128 
129 #define PORT_BROADCAST_STORM		BIT(7)
130 #define PORT_DIFFSERV_ENABLE		BIT(6)
131 #define PORT_802_1P_ENABLE		BIT(5)
132 #define PORT_BASED_PRIO_S		3
133 #define PORT_BASED_PRIO_M		KS_PRIO_M
134 #define PORT_BASED_PRIO_0		0
135 #define PORT_BASED_PRIO_1		1
136 #define PORT_BASED_PRIO_2		2
137 #define PORT_BASED_PRIO_3		3
138 #define PORT_INSERT_TAG			BIT(2)
139 #define PORT_REMOVE_TAG			BIT(1)
140 #define PORT_QUEUE_SPLIT_L		BIT(0)
141 
142 #define REG_PORT_1_CTRL_1		0x11
143 #define REG_PORT_2_CTRL_1		0x21
144 #define REG_PORT_3_CTRL_1		0x31
145 #define REG_PORT_4_CTRL_1		0x41
146 #define REG_PORT_5_CTRL_1		0x51
147 
148 #define PORT_MIRROR_SNIFFER		BIT(7)
149 #define PORT_MIRROR_RX			BIT(6)
150 #define PORT_MIRROR_TX			BIT(5)
151 #define PORT_VLAN_MEMBERSHIP		KS_PORT_M
152 
153 #define REG_PORT_1_CTRL_2		0x12
154 #define REG_PORT_2_CTRL_2		0x22
155 #define REG_PORT_3_CTRL_2		0x32
156 #define REG_PORT_4_CTRL_2		0x42
157 #define REG_PORT_5_CTRL_2		0x52
158 
159 #define PORT_INGRESS_FILTER		BIT(6)
160 #define PORT_DISCARD_NON_VID		BIT(5)
161 #define PORT_FORCE_FLOW_CTRL		BIT(4)
162 #define PORT_BACK_PRESSURE		BIT(3)
163 #define PORT_TX_ENABLE			BIT(2)
164 #define PORT_RX_ENABLE			BIT(1)
165 #define PORT_LEARN_DISABLE		BIT(0)
166 
167 #define REG_PORT_1_CTRL_3		0x13
168 #define REG_PORT_2_CTRL_3		0x23
169 #define REG_PORT_3_CTRL_3		0x33
170 #define REG_PORT_4_CTRL_3		0x43
171 #define REG_PORT_5_CTRL_3		0x53
172 #define REG_PORT_1_CTRL_4		0x14
173 #define REG_PORT_2_CTRL_4		0x24
174 #define REG_PORT_3_CTRL_4		0x34
175 #define REG_PORT_4_CTRL_4		0x44
176 #define REG_PORT_5_CTRL_4		0x54
177 
178 #define PORT_DEFAULT_VID		0x0001
179 
180 #define REG_PORT_1_CTRL_5		0x15
181 #define REG_PORT_2_CTRL_5		0x25
182 #define REG_PORT_3_CTRL_5		0x35
183 #define REG_PORT_4_CTRL_5		0x45
184 #define REG_PORT_5_CTRL_5		0x55
185 
186 #define PORT_ACL_ENABLE			BIT(2)
187 #define PORT_AUTHEN_MODE		0x3
188 #define PORT_AUTHEN_PASS		0
189 #define PORT_AUTHEN_BLOCK		1
190 #define PORT_AUTHEN_TRAP		2
191 
192 #define REG_PORT_5_CTRL_6		0x56
193 
194 #define PORT_MII_INTERNAL_CLOCK		BIT(7)
195 #define PORT_GMII_1GPS_MODE		BIT(6)
196 #define PORT_RGMII_ID_IN_ENABLE		BIT(4)
197 #define PORT_RGMII_ID_OUT_ENABLE	BIT(3)
198 #define PORT_GMII_MAC_MODE		BIT(2)
199 #define PORT_INTERFACE_TYPE		0x3
200 #define PORT_INTERFACE_MII		0
201 #define PORT_INTERFACE_RMII		1
202 #define PORT_INTERFACE_GMII		2
203 #define PORT_INTERFACE_RGMII		3
204 
205 #define REG_PORT_1_CTRL_7		0x17
206 #define REG_PORT_2_CTRL_7		0x27
207 #define REG_PORT_3_CTRL_7		0x37
208 #define REG_PORT_4_CTRL_7		0x47
209 
210 #define PORT_AUTO_NEG_ASYM_PAUSE	BIT(5)
211 #define PORT_AUTO_NEG_SYM_PAUSE		BIT(4)
212 #define PORT_AUTO_NEG_100BTX_FD		BIT(3)
213 #define PORT_AUTO_NEG_100BTX		BIT(2)
214 #define PORT_AUTO_NEG_10BT_FD		BIT(1)
215 #define PORT_AUTO_NEG_10BT		BIT(0)
216 
217 #define REG_PORT_1_STATUS_0		0x18
218 #define REG_PORT_2_STATUS_0		0x28
219 #define REG_PORT_3_STATUS_0		0x38
220 #define REG_PORT_4_STATUS_0		0x48
221 
222 /* For KSZ8765. */
223 #define PORT_FIBER_MODE			BIT(7)
224 
225 #define PORT_REMOTE_ASYM_PAUSE		BIT(5)
226 #define PORT_REMOTE_SYM_PAUSE		BIT(4)
227 #define PORT_REMOTE_100BTX_FD		BIT(3)
228 #define PORT_REMOTE_100BTX		BIT(2)
229 #define PORT_REMOTE_10BT_FD		BIT(1)
230 #define PORT_REMOTE_10BT		BIT(0)
231 
232 #define REG_PORT_1_STATUS_1		0x19
233 #define REG_PORT_2_STATUS_1		0x29
234 #define REG_PORT_3_STATUS_1		0x39
235 #define REG_PORT_4_STATUS_1		0x49
236 
237 #define PORT_HP_MDIX			BIT(7)
238 #define PORT_REVERSED_POLARITY		BIT(5)
239 #define PORT_TX_FLOW_CTRL		BIT(4)
240 #define PORT_RX_FLOW_CTRL		BIT(3)
241 #define PORT_STAT_SPEED_100MBIT		BIT(2)
242 #define PORT_STAT_FULL_DUPLEX		BIT(1)
243 
244 #define PORT_REMOTE_FAULT		BIT(0)
245 
246 #define REG_PORT_1_LINK_MD_CTRL		0x1A
247 #define REG_PORT_2_LINK_MD_CTRL		0x2A
248 #define REG_PORT_3_LINK_MD_CTRL		0x3A
249 #define REG_PORT_4_LINK_MD_CTRL		0x4A
250 
251 #define PORT_CABLE_10M_SHORT		BIT(7)
252 #define PORT_CABLE_DIAG_RESULT_M	GENMASK(6, 5)
253 #define PORT_CABLE_DIAG_RESULT_S	5
254 #define PORT_CABLE_STAT_NORMAL		0
255 #define PORT_CABLE_STAT_OPEN		1
256 #define PORT_CABLE_STAT_SHORT		2
257 #define PORT_CABLE_STAT_FAILED		3
258 #define PORT_START_CABLE_DIAG		BIT(4)
259 #define PORT_FORCE_LINK			BIT(3)
260 #define PORT_POWER_SAVING		BIT(2)
261 #define PORT_PHY_REMOTE_LOOPBACK	BIT(1)
262 #define PORT_CABLE_FAULT_COUNTER_H	0x01
263 
264 #define REG_PORT_1_LINK_MD_RESULT	0x1B
265 #define REG_PORT_2_LINK_MD_RESULT	0x2B
266 #define REG_PORT_3_LINK_MD_RESULT	0x3B
267 #define REG_PORT_4_LINK_MD_RESULT	0x4B
268 
269 #define PORT_CABLE_FAULT_COUNTER_L	0xFF
270 #define PORT_CABLE_FAULT_COUNTER	0x1FF
271 
272 #define REG_PORT_1_CTRL_9		0x1C
273 #define REG_PORT_2_CTRL_9		0x2C
274 #define REG_PORT_3_CTRL_9		0x3C
275 #define REG_PORT_4_CTRL_9		0x4C
276 
277 #define PORT_AUTO_NEG_ENABLE		BIT(7)
278 #define PORT_AUTO_NEG_DISABLE		BIT(7)
279 #define PORT_FORCE_100_MBIT		BIT(6)
280 #define PORT_FORCE_FULL_DUPLEX		BIT(5)
281 
282 #define REG_PORT_1_CTRL_10		0x1D
283 #define REG_PORT_2_CTRL_10		0x2D
284 #define REG_PORT_3_CTRL_10		0x3D
285 #define REG_PORT_4_CTRL_10		0x4D
286 
287 #define PORT_LED_OFF			BIT(7)
288 #define PORT_TX_DISABLE			BIT(6)
289 #define PORT_AUTO_NEG_RESTART		BIT(5)
290 #define PORT_POWER_DOWN			BIT(3)
291 #define PORT_AUTO_MDIX_DISABLE		BIT(2)
292 #define PORT_FORCE_MDIX			BIT(1)
293 #define PORT_MAC_LOOPBACK		BIT(0)
294 
295 #define REG_PORT_1_STATUS_2		0x1E
296 #define REG_PORT_2_STATUS_2		0x2E
297 #define REG_PORT_3_STATUS_2		0x3E
298 #define REG_PORT_4_STATUS_2		0x4E
299 
300 #define PORT_MDIX_STATUS		BIT(7)
301 #define PORT_AUTO_NEG_COMPLETE		BIT(6)
302 #define PORT_STAT_LINK_GOOD		BIT(5)
303 
304 #define REG_PORT_1_STATUS_3		0x1F
305 #define REG_PORT_2_STATUS_3		0x2F
306 #define REG_PORT_3_STATUS_3		0x3F
307 #define REG_PORT_4_STATUS_3		0x4F
308 
309 #define PORT_PHY_LOOPBACK		BIT(7)
310 #define PORT_PHY_ISOLATE		BIT(5)
311 #define PORT_PHY_SOFT_RESET		BIT(4)
312 #define PORT_PHY_FORCE_LINK		BIT(3)
313 #define PORT_PHY_MODE_M			0x7
314 #define PHY_MODE_IN_AUTO_NEG		1
315 #define PHY_MODE_10BT_HALF		2
316 #define PHY_MODE_100BT_HALF		3
317 #define PHY_MODE_10BT_FULL		5
318 #define PHY_MODE_100BT_FULL		6
319 #define PHY_MODE_ISOLDATE		7
320 
321 #define REG_PORT_CTRL_0			0x00
322 #define REG_PORT_CTRL_1			0x01
323 #define REG_PORT_CTRL_2			0x02
324 #define REG_PORT_CTRL_VID		0x03
325 
326 #define REG_PORT_CTRL_5			0x05
327 
328 #define REG_PORT_STATUS_0		0x08
329 #define REG_PORT_STATUS_1		0x09
330 #define REG_PORT_LINK_MD_CTRL		0x0A
331 #define REG_PORT_LINK_MD_RESULT		0x0B
332 #define REG_PORT_CTRL_9			0x0C
333 #define REG_PORT_CTRL_10		0x0D
334 #define REG_PORT_STATUS_3		0x0F
335 
336 #define REG_PORT_CTRL_12		0xA0
337 #define REG_PORT_CTRL_13		0xA1
338 #define REG_PORT_RATE_CTRL_3		0xA2
339 #define REG_PORT_RATE_CTRL_2		0xA3
340 #define REG_PORT_RATE_CTRL_1		0xA4
341 #define REG_PORT_RATE_CTRL_0		0xA5
342 #define REG_PORT_RATE_LIMIT		0xA6
343 #define REG_PORT_IN_RATE_0		0xA7
344 #define REG_PORT_IN_RATE_1		0xA8
345 #define REG_PORT_IN_RATE_2		0xA9
346 #define REG_PORT_IN_RATE_3		0xAA
347 #define REG_PORT_OUT_RATE_0		0xAB
348 #define REG_PORT_OUT_RATE_1		0xAC
349 #define REG_PORT_OUT_RATE_2		0xAD
350 #define REG_PORT_OUT_RATE_3		0xAE
351 
352 #define PORT_CTRL_ADDR(port, addr)		\
353 	((addr) + REG_PORT_1_CTRL_0 + (port) *	\
354 		(REG_PORT_2_CTRL_0 - REG_PORT_1_CTRL_0))
355 
356 #define REG_SW_MAC_ADDR_0		0x68
357 #define REG_SW_MAC_ADDR_1		0x69
358 #define REG_SW_MAC_ADDR_2		0x6A
359 #define REG_SW_MAC_ADDR_3		0x6B
360 #define REG_SW_MAC_ADDR_4		0x6C
361 #define REG_SW_MAC_ADDR_5		0x6D
362 
363 #define TABLE_EXT_SELECT_S		5
364 #define TABLE_EEE_V			1
365 #define TABLE_ACL_V			2
366 #define TABLE_PME_V			4
367 #define TABLE_LINK_MD_V			5
368 #define TABLE_EEE			(TABLE_EEE_V << TABLE_EXT_SELECT_S)
369 #define TABLE_ACL			(TABLE_ACL_V << TABLE_EXT_SELECT_S)
370 #define TABLE_PME			(TABLE_PME_V << TABLE_EXT_SELECT_S)
371 #define TABLE_LINK_MD			(TABLE_LINK_MD << TABLE_EXT_SELECT_S)
372 #define TABLE_READ			BIT(4)
373 #define TABLE_SELECT_S			2
374 #define TABLE_STATIC_MAC_V		0
375 #define TABLE_VLAN_V			1
376 #define TABLE_DYNAMIC_MAC_V		2
377 #define TABLE_MIB_V			3
378 #define TABLE_STATIC_MAC		(TABLE_STATIC_MAC_V << TABLE_SELECT_S)
379 #define TABLE_VLAN			(TABLE_VLAN_V << TABLE_SELECT_S)
380 #define TABLE_DYNAMIC_MAC		(TABLE_DYNAMIC_MAC_V << TABLE_SELECT_S)
381 #define TABLE_MIB			(TABLE_MIB_V << TABLE_SELECT_S)
382 
383 #define REG_IND_CTRL_1			0x6F
384 
385 #define TABLE_ENTRY_MASK		0x03FF
386 #define TABLE_EXT_ENTRY_MASK		0x0FFF
387 
388 #define REG_IND_DATA_5			0x73
389 #define REG_IND_DATA_2			0x76
390 #define REG_IND_DATA_1			0x77
391 #define REG_IND_DATA_0			0x78
392 
393 #define REG_IND_DATA_PME_EEE_ACL	0xA0
394 
395 #define REG_INT_STATUS			0x7C
396 #define REG_INT_ENABLE			0x7D
397 
398 #define INT_PME				BIT(4)
399 
400 #define REG_ACL_INT_STATUS		0x7E
401 #define REG_ACL_INT_ENABLE		0x7F
402 
403 #define INT_PORT_5			BIT(4)
404 #define INT_PORT_4			BIT(3)
405 #define INT_PORT_3			BIT(2)
406 #define INT_PORT_2			BIT(1)
407 #define INT_PORT_1			BIT(0)
408 
409 #define INT_PORT_ALL			\
410 	(INT_PORT_5 | INT_PORT_4 | INT_PORT_3 | INT_PORT_2 | INT_PORT_1)
411 
412 #define REG_SW_CTRL_12			0x80
413 #define REG_SW_CTRL_13			0x81
414 
415 #define SWITCH_802_1P_MASK		3
416 #define SWITCH_802_1P_BASE		3
417 #define SWITCH_802_1P_SHIFT		2
418 
419 #define SW_802_1P_MAP_M			KS_PRIO_M
420 #define SW_802_1P_MAP_S			KS_PRIO_S
421 
422 #define REG_SWITCH_CTRL_14		0x82
423 
424 #define SW_PRIO_MAPPING_M		KS_PRIO_M
425 #define SW_PRIO_MAPPING_S		6
426 #define SW_PRIO_MAP_3_HI		0
427 #define SW_PRIO_MAP_2_HI		2
428 #define SW_PRIO_MAP_0_LO		3
429 
430 #define REG_SW_CTRL_15			0x83
431 #define REG_SW_CTRL_16			0x84
432 #define REG_SW_CTRL_17			0x85
433 #define REG_SW_CTRL_18			0x86
434 
435 #define SW_SELF_ADDR_FILTER_ENABLE	BIT(6)
436 
437 #define REG_SW_UNK_UCAST_CTRL		0x83
438 #define REG_SW_UNK_MCAST_CTRL		0x84
439 #define REG_SW_UNK_VID_CTRL		0x85
440 #define REG_SW_UNK_IP_MCAST_CTRL	0x86
441 
442 #define SW_UNK_FWD_ENABLE		BIT(5)
443 #define SW_UNK_FWD_MAP			KS_PORT_M
444 
445 #define REG_SW_CTRL_19			0x87
446 
447 #define SW_IN_RATE_LIMIT_PERIOD_M	0x3
448 #define SW_IN_RATE_LIMIT_PERIOD_S	4
449 #define SW_IN_RATE_LIMIT_16_MS		0
450 #define SW_IN_RATE_LIMIT_64_MS		1
451 #define SW_IN_RATE_LIMIT_256_MS		2
452 #define SW_OUT_RATE_LIMIT_QUEUE_BASED	BIT(3)
453 #define SW_INS_TAG_ENABLE		BIT(2)
454 
455 #define REG_TOS_PRIO_CTRL_0		0x90
456 #define REG_TOS_PRIO_CTRL_1		0x91
457 #define REG_TOS_PRIO_CTRL_2		0x92
458 #define REG_TOS_PRIO_CTRL_3		0x93
459 #define REG_TOS_PRIO_CTRL_4		0x94
460 #define REG_TOS_PRIO_CTRL_5		0x95
461 #define REG_TOS_PRIO_CTRL_6		0x96
462 #define REG_TOS_PRIO_CTRL_7		0x97
463 #define REG_TOS_PRIO_CTRL_8		0x98
464 #define REG_TOS_PRIO_CTRL_9		0x99
465 #define REG_TOS_PRIO_CTRL_10		0x9A
466 #define REG_TOS_PRIO_CTRL_11		0x9B
467 #define REG_TOS_PRIO_CTRL_12		0x9C
468 #define REG_TOS_PRIO_CTRL_13		0x9D
469 #define REG_TOS_PRIO_CTRL_14		0x9E
470 #define REG_TOS_PRIO_CTRL_15		0x9F
471 
472 #define TOS_PRIO_M			KS_PRIO_M
473 #define TOS_PRIO_S			KS_PRIO_S
474 
475 #define REG_SW_CTRL_20			0xA3
476 
477 #define SW_GMII_DRIVE_STRENGTH_S	4
478 #define SW_DRIVE_STRENGTH_M		0x7
479 #define SW_DRIVE_STRENGTH_2MA		0
480 #define SW_DRIVE_STRENGTH_4MA		1
481 #define SW_DRIVE_STRENGTH_8MA		2
482 #define SW_DRIVE_STRENGTH_12MA		3
483 #define SW_DRIVE_STRENGTH_16MA		4
484 #define SW_DRIVE_STRENGTH_20MA		5
485 #define SW_DRIVE_STRENGTH_24MA		6
486 #define SW_DRIVE_STRENGTH_28MA		7
487 #define SW_MII_DRIVE_STRENGTH_S		0
488 
489 #define REG_SW_CTRL_21			0xA4
490 
491 #define SW_IPV6_MLD_OPTION		BIT(3)
492 #define SW_IPV6_MLD_SNOOP		BIT(2)
493 
494 #define REG_PORT_1_CTRL_12		0xB0
495 #define REG_PORT_2_CTRL_12		0xC0
496 #define REG_PORT_3_CTRL_12		0xD0
497 #define REG_PORT_4_CTRL_12		0xE0
498 #define REG_PORT_5_CTRL_12		0xF0
499 
500 #define PORT_PASS_ALL			BIT(6)
501 #define PORT_INS_TAG_FOR_PORT_5_S	3
502 #define PORT_INS_TAG_FOR_PORT_5		BIT(3)
503 #define PORT_INS_TAG_FOR_PORT_4		BIT(2)
504 #define PORT_INS_TAG_FOR_PORT_3		BIT(1)
505 #define PORT_INS_TAG_FOR_PORT_2		BIT(0)
506 
507 #define REG_PORT_1_CTRL_13		0xB1
508 #define REG_PORT_2_CTRL_13		0xC1
509 #define REG_PORT_3_CTRL_13		0xD1
510 #define REG_PORT_4_CTRL_13		0xE1
511 #define REG_PORT_5_CTRL_13		0xF1
512 
513 #define PORT_QUEUE_SPLIT_H		BIT(1)
514 #define PORT_QUEUE_SPLIT_1		0
515 #define PORT_QUEUE_SPLIT_2		1
516 #define PORT_QUEUE_SPLIT_4		2
517 #define PORT_DROP_TAG			BIT(0)
518 
519 #define REG_PORT_1_CTRL_14		0xB2
520 #define REG_PORT_2_CTRL_14		0xC2
521 #define REG_PORT_3_CTRL_14		0xD2
522 #define REG_PORT_4_CTRL_14		0xE2
523 #define REG_PORT_5_CTRL_14		0xF2
524 #define REG_PORT_1_CTRL_15		0xB3
525 #define REG_PORT_2_CTRL_15		0xC3
526 #define REG_PORT_3_CTRL_15		0xD3
527 #define REG_PORT_4_CTRL_15		0xE3
528 #define REG_PORT_5_CTRL_15		0xF3
529 #define REG_PORT_1_CTRL_16		0xB4
530 #define REG_PORT_2_CTRL_16		0xC4
531 #define REG_PORT_3_CTRL_16		0xD4
532 #define REG_PORT_4_CTRL_16		0xE4
533 #define REG_PORT_5_CTRL_16		0xF4
534 #define REG_PORT_1_CTRL_17		0xB5
535 #define REG_PORT_2_CTRL_17		0xC5
536 #define REG_PORT_3_CTRL_17		0xD5
537 #define REG_PORT_4_CTRL_17		0xE5
538 #define REG_PORT_5_CTRL_17		0xF5
539 
540 #define REG_PORT_1_RATE_CTRL_3		0xB2
541 #define REG_PORT_1_RATE_CTRL_2		0xB3
542 #define REG_PORT_1_RATE_CTRL_1		0xB4
543 #define REG_PORT_1_RATE_CTRL_0		0xB5
544 #define REG_PORT_2_RATE_CTRL_3		0xC2
545 #define REG_PORT_2_RATE_CTRL_2		0xC3
546 #define REG_PORT_2_RATE_CTRL_1		0xC4
547 #define REG_PORT_2_RATE_CTRL_0		0xC5
548 #define REG_PORT_3_RATE_CTRL_3		0xD2
549 #define REG_PORT_3_RATE_CTRL_2		0xD3
550 #define REG_PORT_3_RATE_CTRL_1		0xD4
551 #define REG_PORT_3_RATE_CTRL_0		0xD5
552 #define REG_PORT_4_RATE_CTRL_3		0xE2
553 #define REG_PORT_4_RATE_CTRL_2		0xE3
554 #define REG_PORT_4_RATE_CTRL_1		0xE4
555 #define REG_PORT_4_RATE_CTRL_0		0xE5
556 #define REG_PORT_5_RATE_CTRL_3		0xF2
557 #define REG_PORT_5_RATE_CTRL_2		0xF3
558 #define REG_PORT_5_RATE_CTRL_1		0xF4
559 #define REG_PORT_5_RATE_CTRL_0		0xF5
560 
561 #define RATE_CTRL_ENABLE		BIT(7)
562 #define RATE_RATIO_M			(BIT(7) - 1)
563 
564 #define PORT_OUT_RATE_ENABLE		BIT(7)
565 
566 #define REG_PORT_1_RATE_LIMIT		0xB6
567 #define REG_PORT_2_RATE_LIMIT		0xC6
568 #define REG_PORT_3_RATE_LIMIT		0xD6
569 #define REG_PORT_4_RATE_LIMIT		0xE6
570 #define REG_PORT_5_RATE_LIMIT		0xF6
571 
572 #define PORT_IN_PORT_BASED_S		6
573 #define PORT_RATE_PACKET_BASED_S	5
574 #define PORT_IN_FLOW_CTRL_S		4
575 #define PORT_IN_LIMIT_MODE_M		0x3
576 #define PORT_IN_LIMIT_MODE_S		2
577 #define PORT_COUNT_IFG_S		1
578 #define PORT_COUNT_PREAMBLE_S		0
579 #define PORT_IN_PORT_BASED		BIT(PORT_IN_PORT_BASED_S)
580 #define PORT_RATE_PACKET_BASED		BIT(PORT_RATE_PACKET_BASED_S)
581 #define PORT_IN_FLOW_CTRL		BIT(PORT_IN_FLOW_CTRL_S)
582 #define PORT_IN_ALL			0
583 #define PORT_IN_UNICAST			1
584 #define PORT_IN_MULTICAST		2
585 #define PORT_IN_BROADCAST		3
586 #define PORT_COUNT_IFG			BIT(PORT_COUNT_IFG_S)
587 #define PORT_COUNT_PREAMBLE		BIT(PORT_COUNT_PREAMBLE_S)
588 
589 #define REG_PORT_1_IN_RATE_0		0xB7
590 #define REG_PORT_2_IN_RATE_0		0xC7
591 #define REG_PORT_3_IN_RATE_0		0xD7
592 #define REG_PORT_4_IN_RATE_0		0xE7
593 #define REG_PORT_5_IN_RATE_0		0xF7
594 #define REG_PORT_1_IN_RATE_1		0xB8
595 #define REG_PORT_2_IN_RATE_1		0xC8
596 #define REG_PORT_3_IN_RATE_1		0xD8
597 #define REG_PORT_4_IN_RATE_1		0xE8
598 #define REG_PORT_5_IN_RATE_1		0xF8
599 #define REG_PORT_1_IN_RATE_2		0xB9
600 #define REG_PORT_2_IN_RATE_2		0xC9
601 #define REG_PORT_3_IN_RATE_2		0xD9
602 #define REG_PORT_4_IN_RATE_2		0xE9
603 #define REG_PORT_5_IN_RATE_2		0xF9
604 #define REG_PORT_1_IN_RATE_3		0xBA
605 #define REG_PORT_2_IN_RATE_3		0xCA
606 #define REG_PORT_3_IN_RATE_3		0xDA
607 #define REG_PORT_4_IN_RATE_3		0xEA
608 #define REG_PORT_5_IN_RATE_3		0xFA
609 
610 #define PORT_IN_RATE_ENABLE		BIT(7)
611 #define PORT_RATE_LIMIT_M		(BIT(7) - 1)
612 
613 #define REG_PORT_1_OUT_RATE_0		0xBB
614 #define REG_PORT_2_OUT_RATE_0		0xCB
615 #define REG_PORT_3_OUT_RATE_0		0xDB
616 #define REG_PORT_4_OUT_RATE_0		0xEB
617 #define REG_PORT_5_OUT_RATE_0		0xFB
618 #define REG_PORT_1_OUT_RATE_1		0xBC
619 #define REG_PORT_2_OUT_RATE_1		0xCC
620 #define REG_PORT_3_OUT_RATE_1		0xDC
621 #define REG_PORT_4_OUT_RATE_1		0xEC
622 #define REG_PORT_5_OUT_RATE_1		0xFC
623 #define REG_PORT_1_OUT_RATE_2		0xBD
624 #define REG_PORT_2_OUT_RATE_2		0xCD
625 #define REG_PORT_3_OUT_RATE_2		0xDD
626 #define REG_PORT_4_OUT_RATE_2		0xED
627 #define REG_PORT_5_OUT_RATE_2		0xFD
628 #define REG_PORT_1_OUT_RATE_3		0xBE
629 #define REG_PORT_2_OUT_RATE_3		0xCE
630 #define REG_PORT_3_OUT_RATE_3		0xDE
631 #define REG_PORT_4_OUT_RATE_3		0xEE
632 #define REG_PORT_5_OUT_RATE_3		0xFE
633 
634 /* PME */
635 
636 #define SW_PME_OUTPUT_ENABLE		BIT(1)
637 #define SW_PME_ACTIVE_HIGH		BIT(0)
638 
639 #define PORT_MAGIC_PACKET_DETECT	BIT(2)
640 #define PORT_LINK_UP_DETECT		BIT(1)
641 #define PORT_ENERGY_DETECT		BIT(0)
642 
643 /* ACL */
644 
645 #define ACL_FIRST_RULE_M		0xF
646 
647 #define ACL_MODE_M			0x3
648 #define ACL_MODE_S			4
649 #define ACL_MODE_DISABLE		0
650 #define ACL_MODE_LAYER_2		1
651 #define ACL_MODE_LAYER_3		2
652 #define ACL_MODE_LAYER_4		3
653 #define ACL_ENABLE_M			0x3
654 #define ACL_ENABLE_S			2
655 #define ACL_ENABLE_2_COUNT		0
656 #define ACL_ENABLE_2_TYPE		1
657 #define ACL_ENABLE_2_MAC		2
658 #define ACL_ENABLE_2_BOTH		3
659 #define ACL_ENABLE_3_IP			1
660 #define ACL_ENABLE_3_SRC_DST_COMP	2
661 #define ACL_ENABLE_4_PROTOCOL		0
662 #define ACL_ENABLE_4_TCP_PORT_COMP	1
663 #define ACL_ENABLE_4_UDP_PORT_COMP	2
664 #define ACL_ENABLE_4_TCP_SEQN_COMP	3
665 #define ACL_SRC				BIT(1)
666 #define ACL_EQUAL			BIT(0)
667 
668 #define ACL_MAX_PORT			0xFFFF
669 
670 #define ACL_MIN_PORT			0xFFFF
671 #define ACL_IP_ADDR			0xFFFFFFFF
672 #define ACL_TCP_SEQNUM			0xFFFFFFFF
673 
674 #define ACL_RESERVED			0xF8
675 #define ACL_PORT_MODE_M			0x3
676 #define ACL_PORT_MODE_S			1
677 #define ACL_PORT_MODE_DISABLE		0
678 #define ACL_PORT_MODE_EITHER		1
679 #define ACL_PORT_MODE_IN_RANGE		2
680 #define ACL_PORT_MODE_OUT_OF_RANGE	3
681 
682 #define ACL_TCP_FLAG_ENABLE		BIT(0)
683 
684 #define ACL_TCP_FLAG_M			0xFF
685 
686 #define ACL_TCP_FLAG			0xFF
687 #define ACL_ETH_TYPE			0xFFFF
688 #define ACL_IP_M			0xFFFFFFFF
689 
690 #define ACL_PRIO_MODE_M			0x3
691 #define ACL_PRIO_MODE_S			6
692 #define ACL_PRIO_MODE_DISABLE		0
693 #define ACL_PRIO_MODE_HIGHER		1
694 #define ACL_PRIO_MODE_LOWER		2
695 #define ACL_PRIO_MODE_REPLACE		3
696 #define ACL_PRIO_M			0x7
697 #define ACL_PRIO_S			3
698 #define ACL_VLAN_PRIO_REPLACE		BIT(2)
699 #define ACL_VLAN_PRIO_M			0x7
700 #define ACL_VLAN_PRIO_HI_M		0x3
701 
702 #define ACL_VLAN_PRIO_LO_M		0x8
703 #define ACL_VLAN_PRIO_S			7
704 #define ACL_MAP_MODE_M			0x3
705 #define ACL_MAP_MODE_S			5
706 #define ACL_MAP_MODE_DISABLE		0
707 #define ACL_MAP_MODE_OR			1
708 #define ACL_MAP_MODE_AND		2
709 #define ACL_MAP_MODE_REPLACE		3
710 #define ACL_MAP_PORT_M			0x1F
711 
712 #define ACL_CNT_M			(BIT(11) - 1)
713 #define ACL_CNT_S			5
714 #define ACL_MSEC_UNIT			BIT(4)
715 #define ACL_INTR_MODE			BIT(3)
716 
717 #define REG_PORT_ACL_BYTE_EN_MSB	0x10
718 
719 #define ACL_BYTE_EN_MSB_M		0x3F
720 
721 #define REG_PORT_ACL_BYTE_EN_LSB	0x11
722 
723 #define ACL_ACTION_START		0xA
724 #define ACL_ACTION_LEN			2
725 #define ACL_INTR_CNT_START		0xB
726 #define ACL_RULESET_START		0xC
727 #define ACL_RULESET_LEN			2
728 #define ACL_TABLE_LEN			14
729 
730 #define ACL_ACTION_ENABLE		0x000C
731 #define ACL_MATCH_ENABLE		0x1FF0
732 #define ACL_RULESET_ENABLE		0x2003
733 #define ACL_BYTE_ENABLE			((ACL_BYTE_EN_MSB_M << 8) | 0xFF)
734 #define ACL_MODE_ENABLE			(0x10 << 8)
735 
736 #define REG_PORT_ACL_CTRL_0		0x12
737 
738 #define PORT_ACL_WRITE_DONE		BIT(6)
739 #define PORT_ACL_READ_DONE		BIT(5)
740 #define PORT_ACL_WRITE			BIT(4)
741 #define PORT_ACL_INDEX_M		0xF
742 
743 #define REG_PORT_ACL_CTRL_1		0x13
744 
745 #define PORT_ACL_FORCE_DLR_MISS		BIT(0)
746 
747 #define KSZ8795_ID_HI			0x0022
748 #define KSZ8795_ID_LO			0x1550
749 #define KSZ8863_ID_LO			0x1430
750 
751 #define KSZ8795_SW_ID			0x8795
752 
753 #define PHY_REG_LINK_MD			0x1D
754 
755 #define PHY_START_CABLE_DIAG		BIT(15)
756 #define PHY_CABLE_DIAG_RESULT_M		GENMASK(14, 13)
757 #define PHY_CABLE_DIAG_RESULT		0x6000
758 #define PHY_CABLE_STAT_NORMAL		0x0000
759 #define PHY_CABLE_STAT_OPEN		0x2000
760 #define PHY_CABLE_STAT_SHORT		0x4000
761 #define PHY_CABLE_STAT_FAILED		0x6000
762 #define PHY_CABLE_10M_SHORT		BIT(12)
763 #define PHY_CABLE_FAULT_COUNTER_M	GENMASK(8, 0)
764 
765 #define PHY_REG_PHY_CTRL		0x1F
766 
767 #define PHY_MODE_M			0x7
768 #define PHY_MODE_S			8
769 #define PHY_STAT_REVERSED_POLARITY	BIT(5)
770 #define PHY_STAT_MDIX			BIT(4)
771 #define PHY_FORCE_LINK			BIT(3)
772 #define PHY_POWER_SAVING_ENABLE		BIT(2)
773 #define PHY_REMOTE_LOOPBACK		BIT(1)
774 
775 /* Chip resource */
776 
777 #define PRIO_QUEUES			4
778 
779 #define KS_PRIO_IN_REG			4
780 
781 #define MIB_COUNTER_NUM		0x20
782 
783 /* Common names used by other drivers */
784 
785 #define P_BCAST_STORM_CTRL		REG_PORT_CTRL_0
786 #define P_PRIO_CTRL			REG_PORT_CTRL_0
787 #define P_TAG_CTRL			REG_PORT_CTRL_0
788 #define P_MIRROR_CTRL			REG_PORT_CTRL_1
789 #define P_802_1P_CTRL			REG_PORT_CTRL_2
790 #define P_STP_CTRL			REG_PORT_CTRL_2
791 #define P_PASS_ALL_CTRL			REG_PORT_CTRL_12
792 #define P_INS_SRC_PVID_CTRL		REG_PORT_CTRL_12
793 #define P_DROP_TAG_CTRL			REG_PORT_CTRL_13
794 #define P_RATE_LIMIT_CTRL		REG_PORT_RATE_LIMIT
795 
796 #define S_UNKNOWN_DA_CTRL		REG_SWITCH_CTRL_12
797 #define S_FORWARD_INVALID_VID_CTRL	REG_FORWARD_INVALID_VID
798 
799 #define S_FLUSH_TABLE_CTRL		REG_SW_CTRL_0
800 #define S_LINK_AGING_CTRL		REG_SW_CTRL_0
801 #define S_HUGE_PACKET_CTRL		REG_SW_CTRL_1
802 #define S_MIRROR_CTRL			REG_SW_CTRL_3
803 #define S_REPLACE_VID_CTRL		REG_SW_CTRL_4
804 #define S_PASS_PAUSE_CTRL		REG_SW_CTRL_10
805 #define S_802_1P_PRIO_CTRL		REG_SW_CTRL_12
806 #define S_TOS_PRIO_CTRL			REG_TOS_PRIO_CTRL_0
807 #define S_IPV6_MLD_CTRL			REG_SW_CTRL_21
808 
809 #define IND_ACC_TABLE(table)		((table) << 8)
810 
811 /* Driver set switch broadcast storm protection at 10% rate. */
812 #define BROADCAST_STORM_PROT_RATE	10
813 
814 /* 148,800 frames * 67 ms / 100 */
815 #define BROADCAST_STORM_VALUE		9969
816 
817 /**
818  * MIB_COUNTER_VALUE			00-00000000-3FFFFFFF
819  * MIB_TOTAL_BYTES			00-0000000F-FFFFFFFF
820  * MIB_PACKET_DROPPED			00-00000000-0000FFFF
821  * MIB_COUNTER_VALID			00-00000020-00000000
822  * MIB_COUNTER_OVERFLOW			00-00000040-00000000
823  */
824 
825 #define MIB_COUNTER_VALUE		0x3FFFFFFF
826 
827 #define KSZ8795_MIB_TOTAL_RX_0		0x100
828 #define KSZ8795_MIB_TOTAL_TX_0		0x101
829 #define KSZ8795_MIB_TOTAL_RX_1		0x104
830 #define KSZ8795_MIB_TOTAL_TX_1		0x105
831 
832 #define KSZ8863_MIB_PACKET_DROPPED_TX_0 0x100
833 #define KSZ8863_MIB_PACKET_DROPPED_RX_0 0x105
834 
835 #define MIB_PACKET_DROPPED		0x0000FFFF
836 
837 #define MIB_TOTAL_BYTES_H		0x0000000F
838 
839 #define TAIL_TAG_OVERRIDE		BIT(6)
840 #define TAIL_TAG_LOOKUP			BIT(7)
841 
842 #define FID_ENTRIES			128
843 
844 #endif
845