1e66f840cSTristram Ha /* SPDX-License-Identifier: GPL-2.0-or-later */ 2e66f840cSTristram Ha /* 3e66f840cSTristram Ha * Microchip KSZ8795 register definitions 4e66f840cSTristram Ha * 5e66f840cSTristram Ha * Copyright (c) 2017 Microchip Technology Inc. 6e66f840cSTristram Ha * Tristram Ha <Tristram.Ha@microchip.com> 7e66f840cSTristram Ha */ 8e66f840cSTristram Ha 9e66f840cSTristram Ha #ifndef __KSZ8795_REG_H 10e66f840cSTristram Ha #define __KSZ8795_REG_H 11e66f840cSTristram Ha 12e66f840cSTristram Ha #define KS_PORT_M 0x1F 13e66f840cSTristram Ha 14e66f840cSTristram Ha #define KS_PRIO_M 0x3 15e66f840cSTristram Ha #define KS_PRIO_S 2 16e66f840cSTristram Ha 17e66f840cSTristram Ha #define REG_CHIP_ID0 0x00 18e66f840cSTristram Ha 194b20a07eSOleksij Rempel #define KSZ87_FAMILY_ID 0x87 204b20a07eSOleksij Rempel #define KSZ88_FAMILY_ID 0x88 21e66f840cSTristram Ha 22e66f840cSTristram Ha #define REG_CHIP_ID1 0x01 23e66f840cSTristram Ha 24e66f840cSTristram Ha #define SW_CHIP_ID_M 0xF0 25e66f840cSTristram Ha #define SW_CHIP_ID_S 4 26e66f840cSTristram Ha #define SW_REVISION_M 0x0E 27e66f840cSTristram Ha #define SW_REVISION_S 1 28e66f840cSTristram Ha #define SW_START 0x01 29e66f840cSTristram Ha 30e66f840cSTristram Ha #define CHIP_ID_94 0x60 31e66f840cSTristram Ha #define CHIP_ID_95 0x90 324b20a07eSOleksij Rempel #define CHIP_ID_63 0x30 334b20a07eSOleksij Rempel 344b20a07eSOleksij Rempel #define KSZ8863_REG_SW_RESET 0x43 354b20a07eSOleksij Rempel 364b20a07eSOleksij Rempel #define KSZ8863_GLOBAL_SOFTWARE_RESET BIT(4) 374b20a07eSOleksij Rempel #define KSZ8863_PCS_RESET BIT(0) 38e66f840cSTristram Ha 39e66f840cSTristram Ha #define REG_SW_CTRL_0 0x02 40e66f840cSTristram Ha 41e66f840cSTristram Ha #define SW_NEW_BACKOFF BIT(7) 42e66f840cSTristram Ha #define SW_GLOBAL_RESET BIT(6) 43e66f840cSTristram Ha #define SW_FLUSH_DYN_MAC_TABLE BIT(5) 44e66f840cSTristram Ha #define SW_FLUSH_STA_MAC_TABLE BIT(4) 45e66f840cSTristram Ha #define SW_LINK_AUTO_AGING BIT(0) 46e66f840cSTristram Ha 47e66f840cSTristram Ha #define REG_SW_CTRL_1 0x03 48e66f840cSTristram Ha 49e66f840cSTristram Ha #define SW_HUGE_PACKET BIT(6) 50e66f840cSTristram Ha #define SW_TX_FLOW_CTRL_DISABLE BIT(5) 51e66f840cSTristram Ha #define SW_RX_FLOW_CTRL_DISABLE BIT(4) 52e66f840cSTristram Ha #define SW_CHECK_LENGTH BIT(3) 53e66f840cSTristram Ha #define SW_AGING_ENABLE BIT(2) 54e66f840cSTristram Ha #define SW_FAST_AGING BIT(1) 55e66f840cSTristram Ha #define SW_AGGR_BACKOFF BIT(0) 56e66f840cSTristram Ha 57e66f840cSTristram Ha #define REG_SW_CTRL_2 0x04 58e66f840cSTristram Ha 59e66f840cSTristram Ha #define UNICAST_VLAN_BOUNDARY BIT(7) 60e66f840cSTristram Ha #define MULTICAST_STORM_DISABLE BIT(6) 61e66f840cSTristram Ha #define SW_BACK_PRESSURE BIT(5) 62e66f840cSTristram Ha #define FAIR_FLOW_CTRL BIT(4) 63e66f840cSTristram Ha #define NO_EXC_COLLISION_DROP BIT(3) 64e66f840cSTristram Ha #define SW_LEGAL_PACKET_DISABLE BIT(1) 65e66f840cSTristram Ha 66e66f840cSTristram Ha #define REG_SW_CTRL_3 0x05 67e66f840cSTristram Ha #define WEIGHTED_FAIR_QUEUE_ENABLE BIT(3) 68e66f840cSTristram Ha 69e66f840cSTristram Ha #define SW_VLAN_ENABLE BIT(7) 70e66f840cSTristram Ha #define SW_IGMP_SNOOP BIT(6) 71e66f840cSTristram Ha #define SW_MIRROR_RX_TX BIT(0) 72e66f840cSTristram Ha 73e66f840cSTristram Ha #define REG_SW_CTRL_4 0x06 74e66f840cSTristram Ha 75e66f840cSTristram Ha #define SW_HALF_DUPLEX_FLOW_CTRL BIT(7) 76e66f840cSTristram Ha #define SW_HALF_DUPLEX BIT(6) 77e66f840cSTristram Ha #define SW_FLOW_CTRL BIT(5) 78e66f840cSTristram Ha #define SW_10_MBIT BIT(4) 79e66f840cSTristram Ha #define SW_REPLACE_VID BIT(3) 80e66f840cSTristram Ha #define BROADCAST_STORM_RATE_HI 0x07 81e66f840cSTristram Ha 82e66f840cSTristram Ha #define REG_SW_CTRL_5 0x07 83e66f840cSTristram Ha 84e66f840cSTristram Ha #define BROADCAST_STORM_RATE_LO 0xFF 85e66f840cSTristram Ha #define BROADCAST_STORM_RATE 0x07FF 86e66f840cSTristram Ha 87e66f840cSTristram Ha #define REG_SW_CTRL_6 0x08 88e66f840cSTristram Ha 89e66f840cSTristram Ha #define SW_MIB_COUNTER_FLUSH BIT(7) 90e66f840cSTristram Ha #define SW_MIB_COUNTER_FREEZE BIT(6) 91e66f840cSTristram Ha #define SW_MIB_COUNTER_CTRL_ENABLE KS_PORT_M 92e66f840cSTristram Ha 93e66f840cSTristram Ha #define REG_SW_CTRL_9 0x0B 94e66f840cSTristram Ha 95e66f840cSTristram Ha #define SPI_CLK_125_MHZ 0x80 96e66f840cSTristram Ha #define SPI_CLK_62_5_MHZ 0x40 97e66f840cSTristram Ha #define SPI_CLK_31_25_MHZ 0x00 98e66f840cSTristram Ha 99e66f840cSTristram Ha #define SW_LED_MODE_M 0x3 100e66f840cSTristram Ha #define SW_LED_MODE_S 4 101e66f840cSTristram Ha #define SW_LED_LINK_ACT_SPEED 0 102e66f840cSTristram Ha #define SW_LED_LINK_ACT 1 103e66f840cSTristram Ha #define SW_LED_LINK_ACT_DUPLEX 2 104e66f840cSTristram Ha #define SW_LED_LINK_DUPLEX 3 105e66f840cSTristram Ha 106e66f840cSTristram Ha #define REG_SW_CTRL_10 0x0C 107e66f840cSTristram Ha 108e66f840cSTristram Ha #define SW_PASS_PAUSE BIT(0) 109e66f840cSTristram Ha 110e66f840cSTristram Ha #define REG_SW_CTRL_11 0x0D 111e66f840cSTristram Ha 112e66f840cSTristram Ha #define REG_POWER_MANAGEMENT_1 0x0E 113e66f840cSTristram Ha 114e66f840cSTristram Ha #define SW_PLL_POWER_DOWN BIT(5) 115e66f840cSTristram Ha #define SW_POWER_MANAGEMENT_MODE_M 0x3 116e66f840cSTristram Ha #define SW_POWER_MANAGEMENT_MODE_S 3 117e66f840cSTristram Ha #define SW_POWER_NORMAL 0 118e66f840cSTristram Ha #define SW_ENERGY_DETECTION 1 119e66f840cSTristram Ha #define SW_SOFTWARE_POWER_DOWN 2 120e66f840cSTristram Ha 121e66f840cSTristram Ha #define REG_POWER_MANAGEMENT_2 0x0F 122e66f840cSTristram Ha 123e66f840cSTristram Ha #define REG_PORT_1_CTRL_0 0x10 124e66f840cSTristram Ha #define REG_PORT_2_CTRL_0 0x20 125e66f840cSTristram Ha #define REG_PORT_3_CTRL_0 0x30 126e66f840cSTristram Ha #define REG_PORT_4_CTRL_0 0x40 127e66f840cSTristram Ha #define REG_PORT_5_CTRL_0 0x50 128e66f840cSTristram Ha 129e66f840cSTristram Ha #define PORT_BROADCAST_STORM BIT(7) 130e66f840cSTristram Ha #define PORT_DIFFSERV_ENABLE BIT(6) 131e66f840cSTristram Ha #define PORT_802_1P_ENABLE BIT(5) 132e66f840cSTristram Ha #define PORT_BASED_PRIO_S 3 133e66f840cSTristram Ha #define PORT_BASED_PRIO_M KS_PRIO_M 134e66f840cSTristram Ha #define PORT_BASED_PRIO_0 0 135e66f840cSTristram Ha #define PORT_BASED_PRIO_1 1 136e66f840cSTristram Ha #define PORT_BASED_PRIO_2 2 137e66f840cSTristram Ha #define PORT_BASED_PRIO_3 3 138e66f840cSTristram Ha #define PORT_INSERT_TAG BIT(2) 139e66f840cSTristram Ha #define PORT_REMOVE_TAG BIT(1) 140e66f840cSTristram Ha #define PORT_QUEUE_SPLIT_L BIT(0) 141e66f840cSTristram Ha 142e66f840cSTristram Ha #define REG_PORT_1_CTRL_1 0x11 143e66f840cSTristram Ha #define REG_PORT_2_CTRL_1 0x21 144e66f840cSTristram Ha #define REG_PORT_3_CTRL_1 0x31 145e66f840cSTristram Ha #define REG_PORT_4_CTRL_1 0x41 146e66f840cSTristram Ha #define REG_PORT_5_CTRL_1 0x51 147e66f840cSTristram Ha 148e66f840cSTristram Ha #define PORT_MIRROR_SNIFFER BIT(7) 149e66f840cSTristram Ha #define PORT_MIRROR_RX BIT(6) 150e66f840cSTristram Ha #define PORT_MIRROR_TX BIT(5) 151e66f840cSTristram Ha #define PORT_VLAN_MEMBERSHIP KS_PORT_M 152e66f840cSTristram Ha 153e66f840cSTristram Ha #define REG_PORT_1_CTRL_2 0x12 154e66f840cSTristram Ha #define REG_PORT_2_CTRL_2 0x22 155e66f840cSTristram Ha #define REG_PORT_3_CTRL_2 0x32 156e66f840cSTristram Ha #define REG_PORT_4_CTRL_2 0x42 157e66f840cSTristram Ha #define REG_PORT_5_CTRL_2 0x52 158e66f840cSTristram Ha 159e66f840cSTristram Ha #define PORT_INGRESS_FILTER BIT(6) 160e66f840cSTristram Ha #define PORT_DISCARD_NON_VID BIT(5) 161e66f840cSTristram Ha #define PORT_FORCE_FLOW_CTRL BIT(4) 162e66f840cSTristram Ha #define PORT_BACK_PRESSURE BIT(3) 163e66f840cSTristram Ha #define PORT_TX_ENABLE BIT(2) 164e66f840cSTristram Ha #define PORT_RX_ENABLE BIT(1) 165e66f840cSTristram Ha #define PORT_LEARN_DISABLE BIT(0) 166e66f840cSTristram Ha 167e66f840cSTristram Ha #define REG_PORT_1_CTRL_3 0x13 168e66f840cSTristram Ha #define REG_PORT_2_CTRL_3 0x23 169e66f840cSTristram Ha #define REG_PORT_3_CTRL_3 0x33 170e66f840cSTristram Ha #define REG_PORT_4_CTRL_3 0x43 171e66f840cSTristram Ha #define REG_PORT_5_CTRL_3 0x53 172e66f840cSTristram Ha #define REG_PORT_1_CTRL_4 0x14 173e66f840cSTristram Ha #define REG_PORT_2_CTRL_4 0x24 174e66f840cSTristram Ha #define REG_PORT_3_CTRL_4 0x34 175e66f840cSTristram Ha #define REG_PORT_4_CTRL_4 0x44 176e66f840cSTristram Ha #define REG_PORT_5_CTRL_4 0x54 177e66f840cSTristram Ha 178e66f840cSTristram Ha #define PORT_DEFAULT_VID 0x0001 179e66f840cSTristram Ha 180e66f840cSTristram Ha #define REG_PORT_1_CTRL_5 0x15 181e66f840cSTristram Ha #define REG_PORT_2_CTRL_5 0x25 182e66f840cSTristram Ha #define REG_PORT_3_CTRL_5 0x35 183e66f840cSTristram Ha #define REG_PORT_4_CTRL_5 0x45 184e66f840cSTristram Ha #define REG_PORT_5_CTRL_5 0x55 185e66f840cSTristram Ha 186e66f840cSTristram Ha #define PORT_ACL_ENABLE BIT(2) 187e66f840cSTristram Ha #define PORT_AUTHEN_MODE 0x3 188e66f840cSTristram Ha #define PORT_AUTHEN_PASS 0 189e66f840cSTristram Ha #define PORT_AUTHEN_BLOCK 1 190e66f840cSTristram Ha #define PORT_AUTHEN_TRAP 2 191e66f840cSTristram Ha 192e66f840cSTristram Ha #define REG_PORT_5_CTRL_6 0x56 193e66f840cSTristram Ha 194e66f840cSTristram Ha #define PORT_MII_INTERNAL_CLOCK BIT(7) 195e66f840cSTristram Ha #define PORT_GMII_1GPS_MODE BIT(6) 196e66f840cSTristram Ha #define PORT_RGMII_ID_IN_ENABLE BIT(4) 197e66f840cSTristram Ha #define PORT_RGMII_ID_OUT_ENABLE BIT(3) 198e66f840cSTristram Ha #define PORT_GMII_MAC_MODE BIT(2) 199e66f840cSTristram Ha #define PORT_INTERFACE_TYPE 0x3 200e66f840cSTristram Ha #define PORT_INTERFACE_MII 0 201e66f840cSTristram Ha #define PORT_INTERFACE_RMII 1 202e66f840cSTristram Ha #define PORT_INTERFACE_GMII 2 203e66f840cSTristram Ha #define PORT_INTERFACE_RGMII 3 204e66f840cSTristram Ha 205e66f840cSTristram Ha #define REG_PORT_1_CTRL_7 0x17 206e66f840cSTristram Ha #define REG_PORT_2_CTRL_7 0x27 207e66f840cSTristram Ha #define REG_PORT_3_CTRL_7 0x37 208e66f840cSTristram Ha #define REG_PORT_4_CTRL_7 0x47 209e66f840cSTristram Ha 210e66f840cSTristram Ha #define PORT_AUTO_NEG_ASYM_PAUSE BIT(5) 211e66f840cSTristram Ha #define PORT_AUTO_NEG_SYM_PAUSE BIT(4) 212e66f840cSTristram Ha #define PORT_AUTO_NEG_100BTX_FD BIT(3) 213e66f840cSTristram Ha #define PORT_AUTO_NEG_100BTX BIT(2) 214e66f840cSTristram Ha #define PORT_AUTO_NEG_10BT_FD BIT(1) 215e66f840cSTristram Ha #define PORT_AUTO_NEG_10BT BIT(0) 216e66f840cSTristram Ha 217e66f840cSTristram Ha #define REG_PORT_1_STATUS_0 0x18 218e66f840cSTristram Ha #define REG_PORT_2_STATUS_0 0x28 219e66f840cSTristram Ha #define REG_PORT_3_STATUS_0 0x38 220e66f840cSTristram Ha #define REG_PORT_4_STATUS_0 0x48 221e66f840cSTristram Ha 222e66f840cSTristram Ha /* For KSZ8765. */ 223e66f840cSTristram Ha #define PORT_FIBER_MODE BIT(7) 224e66f840cSTristram Ha 225e66f840cSTristram Ha #define PORT_REMOTE_ASYM_PAUSE BIT(5) 226e66f840cSTristram Ha #define PORT_REMOTE_SYM_PAUSE BIT(4) 227e66f840cSTristram Ha #define PORT_REMOTE_100BTX_FD BIT(3) 228e66f840cSTristram Ha #define PORT_REMOTE_100BTX BIT(2) 229e66f840cSTristram Ha #define PORT_REMOTE_10BT_FD BIT(1) 230e66f840cSTristram Ha #define PORT_REMOTE_10BT BIT(0) 231e66f840cSTristram Ha 232e66f840cSTristram Ha #define REG_PORT_1_STATUS_1 0x19 233e66f840cSTristram Ha #define REG_PORT_2_STATUS_1 0x29 234e66f840cSTristram Ha #define REG_PORT_3_STATUS_1 0x39 235e66f840cSTristram Ha #define REG_PORT_4_STATUS_1 0x49 236e66f840cSTristram Ha 237e66f840cSTristram Ha #define PORT_HP_MDIX BIT(7) 238e66f840cSTristram Ha #define PORT_REVERSED_POLARITY BIT(5) 239e66f840cSTristram Ha #define PORT_TX_FLOW_CTRL BIT(4) 240e66f840cSTristram Ha #define PORT_RX_FLOW_CTRL BIT(3) 241e66f840cSTristram Ha #define PORT_STAT_SPEED_100MBIT BIT(2) 242e66f840cSTristram Ha #define PORT_STAT_FULL_DUPLEX BIT(1) 243e66f840cSTristram Ha 244e66f840cSTristram Ha #define PORT_REMOTE_FAULT BIT(0) 245e66f840cSTristram Ha 246e66f840cSTristram Ha #define REG_PORT_1_LINK_MD_CTRL 0x1A 247e66f840cSTristram Ha #define REG_PORT_2_LINK_MD_CTRL 0x2A 248e66f840cSTristram Ha #define REG_PORT_3_LINK_MD_CTRL 0x3A 249e66f840cSTristram Ha #define REG_PORT_4_LINK_MD_CTRL 0x4A 250e66f840cSTristram Ha 251e66f840cSTristram Ha #define PORT_CABLE_10M_SHORT BIT(7) 25236838050SOleksij Rempel #define PORT_CABLE_DIAG_RESULT_M GENMASK(6, 5) 253e66f840cSTristram Ha #define PORT_CABLE_DIAG_RESULT_S 5 254e66f840cSTristram Ha #define PORT_CABLE_STAT_NORMAL 0 255e66f840cSTristram Ha #define PORT_CABLE_STAT_OPEN 1 256e66f840cSTristram Ha #define PORT_CABLE_STAT_SHORT 2 257e66f840cSTristram Ha #define PORT_CABLE_STAT_FAILED 3 258e66f840cSTristram Ha #define PORT_START_CABLE_DIAG BIT(4) 259e66f840cSTristram Ha #define PORT_FORCE_LINK BIT(3) 260e66f840cSTristram Ha #define PORT_POWER_SAVING BIT(2) 261e66f840cSTristram Ha #define PORT_PHY_REMOTE_LOOPBACK BIT(1) 262e66f840cSTristram Ha #define PORT_CABLE_FAULT_COUNTER_H 0x01 263e66f840cSTristram Ha 264e66f840cSTristram Ha #define REG_PORT_1_LINK_MD_RESULT 0x1B 265e66f840cSTristram Ha #define REG_PORT_2_LINK_MD_RESULT 0x2B 266e66f840cSTristram Ha #define REG_PORT_3_LINK_MD_RESULT 0x3B 267e66f840cSTristram Ha #define REG_PORT_4_LINK_MD_RESULT 0x4B 268e66f840cSTristram Ha 269e66f840cSTristram Ha #define PORT_CABLE_FAULT_COUNTER_L 0xFF 270e66f840cSTristram Ha #define PORT_CABLE_FAULT_COUNTER 0x1FF 271e66f840cSTristram Ha 272e66f840cSTristram Ha #define REG_PORT_1_CTRL_9 0x1C 273e66f840cSTristram Ha #define REG_PORT_2_CTRL_9 0x2C 274e66f840cSTristram Ha #define REG_PORT_3_CTRL_9 0x3C 275e66f840cSTristram Ha #define REG_PORT_4_CTRL_9 0x4C 276e66f840cSTristram Ha 2774b20a07eSOleksij Rempel #define PORT_AUTO_NEG_ENABLE BIT(7) 278e66f840cSTristram Ha #define PORT_AUTO_NEG_DISABLE BIT(7) 279e66f840cSTristram Ha #define PORT_FORCE_100_MBIT BIT(6) 280e66f840cSTristram Ha #define PORT_FORCE_FULL_DUPLEX BIT(5) 281e66f840cSTristram Ha 282e66f840cSTristram Ha #define REG_PORT_1_CTRL_10 0x1D 283e66f840cSTristram Ha #define REG_PORT_2_CTRL_10 0x2D 284e66f840cSTristram Ha #define REG_PORT_3_CTRL_10 0x3D 285e66f840cSTristram Ha #define REG_PORT_4_CTRL_10 0x4D 286e66f840cSTristram Ha 287e66f840cSTristram Ha #define PORT_LED_OFF BIT(7) 288e66f840cSTristram Ha #define PORT_TX_DISABLE BIT(6) 289e66f840cSTristram Ha #define PORT_AUTO_NEG_RESTART BIT(5) 290e66f840cSTristram Ha #define PORT_POWER_DOWN BIT(3) 291e66f840cSTristram Ha #define PORT_AUTO_MDIX_DISABLE BIT(2) 292e66f840cSTristram Ha #define PORT_FORCE_MDIX BIT(1) 293e66f840cSTristram Ha #define PORT_MAC_LOOPBACK BIT(0) 294e66f840cSTristram Ha 295e66f840cSTristram Ha #define REG_PORT_1_STATUS_2 0x1E 296e66f840cSTristram Ha #define REG_PORT_2_STATUS_2 0x2E 297e66f840cSTristram Ha #define REG_PORT_3_STATUS_2 0x3E 298e66f840cSTristram Ha #define REG_PORT_4_STATUS_2 0x4E 299e66f840cSTristram Ha 300e66f840cSTristram Ha #define PORT_MDIX_STATUS BIT(7) 301e66f840cSTristram Ha #define PORT_AUTO_NEG_COMPLETE BIT(6) 302e66f840cSTristram Ha #define PORT_STAT_LINK_GOOD BIT(5) 303e66f840cSTristram Ha 304e66f840cSTristram Ha #define REG_PORT_1_STATUS_3 0x1F 305e66f840cSTristram Ha #define REG_PORT_2_STATUS_3 0x2F 306e66f840cSTristram Ha #define REG_PORT_3_STATUS_3 0x3F 307e66f840cSTristram Ha #define REG_PORT_4_STATUS_3 0x4F 308e66f840cSTristram Ha 309e66f840cSTristram Ha #define PORT_PHY_LOOPBACK BIT(7) 310e66f840cSTristram Ha #define PORT_PHY_ISOLATE BIT(5) 311e66f840cSTristram Ha #define PORT_PHY_SOFT_RESET BIT(4) 312e66f840cSTristram Ha #define PORT_PHY_FORCE_LINK BIT(3) 313e66f840cSTristram Ha #define PORT_PHY_MODE_M 0x7 314e66f840cSTristram Ha #define PHY_MODE_IN_AUTO_NEG 1 315e66f840cSTristram Ha #define PHY_MODE_10BT_HALF 2 316e66f840cSTristram Ha #define PHY_MODE_100BT_HALF 3 317e66f840cSTristram Ha #define PHY_MODE_10BT_FULL 5 318e66f840cSTristram Ha #define PHY_MODE_100BT_FULL 6 319e66f840cSTristram Ha #define PHY_MODE_ISOLDATE 7 320e66f840cSTristram Ha 321e66f840cSTristram Ha #define REG_PORT_CTRL_0 0x00 322e66f840cSTristram Ha #define REG_PORT_CTRL_1 0x01 323e66f840cSTristram Ha #define REG_PORT_CTRL_2 0x02 324e66f840cSTristram Ha #define REG_PORT_CTRL_VID 0x03 325e66f840cSTristram Ha 326e66f840cSTristram Ha #define REG_PORT_CTRL_5 0x05 327e66f840cSTristram Ha 328e66f840cSTristram Ha #define REG_PORT_STATUS_0 0x08 329e66f840cSTristram Ha #define REG_PORT_STATUS_1 0x09 330e66f840cSTristram Ha #define REG_PORT_LINK_MD_CTRL 0x0A 331e66f840cSTristram Ha #define REG_PORT_LINK_MD_RESULT 0x0B 332e66f840cSTristram Ha #define REG_PORT_CTRL_9 0x0C 333e66f840cSTristram Ha #define REG_PORT_CTRL_10 0x0D 334e66f840cSTristram Ha #define REG_PORT_STATUS_3 0x0F 335e66f840cSTristram Ha 336e66f840cSTristram Ha #define REG_PORT_CTRL_12 0xA0 337e66f840cSTristram Ha #define REG_PORT_CTRL_13 0xA1 338e66f840cSTristram Ha #define REG_PORT_RATE_CTRL_3 0xA2 339e66f840cSTristram Ha #define REG_PORT_RATE_CTRL_2 0xA3 340e66f840cSTristram Ha #define REG_PORT_RATE_CTRL_1 0xA4 341e66f840cSTristram Ha #define REG_PORT_RATE_CTRL_0 0xA5 342e66f840cSTristram Ha #define REG_PORT_RATE_LIMIT 0xA6 343e66f840cSTristram Ha #define REG_PORT_IN_RATE_0 0xA7 344e66f840cSTristram Ha #define REG_PORT_IN_RATE_1 0xA8 345e66f840cSTristram Ha #define REG_PORT_IN_RATE_2 0xA9 346e66f840cSTristram Ha #define REG_PORT_IN_RATE_3 0xAA 347e66f840cSTristram Ha #define REG_PORT_OUT_RATE_0 0xAB 348e66f840cSTristram Ha #define REG_PORT_OUT_RATE_1 0xAC 349e66f840cSTristram Ha #define REG_PORT_OUT_RATE_2 0xAD 350e66f840cSTristram Ha #define REG_PORT_OUT_RATE_3 0xAE 351e66f840cSTristram Ha 352e66f840cSTristram Ha #define PORT_CTRL_ADDR(port, addr) \ 353e66f840cSTristram Ha ((addr) + REG_PORT_1_CTRL_0 + (port) * \ 354e66f840cSTristram Ha (REG_PORT_2_CTRL_0 - REG_PORT_1_CTRL_0)) 355e66f840cSTristram Ha 356e66f840cSTristram Ha #define REG_SW_MAC_ADDR_0 0x68 357e66f840cSTristram Ha #define REG_SW_MAC_ADDR_1 0x69 358e66f840cSTristram Ha #define REG_SW_MAC_ADDR_2 0x6A 359e66f840cSTristram Ha #define REG_SW_MAC_ADDR_3 0x6B 360e66f840cSTristram Ha #define REG_SW_MAC_ADDR_4 0x6C 361e66f840cSTristram Ha #define REG_SW_MAC_ADDR_5 0x6D 362e66f840cSTristram Ha 363e66f840cSTristram Ha #define TABLE_EXT_SELECT_S 5 364e66f840cSTristram Ha #define TABLE_EEE_V 1 365e66f840cSTristram Ha #define TABLE_ACL_V 2 366e66f840cSTristram Ha #define TABLE_PME_V 4 367e66f840cSTristram Ha #define TABLE_LINK_MD_V 5 368e66f840cSTristram Ha #define TABLE_EEE (TABLE_EEE_V << TABLE_EXT_SELECT_S) 369e66f840cSTristram Ha #define TABLE_ACL (TABLE_ACL_V << TABLE_EXT_SELECT_S) 370e66f840cSTristram Ha #define TABLE_PME (TABLE_PME_V << TABLE_EXT_SELECT_S) 371e66f840cSTristram Ha #define TABLE_LINK_MD (TABLE_LINK_MD << TABLE_EXT_SELECT_S) 372e66f840cSTristram Ha #define TABLE_READ BIT(4) 373e66f840cSTristram Ha #define TABLE_SELECT_S 2 374e66f840cSTristram Ha #define TABLE_STATIC_MAC_V 0 375e66f840cSTristram Ha #define TABLE_VLAN_V 1 376e66f840cSTristram Ha #define TABLE_DYNAMIC_MAC_V 2 377e66f840cSTristram Ha #define TABLE_MIB_V 3 378e66f840cSTristram Ha #define TABLE_STATIC_MAC (TABLE_STATIC_MAC_V << TABLE_SELECT_S) 379e66f840cSTristram Ha #define TABLE_VLAN (TABLE_VLAN_V << TABLE_SELECT_S) 380e66f840cSTristram Ha #define TABLE_DYNAMIC_MAC (TABLE_DYNAMIC_MAC_V << TABLE_SELECT_S) 381e66f840cSTristram Ha #define TABLE_MIB (TABLE_MIB_V << TABLE_SELECT_S) 382e66f840cSTristram Ha 383e66f840cSTristram Ha #define REG_IND_CTRL_1 0x6F 384e66f840cSTristram Ha 385e66f840cSTristram Ha #define TABLE_ENTRY_MASK 0x03FF 386e66f840cSTristram Ha #define TABLE_EXT_ENTRY_MASK 0x0FFF 387e66f840cSTristram Ha 388e66f840cSTristram Ha #define REG_IND_DATA_5 0x73 389e66f840cSTristram Ha #define REG_IND_DATA_2 0x76 390e66f840cSTristram Ha #define REG_IND_DATA_1 0x77 391e66f840cSTristram Ha #define REG_IND_DATA_0 0x78 392e66f840cSTristram Ha 393e66f840cSTristram Ha #define REG_IND_DATA_PME_EEE_ACL 0xA0 394e66f840cSTristram Ha 395e66f840cSTristram Ha #define REG_INT_STATUS 0x7C 396e66f840cSTristram Ha #define REG_INT_ENABLE 0x7D 397e66f840cSTristram Ha 398e66f840cSTristram Ha #define INT_PME BIT(4) 399e66f840cSTristram Ha 400e66f840cSTristram Ha #define REG_ACL_INT_STATUS 0x7E 401e66f840cSTristram Ha #define REG_ACL_INT_ENABLE 0x7F 402e66f840cSTristram Ha 403e66f840cSTristram Ha #define INT_PORT_5 BIT(4) 404e66f840cSTristram Ha #define INT_PORT_4 BIT(3) 405e66f840cSTristram Ha #define INT_PORT_3 BIT(2) 406e66f840cSTristram Ha #define INT_PORT_2 BIT(1) 407e66f840cSTristram Ha #define INT_PORT_1 BIT(0) 408e66f840cSTristram Ha 409e66f840cSTristram Ha #define INT_PORT_ALL \ 410e66f840cSTristram Ha (INT_PORT_5 | INT_PORT_4 | INT_PORT_3 | INT_PORT_2 | INT_PORT_1) 411e66f840cSTristram Ha 412e66f840cSTristram Ha #define REG_SW_CTRL_12 0x80 413e66f840cSTristram Ha #define REG_SW_CTRL_13 0x81 414e66f840cSTristram Ha 415e66f840cSTristram Ha #define SWITCH_802_1P_MASK 3 416e66f840cSTristram Ha #define SWITCH_802_1P_BASE 3 417e66f840cSTristram Ha #define SWITCH_802_1P_SHIFT 2 418e66f840cSTristram Ha 419e66f840cSTristram Ha #define SW_802_1P_MAP_M KS_PRIO_M 420e66f840cSTristram Ha #define SW_802_1P_MAP_S KS_PRIO_S 421e66f840cSTristram Ha 422e66f840cSTristram Ha #define REG_SWITCH_CTRL_14 0x82 423e66f840cSTristram Ha 424e66f840cSTristram Ha #define SW_PRIO_MAPPING_M KS_PRIO_M 425e66f840cSTristram Ha #define SW_PRIO_MAPPING_S 6 426e66f840cSTristram Ha #define SW_PRIO_MAP_3_HI 0 427e66f840cSTristram Ha #define SW_PRIO_MAP_2_HI 2 428e66f840cSTristram Ha #define SW_PRIO_MAP_0_LO 3 429e66f840cSTristram Ha 430e66f840cSTristram Ha #define REG_SW_CTRL_15 0x83 431e66f840cSTristram Ha #define REG_SW_CTRL_16 0x84 432e66f840cSTristram Ha #define REG_SW_CTRL_17 0x85 433e66f840cSTristram Ha #define REG_SW_CTRL_18 0x86 434e66f840cSTristram Ha 435e66f840cSTristram Ha #define SW_SELF_ADDR_FILTER_ENABLE BIT(6) 436e66f840cSTristram Ha 437e66f840cSTristram Ha #define REG_SW_UNK_UCAST_CTRL 0x83 438e66f840cSTristram Ha #define REG_SW_UNK_MCAST_CTRL 0x84 439e66f840cSTristram Ha #define REG_SW_UNK_VID_CTRL 0x85 440e66f840cSTristram Ha #define REG_SW_UNK_IP_MCAST_CTRL 0x86 441e66f840cSTristram Ha 442e66f840cSTristram Ha #define SW_UNK_FWD_ENABLE BIT(5) 443e66f840cSTristram Ha #define SW_UNK_FWD_MAP KS_PORT_M 444e66f840cSTristram Ha 445e66f840cSTristram Ha #define REG_SW_CTRL_19 0x87 446e66f840cSTristram Ha 447e66f840cSTristram Ha #define SW_IN_RATE_LIMIT_PERIOD_M 0x3 448e66f840cSTristram Ha #define SW_IN_RATE_LIMIT_PERIOD_S 4 449e66f840cSTristram Ha #define SW_IN_RATE_LIMIT_16_MS 0 450e66f840cSTristram Ha #define SW_IN_RATE_LIMIT_64_MS 1 451e66f840cSTristram Ha #define SW_IN_RATE_LIMIT_256_MS 2 452e66f840cSTristram Ha #define SW_OUT_RATE_LIMIT_QUEUE_BASED BIT(3) 453e66f840cSTristram Ha #define SW_INS_TAG_ENABLE BIT(2) 454e66f840cSTristram Ha 455e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_0 0x90 456e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_1 0x91 457e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_2 0x92 458e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_3 0x93 459e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_4 0x94 460e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_5 0x95 461e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_6 0x96 462e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_7 0x97 463e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_8 0x98 464e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_9 0x99 465e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_10 0x9A 466e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_11 0x9B 467e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_12 0x9C 468e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_13 0x9D 469e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_14 0x9E 470e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_15 0x9F 471e66f840cSTristram Ha 472e66f840cSTristram Ha #define TOS_PRIO_M KS_PRIO_M 473e66f840cSTristram Ha #define TOS_PRIO_S KS_PRIO_S 474e66f840cSTristram Ha 475e66f840cSTristram Ha #define REG_SW_CTRL_20 0xA3 476e66f840cSTristram Ha 477e66f840cSTristram Ha #define SW_GMII_DRIVE_STRENGTH_S 4 478e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_M 0x7 479e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_2MA 0 480e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_4MA 1 481e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_8MA 2 482e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_12MA 3 483e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_16MA 4 484e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_20MA 5 485e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_24MA 6 486e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_28MA 7 487e66f840cSTristram Ha #define SW_MII_DRIVE_STRENGTH_S 0 488e66f840cSTristram Ha 489e66f840cSTristram Ha #define REG_SW_CTRL_21 0xA4 490e66f840cSTristram Ha 491e66f840cSTristram Ha #define SW_IPV6_MLD_OPTION BIT(3) 492e66f840cSTristram Ha #define SW_IPV6_MLD_SNOOP BIT(2) 493e66f840cSTristram Ha 494e66f840cSTristram Ha #define REG_PORT_1_CTRL_12 0xB0 495e66f840cSTristram Ha #define REG_PORT_2_CTRL_12 0xC0 496e66f840cSTristram Ha #define REG_PORT_3_CTRL_12 0xD0 497e66f840cSTristram Ha #define REG_PORT_4_CTRL_12 0xE0 498e66f840cSTristram Ha #define REG_PORT_5_CTRL_12 0xF0 499e66f840cSTristram Ha 500e66f840cSTristram Ha #define PORT_PASS_ALL BIT(6) 501e66f840cSTristram Ha #define PORT_INS_TAG_FOR_PORT_5_S 3 502e66f840cSTristram Ha #define PORT_INS_TAG_FOR_PORT_5 BIT(3) 503e66f840cSTristram Ha #define PORT_INS_TAG_FOR_PORT_4 BIT(2) 504e66f840cSTristram Ha #define PORT_INS_TAG_FOR_PORT_3 BIT(1) 505e66f840cSTristram Ha #define PORT_INS_TAG_FOR_PORT_2 BIT(0) 506e66f840cSTristram Ha 507e66f840cSTristram Ha #define REG_PORT_1_CTRL_13 0xB1 508e66f840cSTristram Ha #define REG_PORT_2_CTRL_13 0xC1 509e66f840cSTristram Ha #define REG_PORT_3_CTRL_13 0xD1 510e66f840cSTristram Ha #define REG_PORT_4_CTRL_13 0xE1 511e66f840cSTristram Ha #define REG_PORT_5_CTRL_13 0xF1 512e66f840cSTristram Ha 513e66f840cSTristram Ha #define PORT_QUEUE_SPLIT_H BIT(1) 514e66f840cSTristram Ha #define PORT_QUEUE_SPLIT_1 0 515e66f840cSTristram Ha #define PORT_QUEUE_SPLIT_2 1 516e66f840cSTristram Ha #define PORT_QUEUE_SPLIT_4 2 517e66f840cSTristram Ha #define PORT_DROP_TAG BIT(0) 518e66f840cSTristram Ha 519e66f840cSTristram Ha #define REG_PORT_1_CTRL_14 0xB2 520e66f840cSTristram Ha #define REG_PORT_2_CTRL_14 0xC2 521e66f840cSTristram Ha #define REG_PORT_3_CTRL_14 0xD2 522e66f840cSTristram Ha #define REG_PORT_4_CTRL_14 0xE2 523e66f840cSTristram Ha #define REG_PORT_5_CTRL_14 0xF2 524e66f840cSTristram Ha #define REG_PORT_1_CTRL_15 0xB3 525e66f840cSTristram Ha #define REG_PORT_2_CTRL_15 0xC3 526e66f840cSTristram Ha #define REG_PORT_3_CTRL_15 0xD3 527e66f840cSTristram Ha #define REG_PORT_4_CTRL_15 0xE3 528e66f840cSTristram Ha #define REG_PORT_5_CTRL_15 0xF3 529e66f840cSTristram Ha #define REG_PORT_1_CTRL_16 0xB4 530e66f840cSTristram Ha #define REG_PORT_2_CTRL_16 0xC4 531e66f840cSTristram Ha #define REG_PORT_3_CTRL_16 0xD4 532e66f840cSTristram Ha #define REG_PORT_4_CTRL_16 0xE4 533e66f840cSTristram Ha #define REG_PORT_5_CTRL_16 0xF4 534e66f840cSTristram Ha #define REG_PORT_1_CTRL_17 0xB5 535e66f840cSTristram Ha #define REG_PORT_2_CTRL_17 0xC5 536e66f840cSTristram Ha #define REG_PORT_3_CTRL_17 0xD5 537e66f840cSTristram Ha #define REG_PORT_4_CTRL_17 0xE5 538e66f840cSTristram Ha #define REG_PORT_5_CTRL_17 0xF5 539e66f840cSTristram Ha 540e66f840cSTristram Ha #define REG_PORT_1_RATE_CTRL_3 0xB2 541e66f840cSTristram Ha #define REG_PORT_1_RATE_CTRL_2 0xB3 542e66f840cSTristram Ha #define REG_PORT_1_RATE_CTRL_1 0xB4 543e66f840cSTristram Ha #define REG_PORT_1_RATE_CTRL_0 0xB5 544e66f840cSTristram Ha #define REG_PORT_2_RATE_CTRL_3 0xC2 545e66f840cSTristram Ha #define REG_PORT_2_RATE_CTRL_2 0xC3 546e66f840cSTristram Ha #define REG_PORT_2_RATE_CTRL_1 0xC4 547e66f840cSTristram Ha #define REG_PORT_2_RATE_CTRL_0 0xC5 548e66f840cSTristram Ha #define REG_PORT_3_RATE_CTRL_3 0xD2 549e66f840cSTristram Ha #define REG_PORT_3_RATE_CTRL_2 0xD3 550e66f840cSTristram Ha #define REG_PORT_3_RATE_CTRL_1 0xD4 551e66f840cSTristram Ha #define REG_PORT_3_RATE_CTRL_0 0xD5 552e66f840cSTristram Ha #define REG_PORT_4_RATE_CTRL_3 0xE2 553e66f840cSTristram Ha #define REG_PORT_4_RATE_CTRL_2 0xE3 554e66f840cSTristram Ha #define REG_PORT_4_RATE_CTRL_1 0xE4 555e66f840cSTristram Ha #define REG_PORT_4_RATE_CTRL_0 0xE5 556e66f840cSTristram Ha #define REG_PORT_5_RATE_CTRL_3 0xF2 557e66f840cSTristram Ha #define REG_PORT_5_RATE_CTRL_2 0xF3 558e66f840cSTristram Ha #define REG_PORT_5_RATE_CTRL_1 0xF4 559e66f840cSTristram Ha #define REG_PORT_5_RATE_CTRL_0 0xF5 560e66f840cSTristram Ha 561e66f840cSTristram Ha #define RATE_CTRL_ENABLE BIT(7) 562e66f840cSTristram Ha #define RATE_RATIO_M (BIT(7) - 1) 563e66f840cSTristram Ha 564e66f840cSTristram Ha #define PORT_OUT_RATE_ENABLE BIT(7) 565e66f840cSTristram Ha 566e66f840cSTristram Ha #define REG_PORT_1_RATE_LIMIT 0xB6 567e66f840cSTristram Ha #define REG_PORT_2_RATE_LIMIT 0xC6 568e66f840cSTristram Ha #define REG_PORT_3_RATE_LIMIT 0xD6 569e66f840cSTristram Ha #define REG_PORT_4_RATE_LIMIT 0xE6 570e66f840cSTristram Ha #define REG_PORT_5_RATE_LIMIT 0xF6 571e66f840cSTristram Ha 572e66f840cSTristram Ha #define PORT_IN_PORT_BASED_S 6 573e66f840cSTristram Ha #define PORT_RATE_PACKET_BASED_S 5 574e66f840cSTristram Ha #define PORT_IN_FLOW_CTRL_S 4 575e66f840cSTristram Ha #define PORT_IN_LIMIT_MODE_M 0x3 576e66f840cSTristram Ha #define PORT_IN_LIMIT_MODE_S 2 577e66f840cSTristram Ha #define PORT_COUNT_IFG_S 1 578e66f840cSTristram Ha #define PORT_COUNT_PREAMBLE_S 0 579e66f840cSTristram Ha #define PORT_IN_PORT_BASED BIT(PORT_IN_PORT_BASED_S) 580e66f840cSTristram Ha #define PORT_RATE_PACKET_BASED BIT(PORT_RATE_PACKET_BASED_S) 581e66f840cSTristram Ha #define PORT_IN_FLOW_CTRL BIT(PORT_IN_FLOW_CTRL_S) 582e66f840cSTristram Ha #define PORT_IN_ALL 0 583e66f840cSTristram Ha #define PORT_IN_UNICAST 1 584e66f840cSTristram Ha #define PORT_IN_MULTICAST 2 585e66f840cSTristram Ha #define PORT_IN_BROADCAST 3 586e66f840cSTristram Ha #define PORT_COUNT_IFG BIT(PORT_COUNT_IFG_S) 587e66f840cSTristram Ha #define PORT_COUNT_PREAMBLE BIT(PORT_COUNT_PREAMBLE_S) 588e66f840cSTristram Ha 589e66f840cSTristram Ha #define REG_PORT_1_IN_RATE_0 0xB7 590e66f840cSTristram Ha #define REG_PORT_2_IN_RATE_0 0xC7 591e66f840cSTristram Ha #define REG_PORT_3_IN_RATE_0 0xD7 592e66f840cSTristram Ha #define REG_PORT_4_IN_RATE_0 0xE7 593e66f840cSTristram Ha #define REG_PORT_5_IN_RATE_0 0xF7 594e66f840cSTristram Ha #define REG_PORT_1_IN_RATE_1 0xB8 595e66f840cSTristram Ha #define REG_PORT_2_IN_RATE_1 0xC8 596e66f840cSTristram Ha #define REG_PORT_3_IN_RATE_1 0xD8 597e66f840cSTristram Ha #define REG_PORT_4_IN_RATE_1 0xE8 598e66f840cSTristram Ha #define REG_PORT_5_IN_RATE_1 0xF8 599e66f840cSTristram Ha #define REG_PORT_1_IN_RATE_2 0xB9 600e66f840cSTristram Ha #define REG_PORT_2_IN_RATE_2 0xC9 601e66f840cSTristram Ha #define REG_PORT_3_IN_RATE_2 0xD9 602e66f840cSTristram Ha #define REG_PORT_4_IN_RATE_2 0xE9 603e66f840cSTristram Ha #define REG_PORT_5_IN_RATE_2 0xF9 604e66f840cSTristram Ha #define REG_PORT_1_IN_RATE_3 0xBA 605e66f840cSTristram Ha #define REG_PORT_2_IN_RATE_3 0xCA 606e66f840cSTristram Ha #define REG_PORT_3_IN_RATE_3 0xDA 607e66f840cSTristram Ha #define REG_PORT_4_IN_RATE_3 0xEA 608e66f840cSTristram Ha #define REG_PORT_5_IN_RATE_3 0xFA 609e66f840cSTristram Ha 610e66f840cSTristram Ha #define PORT_IN_RATE_ENABLE BIT(7) 611e66f840cSTristram Ha #define PORT_RATE_LIMIT_M (BIT(7) - 1) 612e66f840cSTristram Ha 613e66f840cSTristram Ha #define REG_PORT_1_OUT_RATE_0 0xBB 614e66f840cSTristram Ha #define REG_PORT_2_OUT_RATE_0 0xCB 615e66f840cSTristram Ha #define REG_PORT_3_OUT_RATE_0 0xDB 616e66f840cSTristram Ha #define REG_PORT_4_OUT_RATE_0 0xEB 617e66f840cSTristram Ha #define REG_PORT_5_OUT_RATE_0 0xFB 618e66f840cSTristram Ha #define REG_PORT_1_OUT_RATE_1 0xBC 619e66f840cSTristram Ha #define REG_PORT_2_OUT_RATE_1 0xCC 620e66f840cSTristram Ha #define REG_PORT_3_OUT_RATE_1 0xDC 621e66f840cSTristram Ha #define REG_PORT_4_OUT_RATE_1 0xEC 622e66f840cSTristram Ha #define REG_PORT_5_OUT_RATE_1 0xFC 623e66f840cSTristram Ha #define REG_PORT_1_OUT_RATE_2 0xBD 624e66f840cSTristram Ha #define REG_PORT_2_OUT_RATE_2 0xCD 625e66f840cSTristram Ha #define REG_PORT_3_OUT_RATE_2 0xDD 626e66f840cSTristram Ha #define REG_PORT_4_OUT_RATE_2 0xED 627e66f840cSTristram Ha #define REG_PORT_5_OUT_RATE_2 0xFD 628e66f840cSTristram Ha #define REG_PORT_1_OUT_RATE_3 0xBE 629e66f840cSTristram Ha #define REG_PORT_2_OUT_RATE_3 0xCE 630e66f840cSTristram Ha #define REG_PORT_3_OUT_RATE_3 0xDE 631e66f840cSTristram Ha #define REG_PORT_4_OUT_RATE_3 0xEE 632e66f840cSTristram Ha #define REG_PORT_5_OUT_RATE_3 0xFE 633e66f840cSTristram Ha 634*ef3b02a1SBen Hutchings /* 88x3 specific */ 635*ef3b02a1SBen Hutchings 636*ef3b02a1SBen Hutchings #define REG_SW_INSERT_SRC_PVID 0xC2 637*ef3b02a1SBen Hutchings 638e66f840cSTristram Ha /* PME */ 639e66f840cSTristram Ha 640e66f840cSTristram Ha #define SW_PME_OUTPUT_ENABLE BIT(1) 641e66f840cSTristram Ha #define SW_PME_ACTIVE_HIGH BIT(0) 642e66f840cSTristram Ha 643e66f840cSTristram Ha #define PORT_MAGIC_PACKET_DETECT BIT(2) 644e66f840cSTristram Ha #define PORT_LINK_UP_DETECT BIT(1) 645e66f840cSTristram Ha #define PORT_ENERGY_DETECT BIT(0) 646e66f840cSTristram Ha 647e66f840cSTristram Ha /* ACL */ 648e66f840cSTristram Ha 649e66f840cSTristram Ha #define ACL_FIRST_RULE_M 0xF 650e66f840cSTristram Ha 651e66f840cSTristram Ha #define ACL_MODE_M 0x3 652e66f840cSTristram Ha #define ACL_MODE_S 4 653e66f840cSTristram Ha #define ACL_MODE_DISABLE 0 654e66f840cSTristram Ha #define ACL_MODE_LAYER_2 1 655e66f840cSTristram Ha #define ACL_MODE_LAYER_3 2 656e66f840cSTristram Ha #define ACL_MODE_LAYER_4 3 657e66f840cSTristram Ha #define ACL_ENABLE_M 0x3 658e66f840cSTristram Ha #define ACL_ENABLE_S 2 659e66f840cSTristram Ha #define ACL_ENABLE_2_COUNT 0 660e66f840cSTristram Ha #define ACL_ENABLE_2_TYPE 1 661e66f840cSTristram Ha #define ACL_ENABLE_2_MAC 2 662e66f840cSTristram Ha #define ACL_ENABLE_2_BOTH 3 663e66f840cSTristram Ha #define ACL_ENABLE_3_IP 1 664e66f840cSTristram Ha #define ACL_ENABLE_3_SRC_DST_COMP 2 665e66f840cSTristram Ha #define ACL_ENABLE_4_PROTOCOL 0 666e66f840cSTristram Ha #define ACL_ENABLE_4_TCP_PORT_COMP 1 667e66f840cSTristram Ha #define ACL_ENABLE_4_UDP_PORT_COMP 2 668e66f840cSTristram Ha #define ACL_ENABLE_4_TCP_SEQN_COMP 3 669e66f840cSTristram Ha #define ACL_SRC BIT(1) 670e66f840cSTristram Ha #define ACL_EQUAL BIT(0) 671e66f840cSTristram Ha 672e66f840cSTristram Ha #define ACL_MAX_PORT 0xFFFF 673e66f840cSTristram Ha 674e66f840cSTristram Ha #define ACL_MIN_PORT 0xFFFF 675e66f840cSTristram Ha #define ACL_IP_ADDR 0xFFFFFFFF 676e66f840cSTristram Ha #define ACL_TCP_SEQNUM 0xFFFFFFFF 677e66f840cSTristram Ha 678e66f840cSTristram Ha #define ACL_RESERVED 0xF8 679e66f840cSTristram Ha #define ACL_PORT_MODE_M 0x3 680e66f840cSTristram Ha #define ACL_PORT_MODE_S 1 681e66f840cSTristram Ha #define ACL_PORT_MODE_DISABLE 0 682e66f840cSTristram Ha #define ACL_PORT_MODE_EITHER 1 683e66f840cSTristram Ha #define ACL_PORT_MODE_IN_RANGE 2 684e66f840cSTristram Ha #define ACL_PORT_MODE_OUT_OF_RANGE 3 685e66f840cSTristram Ha 686e66f840cSTristram Ha #define ACL_TCP_FLAG_ENABLE BIT(0) 687e66f840cSTristram Ha 688e66f840cSTristram Ha #define ACL_TCP_FLAG_M 0xFF 689e66f840cSTristram Ha 690e66f840cSTristram Ha #define ACL_TCP_FLAG 0xFF 691e66f840cSTristram Ha #define ACL_ETH_TYPE 0xFFFF 692e66f840cSTristram Ha #define ACL_IP_M 0xFFFFFFFF 693e66f840cSTristram Ha 694e66f840cSTristram Ha #define ACL_PRIO_MODE_M 0x3 695e66f840cSTristram Ha #define ACL_PRIO_MODE_S 6 696e66f840cSTristram Ha #define ACL_PRIO_MODE_DISABLE 0 697e66f840cSTristram Ha #define ACL_PRIO_MODE_HIGHER 1 698e66f840cSTristram Ha #define ACL_PRIO_MODE_LOWER 2 699e66f840cSTristram Ha #define ACL_PRIO_MODE_REPLACE 3 700e66f840cSTristram Ha #define ACL_PRIO_M 0x7 701e66f840cSTristram Ha #define ACL_PRIO_S 3 702e66f840cSTristram Ha #define ACL_VLAN_PRIO_REPLACE BIT(2) 703e66f840cSTristram Ha #define ACL_VLAN_PRIO_M 0x7 704e66f840cSTristram Ha #define ACL_VLAN_PRIO_HI_M 0x3 705e66f840cSTristram Ha 706e66f840cSTristram Ha #define ACL_VLAN_PRIO_LO_M 0x8 707e66f840cSTristram Ha #define ACL_VLAN_PRIO_S 7 708e66f840cSTristram Ha #define ACL_MAP_MODE_M 0x3 709e66f840cSTristram Ha #define ACL_MAP_MODE_S 5 710e66f840cSTristram Ha #define ACL_MAP_MODE_DISABLE 0 711e66f840cSTristram Ha #define ACL_MAP_MODE_OR 1 712e66f840cSTristram Ha #define ACL_MAP_MODE_AND 2 713e66f840cSTristram Ha #define ACL_MAP_MODE_REPLACE 3 714e66f840cSTristram Ha #define ACL_MAP_PORT_M 0x1F 715e66f840cSTristram Ha 716e66f840cSTristram Ha #define ACL_CNT_M (BIT(11) - 1) 717e66f840cSTristram Ha #define ACL_CNT_S 5 718e66f840cSTristram Ha #define ACL_MSEC_UNIT BIT(4) 719e66f840cSTristram Ha #define ACL_INTR_MODE BIT(3) 720e66f840cSTristram Ha 721e66f840cSTristram Ha #define REG_PORT_ACL_BYTE_EN_MSB 0x10 722e66f840cSTristram Ha 723e66f840cSTristram Ha #define ACL_BYTE_EN_MSB_M 0x3F 724e66f840cSTristram Ha 725e66f840cSTristram Ha #define REG_PORT_ACL_BYTE_EN_LSB 0x11 726e66f840cSTristram Ha 727e66f840cSTristram Ha #define ACL_ACTION_START 0xA 728e66f840cSTristram Ha #define ACL_ACTION_LEN 2 729e66f840cSTristram Ha #define ACL_INTR_CNT_START 0xB 730e66f840cSTristram Ha #define ACL_RULESET_START 0xC 731e66f840cSTristram Ha #define ACL_RULESET_LEN 2 732e66f840cSTristram Ha #define ACL_TABLE_LEN 14 733e66f840cSTristram Ha 734e66f840cSTristram Ha #define ACL_ACTION_ENABLE 0x000C 735e66f840cSTristram Ha #define ACL_MATCH_ENABLE 0x1FF0 736e66f840cSTristram Ha #define ACL_RULESET_ENABLE 0x2003 737e66f840cSTristram Ha #define ACL_BYTE_ENABLE ((ACL_BYTE_EN_MSB_M << 8) | 0xFF) 738e66f840cSTristram Ha #define ACL_MODE_ENABLE (0x10 << 8) 739e66f840cSTristram Ha 740e66f840cSTristram Ha #define REG_PORT_ACL_CTRL_0 0x12 741e66f840cSTristram Ha 742e66f840cSTristram Ha #define PORT_ACL_WRITE_DONE BIT(6) 743e66f840cSTristram Ha #define PORT_ACL_READ_DONE BIT(5) 744e66f840cSTristram Ha #define PORT_ACL_WRITE BIT(4) 745e66f840cSTristram Ha #define PORT_ACL_INDEX_M 0xF 746e66f840cSTristram Ha 747e66f840cSTristram Ha #define REG_PORT_ACL_CTRL_1 0x13 748e66f840cSTristram Ha 749e66f840cSTristram Ha #define PORT_ACL_FORCE_DLR_MISS BIT(0) 750e66f840cSTristram Ha 751e66f840cSTristram Ha #define KSZ8795_ID_HI 0x0022 752e66f840cSTristram Ha #define KSZ8795_ID_LO 0x1550 7534b20a07eSOleksij Rempel #define KSZ8863_ID_LO 0x1430 754e66f840cSTristram Ha 755e66f840cSTristram Ha #define KSZ8795_SW_ID 0x8795 756e66f840cSTristram Ha 757e66f840cSTristram Ha #define PHY_REG_LINK_MD 0x1D 758e66f840cSTristram Ha 759e66f840cSTristram Ha #define PHY_START_CABLE_DIAG BIT(15) 76036838050SOleksij Rempel #define PHY_CABLE_DIAG_RESULT_M GENMASK(14, 13) 761e66f840cSTristram Ha #define PHY_CABLE_DIAG_RESULT 0x6000 762e66f840cSTristram Ha #define PHY_CABLE_STAT_NORMAL 0x0000 763e66f840cSTristram Ha #define PHY_CABLE_STAT_OPEN 0x2000 764e66f840cSTristram Ha #define PHY_CABLE_STAT_SHORT 0x4000 765e66f840cSTristram Ha #define PHY_CABLE_STAT_FAILED 0x6000 766e66f840cSTristram Ha #define PHY_CABLE_10M_SHORT BIT(12) 76736838050SOleksij Rempel #define PHY_CABLE_FAULT_COUNTER_M GENMASK(8, 0) 768e66f840cSTristram Ha 769e66f840cSTristram Ha #define PHY_REG_PHY_CTRL 0x1F 770e66f840cSTristram Ha 771e66f840cSTristram Ha #define PHY_MODE_M 0x7 772e66f840cSTristram Ha #define PHY_MODE_S 8 773e66f840cSTristram Ha #define PHY_STAT_REVERSED_POLARITY BIT(5) 774e66f840cSTristram Ha #define PHY_STAT_MDIX BIT(4) 775e66f840cSTristram Ha #define PHY_FORCE_LINK BIT(3) 776e66f840cSTristram Ha #define PHY_POWER_SAVING_ENABLE BIT(2) 777e66f840cSTristram Ha #define PHY_REMOTE_LOOPBACK BIT(1) 778e66f840cSTristram Ha 779e66f840cSTristram Ha /* Chip resource */ 780e66f840cSTristram Ha 781e66f840cSTristram Ha #define PRIO_QUEUES 4 782e66f840cSTristram Ha 783e66f840cSTristram Ha #define KS_PRIO_IN_REG 4 784e66f840cSTristram Ha 7854b20a07eSOleksij Rempel #define MIB_COUNTER_NUM 0x20 786e66f840cSTristram Ha 787e66f840cSTristram Ha /* Common names used by other drivers */ 788e66f840cSTristram Ha 789e66f840cSTristram Ha #define P_BCAST_STORM_CTRL REG_PORT_CTRL_0 790e66f840cSTristram Ha #define P_PRIO_CTRL REG_PORT_CTRL_0 791e66f840cSTristram Ha #define P_TAG_CTRL REG_PORT_CTRL_0 792e66f840cSTristram Ha #define P_MIRROR_CTRL REG_PORT_CTRL_1 793e66f840cSTristram Ha #define P_802_1P_CTRL REG_PORT_CTRL_2 794e66f840cSTristram Ha #define P_STP_CTRL REG_PORT_CTRL_2 795e66f840cSTristram Ha #define P_PASS_ALL_CTRL REG_PORT_CTRL_12 796e66f840cSTristram Ha #define P_INS_SRC_PVID_CTRL REG_PORT_CTRL_12 797e66f840cSTristram Ha #define P_DROP_TAG_CTRL REG_PORT_CTRL_13 798e66f840cSTristram Ha #define P_RATE_LIMIT_CTRL REG_PORT_RATE_LIMIT 799e66f840cSTristram Ha 800e66f840cSTristram Ha #define S_UNKNOWN_DA_CTRL REG_SWITCH_CTRL_12 801e66f840cSTristram Ha #define S_FORWARD_INVALID_VID_CTRL REG_FORWARD_INVALID_VID 802e66f840cSTristram Ha 803e66f840cSTristram Ha #define S_FLUSH_TABLE_CTRL REG_SW_CTRL_0 804e66f840cSTristram Ha #define S_LINK_AGING_CTRL REG_SW_CTRL_0 805e66f840cSTristram Ha #define S_HUGE_PACKET_CTRL REG_SW_CTRL_1 806e66f840cSTristram Ha #define S_MIRROR_CTRL REG_SW_CTRL_3 807e66f840cSTristram Ha #define S_REPLACE_VID_CTRL REG_SW_CTRL_4 808e66f840cSTristram Ha #define S_PASS_PAUSE_CTRL REG_SW_CTRL_10 809e66f840cSTristram Ha #define S_802_1P_PRIO_CTRL REG_SW_CTRL_12 810e66f840cSTristram Ha #define S_TOS_PRIO_CTRL REG_TOS_PRIO_CTRL_0 811e66f840cSTristram Ha #define S_IPV6_MLD_CTRL REG_SW_CTRL_21 812e66f840cSTristram Ha 813e66f840cSTristram Ha #define IND_ACC_TABLE(table) ((table) << 8) 814e66f840cSTristram Ha 815e66f840cSTristram Ha /* Driver set switch broadcast storm protection at 10% rate. */ 816e66f840cSTristram Ha #define BROADCAST_STORM_PROT_RATE 10 817e66f840cSTristram Ha 818e66f840cSTristram Ha /* 148,800 frames * 67 ms / 100 */ 819e66f840cSTristram Ha #define BROADCAST_STORM_VALUE 9969 820e66f840cSTristram Ha 821e66f840cSTristram Ha /** 822e66f840cSTristram Ha * MIB_COUNTER_VALUE 00-00000000-3FFFFFFF 823e66f840cSTristram Ha * MIB_TOTAL_BYTES 00-0000000F-FFFFFFFF 824e66f840cSTristram Ha * MIB_PACKET_DROPPED 00-00000000-0000FFFF 825e66f840cSTristram Ha * MIB_COUNTER_VALID 00-00000020-00000000 826e66f840cSTristram Ha * MIB_COUNTER_OVERFLOW 00-00000040-00000000 827e66f840cSTristram Ha */ 828e66f840cSTristram Ha 829e66f840cSTristram Ha #define MIB_COUNTER_VALUE 0x3FFFFFFF 830e66f840cSTristram Ha 8314b20a07eSOleksij Rempel #define KSZ8795_MIB_TOTAL_RX_0 0x100 8324b20a07eSOleksij Rempel #define KSZ8795_MIB_TOTAL_TX_0 0x101 8334b20a07eSOleksij Rempel #define KSZ8795_MIB_TOTAL_RX_1 0x104 8344b20a07eSOleksij Rempel #define KSZ8795_MIB_TOTAL_TX_1 0x105 8354b20a07eSOleksij Rempel 8364b20a07eSOleksij Rempel #define KSZ8863_MIB_PACKET_DROPPED_TX_0 0x100 8374b20a07eSOleksij Rempel #define KSZ8863_MIB_PACKET_DROPPED_RX_0 0x105 838e66f840cSTristram Ha 839e66f840cSTristram Ha #define MIB_PACKET_DROPPED 0x0000FFFF 840e66f840cSTristram Ha 841e66f840cSTristram Ha #define MIB_TOTAL_BYTES_H 0x0000000F 842e66f840cSTristram Ha 843e66f840cSTristram Ha #define TAIL_TAG_OVERRIDE BIT(6) 844e66f840cSTristram Ha #define TAIL_TAG_LOOKUP BIT(7) 845e66f840cSTristram Ha 846e66f840cSTristram Ha #define FID_ENTRIES 128 847e66f840cSTristram Ha 848e66f840cSTristram Ha #endif 849