1e66f840cSTristram Ha /* SPDX-License-Identifier: GPL-2.0-or-later */ 2e66f840cSTristram Ha /* 3e66f840cSTristram Ha * Microchip KSZ8795 register definitions 4e66f840cSTristram Ha * 5e66f840cSTristram Ha * Copyright (c) 2017 Microchip Technology Inc. 6e66f840cSTristram Ha * Tristram Ha <Tristram.Ha@microchip.com> 7e66f840cSTristram Ha */ 8e66f840cSTristram Ha 9e66f840cSTristram Ha #ifndef __KSZ8795_REG_H 10e66f840cSTristram Ha #define __KSZ8795_REG_H 11e66f840cSTristram Ha 12e66f840cSTristram Ha #define KS_PORT_M 0x1F 13e66f840cSTristram Ha 14e66f840cSTristram Ha #define KS_PRIO_M 0x3 15e66f840cSTristram Ha #define KS_PRIO_S 2 16e66f840cSTristram Ha 17e66f840cSTristram Ha #define REG_CHIP_ID0 0x00 18e66f840cSTristram Ha 19e66f840cSTristram Ha #define FAMILY_ID 0x87 20e66f840cSTristram Ha 21e66f840cSTristram Ha #define REG_CHIP_ID1 0x01 22e66f840cSTristram Ha 23e66f840cSTristram Ha #define SW_CHIP_ID_M 0xF0 24e66f840cSTristram Ha #define SW_CHIP_ID_S 4 25e66f840cSTristram Ha #define SW_REVISION_M 0x0E 26e66f840cSTristram Ha #define SW_REVISION_S 1 27e66f840cSTristram Ha #define SW_START 0x01 28e66f840cSTristram Ha 29e66f840cSTristram Ha #define CHIP_ID_94 0x60 30e66f840cSTristram Ha #define CHIP_ID_95 0x90 31e66f840cSTristram Ha 32e66f840cSTristram Ha #define REG_SW_CTRL_0 0x02 33e66f840cSTristram Ha 34e66f840cSTristram Ha #define SW_NEW_BACKOFF BIT(7) 35e66f840cSTristram Ha #define SW_GLOBAL_RESET BIT(6) 36e66f840cSTristram Ha #define SW_FLUSH_DYN_MAC_TABLE BIT(5) 37e66f840cSTristram Ha #define SW_FLUSH_STA_MAC_TABLE BIT(4) 38e66f840cSTristram Ha #define SW_LINK_AUTO_AGING BIT(0) 39e66f840cSTristram Ha 40e66f840cSTristram Ha #define REG_SW_CTRL_1 0x03 41e66f840cSTristram Ha 42e66f840cSTristram Ha #define SW_HUGE_PACKET BIT(6) 43e66f840cSTristram Ha #define SW_TX_FLOW_CTRL_DISABLE BIT(5) 44e66f840cSTristram Ha #define SW_RX_FLOW_CTRL_DISABLE BIT(4) 45e66f840cSTristram Ha #define SW_CHECK_LENGTH BIT(3) 46e66f840cSTristram Ha #define SW_AGING_ENABLE BIT(2) 47e66f840cSTristram Ha #define SW_FAST_AGING BIT(1) 48e66f840cSTristram Ha #define SW_AGGR_BACKOFF BIT(0) 49e66f840cSTristram Ha 50e66f840cSTristram Ha #define REG_SW_CTRL_2 0x04 51e66f840cSTristram Ha 52e66f840cSTristram Ha #define UNICAST_VLAN_BOUNDARY BIT(7) 53e66f840cSTristram Ha #define MULTICAST_STORM_DISABLE BIT(6) 54e66f840cSTristram Ha #define SW_BACK_PRESSURE BIT(5) 55e66f840cSTristram Ha #define FAIR_FLOW_CTRL BIT(4) 56e66f840cSTristram Ha #define NO_EXC_COLLISION_DROP BIT(3) 57e66f840cSTristram Ha #define SW_LEGAL_PACKET_DISABLE BIT(1) 58e66f840cSTristram Ha 59e66f840cSTristram Ha #define REG_SW_CTRL_3 0x05 60e66f840cSTristram Ha #define WEIGHTED_FAIR_QUEUE_ENABLE BIT(3) 61e66f840cSTristram Ha 62e66f840cSTristram Ha #define SW_VLAN_ENABLE BIT(7) 63e66f840cSTristram Ha #define SW_IGMP_SNOOP BIT(6) 64e66f840cSTristram Ha #define SW_MIRROR_RX_TX BIT(0) 65e66f840cSTristram Ha 66e66f840cSTristram Ha #define REG_SW_CTRL_4 0x06 67e66f840cSTristram Ha 68e66f840cSTristram Ha #define SW_HALF_DUPLEX_FLOW_CTRL BIT(7) 69e66f840cSTristram Ha #define SW_HALF_DUPLEX BIT(6) 70e66f840cSTristram Ha #define SW_FLOW_CTRL BIT(5) 71e66f840cSTristram Ha #define SW_10_MBIT BIT(4) 72e66f840cSTristram Ha #define SW_REPLACE_VID BIT(3) 73e66f840cSTristram Ha #define BROADCAST_STORM_RATE_HI 0x07 74e66f840cSTristram Ha 75e66f840cSTristram Ha #define REG_SW_CTRL_5 0x07 76e66f840cSTristram Ha 77e66f840cSTristram Ha #define BROADCAST_STORM_RATE_LO 0xFF 78e66f840cSTristram Ha #define BROADCAST_STORM_RATE 0x07FF 79e66f840cSTristram Ha 80e66f840cSTristram Ha #define REG_SW_CTRL_6 0x08 81e66f840cSTristram Ha 82e66f840cSTristram Ha #define SW_MIB_COUNTER_FLUSH BIT(7) 83e66f840cSTristram Ha #define SW_MIB_COUNTER_FREEZE BIT(6) 84e66f840cSTristram Ha #define SW_MIB_COUNTER_CTRL_ENABLE KS_PORT_M 85e66f840cSTristram Ha 86e66f840cSTristram Ha #define REG_SW_CTRL_9 0x0B 87e66f840cSTristram Ha 88e66f840cSTristram Ha #define SPI_CLK_125_MHZ 0x80 89e66f840cSTristram Ha #define SPI_CLK_62_5_MHZ 0x40 90e66f840cSTristram Ha #define SPI_CLK_31_25_MHZ 0x00 91e66f840cSTristram Ha 92e66f840cSTristram Ha #define SW_LED_MODE_M 0x3 93e66f840cSTristram Ha #define SW_LED_MODE_S 4 94e66f840cSTristram Ha #define SW_LED_LINK_ACT_SPEED 0 95e66f840cSTristram Ha #define SW_LED_LINK_ACT 1 96e66f840cSTristram Ha #define SW_LED_LINK_ACT_DUPLEX 2 97e66f840cSTristram Ha #define SW_LED_LINK_DUPLEX 3 98e66f840cSTristram Ha 99e66f840cSTristram Ha #define REG_SW_CTRL_10 0x0C 100e66f840cSTristram Ha 101e66f840cSTristram Ha #define SW_TAIL_TAG_ENABLE BIT(1) 102e66f840cSTristram Ha #define SW_PASS_PAUSE BIT(0) 103e66f840cSTristram Ha 104e66f840cSTristram Ha #define REG_SW_CTRL_11 0x0D 105e66f840cSTristram Ha 106e66f840cSTristram Ha #define REG_POWER_MANAGEMENT_1 0x0E 107e66f840cSTristram Ha 108e66f840cSTristram Ha #define SW_PLL_POWER_DOWN BIT(5) 109e66f840cSTristram Ha #define SW_POWER_MANAGEMENT_MODE_M 0x3 110e66f840cSTristram Ha #define SW_POWER_MANAGEMENT_MODE_S 3 111e66f840cSTristram Ha #define SW_POWER_NORMAL 0 112e66f840cSTristram Ha #define SW_ENERGY_DETECTION 1 113e66f840cSTristram Ha #define SW_SOFTWARE_POWER_DOWN 2 114e66f840cSTristram Ha 115e66f840cSTristram Ha #define REG_POWER_MANAGEMENT_2 0x0F 116e66f840cSTristram Ha 117e66f840cSTristram Ha #define REG_PORT_1_CTRL_0 0x10 118e66f840cSTristram Ha #define REG_PORT_2_CTRL_0 0x20 119e66f840cSTristram Ha #define REG_PORT_3_CTRL_0 0x30 120e66f840cSTristram Ha #define REG_PORT_4_CTRL_0 0x40 121e66f840cSTristram Ha #define REG_PORT_5_CTRL_0 0x50 122e66f840cSTristram Ha 123e66f840cSTristram Ha #define PORT_BROADCAST_STORM BIT(7) 124e66f840cSTristram Ha #define PORT_DIFFSERV_ENABLE BIT(6) 125e66f840cSTristram Ha #define PORT_802_1P_ENABLE BIT(5) 126e66f840cSTristram Ha #define PORT_BASED_PRIO_S 3 127e66f840cSTristram Ha #define PORT_BASED_PRIO_M KS_PRIO_M 128e66f840cSTristram Ha #define PORT_BASED_PRIO_0 0 129e66f840cSTristram Ha #define PORT_BASED_PRIO_1 1 130e66f840cSTristram Ha #define PORT_BASED_PRIO_2 2 131e66f840cSTristram Ha #define PORT_BASED_PRIO_3 3 132e66f840cSTristram Ha #define PORT_INSERT_TAG BIT(2) 133e66f840cSTristram Ha #define PORT_REMOVE_TAG BIT(1) 134e66f840cSTristram Ha #define PORT_QUEUE_SPLIT_L BIT(0) 135e66f840cSTristram Ha 136e66f840cSTristram Ha #define REG_PORT_1_CTRL_1 0x11 137e66f840cSTristram Ha #define REG_PORT_2_CTRL_1 0x21 138e66f840cSTristram Ha #define REG_PORT_3_CTRL_1 0x31 139e66f840cSTristram Ha #define REG_PORT_4_CTRL_1 0x41 140e66f840cSTristram Ha #define REG_PORT_5_CTRL_1 0x51 141e66f840cSTristram Ha 142e66f840cSTristram Ha #define PORT_MIRROR_SNIFFER BIT(7) 143e66f840cSTristram Ha #define PORT_MIRROR_RX BIT(6) 144e66f840cSTristram Ha #define PORT_MIRROR_TX BIT(5) 145e66f840cSTristram Ha #define PORT_VLAN_MEMBERSHIP KS_PORT_M 146e66f840cSTristram Ha 147e66f840cSTristram Ha #define REG_PORT_1_CTRL_2 0x12 148e66f840cSTristram Ha #define REG_PORT_2_CTRL_2 0x22 149e66f840cSTristram Ha #define REG_PORT_3_CTRL_2 0x32 150e66f840cSTristram Ha #define REG_PORT_4_CTRL_2 0x42 151e66f840cSTristram Ha #define REG_PORT_5_CTRL_2 0x52 152e66f840cSTristram Ha 153e66f840cSTristram Ha #define PORT_802_1P_REMAPPING BIT(7) 154e66f840cSTristram Ha #define PORT_INGRESS_FILTER BIT(6) 155e66f840cSTristram Ha #define PORT_DISCARD_NON_VID BIT(5) 156e66f840cSTristram Ha #define PORT_FORCE_FLOW_CTRL BIT(4) 157e66f840cSTristram Ha #define PORT_BACK_PRESSURE BIT(3) 158e66f840cSTristram Ha #define PORT_TX_ENABLE BIT(2) 159e66f840cSTristram Ha #define PORT_RX_ENABLE BIT(1) 160e66f840cSTristram Ha #define PORT_LEARN_DISABLE BIT(0) 161e66f840cSTristram Ha 162e66f840cSTristram Ha #define REG_PORT_1_CTRL_3 0x13 163e66f840cSTristram Ha #define REG_PORT_2_CTRL_3 0x23 164e66f840cSTristram Ha #define REG_PORT_3_CTRL_3 0x33 165e66f840cSTristram Ha #define REG_PORT_4_CTRL_3 0x43 166e66f840cSTristram Ha #define REG_PORT_5_CTRL_3 0x53 167e66f840cSTristram Ha #define REG_PORT_1_CTRL_4 0x14 168e66f840cSTristram Ha #define REG_PORT_2_CTRL_4 0x24 169e66f840cSTristram Ha #define REG_PORT_3_CTRL_4 0x34 170e66f840cSTristram Ha #define REG_PORT_4_CTRL_4 0x44 171e66f840cSTristram Ha #define REG_PORT_5_CTRL_4 0x54 172e66f840cSTristram Ha 173e66f840cSTristram Ha #define PORT_DEFAULT_VID 0x0001 174e66f840cSTristram Ha 175e66f840cSTristram Ha #define REG_PORT_1_CTRL_5 0x15 176e66f840cSTristram Ha #define REG_PORT_2_CTRL_5 0x25 177e66f840cSTristram Ha #define REG_PORT_3_CTRL_5 0x35 178e66f840cSTristram Ha #define REG_PORT_4_CTRL_5 0x45 179e66f840cSTristram Ha #define REG_PORT_5_CTRL_5 0x55 180e66f840cSTristram Ha 181e66f840cSTristram Ha #define PORT_ACL_ENABLE BIT(2) 182e66f840cSTristram Ha #define PORT_AUTHEN_MODE 0x3 183e66f840cSTristram Ha #define PORT_AUTHEN_PASS 0 184e66f840cSTristram Ha #define PORT_AUTHEN_BLOCK 1 185e66f840cSTristram Ha #define PORT_AUTHEN_TRAP 2 186e66f840cSTristram Ha 187e66f840cSTristram Ha #define REG_PORT_5_CTRL_6 0x56 188e66f840cSTristram Ha 189e66f840cSTristram Ha #define PORT_MII_INTERNAL_CLOCK BIT(7) 190e66f840cSTristram Ha #define PORT_GMII_1GPS_MODE BIT(6) 191e66f840cSTristram Ha #define PORT_RGMII_ID_IN_ENABLE BIT(4) 192e66f840cSTristram Ha #define PORT_RGMII_ID_OUT_ENABLE BIT(3) 193e66f840cSTristram Ha #define PORT_GMII_MAC_MODE BIT(2) 194e66f840cSTristram Ha #define PORT_INTERFACE_TYPE 0x3 195e66f840cSTristram Ha #define PORT_INTERFACE_MII 0 196e66f840cSTristram Ha #define PORT_INTERFACE_RMII 1 197e66f840cSTristram Ha #define PORT_INTERFACE_GMII 2 198e66f840cSTristram Ha #define PORT_INTERFACE_RGMII 3 199e66f840cSTristram Ha 200e66f840cSTristram Ha #define REG_PORT_1_CTRL_7 0x17 201e66f840cSTristram Ha #define REG_PORT_2_CTRL_7 0x27 202e66f840cSTristram Ha #define REG_PORT_3_CTRL_7 0x37 203e66f840cSTristram Ha #define REG_PORT_4_CTRL_7 0x47 204e66f840cSTristram Ha 205e66f840cSTristram Ha #define PORT_AUTO_NEG_ASYM_PAUSE BIT(5) 206e66f840cSTristram Ha #define PORT_AUTO_NEG_SYM_PAUSE BIT(4) 207e66f840cSTristram Ha #define PORT_AUTO_NEG_100BTX_FD BIT(3) 208e66f840cSTristram Ha #define PORT_AUTO_NEG_100BTX BIT(2) 209e66f840cSTristram Ha #define PORT_AUTO_NEG_10BT_FD BIT(1) 210e66f840cSTristram Ha #define PORT_AUTO_NEG_10BT BIT(0) 211e66f840cSTristram Ha 212e66f840cSTristram Ha #define REG_PORT_1_STATUS_0 0x18 213e66f840cSTristram Ha #define REG_PORT_2_STATUS_0 0x28 214e66f840cSTristram Ha #define REG_PORT_3_STATUS_0 0x38 215e66f840cSTristram Ha #define REG_PORT_4_STATUS_0 0x48 216e66f840cSTristram Ha 217e66f840cSTristram Ha /* For KSZ8765. */ 218e66f840cSTristram Ha #define PORT_FIBER_MODE BIT(7) 219e66f840cSTristram Ha 220e66f840cSTristram Ha #define PORT_REMOTE_ASYM_PAUSE BIT(5) 221e66f840cSTristram Ha #define PORT_REMOTE_SYM_PAUSE BIT(4) 222e66f840cSTristram Ha #define PORT_REMOTE_100BTX_FD BIT(3) 223e66f840cSTristram Ha #define PORT_REMOTE_100BTX BIT(2) 224e66f840cSTristram Ha #define PORT_REMOTE_10BT_FD BIT(1) 225e66f840cSTristram Ha #define PORT_REMOTE_10BT BIT(0) 226e66f840cSTristram Ha 227e66f840cSTristram Ha #define REG_PORT_1_STATUS_1 0x19 228e66f840cSTristram Ha #define REG_PORT_2_STATUS_1 0x29 229e66f840cSTristram Ha #define REG_PORT_3_STATUS_1 0x39 230e66f840cSTristram Ha #define REG_PORT_4_STATUS_1 0x49 231e66f840cSTristram Ha 232e66f840cSTristram Ha #define PORT_HP_MDIX BIT(7) 233e66f840cSTristram Ha #define PORT_REVERSED_POLARITY BIT(5) 234e66f840cSTristram Ha #define PORT_TX_FLOW_CTRL BIT(4) 235e66f840cSTristram Ha #define PORT_RX_FLOW_CTRL BIT(3) 236e66f840cSTristram Ha #define PORT_STAT_SPEED_100MBIT BIT(2) 237e66f840cSTristram Ha #define PORT_STAT_FULL_DUPLEX BIT(1) 238e66f840cSTristram Ha 239e66f840cSTristram Ha #define PORT_REMOTE_FAULT BIT(0) 240e66f840cSTristram Ha 241e66f840cSTristram Ha #define REG_PORT_1_LINK_MD_CTRL 0x1A 242e66f840cSTristram Ha #define REG_PORT_2_LINK_MD_CTRL 0x2A 243e66f840cSTristram Ha #define REG_PORT_3_LINK_MD_CTRL 0x3A 244e66f840cSTristram Ha #define REG_PORT_4_LINK_MD_CTRL 0x4A 245e66f840cSTristram Ha 246e66f840cSTristram Ha #define PORT_CABLE_10M_SHORT BIT(7) 247e66f840cSTristram Ha #define PORT_CABLE_DIAG_RESULT_M 0x3 248e66f840cSTristram Ha #define PORT_CABLE_DIAG_RESULT_S 5 249e66f840cSTristram Ha #define PORT_CABLE_STAT_NORMAL 0 250e66f840cSTristram Ha #define PORT_CABLE_STAT_OPEN 1 251e66f840cSTristram Ha #define PORT_CABLE_STAT_SHORT 2 252e66f840cSTristram Ha #define PORT_CABLE_STAT_FAILED 3 253e66f840cSTristram Ha #define PORT_START_CABLE_DIAG BIT(4) 254e66f840cSTristram Ha #define PORT_FORCE_LINK BIT(3) 255e66f840cSTristram Ha #define PORT_POWER_SAVING BIT(2) 256e66f840cSTristram Ha #define PORT_PHY_REMOTE_LOOPBACK BIT(1) 257e66f840cSTristram Ha #define PORT_CABLE_FAULT_COUNTER_H 0x01 258e66f840cSTristram Ha 259e66f840cSTristram Ha #define REG_PORT_1_LINK_MD_RESULT 0x1B 260e66f840cSTristram Ha #define REG_PORT_2_LINK_MD_RESULT 0x2B 261e66f840cSTristram Ha #define REG_PORT_3_LINK_MD_RESULT 0x3B 262e66f840cSTristram Ha #define REG_PORT_4_LINK_MD_RESULT 0x4B 263e66f840cSTristram Ha 264e66f840cSTristram Ha #define PORT_CABLE_FAULT_COUNTER_L 0xFF 265e66f840cSTristram Ha #define PORT_CABLE_FAULT_COUNTER 0x1FF 266e66f840cSTristram Ha 267e66f840cSTristram Ha #define REG_PORT_1_CTRL_9 0x1C 268e66f840cSTristram Ha #define REG_PORT_2_CTRL_9 0x2C 269e66f840cSTristram Ha #define REG_PORT_3_CTRL_9 0x3C 270e66f840cSTristram Ha #define REG_PORT_4_CTRL_9 0x4C 271e66f840cSTristram Ha 272e66f840cSTristram Ha #define PORT_AUTO_NEG_DISABLE BIT(7) 273e66f840cSTristram Ha #define PORT_FORCE_100_MBIT BIT(6) 274e66f840cSTristram Ha #define PORT_FORCE_FULL_DUPLEX BIT(5) 275e66f840cSTristram Ha 276e66f840cSTristram Ha #define REG_PORT_1_CTRL_10 0x1D 277e66f840cSTristram Ha #define REG_PORT_2_CTRL_10 0x2D 278e66f840cSTristram Ha #define REG_PORT_3_CTRL_10 0x3D 279e66f840cSTristram Ha #define REG_PORT_4_CTRL_10 0x4D 280e66f840cSTristram Ha 281e66f840cSTristram Ha #define PORT_LED_OFF BIT(7) 282e66f840cSTristram Ha #define PORT_TX_DISABLE BIT(6) 283e66f840cSTristram Ha #define PORT_AUTO_NEG_RESTART BIT(5) 284e66f840cSTristram Ha #define PORT_POWER_DOWN BIT(3) 285e66f840cSTristram Ha #define PORT_AUTO_MDIX_DISABLE BIT(2) 286e66f840cSTristram Ha #define PORT_FORCE_MDIX BIT(1) 287e66f840cSTristram Ha #define PORT_MAC_LOOPBACK BIT(0) 288e66f840cSTristram Ha 289e66f840cSTristram Ha #define REG_PORT_1_STATUS_2 0x1E 290e66f840cSTristram Ha #define REG_PORT_2_STATUS_2 0x2E 291e66f840cSTristram Ha #define REG_PORT_3_STATUS_2 0x3E 292e66f840cSTristram Ha #define REG_PORT_4_STATUS_2 0x4E 293e66f840cSTristram Ha 294e66f840cSTristram Ha #define PORT_MDIX_STATUS BIT(7) 295e66f840cSTristram Ha #define PORT_AUTO_NEG_COMPLETE BIT(6) 296e66f840cSTristram Ha #define PORT_STAT_LINK_GOOD BIT(5) 297e66f840cSTristram Ha 298e66f840cSTristram Ha #define REG_PORT_1_STATUS_3 0x1F 299e66f840cSTristram Ha #define REG_PORT_2_STATUS_3 0x2F 300e66f840cSTristram Ha #define REG_PORT_3_STATUS_3 0x3F 301e66f840cSTristram Ha #define REG_PORT_4_STATUS_3 0x4F 302e66f840cSTristram Ha 303e66f840cSTristram Ha #define PORT_PHY_LOOPBACK BIT(7) 304e66f840cSTristram Ha #define PORT_PHY_ISOLATE BIT(5) 305e66f840cSTristram Ha #define PORT_PHY_SOFT_RESET BIT(4) 306e66f840cSTristram Ha #define PORT_PHY_FORCE_LINK BIT(3) 307e66f840cSTristram Ha #define PORT_PHY_MODE_M 0x7 308e66f840cSTristram Ha #define PHY_MODE_IN_AUTO_NEG 1 309e66f840cSTristram Ha #define PHY_MODE_10BT_HALF 2 310e66f840cSTristram Ha #define PHY_MODE_100BT_HALF 3 311e66f840cSTristram Ha #define PHY_MODE_10BT_FULL 5 312e66f840cSTristram Ha #define PHY_MODE_100BT_FULL 6 313e66f840cSTristram Ha #define PHY_MODE_ISOLDATE 7 314e66f840cSTristram Ha 315e66f840cSTristram Ha #define REG_PORT_CTRL_0 0x00 316e66f840cSTristram Ha #define REG_PORT_CTRL_1 0x01 317e66f840cSTristram Ha #define REG_PORT_CTRL_2 0x02 318e66f840cSTristram Ha #define REG_PORT_CTRL_VID 0x03 319e66f840cSTristram Ha 320e66f840cSTristram Ha #define REG_PORT_CTRL_5 0x05 321e66f840cSTristram Ha 322e66f840cSTristram Ha #define REG_PORT_CTRL_7 0x07 323e66f840cSTristram Ha #define REG_PORT_STATUS_0 0x08 324e66f840cSTristram Ha #define REG_PORT_STATUS_1 0x09 325e66f840cSTristram Ha #define REG_PORT_LINK_MD_CTRL 0x0A 326e66f840cSTristram Ha #define REG_PORT_LINK_MD_RESULT 0x0B 327e66f840cSTristram Ha #define REG_PORT_CTRL_9 0x0C 328e66f840cSTristram Ha #define REG_PORT_CTRL_10 0x0D 329e66f840cSTristram Ha #define REG_PORT_STATUS_2 0x0E 330e66f840cSTristram Ha #define REG_PORT_STATUS_3 0x0F 331e66f840cSTristram Ha 332e66f840cSTristram Ha #define REG_PORT_CTRL_12 0xA0 333e66f840cSTristram Ha #define REG_PORT_CTRL_13 0xA1 334e66f840cSTristram Ha #define REG_PORT_RATE_CTRL_3 0xA2 335e66f840cSTristram Ha #define REG_PORT_RATE_CTRL_2 0xA3 336e66f840cSTristram Ha #define REG_PORT_RATE_CTRL_1 0xA4 337e66f840cSTristram Ha #define REG_PORT_RATE_CTRL_0 0xA5 338e66f840cSTristram Ha #define REG_PORT_RATE_LIMIT 0xA6 339e66f840cSTristram Ha #define REG_PORT_IN_RATE_0 0xA7 340e66f840cSTristram Ha #define REG_PORT_IN_RATE_1 0xA8 341e66f840cSTristram Ha #define REG_PORT_IN_RATE_2 0xA9 342e66f840cSTristram Ha #define REG_PORT_IN_RATE_3 0xAA 343e66f840cSTristram Ha #define REG_PORT_OUT_RATE_0 0xAB 344e66f840cSTristram Ha #define REG_PORT_OUT_RATE_1 0xAC 345e66f840cSTristram Ha #define REG_PORT_OUT_RATE_2 0xAD 346e66f840cSTristram Ha #define REG_PORT_OUT_RATE_3 0xAE 347e66f840cSTristram Ha 348e66f840cSTristram Ha #define PORT_CTRL_ADDR(port, addr) \ 349e66f840cSTristram Ha ((addr) + REG_PORT_1_CTRL_0 + (port) * \ 350e66f840cSTristram Ha (REG_PORT_2_CTRL_0 - REG_PORT_1_CTRL_0)) 351e66f840cSTristram Ha 352e66f840cSTristram Ha #define REG_SW_MAC_ADDR_0 0x68 353e66f840cSTristram Ha #define REG_SW_MAC_ADDR_1 0x69 354e66f840cSTristram Ha #define REG_SW_MAC_ADDR_2 0x6A 355e66f840cSTristram Ha #define REG_SW_MAC_ADDR_3 0x6B 356e66f840cSTristram Ha #define REG_SW_MAC_ADDR_4 0x6C 357e66f840cSTristram Ha #define REG_SW_MAC_ADDR_5 0x6D 358e66f840cSTristram Ha 359e66f840cSTristram Ha #define REG_IND_CTRL_0 0x6E 360e66f840cSTristram Ha 361e66f840cSTristram Ha #define TABLE_EXT_SELECT_S 5 362e66f840cSTristram Ha #define TABLE_EEE_V 1 363e66f840cSTristram Ha #define TABLE_ACL_V 2 364e66f840cSTristram Ha #define TABLE_PME_V 4 365e66f840cSTristram Ha #define TABLE_LINK_MD_V 5 366e66f840cSTristram Ha #define TABLE_EEE (TABLE_EEE_V << TABLE_EXT_SELECT_S) 367e66f840cSTristram Ha #define TABLE_ACL (TABLE_ACL_V << TABLE_EXT_SELECT_S) 368e66f840cSTristram Ha #define TABLE_PME (TABLE_PME_V << TABLE_EXT_SELECT_S) 369e66f840cSTristram Ha #define TABLE_LINK_MD (TABLE_LINK_MD << TABLE_EXT_SELECT_S) 370e66f840cSTristram Ha #define TABLE_READ BIT(4) 371e66f840cSTristram Ha #define TABLE_SELECT_S 2 372e66f840cSTristram Ha #define TABLE_STATIC_MAC_V 0 373e66f840cSTristram Ha #define TABLE_VLAN_V 1 374e66f840cSTristram Ha #define TABLE_DYNAMIC_MAC_V 2 375e66f840cSTristram Ha #define TABLE_MIB_V 3 376e66f840cSTristram Ha #define TABLE_STATIC_MAC (TABLE_STATIC_MAC_V << TABLE_SELECT_S) 377e66f840cSTristram Ha #define TABLE_VLAN (TABLE_VLAN_V << TABLE_SELECT_S) 378e66f840cSTristram Ha #define TABLE_DYNAMIC_MAC (TABLE_DYNAMIC_MAC_V << TABLE_SELECT_S) 379e66f840cSTristram Ha #define TABLE_MIB (TABLE_MIB_V << TABLE_SELECT_S) 380e66f840cSTristram Ha 381e66f840cSTristram Ha #define REG_IND_CTRL_1 0x6F 382e66f840cSTristram Ha 383e66f840cSTristram Ha #define TABLE_ENTRY_MASK 0x03FF 384e66f840cSTristram Ha #define TABLE_EXT_ENTRY_MASK 0x0FFF 385e66f840cSTristram Ha 386e66f840cSTristram Ha #define REG_IND_DATA_8 0x70 387e66f840cSTristram Ha #define REG_IND_DATA_7 0x71 388e66f840cSTristram Ha #define REG_IND_DATA_6 0x72 389e66f840cSTristram Ha #define REG_IND_DATA_5 0x73 390e66f840cSTristram Ha #define REG_IND_DATA_4 0x74 391e66f840cSTristram Ha #define REG_IND_DATA_3 0x75 392e66f840cSTristram Ha #define REG_IND_DATA_2 0x76 393e66f840cSTristram Ha #define REG_IND_DATA_1 0x77 394e66f840cSTristram Ha #define REG_IND_DATA_0 0x78 395e66f840cSTristram Ha 396e66f840cSTristram Ha #define REG_IND_DATA_PME_EEE_ACL 0xA0 397e66f840cSTristram Ha 398e66f840cSTristram Ha #define REG_IND_DATA_CHECK REG_IND_DATA_6 399e66f840cSTristram Ha #define REG_IND_MIB_CHECK REG_IND_DATA_4 400e66f840cSTristram Ha #define REG_IND_DATA_HI REG_IND_DATA_7 401e66f840cSTristram Ha #define REG_IND_DATA_LO REG_IND_DATA_3 402e66f840cSTristram Ha 403e66f840cSTristram Ha #define REG_INT_STATUS 0x7C 404e66f840cSTristram Ha #define REG_INT_ENABLE 0x7D 405e66f840cSTristram Ha 406e66f840cSTristram Ha #define INT_PME BIT(4) 407e66f840cSTristram Ha 408e66f840cSTristram Ha #define REG_ACL_INT_STATUS 0x7E 409e66f840cSTristram Ha #define REG_ACL_INT_ENABLE 0x7F 410e66f840cSTristram Ha 411e66f840cSTristram Ha #define INT_PORT_5 BIT(4) 412e66f840cSTristram Ha #define INT_PORT_4 BIT(3) 413e66f840cSTristram Ha #define INT_PORT_3 BIT(2) 414e66f840cSTristram Ha #define INT_PORT_2 BIT(1) 415e66f840cSTristram Ha #define INT_PORT_1 BIT(0) 416e66f840cSTristram Ha 417e66f840cSTristram Ha #define INT_PORT_ALL \ 418e66f840cSTristram Ha (INT_PORT_5 | INT_PORT_4 | INT_PORT_3 | INT_PORT_2 | INT_PORT_1) 419e66f840cSTristram Ha 420e66f840cSTristram Ha #define REG_SW_CTRL_12 0x80 421e66f840cSTristram Ha #define REG_SW_CTRL_13 0x81 422e66f840cSTristram Ha 423e66f840cSTristram Ha #define SWITCH_802_1P_MASK 3 424e66f840cSTristram Ha #define SWITCH_802_1P_BASE 3 425e66f840cSTristram Ha #define SWITCH_802_1P_SHIFT 2 426e66f840cSTristram Ha 427e66f840cSTristram Ha #define SW_802_1P_MAP_M KS_PRIO_M 428e66f840cSTristram Ha #define SW_802_1P_MAP_S KS_PRIO_S 429e66f840cSTristram Ha 430e66f840cSTristram Ha #define REG_SWITCH_CTRL_14 0x82 431e66f840cSTristram Ha 432e66f840cSTristram Ha #define SW_PRIO_MAPPING_M KS_PRIO_M 433e66f840cSTristram Ha #define SW_PRIO_MAPPING_S 6 434e66f840cSTristram Ha #define SW_PRIO_MAP_3_HI 0 435e66f840cSTristram Ha #define SW_PRIO_MAP_2_HI 2 436e66f840cSTristram Ha #define SW_PRIO_MAP_0_LO 3 437e66f840cSTristram Ha 438e66f840cSTristram Ha #define REG_SW_CTRL_15 0x83 439e66f840cSTristram Ha #define REG_SW_CTRL_16 0x84 440e66f840cSTristram Ha #define REG_SW_CTRL_17 0x85 441e66f840cSTristram Ha #define REG_SW_CTRL_18 0x86 442e66f840cSTristram Ha 443e66f840cSTristram Ha #define SW_SELF_ADDR_FILTER_ENABLE BIT(6) 444e66f840cSTristram Ha 445e66f840cSTristram Ha #define REG_SW_UNK_UCAST_CTRL 0x83 446e66f840cSTristram Ha #define REG_SW_UNK_MCAST_CTRL 0x84 447e66f840cSTristram Ha #define REG_SW_UNK_VID_CTRL 0x85 448e66f840cSTristram Ha #define REG_SW_UNK_IP_MCAST_CTRL 0x86 449e66f840cSTristram Ha 450e66f840cSTristram Ha #define SW_UNK_FWD_ENABLE BIT(5) 451e66f840cSTristram Ha #define SW_UNK_FWD_MAP KS_PORT_M 452e66f840cSTristram Ha 453e66f840cSTristram Ha #define REG_SW_CTRL_19 0x87 454e66f840cSTristram Ha 455e66f840cSTristram Ha #define SW_IN_RATE_LIMIT_PERIOD_M 0x3 456e66f840cSTristram Ha #define SW_IN_RATE_LIMIT_PERIOD_S 4 457e66f840cSTristram Ha #define SW_IN_RATE_LIMIT_16_MS 0 458e66f840cSTristram Ha #define SW_IN_RATE_LIMIT_64_MS 1 459e66f840cSTristram Ha #define SW_IN_RATE_LIMIT_256_MS 2 460e66f840cSTristram Ha #define SW_OUT_RATE_LIMIT_QUEUE_BASED BIT(3) 461e66f840cSTristram Ha #define SW_INS_TAG_ENABLE BIT(2) 462e66f840cSTristram Ha 463e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_0 0x90 464e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_1 0x91 465e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_2 0x92 466e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_3 0x93 467e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_4 0x94 468e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_5 0x95 469e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_6 0x96 470e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_7 0x97 471e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_8 0x98 472e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_9 0x99 473e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_10 0x9A 474e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_11 0x9B 475e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_12 0x9C 476e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_13 0x9D 477e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_14 0x9E 478e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_15 0x9F 479e66f840cSTristram Ha 480e66f840cSTristram Ha #define TOS_PRIO_M KS_PRIO_M 481e66f840cSTristram Ha #define TOS_PRIO_S KS_PRIO_S 482e66f840cSTristram Ha 483e66f840cSTristram Ha #define REG_SW_CTRL_20 0xA3 484e66f840cSTristram Ha 485e66f840cSTristram Ha #define SW_GMII_DRIVE_STRENGTH_S 4 486e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_M 0x7 487e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_2MA 0 488e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_4MA 1 489e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_8MA 2 490e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_12MA 3 491e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_16MA 4 492e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_20MA 5 493e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_24MA 6 494e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_28MA 7 495e66f840cSTristram Ha #define SW_MII_DRIVE_STRENGTH_S 0 496e66f840cSTristram Ha 497e66f840cSTristram Ha #define REG_SW_CTRL_21 0xA4 498e66f840cSTristram Ha 499e66f840cSTristram Ha #define SW_IPV6_MLD_OPTION BIT(3) 500e66f840cSTristram Ha #define SW_IPV6_MLD_SNOOP BIT(2) 501e66f840cSTristram Ha 502e66f840cSTristram Ha #define REG_PORT_1_CTRL_12 0xB0 503e66f840cSTristram Ha #define REG_PORT_2_CTRL_12 0xC0 504e66f840cSTristram Ha #define REG_PORT_3_CTRL_12 0xD0 505e66f840cSTristram Ha #define REG_PORT_4_CTRL_12 0xE0 506e66f840cSTristram Ha #define REG_PORT_5_CTRL_12 0xF0 507e66f840cSTristram Ha 508e66f840cSTristram Ha #define PORT_PASS_ALL BIT(6) 509e66f840cSTristram Ha #define PORT_INS_TAG_FOR_PORT_5_S 3 510e66f840cSTristram Ha #define PORT_INS_TAG_FOR_PORT_5 BIT(3) 511e66f840cSTristram Ha #define PORT_INS_TAG_FOR_PORT_4 BIT(2) 512e66f840cSTristram Ha #define PORT_INS_TAG_FOR_PORT_3 BIT(1) 513e66f840cSTristram Ha #define PORT_INS_TAG_FOR_PORT_2 BIT(0) 514e66f840cSTristram Ha 515e66f840cSTristram Ha #define REG_PORT_1_CTRL_13 0xB1 516e66f840cSTristram Ha #define REG_PORT_2_CTRL_13 0xC1 517e66f840cSTristram Ha #define REG_PORT_3_CTRL_13 0xD1 518e66f840cSTristram Ha #define REG_PORT_4_CTRL_13 0xE1 519e66f840cSTristram Ha #define REG_PORT_5_CTRL_13 0xF1 520e66f840cSTristram Ha 521e66f840cSTristram Ha #define PORT_QUEUE_SPLIT_H BIT(1) 522e66f840cSTristram Ha #define PORT_QUEUE_SPLIT_1 0 523e66f840cSTristram Ha #define PORT_QUEUE_SPLIT_2 1 524e66f840cSTristram Ha #define PORT_QUEUE_SPLIT_4 2 525e66f840cSTristram Ha #define PORT_DROP_TAG BIT(0) 526e66f840cSTristram Ha 527e66f840cSTristram Ha #define REG_PORT_1_CTRL_14 0xB2 528e66f840cSTristram Ha #define REG_PORT_2_CTRL_14 0xC2 529e66f840cSTristram Ha #define REG_PORT_3_CTRL_14 0xD2 530e66f840cSTristram Ha #define REG_PORT_4_CTRL_14 0xE2 531e66f840cSTristram Ha #define REG_PORT_5_CTRL_14 0xF2 532e66f840cSTristram Ha #define REG_PORT_1_CTRL_15 0xB3 533e66f840cSTristram Ha #define REG_PORT_2_CTRL_15 0xC3 534e66f840cSTristram Ha #define REG_PORT_3_CTRL_15 0xD3 535e66f840cSTristram Ha #define REG_PORT_4_CTRL_15 0xE3 536e66f840cSTristram Ha #define REG_PORT_5_CTRL_15 0xF3 537e66f840cSTristram Ha #define REG_PORT_1_CTRL_16 0xB4 538e66f840cSTristram Ha #define REG_PORT_2_CTRL_16 0xC4 539e66f840cSTristram Ha #define REG_PORT_3_CTRL_16 0xD4 540e66f840cSTristram Ha #define REG_PORT_4_CTRL_16 0xE4 541e66f840cSTristram Ha #define REG_PORT_5_CTRL_16 0xF4 542e66f840cSTristram Ha #define REG_PORT_1_CTRL_17 0xB5 543e66f840cSTristram Ha #define REG_PORT_2_CTRL_17 0xC5 544e66f840cSTristram Ha #define REG_PORT_3_CTRL_17 0xD5 545e66f840cSTristram Ha #define REG_PORT_4_CTRL_17 0xE5 546e66f840cSTristram Ha #define REG_PORT_5_CTRL_17 0xF5 547e66f840cSTristram Ha 548e66f840cSTristram Ha #define REG_PORT_1_RATE_CTRL_3 0xB2 549e66f840cSTristram Ha #define REG_PORT_1_RATE_CTRL_2 0xB3 550e66f840cSTristram Ha #define REG_PORT_1_RATE_CTRL_1 0xB4 551e66f840cSTristram Ha #define REG_PORT_1_RATE_CTRL_0 0xB5 552e66f840cSTristram Ha #define REG_PORT_2_RATE_CTRL_3 0xC2 553e66f840cSTristram Ha #define REG_PORT_2_RATE_CTRL_2 0xC3 554e66f840cSTristram Ha #define REG_PORT_2_RATE_CTRL_1 0xC4 555e66f840cSTristram Ha #define REG_PORT_2_RATE_CTRL_0 0xC5 556e66f840cSTristram Ha #define REG_PORT_3_RATE_CTRL_3 0xD2 557e66f840cSTristram Ha #define REG_PORT_3_RATE_CTRL_2 0xD3 558e66f840cSTristram Ha #define REG_PORT_3_RATE_CTRL_1 0xD4 559e66f840cSTristram Ha #define REG_PORT_3_RATE_CTRL_0 0xD5 560e66f840cSTristram Ha #define REG_PORT_4_RATE_CTRL_3 0xE2 561e66f840cSTristram Ha #define REG_PORT_4_RATE_CTRL_2 0xE3 562e66f840cSTristram Ha #define REG_PORT_4_RATE_CTRL_1 0xE4 563e66f840cSTristram Ha #define REG_PORT_4_RATE_CTRL_0 0xE5 564e66f840cSTristram Ha #define REG_PORT_5_RATE_CTRL_3 0xF2 565e66f840cSTristram Ha #define REG_PORT_5_RATE_CTRL_2 0xF3 566e66f840cSTristram Ha #define REG_PORT_5_RATE_CTRL_1 0xF4 567e66f840cSTristram Ha #define REG_PORT_5_RATE_CTRL_0 0xF5 568e66f840cSTristram Ha 569e66f840cSTristram Ha #define RATE_CTRL_ENABLE BIT(7) 570e66f840cSTristram Ha #define RATE_RATIO_M (BIT(7) - 1) 571e66f840cSTristram Ha 572e66f840cSTristram Ha #define PORT_OUT_RATE_ENABLE BIT(7) 573e66f840cSTristram Ha 574e66f840cSTristram Ha #define REG_PORT_1_RATE_LIMIT 0xB6 575e66f840cSTristram Ha #define REG_PORT_2_RATE_LIMIT 0xC6 576e66f840cSTristram Ha #define REG_PORT_3_RATE_LIMIT 0xD6 577e66f840cSTristram Ha #define REG_PORT_4_RATE_LIMIT 0xE6 578e66f840cSTristram Ha #define REG_PORT_5_RATE_LIMIT 0xF6 579e66f840cSTristram Ha 580e66f840cSTristram Ha #define PORT_IN_PORT_BASED_S 6 581e66f840cSTristram Ha #define PORT_RATE_PACKET_BASED_S 5 582e66f840cSTristram Ha #define PORT_IN_FLOW_CTRL_S 4 583e66f840cSTristram Ha #define PORT_IN_LIMIT_MODE_M 0x3 584e66f840cSTristram Ha #define PORT_IN_LIMIT_MODE_S 2 585e66f840cSTristram Ha #define PORT_COUNT_IFG_S 1 586e66f840cSTristram Ha #define PORT_COUNT_PREAMBLE_S 0 587e66f840cSTristram Ha #define PORT_IN_PORT_BASED BIT(PORT_IN_PORT_BASED_S) 588e66f840cSTristram Ha #define PORT_RATE_PACKET_BASED BIT(PORT_RATE_PACKET_BASED_S) 589e66f840cSTristram Ha #define PORT_IN_FLOW_CTRL BIT(PORT_IN_FLOW_CTRL_S) 590e66f840cSTristram Ha #define PORT_IN_ALL 0 591e66f840cSTristram Ha #define PORT_IN_UNICAST 1 592e66f840cSTristram Ha #define PORT_IN_MULTICAST 2 593e66f840cSTristram Ha #define PORT_IN_BROADCAST 3 594e66f840cSTristram Ha #define PORT_COUNT_IFG BIT(PORT_COUNT_IFG_S) 595e66f840cSTristram Ha #define PORT_COUNT_PREAMBLE BIT(PORT_COUNT_PREAMBLE_S) 596e66f840cSTristram Ha 597e66f840cSTristram Ha #define REG_PORT_1_IN_RATE_0 0xB7 598e66f840cSTristram Ha #define REG_PORT_2_IN_RATE_0 0xC7 599e66f840cSTristram Ha #define REG_PORT_3_IN_RATE_0 0xD7 600e66f840cSTristram Ha #define REG_PORT_4_IN_RATE_0 0xE7 601e66f840cSTristram Ha #define REG_PORT_5_IN_RATE_0 0xF7 602e66f840cSTristram Ha #define REG_PORT_1_IN_RATE_1 0xB8 603e66f840cSTristram Ha #define REG_PORT_2_IN_RATE_1 0xC8 604e66f840cSTristram Ha #define REG_PORT_3_IN_RATE_1 0xD8 605e66f840cSTristram Ha #define REG_PORT_4_IN_RATE_1 0xE8 606e66f840cSTristram Ha #define REG_PORT_5_IN_RATE_1 0xF8 607e66f840cSTristram Ha #define REG_PORT_1_IN_RATE_2 0xB9 608e66f840cSTristram Ha #define REG_PORT_2_IN_RATE_2 0xC9 609e66f840cSTristram Ha #define REG_PORT_3_IN_RATE_2 0xD9 610e66f840cSTristram Ha #define REG_PORT_4_IN_RATE_2 0xE9 611e66f840cSTristram Ha #define REG_PORT_5_IN_RATE_2 0xF9 612e66f840cSTristram Ha #define REG_PORT_1_IN_RATE_3 0xBA 613e66f840cSTristram Ha #define REG_PORT_2_IN_RATE_3 0xCA 614e66f840cSTristram Ha #define REG_PORT_3_IN_RATE_3 0xDA 615e66f840cSTristram Ha #define REG_PORT_4_IN_RATE_3 0xEA 616e66f840cSTristram Ha #define REG_PORT_5_IN_RATE_3 0xFA 617e66f840cSTristram Ha 618e66f840cSTristram Ha #define PORT_IN_RATE_ENABLE BIT(7) 619e66f840cSTristram Ha #define PORT_RATE_LIMIT_M (BIT(7) - 1) 620e66f840cSTristram Ha 621e66f840cSTristram Ha #define REG_PORT_1_OUT_RATE_0 0xBB 622e66f840cSTristram Ha #define REG_PORT_2_OUT_RATE_0 0xCB 623e66f840cSTristram Ha #define REG_PORT_3_OUT_RATE_0 0xDB 624e66f840cSTristram Ha #define REG_PORT_4_OUT_RATE_0 0xEB 625e66f840cSTristram Ha #define REG_PORT_5_OUT_RATE_0 0xFB 626e66f840cSTristram Ha #define REG_PORT_1_OUT_RATE_1 0xBC 627e66f840cSTristram Ha #define REG_PORT_2_OUT_RATE_1 0xCC 628e66f840cSTristram Ha #define REG_PORT_3_OUT_RATE_1 0xDC 629e66f840cSTristram Ha #define REG_PORT_4_OUT_RATE_1 0xEC 630e66f840cSTristram Ha #define REG_PORT_5_OUT_RATE_1 0xFC 631e66f840cSTristram Ha #define REG_PORT_1_OUT_RATE_2 0xBD 632e66f840cSTristram Ha #define REG_PORT_2_OUT_RATE_2 0xCD 633e66f840cSTristram Ha #define REG_PORT_3_OUT_RATE_2 0xDD 634e66f840cSTristram Ha #define REG_PORT_4_OUT_RATE_2 0xED 635e66f840cSTristram Ha #define REG_PORT_5_OUT_RATE_2 0xFD 636e66f840cSTristram Ha #define REG_PORT_1_OUT_RATE_3 0xBE 637e66f840cSTristram Ha #define REG_PORT_2_OUT_RATE_3 0xCE 638e66f840cSTristram Ha #define REG_PORT_3_OUT_RATE_3 0xDE 639e66f840cSTristram Ha #define REG_PORT_4_OUT_RATE_3 0xEE 640e66f840cSTristram Ha #define REG_PORT_5_OUT_RATE_3 0xFE 641e66f840cSTristram Ha 642e66f840cSTristram Ha /* PME */ 643e66f840cSTristram Ha 644e66f840cSTristram Ha #define SW_PME_OUTPUT_ENABLE BIT(1) 645e66f840cSTristram Ha #define SW_PME_ACTIVE_HIGH BIT(0) 646e66f840cSTristram Ha 647e66f840cSTristram Ha #define PORT_MAGIC_PACKET_DETECT BIT(2) 648e66f840cSTristram Ha #define PORT_LINK_UP_DETECT BIT(1) 649e66f840cSTristram Ha #define PORT_ENERGY_DETECT BIT(0) 650e66f840cSTristram Ha 651e66f840cSTristram Ha /* ACL */ 652e66f840cSTristram Ha 653e66f840cSTristram Ha #define ACL_FIRST_RULE_M 0xF 654e66f840cSTristram Ha 655e66f840cSTristram Ha #define ACL_MODE_M 0x3 656e66f840cSTristram Ha #define ACL_MODE_S 4 657e66f840cSTristram Ha #define ACL_MODE_DISABLE 0 658e66f840cSTristram Ha #define ACL_MODE_LAYER_2 1 659e66f840cSTristram Ha #define ACL_MODE_LAYER_3 2 660e66f840cSTristram Ha #define ACL_MODE_LAYER_4 3 661e66f840cSTristram Ha #define ACL_ENABLE_M 0x3 662e66f840cSTristram Ha #define ACL_ENABLE_S 2 663e66f840cSTristram Ha #define ACL_ENABLE_2_COUNT 0 664e66f840cSTristram Ha #define ACL_ENABLE_2_TYPE 1 665e66f840cSTristram Ha #define ACL_ENABLE_2_MAC 2 666e66f840cSTristram Ha #define ACL_ENABLE_2_BOTH 3 667e66f840cSTristram Ha #define ACL_ENABLE_3_IP 1 668e66f840cSTristram Ha #define ACL_ENABLE_3_SRC_DST_COMP 2 669e66f840cSTristram Ha #define ACL_ENABLE_4_PROTOCOL 0 670e66f840cSTristram Ha #define ACL_ENABLE_4_TCP_PORT_COMP 1 671e66f840cSTristram Ha #define ACL_ENABLE_4_UDP_PORT_COMP 2 672e66f840cSTristram Ha #define ACL_ENABLE_4_TCP_SEQN_COMP 3 673e66f840cSTristram Ha #define ACL_SRC BIT(1) 674e66f840cSTristram Ha #define ACL_EQUAL BIT(0) 675e66f840cSTristram Ha 676e66f840cSTristram Ha #define ACL_MAX_PORT 0xFFFF 677e66f840cSTristram Ha 678e66f840cSTristram Ha #define ACL_MIN_PORT 0xFFFF 679e66f840cSTristram Ha #define ACL_IP_ADDR 0xFFFFFFFF 680e66f840cSTristram Ha #define ACL_TCP_SEQNUM 0xFFFFFFFF 681e66f840cSTristram Ha 682e66f840cSTristram Ha #define ACL_RESERVED 0xF8 683e66f840cSTristram Ha #define ACL_PORT_MODE_M 0x3 684e66f840cSTristram Ha #define ACL_PORT_MODE_S 1 685e66f840cSTristram Ha #define ACL_PORT_MODE_DISABLE 0 686e66f840cSTristram Ha #define ACL_PORT_MODE_EITHER 1 687e66f840cSTristram Ha #define ACL_PORT_MODE_IN_RANGE 2 688e66f840cSTristram Ha #define ACL_PORT_MODE_OUT_OF_RANGE 3 689e66f840cSTristram Ha 690e66f840cSTristram Ha #define ACL_TCP_FLAG_ENABLE BIT(0) 691e66f840cSTristram Ha 692e66f840cSTristram Ha #define ACL_TCP_FLAG_M 0xFF 693e66f840cSTristram Ha 694e66f840cSTristram Ha #define ACL_TCP_FLAG 0xFF 695e66f840cSTristram Ha #define ACL_ETH_TYPE 0xFFFF 696e66f840cSTristram Ha #define ACL_IP_M 0xFFFFFFFF 697e66f840cSTristram Ha 698e66f840cSTristram Ha #define ACL_PRIO_MODE_M 0x3 699e66f840cSTristram Ha #define ACL_PRIO_MODE_S 6 700e66f840cSTristram Ha #define ACL_PRIO_MODE_DISABLE 0 701e66f840cSTristram Ha #define ACL_PRIO_MODE_HIGHER 1 702e66f840cSTristram Ha #define ACL_PRIO_MODE_LOWER 2 703e66f840cSTristram Ha #define ACL_PRIO_MODE_REPLACE 3 704e66f840cSTristram Ha #define ACL_PRIO_M 0x7 705e66f840cSTristram Ha #define ACL_PRIO_S 3 706e66f840cSTristram Ha #define ACL_VLAN_PRIO_REPLACE BIT(2) 707e66f840cSTristram Ha #define ACL_VLAN_PRIO_M 0x7 708e66f840cSTristram Ha #define ACL_VLAN_PRIO_HI_M 0x3 709e66f840cSTristram Ha 710e66f840cSTristram Ha #define ACL_VLAN_PRIO_LO_M 0x8 711e66f840cSTristram Ha #define ACL_VLAN_PRIO_S 7 712e66f840cSTristram Ha #define ACL_MAP_MODE_M 0x3 713e66f840cSTristram Ha #define ACL_MAP_MODE_S 5 714e66f840cSTristram Ha #define ACL_MAP_MODE_DISABLE 0 715e66f840cSTristram Ha #define ACL_MAP_MODE_OR 1 716e66f840cSTristram Ha #define ACL_MAP_MODE_AND 2 717e66f840cSTristram Ha #define ACL_MAP_MODE_REPLACE 3 718e66f840cSTristram Ha #define ACL_MAP_PORT_M 0x1F 719e66f840cSTristram Ha 720e66f840cSTristram Ha #define ACL_CNT_M (BIT(11) - 1) 721e66f840cSTristram Ha #define ACL_CNT_S 5 722e66f840cSTristram Ha #define ACL_MSEC_UNIT BIT(4) 723e66f840cSTristram Ha #define ACL_INTR_MODE BIT(3) 724e66f840cSTristram Ha 725e66f840cSTristram Ha #define REG_PORT_ACL_BYTE_EN_MSB 0x10 726e66f840cSTristram Ha 727e66f840cSTristram Ha #define ACL_BYTE_EN_MSB_M 0x3F 728e66f840cSTristram Ha 729e66f840cSTristram Ha #define REG_PORT_ACL_BYTE_EN_LSB 0x11 730e66f840cSTristram Ha 731e66f840cSTristram Ha #define ACL_ACTION_START 0xA 732e66f840cSTristram Ha #define ACL_ACTION_LEN 2 733e66f840cSTristram Ha #define ACL_INTR_CNT_START 0xB 734e66f840cSTristram Ha #define ACL_RULESET_START 0xC 735e66f840cSTristram Ha #define ACL_RULESET_LEN 2 736e66f840cSTristram Ha #define ACL_TABLE_LEN 14 737e66f840cSTristram Ha 738e66f840cSTristram Ha #define ACL_ACTION_ENABLE 0x000C 739e66f840cSTristram Ha #define ACL_MATCH_ENABLE 0x1FF0 740e66f840cSTristram Ha #define ACL_RULESET_ENABLE 0x2003 741e66f840cSTristram Ha #define ACL_BYTE_ENABLE ((ACL_BYTE_EN_MSB_M << 8) | 0xFF) 742e66f840cSTristram Ha #define ACL_MODE_ENABLE (0x10 << 8) 743e66f840cSTristram Ha 744e66f840cSTristram Ha #define REG_PORT_ACL_CTRL_0 0x12 745e66f840cSTristram Ha 746e66f840cSTristram Ha #define PORT_ACL_WRITE_DONE BIT(6) 747e66f840cSTristram Ha #define PORT_ACL_READ_DONE BIT(5) 748e66f840cSTristram Ha #define PORT_ACL_WRITE BIT(4) 749e66f840cSTristram Ha #define PORT_ACL_INDEX_M 0xF 750e66f840cSTristram Ha 751e66f840cSTristram Ha #define REG_PORT_ACL_CTRL_1 0x13 752e66f840cSTristram Ha 753e66f840cSTristram Ha #define PORT_ACL_FORCE_DLR_MISS BIT(0) 754e66f840cSTristram Ha 755e66f840cSTristram Ha #ifndef PHY_REG_CTRL 756e66f840cSTristram Ha #define PHY_REG_CTRL 0 757e66f840cSTristram Ha 758e66f840cSTristram Ha #define PHY_RESET BIT(15) 759e66f840cSTristram Ha #define PHY_LOOPBACK BIT(14) 760e66f840cSTristram Ha #define PHY_SPEED_100MBIT BIT(13) 761e66f840cSTristram Ha #define PHY_AUTO_NEG_ENABLE BIT(12) 762e66f840cSTristram Ha #define PHY_POWER_DOWN BIT(11) 763e66f840cSTristram Ha #define PHY_MII_DISABLE BIT(10) 764e66f840cSTristram Ha #define PHY_AUTO_NEG_RESTART BIT(9) 765e66f840cSTristram Ha #define PHY_FULL_DUPLEX BIT(8) 766e66f840cSTristram Ha #define PHY_COLLISION_TEST_NOT BIT(7) 767e66f840cSTristram Ha #define PHY_HP_MDIX BIT(5) 768e66f840cSTristram Ha #define PHY_FORCE_MDIX BIT(4) 769e66f840cSTristram Ha #define PHY_AUTO_MDIX_DISABLE BIT(3) 770e66f840cSTristram Ha #define PHY_REMOTE_FAULT_DISABLE BIT(2) 771e66f840cSTristram Ha #define PHY_TRANSMIT_DISABLE BIT(1) 772e66f840cSTristram Ha #define PHY_LED_DISABLE BIT(0) 773e66f840cSTristram Ha 774e66f840cSTristram Ha #define PHY_REG_STATUS 1 775e66f840cSTristram Ha 776e66f840cSTristram Ha #define PHY_100BT4_CAPABLE BIT(15) 777e66f840cSTristram Ha #define PHY_100BTX_FD_CAPABLE BIT(14) 778e66f840cSTristram Ha #define PHY_100BTX_CAPABLE BIT(13) 779e66f840cSTristram Ha #define PHY_10BT_FD_CAPABLE BIT(12) 780e66f840cSTristram Ha #define PHY_10BT_CAPABLE BIT(11) 781e66f840cSTristram Ha #define PHY_MII_SUPPRESS_CAPABLE_NOT BIT(6) 782e66f840cSTristram Ha #define PHY_AUTO_NEG_ACKNOWLEDGE BIT(5) 783e66f840cSTristram Ha #define PHY_REMOTE_FAULT BIT(4) 784e66f840cSTristram Ha #define PHY_AUTO_NEG_CAPABLE BIT(3) 785e66f840cSTristram Ha #define PHY_LINK_STATUS BIT(2) 786e66f840cSTristram Ha #define PHY_JABBER_DETECT_NOT BIT(1) 787e66f840cSTristram Ha #define PHY_EXTENDED_CAPABILITY BIT(0) 788e66f840cSTristram Ha 789e66f840cSTristram Ha #define PHY_REG_ID_1 2 790e66f840cSTristram Ha #define PHY_REG_ID_2 3 791e66f840cSTristram Ha 792e66f840cSTristram Ha #define PHY_REG_AUTO_NEGOTIATION 4 793e66f840cSTristram Ha 794e66f840cSTristram Ha #define PHY_AUTO_NEG_NEXT_PAGE_NOT BIT(15) 795e66f840cSTristram Ha #define PHY_AUTO_NEG_REMOTE_FAULT_NOT BIT(13) 796e66f840cSTristram Ha #define PHY_AUTO_NEG_SYM_PAUSE BIT(10) 797e66f840cSTristram Ha #define PHY_AUTO_NEG_100BT4 BIT(9) 798e66f840cSTristram Ha #define PHY_AUTO_NEG_100BTX_FD BIT(8) 799e66f840cSTristram Ha #define PHY_AUTO_NEG_100BTX BIT(7) 800e66f840cSTristram Ha #define PHY_AUTO_NEG_10BT_FD BIT(6) 801e66f840cSTristram Ha #define PHY_AUTO_NEG_10BT BIT(5) 802e66f840cSTristram Ha #define PHY_AUTO_NEG_SELECTOR 0x001F 803e66f840cSTristram Ha #define PHY_AUTO_NEG_802_3 0x0001 804e66f840cSTristram Ha 805e66f840cSTristram Ha #define PHY_REG_REMOTE_CAPABILITY 5 806e66f840cSTristram Ha 807e66f840cSTristram Ha #define PHY_REMOTE_NEXT_PAGE_NOT BIT(15) 808e66f840cSTristram Ha #define PHY_REMOTE_ACKNOWLEDGE_NOT BIT(14) 809e66f840cSTristram Ha #define PHY_REMOTE_REMOTE_FAULT_NOT BIT(13) 810e66f840cSTristram Ha #define PHY_REMOTE_SYM_PAUSE BIT(10) 811e66f840cSTristram Ha #define PHY_REMOTE_100BTX_FD BIT(8) 812e66f840cSTristram Ha #define PHY_REMOTE_100BTX BIT(7) 813e66f840cSTristram Ha #define PHY_REMOTE_10BT_FD BIT(6) 814e66f840cSTristram Ha #define PHY_REMOTE_10BT BIT(5) 815e66f840cSTristram Ha #endif 816e66f840cSTristram Ha 817e66f840cSTristram Ha #define KSZ8795_ID_HI 0x0022 818e66f840cSTristram Ha #define KSZ8795_ID_LO 0x1550 819e66f840cSTristram Ha 820e66f840cSTristram Ha #define KSZ8795_SW_ID 0x8795 821e66f840cSTristram Ha 822e66f840cSTristram Ha #define PHY_REG_LINK_MD 0x1D 823e66f840cSTristram Ha 824e66f840cSTristram Ha #define PHY_START_CABLE_DIAG BIT(15) 825e66f840cSTristram Ha #define PHY_CABLE_DIAG_RESULT 0x6000 826e66f840cSTristram Ha #define PHY_CABLE_STAT_NORMAL 0x0000 827e66f840cSTristram Ha #define PHY_CABLE_STAT_OPEN 0x2000 828e66f840cSTristram Ha #define PHY_CABLE_STAT_SHORT 0x4000 829e66f840cSTristram Ha #define PHY_CABLE_STAT_FAILED 0x6000 830e66f840cSTristram Ha #define PHY_CABLE_10M_SHORT BIT(12) 831e66f840cSTristram Ha #define PHY_CABLE_FAULT_COUNTER 0x01FF 832e66f840cSTristram Ha 833e66f840cSTristram Ha #define PHY_REG_PHY_CTRL 0x1F 834e66f840cSTristram Ha 835e66f840cSTristram Ha #define PHY_MODE_M 0x7 836e66f840cSTristram Ha #define PHY_MODE_S 8 837e66f840cSTristram Ha #define PHY_STAT_REVERSED_POLARITY BIT(5) 838e66f840cSTristram Ha #define PHY_STAT_MDIX BIT(4) 839e66f840cSTristram Ha #define PHY_FORCE_LINK BIT(3) 840e66f840cSTristram Ha #define PHY_POWER_SAVING_ENABLE BIT(2) 841e66f840cSTristram Ha #define PHY_REMOTE_LOOPBACK BIT(1) 842e66f840cSTristram Ha 843e66f840cSTristram Ha /* Chip resource */ 844e66f840cSTristram Ha 845e66f840cSTristram Ha #define PRIO_QUEUES 4 846e66f840cSTristram Ha 847e66f840cSTristram Ha #define KS_PRIO_IN_REG 4 848e66f840cSTristram Ha 849e66f840cSTristram Ha #define TOTAL_PORT_NUM 5 850e66f840cSTristram Ha 851e66f840cSTristram Ha /* Host port can only be last of them. */ 852e66f840cSTristram Ha #define SWITCH_PORT_NUM (TOTAL_PORT_NUM - 1) 853e66f840cSTristram Ha 854e66f840cSTristram Ha #define KSZ8795_COUNTER_NUM 0x20 855e66f840cSTristram Ha #define TOTAL_KSZ8795_COUNTER_NUM (KSZ8795_COUNTER_NUM + 4) 856e66f840cSTristram Ha 857e66f840cSTristram Ha #define SWITCH_COUNTER_NUM KSZ8795_COUNTER_NUM 858e66f840cSTristram Ha #define TOTAL_SWITCH_COUNTER_NUM TOTAL_KSZ8795_COUNTER_NUM 859e66f840cSTristram Ha 860e66f840cSTristram Ha /* Common names used by other drivers */ 861e66f840cSTristram Ha 862e66f840cSTristram Ha #define P_BCAST_STORM_CTRL REG_PORT_CTRL_0 863e66f840cSTristram Ha #define P_PRIO_CTRL REG_PORT_CTRL_0 864e66f840cSTristram Ha #define P_TAG_CTRL REG_PORT_CTRL_0 865e66f840cSTristram Ha #define P_MIRROR_CTRL REG_PORT_CTRL_1 866e66f840cSTristram Ha #define P_802_1P_CTRL REG_PORT_CTRL_2 867e66f840cSTristram Ha #define P_STP_CTRL REG_PORT_CTRL_2 868e66f840cSTristram Ha #define P_LOCAL_CTRL REG_PORT_CTRL_7 869e66f840cSTristram Ha #define P_REMOTE_STATUS REG_PORT_STATUS_0 870e66f840cSTristram Ha #define P_FORCE_CTRL REG_PORT_CTRL_9 871e66f840cSTristram Ha #define P_NEG_RESTART_CTRL REG_PORT_CTRL_10 872e66f840cSTristram Ha #define P_SPEED_STATUS REG_PORT_STATUS_1 873e66f840cSTristram Ha #define P_LINK_STATUS REG_PORT_STATUS_2 874e66f840cSTristram Ha #define P_PASS_ALL_CTRL REG_PORT_CTRL_12 875e66f840cSTristram Ha #define P_INS_SRC_PVID_CTRL REG_PORT_CTRL_12 876e66f840cSTristram Ha #define P_DROP_TAG_CTRL REG_PORT_CTRL_13 877e66f840cSTristram Ha #define P_RATE_LIMIT_CTRL REG_PORT_RATE_LIMIT 878e66f840cSTristram Ha 879e66f840cSTristram Ha #define S_UNKNOWN_DA_CTRL REG_SWITCH_CTRL_12 880e66f840cSTristram Ha #define S_FORWARD_INVALID_VID_CTRL REG_FORWARD_INVALID_VID 881e66f840cSTristram Ha 882e66f840cSTristram Ha #define S_FLUSH_TABLE_CTRL REG_SW_CTRL_0 883e66f840cSTristram Ha #define S_LINK_AGING_CTRL REG_SW_CTRL_0 884e66f840cSTristram Ha #define S_HUGE_PACKET_CTRL REG_SW_CTRL_1 885e66f840cSTristram Ha #define S_MIRROR_CTRL REG_SW_CTRL_3 886e66f840cSTristram Ha #define S_REPLACE_VID_CTRL REG_SW_CTRL_4 887e66f840cSTristram Ha #define S_PASS_PAUSE_CTRL REG_SW_CTRL_10 888e66f840cSTristram Ha #define S_TAIL_TAG_CTRL REG_SW_CTRL_10 889e66f840cSTristram Ha #define S_802_1P_PRIO_CTRL REG_SW_CTRL_12 890e66f840cSTristram Ha #define S_TOS_PRIO_CTRL REG_TOS_PRIO_CTRL_0 891e66f840cSTristram Ha #define S_IPV6_MLD_CTRL REG_SW_CTRL_21 892e66f840cSTristram Ha 893e66f840cSTristram Ha #define IND_ACC_TABLE(table) ((table) << 8) 894e66f840cSTristram Ha 895e66f840cSTristram Ha /* Driver set switch broadcast storm protection at 10% rate. */ 896e66f840cSTristram Ha #define BROADCAST_STORM_PROT_RATE 10 897e66f840cSTristram Ha 898e66f840cSTristram Ha /* 148,800 frames * 67 ms / 100 */ 899e66f840cSTristram Ha #define BROADCAST_STORM_VALUE 9969 900e66f840cSTristram Ha 901e66f840cSTristram Ha /** 902e66f840cSTristram Ha * STATIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF 903e66f840cSTristram Ha * STATIC_MAC_TABLE_FWD_PORTS 00-001F0000-00000000 904e66f840cSTristram Ha * STATIC_MAC_TABLE_VALID 00-00200000-00000000 905e66f840cSTristram Ha * STATIC_MAC_TABLE_OVERRIDE 00-00400000-00000000 906e66f840cSTristram Ha * STATIC_MAC_TABLE_USE_FID 00-00800000-00000000 907e66f840cSTristram Ha * STATIC_MAC_TABLE_FID 00-7F000000-00000000 908e66f840cSTristram Ha */ 909e66f840cSTristram Ha 910e66f840cSTristram Ha #define STATIC_MAC_TABLE_ADDR 0x0000FFFF 911e66f840cSTristram Ha #define STATIC_MAC_TABLE_FWD_PORTS 0x001F0000 912e66f840cSTristram Ha #define STATIC_MAC_TABLE_VALID 0x00200000 913e66f840cSTristram Ha #define STATIC_MAC_TABLE_OVERRIDE 0x00400000 914e66f840cSTristram Ha #define STATIC_MAC_TABLE_USE_FID 0x00800000 915e66f840cSTristram Ha #define STATIC_MAC_TABLE_FID 0x7F000000 916e66f840cSTristram Ha 917e66f840cSTristram Ha #define STATIC_MAC_FWD_PORTS_S 16 918e66f840cSTristram Ha #define STATIC_MAC_FID_S 24 919e66f840cSTristram Ha 920e66f840cSTristram Ha /** 921e66f840cSTristram Ha * VLAN_TABLE_FID 00-007F007F-007F007F 922e66f840cSTristram Ha * VLAN_TABLE_MEMBERSHIP 00-0F800F80-0F800F80 923e66f840cSTristram Ha * VLAN_TABLE_VALID 00-10001000-10001000 924e66f840cSTristram Ha */ 925e66f840cSTristram Ha 926e66f840cSTristram Ha #define VLAN_TABLE_FID 0x007F 927e66f840cSTristram Ha #define VLAN_TABLE_MEMBERSHIP 0x0F80 928e66f840cSTristram Ha #define VLAN_TABLE_VALID 0x1000 929e66f840cSTristram Ha 930e66f840cSTristram Ha #define VLAN_TABLE_MEMBERSHIP_S 7 931e66f840cSTristram Ha #define VLAN_TABLE_S 16 932e66f840cSTristram Ha 933e66f840cSTristram Ha /** 934e66f840cSTristram Ha * DYNAMIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF 935e66f840cSTristram Ha * DYNAMIC_MAC_TABLE_FID 00-007F0000-00000000 936e66f840cSTristram Ha * DYNAMIC_MAC_TABLE_NOT_READY 00-00800000-00000000 937e66f840cSTristram Ha * DYNAMIC_MAC_TABLE_SRC_PORT 00-07000000-00000000 938e66f840cSTristram Ha * DYNAMIC_MAC_TABLE_TIMESTAMP 00-18000000-00000000 939e66f840cSTristram Ha * DYNAMIC_MAC_TABLE_ENTRIES 7F-E0000000-00000000 940e66f840cSTristram Ha * DYNAMIC_MAC_TABLE_MAC_EMPTY 80-00000000-00000000 941e66f840cSTristram Ha */ 942e66f840cSTristram Ha 943e66f840cSTristram Ha #define DYNAMIC_MAC_TABLE_ADDR 0x0000FFFF 944e66f840cSTristram Ha #define DYNAMIC_MAC_TABLE_FID 0x007F0000 945e66f840cSTristram Ha #define DYNAMIC_MAC_TABLE_SRC_PORT 0x07000000 946e66f840cSTristram Ha #define DYNAMIC_MAC_TABLE_TIMESTAMP 0x18000000 947e66f840cSTristram Ha #define DYNAMIC_MAC_TABLE_ENTRIES 0xE0000000 948e66f840cSTristram Ha 949e66f840cSTristram Ha #define DYNAMIC_MAC_TABLE_NOT_READY 0x80 950e66f840cSTristram Ha 951e66f840cSTristram Ha #define DYNAMIC_MAC_TABLE_ENTRIES_H 0x7F 952e66f840cSTristram Ha #define DYNAMIC_MAC_TABLE_MAC_EMPTY 0x80 953e66f840cSTristram Ha 954e66f840cSTristram Ha #define DYNAMIC_MAC_FID_S 16 955e66f840cSTristram Ha #define DYNAMIC_MAC_SRC_PORT_S 24 956e66f840cSTristram Ha #define DYNAMIC_MAC_TIMESTAMP_S 27 957e66f840cSTristram Ha #define DYNAMIC_MAC_ENTRIES_S 29 958e66f840cSTristram Ha #define DYNAMIC_MAC_ENTRIES_H_S 3 959e66f840cSTristram Ha 960e66f840cSTristram Ha /** 961e66f840cSTristram Ha * MIB_COUNTER_VALUE 00-00000000-3FFFFFFF 962e66f840cSTristram Ha * MIB_TOTAL_BYTES 00-0000000F-FFFFFFFF 963e66f840cSTristram Ha * MIB_PACKET_DROPPED 00-00000000-0000FFFF 964e66f840cSTristram Ha * MIB_COUNTER_VALID 00-00000020-00000000 965e66f840cSTristram Ha * MIB_COUNTER_OVERFLOW 00-00000040-00000000 966e66f840cSTristram Ha */ 967e66f840cSTristram Ha 968e66f840cSTristram Ha #define MIB_COUNTER_OVERFLOW BIT(6) 969e66f840cSTristram Ha #define MIB_COUNTER_VALID BIT(5) 970e66f840cSTristram Ha 971e66f840cSTristram Ha #define MIB_COUNTER_VALUE 0x3FFFFFFF 972e66f840cSTristram Ha 973e66f840cSTristram Ha #define KS_MIB_TOTAL_RX_0 0x100 974e66f840cSTristram Ha #define KS_MIB_TOTAL_TX_0 0x101 975e66f840cSTristram Ha #define KS_MIB_PACKET_DROPPED_RX_0 0x102 976e66f840cSTristram Ha #define KS_MIB_PACKET_DROPPED_TX_0 0x103 977e66f840cSTristram Ha #define KS_MIB_TOTAL_RX_1 0x104 978e66f840cSTristram Ha #define KS_MIB_TOTAL_TX_1 0x105 979e66f840cSTristram Ha #define KS_MIB_PACKET_DROPPED_TX_1 0x106 980e66f840cSTristram Ha #define KS_MIB_PACKET_DROPPED_RX_1 0x107 981e66f840cSTristram Ha #define KS_MIB_TOTAL_RX_2 0x108 982e66f840cSTristram Ha #define KS_MIB_TOTAL_TX_2 0x109 983e66f840cSTristram Ha #define KS_MIB_PACKET_DROPPED_TX_2 0x10A 984e66f840cSTristram Ha #define KS_MIB_PACKET_DROPPED_RX_2 0x10B 985e66f840cSTristram Ha #define KS_MIB_TOTAL_RX_3 0x10C 986e66f840cSTristram Ha #define KS_MIB_TOTAL_TX_3 0x10D 987e66f840cSTristram Ha #define KS_MIB_PACKET_DROPPED_TX_3 0x10E 988e66f840cSTristram Ha #define KS_MIB_PACKET_DROPPED_RX_3 0x10F 989e66f840cSTristram Ha #define KS_MIB_TOTAL_RX_4 0x110 990e66f840cSTristram Ha #define KS_MIB_TOTAL_TX_4 0x111 991e66f840cSTristram Ha #define KS_MIB_PACKET_DROPPED_TX_4 0x112 992e66f840cSTristram Ha #define KS_MIB_PACKET_DROPPED_RX_4 0x113 993e66f840cSTristram Ha 994e66f840cSTristram Ha #define MIB_PACKET_DROPPED 0x0000FFFF 995e66f840cSTristram Ha 996e66f840cSTristram Ha #define MIB_TOTAL_BYTES_H 0x0000000F 997e66f840cSTristram Ha 998e66f840cSTristram Ha #define TAIL_TAG_OVERRIDE BIT(6) 999e66f840cSTristram Ha #define TAIL_TAG_LOOKUP BIT(7) 1000e66f840cSTristram Ha 1001e66f840cSTristram Ha #define VLAN_TABLE_ENTRIES (4096 / 4) 1002e66f840cSTristram Ha #define FID_ENTRIES 128 1003e66f840cSTristram Ha 1004e66f840cSTristram Ha #endif 1005