1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ8795 switch driver 4 * 5 * Copyright (C) 2017 Microchip Technology Inc. 6 * Tristram Ha <Tristram.Ha@microchip.com> 7 */ 8 9 #include <linux/delay.h> 10 #include <linux/export.h> 11 #include <linux/gpio.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/platform_data/microchip-ksz.h> 15 #include <linux/phy.h> 16 #include <linux/etherdevice.h> 17 #include <linux/if_bridge.h> 18 #include <net/dsa.h> 19 #include <net/switchdev.h> 20 21 #include "ksz_common.h" 22 #include "ksz8795_reg.h" 23 #include "ksz8.h" 24 25 static const u8 ksz8795_regs[] = { 26 [REG_IND_CTRL_0] = 0x6E, 27 [REG_IND_DATA_8] = 0x70, 28 [REG_IND_DATA_CHECK] = 0x72, 29 [REG_IND_DATA_HI] = 0x71, 30 [REG_IND_DATA_LO] = 0x75, 31 [REG_IND_MIB_CHECK] = 0x74, 32 [P_FORCE_CTRL] = 0x0C, 33 [P_LINK_STATUS] = 0x0E, 34 [P_LOCAL_CTRL] = 0x07, 35 [P_NEG_RESTART_CTRL] = 0x0D, 36 [P_REMOTE_STATUS] = 0x08, 37 [P_SPEED_STATUS] = 0x09, 38 [S_TAIL_TAG_CTRL] = 0x0C, 39 }; 40 41 static const u32 ksz8795_masks[] = { 42 [PORT_802_1P_REMAPPING] = BIT(7), 43 [SW_TAIL_TAG_ENABLE] = BIT(1), 44 [MIB_COUNTER_OVERFLOW] = BIT(6), 45 [MIB_COUNTER_VALID] = BIT(5), 46 [VLAN_TABLE_FID] = GENMASK(6, 0), 47 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 48 [VLAN_TABLE_VALID] = BIT(12), 49 [STATIC_MAC_TABLE_VALID] = BIT(21), 50 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 51 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 52 [STATIC_MAC_TABLE_OVERRIDE] = BIT(26), 53 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(24, 20), 54 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 55 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(8), 56 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 57 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 58 [DYNAMIC_MAC_TABLE_FID] = GENMASK(26, 20), 59 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 60 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 61 }; 62 63 static const u8 ksz8795_shifts[] = { 64 [VLAN_TABLE_MEMBERSHIP_S] = 7, 65 [VLAN_TABLE] = 16, 66 [STATIC_MAC_FWD_PORTS] = 16, 67 [STATIC_MAC_FID] = 24, 68 [DYNAMIC_MAC_ENTRIES_H] = 3, 69 [DYNAMIC_MAC_ENTRIES] = 29, 70 [DYNAMIC_MAC_FID] = 16, 71 [DYNAMIC_MAC_TIMESTAMP] = 27, 72 [DYNAMIC_MAC_SRC_PORT] = 24, 73 }; 74 75 static const u8 ksz8863_regs[] = { 76 [REG_IND_CTRL_0] = 0x79, 77 [REG_IND_DATA_8] = 0x7B, 78 [REG_IND_DATA_CHECK] = 0x7B, 79 [REG_IND_DATA_HI] = 0x7C, 80 [REG_IND_DATA_LO] = 0x80, 81 [REG_IND_MIB_CHECK] = 0x80, 82 [P_FORCE_CTRL] = 0x0C, 83 [P_LINK_STATUS] = 0x0E, 84 [P_LOCAL_CTRL] = 0x0C, 85 [P_NEG_RESTART_CTRL] = 0x0D, 86 [P_REMOTE_STATUS] = 0x0E, 87 [P_SPEED_STATUS] = 0x0F, 88 [S_TAIL_TAG_CTRL] = 0x03, 89 }; 90 91 static const u32 ksz8863_masks[] = { 92 [PORT_802_1P_REMAPPING] = BIT(3), 93 [SW_TAIL_TAG_ENABLE] = BIT(6), 94 [MIB_COUNTER_OVERFLOW] = BIT(7), 95 [MIB_COUNTER_VALID] = BIT(6), 96 [VLAN_TABLE_FID] = GENMASK(15, 12), 97 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 98 [VLAN_TABLE_VALID] = BIT(19), 99 [STATIC_MAC_TABLE_VALID] = BIT(19), 100 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 101 [STATIC_MAC_TABLE_FID] = GENMASK(29, 26), 102 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 103 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 104 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(5, 0), 105 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 106 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 107 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 28), 108 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 109 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 110 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 111 }; 112 113 static u8 ksz8863_shifts[] = { 114 [VLAN_TABLE_MEMBERSHIP_S] = 16, 115 [STATIC_MAC_FWD_PORTS] = 16, 116 [STATIC_MAC_FID] = 22, 117 [DYNAMIC_MAC_ENTRIES_H] = 3, 118 [DYNAMIC_MAC_ENTRIES] = 24, 119 [DYNAMIC_MAC_FID] = 16, 120 [DYNAMIC_MAC_TIMESTAMP] = 24, 121 [DYNAMIC_MAC_SRC_PORT] = 20, 122 }; 123 124 struct mib_names { 125 char string[ETH_GSTRING_LEN]; 126 }; 127 128 static const struct mib_names ksz87xx_mib_names[] = { 129 { "rx_hi" }, 130 { "rx_undersize" }, 131 { "rx_fragments" }, 132 { "rx_oversize" }, 133 { "rx_jabbers" }, 134 { "rx_symbol_err" }, 135 { "rx_crc_err" }, 136 { "rx_align_err" }, 137 { "rx_mac_ctrl" }, 138 { "rx_pause" }, 139 { "rx_bcast" }, 140 { "rx_mcast" }, 141 { "rx_ucast" }, 142 { "rx_64_or_less" }, 143 { "rx_65_127" }, 144 { "rx_128_255" }, 145 { "rx_256_511" }, 146 { "rx_512_1023" }, 147 { "rx_1024_1522" }, 148 { "rx_1523_2000" }, 149 { "rx_2001" }, 150 { "tx_hi" }, 151 { "tx_late_col" }, 152 { "tx_pause" }, 153 { "tx_bcast" }, 154 { "tx_mcast" }, 155 { "tx_ucast" }, 156 { "tx_deferred" }, 157 { "tx_total_col" }, 158 { "tx_exc_col" }, 159 { "tx_single_col" }, 160 { "tx_mult_col" }, 161 { "rx_total" }, 162 { "tx_total" }, 163 { "rx_discards" }, 164 { "tx_discards" }, 165 }; 166 167 static const struct mib_names ksz88xx_mib_names[] = { 168 { "rx" }, 169 { "rx_hi" }, 170 { "rx_undersize" }, 171 { "rx_fragments" }, 172 { "rx_oversize" }, 173 { "rx_jabbers" }, 174 { "rx_symbol_err" }, 175 { "rx_crc_err" }, 176 { "rx_align_err" }, 177 { "rx_mac_ctrl" }, 178 { "rx_pause" }, 179 { "rx_bcast" }, 180 { "rx_mcast" }, 181 { "rx_ucast" }, 182 { "rx_64_or_less" }, 183 { "rx_65_127" }, 184 { "rx_128_255" }, 185 { "rx_256_511" }, 186 { "rx_512_1023" }, 187 { "rx_1024_1522" }, 188 { "tx" }, 189 { "tx_hi" }, 190 { "tx_late_col" }, 191 { "tx_pause" }, 192 { "tx_bcast" }, 193 { "tx_mcast" }, 194 { "tx_ucast" }, 195 { "tx_deferred" }, 196 { "tx_total_col" }, 197 { "tx_exc_col" }, 198 { "tx_single_col" }, 199 { "tx_mult_col" }, 200 { "rx_discards" }, 201 { "tx_discards" }, 202 }; 203 204 static bool ksz_is_ksz88x3(struct ksz_device *dev) 205 { 206 return dev->chip_id == 0x8830; 207 } 208 209 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 210 { 211 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0); 212 } 213 214 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 215 bool set) 216 { 217 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset), 218 bits, set ? bits : 0); 219 } 220 221 static int ksz8_reset_switch(struct ksz_device *dev) 222 { 223 if (ksz_is_ksz88x3(dev)) { 224 /* reset switch */ 225 ksz_cfg(dev, KSZ8863_REG_SW_RESET, 226 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, true); 227 ksz_cfg(dev, KSZ8863_REG_SW_RESET, 228 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, false); 229 } else { 230 /* reset switch */ 231 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 232 SW_SOFTWARE_POWER_DOWN << SW_POWER_MANAGEMENT_MODE_S); 233 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 0); 234 } 235 236 return 0; 237 } 238 239 static void ksz8795_set_prio_queue(struct ksz_device *dev, int port, int queue) 240 { 241 u8 hi, lo; 242 243 /* Number of queues can only be 1, 2, or 4. */ 244 switch (queue) { 245 case 4: 246 case 3: 247 queue = PORT_QUEUE_SPLIT_4; 248 break; 249 case 2: 250 queue = PORT_QUEUE_SPLIT_2; 251 break; 252 default: 253 queue = PORT_QUEUE_SPLIT_1; 254 } 255 ksz_pread8(dev, port, REG_PORT_CTRL_0, &lo); 256 ksz_pread8(dev, port, P_DROP_TAG_CTRL, &hi); 257 lo &= ~PORT_QUEUE_SPLIT_L; 258 if (queue & PORT_QUEUE_SPLIT_2) 259 lo |= PORT_QUEUE_SPLIT_L; 260 hi &= ~PORT_QUEUE_SPLIT_H; 261 if (queue & PORT_QUEUE_SPLIT_4) 262 hi |= PORT_QUEUE_SPLIT_H; 263 ksz_pwrite8(dev, port, REG_PORT_CTRL_0, lo); 264 ksz_pwrite8(dev, port, P_DROP_TAG_CTRL, hi); 265 266 /* Default is port based for egress rate limit. */ 267 if (queue != PORT_QUEUE_SPLIT_1) 268 ksz_cfg(dev, REG_SW_CTRL_19, SW_OUT_RATE_LIMIT_QUEUE_BASED, 269 true); 270 } 271 272 static void ksz8_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt) 273 { 274 struct ksz8 *ksz8 = dev->priv; 275 const u32 *masks; 276 const u8 *regs; 277 u16 ctrl_addr; 278 u32 data; 279 u8 check; 280 int loop; 281 282 masks = ksz8->masks; 283 regs = ksz8->regs; 284 285 ctrl_addr = addr + dev->reg_mib_cnt * port; 286 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 287 288 mutex_lock(&dev->alu_mutex); 289 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 290 291 /* It is almost guaranteed to always read the valid bit because of 292 * slow SPI speed. 293 */ 294 for (loop = 2; loop > 0; loop--) { 295 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check); 296 297 if (check & masks[MIB_COUNTER_VALID]) { 298 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 299 if (check & masks[MIB_COUNTER_OVERFLOW]) 300 *cnt += MIB_COUNTER_VALUE + 1; 301 *cnt += data & MIB_COUNTER_VALUE; 302 break; 303 } 304 } 305 mutex_unlock(&dev->alu_mutex); 306 } 307 308 static void ksz8795_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 309 u64 *dropped, u64 *cnt) 310 { 311 struct ksz8 *ksz8 = dev->priv; 312 const u32 *masks; 313 const u8 *regs; 314 u16 ctrl_addr; 315 u32 data; 316 u8 check; 317 int loop; 318 319 masks = ksz8->masks; 320 regs = ksz8->regs; 321 322 addr -= dev->reg_mib_cnt; 323 ctrl_addr = (KSZ8795_MIB_TOTAL_RX_1 - KSZ8795_MIB_TOTAL_RX_0) * port; 324 ctrl_addr += addr + KSZ8795_MIB_TOTAL_RX_0; 325 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 326 327 mutex_lock(&dev->alu_mutex); 328 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 329 330 /* It is almost guaranteed to always read the valid bit because of 331 * slow SPI speed. 332 */ 333 for (loop = 2; loop > 0; loop--) { 334 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check); 335 336 if (check & masks[MIB_COUNTER_VALID]) { 337 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 338 if (addr < 2) { 339 u64 total; 340 341 total = check & MIB_TOTAL_BYTES_H; 342 total <<= 32; 343 *cnt += total; 344 *cnt += data; 345 if (check & masks[MIB_COUNTER_OVERFLOW]) { 346 total = MIB_TOTAL_BYTES_H + 1; 347 total <<= 32; 348 *cnt += total; 349 } 350 } else { 351 if (check & masks[MIB_COUNTER_OVERFLOW]) 352 *cnt += MIB_PACKET_DROPPED + 1; 353 *cnt += data & MIB_PACKET_DROPPED; 354 } 355 break; 356 } 357 } 358 mutex_unlock(&dev->alu_mutex); 359 } 360 361 static void ksz8863_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 362 u64 *dropped, u64 *cnt) 363 { 364 struct ksz8 *ksz8 = dev->priv; 365 const u8 *regs = ksz8->regs; 366 u32 *last = (u32 *)dropped; 367 u16 ctrl_addr; 368 u32 data; 369 u32 cur; 370 371 addr -= dev->reg_mib_cnt; 372 ctrl_addr = addr ? KSZ8863_MIB_PACKET_DROPPED_TX_0 : 373 KSZ8863_MIB_PACKET_DROPPED_RX_0; 374 ctrl_addr += port; 375 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 376 377 mutex_lock(&dev->alu_mutex); 378 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 379 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 380 mutex_unlock(&dev->alu_mutex); 381 382 data &= MIB_PACKET_DROPPED; 383 cur = last[addr]; 384 if (data != cur) { 385 last[addr] = data; 386 if (data < cur) 387 data += MIB_PACKET_DROPPED + 1; 388 data -= cur; 389 *cnt += data; 390 } 391 } 392 393 static void ksz8_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 394 u64 *dropped, u64 *cnt) 395 { 396 if (ksz_is_ksz88x3(dev)) 397 ksz8863_r_mib_pkt(dev, port, addr, dropped, cnt); 398 else 399 ksz8795_r_mib_pkt(dev, port, addr, dropped, cnt); 400 } 401 402 static void ksz8_freeze_mib(struct ksz_device *dev, int port, bool freeze) 403 { 404 if (ksz_is_ksz88x3(dev)) 405 return; 406 407 /* enable the port for flush/freeze function */ 408 if (freeze) 409 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true); 410 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FREEZE, freeze); 411 412 /* disable the port after freeze is done */ 413 if (!freeze) 414 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false); 415 } 416 417 static void ksz8_port_init_cnt(struct ksz_device *dev, int port) 418 { 419 struct ksz_port_mib *mib = &dev->ports[port].mib; 420 u64 *dropped; 421 422 if (!ksz_is_ksz88x3(dev)) { 423 /* flush all enabled port MIB counters */ 424 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true); 425 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FLUSH, true); 426 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false); 427 } 428 429 mib->cnt_ptr = 0; 430 431 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 432 while (mib->cnt_ptr < dev->reg_mib_cnt) { 433 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 434 &mib->counters[mib->cnt_ptr]); 435 ++mib->cnt_ptr; 436 } 437 438 /* last one in storage */ 439 dropped = &mib->counters[dev->mib_cnt]; 440 441 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 442 while (mib->cnt_ptr < dev->mib_cnt) { 443 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 444 dropped, &mib->counters[mib->cnt_ptr]); 445 ++mib->cnt_ptr; 446 } 447 mib->cnt_ptr = 0; 448 memset(mib->counters, 0, dev->mib_cnt * sizeof(u64)); 449 } 450 451 static void ksz8_r_table(struct ksz_device *dev, int table, u16 addr, u64 *data) 452 { 453 struct ksz8 *ksz8 = dev->priv; 454 const u8 *regs = ksz8->regs; 455 u16 ctrl_addr; 456 457 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr; 458 459 mutex_lock(&dev->alu_mutex); 460 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 461 ksz_read64(dev, regs[REG_IND_DATA_HI], data); 462 mutex_unlock(&dev->alu_mutex); 463 } 464 465 static void ksz8_w_table(struct ksz_device *dev, int table, u16 addr, u64 data) 466 { 467 struct ksz8 *ksz8 = dev->priv; 468 const u8 *regs = ksz8->regs; 469 u16 ctrl_addr; 470 471 ctrl_addr = IND_ACC_TABLE(table) | addr; 472 473 mutex_lock(&dev->alu_mutex); 474 ksz_write64(dev, regs[REG_IND_DATA_HI], data); 475 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 476 mutex_unlock(&dev->alu_mutex); 477 } 478 479 static int ksz8_valid_dyn_entry(struct ksz_device *dev, u8 *data) 480 { 481 struct ksz8 *ksz8 = dev->priv; 482 int timeout = 100; 483 const u32 *masks; 484 const u8 *regs; 485 486 masks = ksz8->masks; 487 regs = ksz8->regs; 488 489 do { 490 ksz_read8(dev, regs[REG_IND_DATA_CHECK], data); 491 timeout--; 492 } while ((*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) && timeout); 493 494 /* Entry is not ready for accessing. */ 495 if (*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) { 496 return -EAGAIN; 497 /* Entry is ready for accessing. */ 498 } else { 499 ksz_read8(dev, regs[REG_IND_DATA_8], data); 500 501 /* There is no valid entry in the table. */ 502 if (*data & masks[DYNAMIC_MAC_TABLE_MAC_EMPTY]) 503 return -ENXIO; 504 } 505 return 0; 506 } 507 508 static int ksz8_r_dyn_mac_table(struct ksz_device *dev, u16 addr, 509 u8 *mac_addr, u8 *fid, u8 *src_port, 510 u8 *timestamp, u16 *entries) 511 { 512 struct ksz8 *ksz8 = dev->priv; 513 u32 data_hi, data_lo; 514 const u8 *shifts; 515 const u32 *masks; 516 const u8 *regs; 517 u16 ctrl_addr; 518 u8 data; 519 int rc; 520 521 shifts = ksz8->shifts; 522 masks = ksz8->masks; 523 regs = ksz8->regs; 524 525 ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr; 526 527 mutex_lock(&dev->alu_mutex); 528 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 529 530 rc = ksz8_valid_dyn_entry(dev, &data); 531 if (rc == -EAGAIN) { 532 if (addr == 0) 533 *entries = 0; 534 } else if (rc == -ENXIO) { 535 *entries = 0; 536 /* At least one valid entry in the table. */ 537 } else { 538 u64 buf = 0; 539 int cnt; 540 541 ksz_read64(dev, regs[REG_IND_DATA_HI], &buf); 542 data_hi = (u32)(buf >> 32); 543 data_lo = (u32)buf; 544 545 /* Check out how many valid entry in the table. */ 546 cnt = data & masks[DYNAMIC_MAC_TABLE_ENTRIES_H]; 547 cnt <<= shifts[DYNAMIC_MAC_ENTRIES_H]; 548 cnt |= (data_hi & masks[DYNAMIC_MAC_TABLE_ENTRIES]) >> 549 shifts[DYNAMIC_MAC_ENTRIES]; 550 *entries = cnt + 1; 551 552 *fid = (data_hi & masks[DYNAMIC_MAC_TABLE_FID]) >> 553 shifts[DYNAMIC_MAC_FID]; 554 *src_port = (data_hi & masks[DYNAMIC_MAC_TABLE_SRC_PORT]) >> 555 shifts[DYNAMIC_MAC_SRC_PORT]; 556 *timestamp = (data_hi & masks[DYNAMIC_MAC_TABLE_TIMESTAMP]) >> 557 shifts[DYNAMIC_MAC_TIMESTAMP]; 558 559 mac_addr[5] = (u8)data_lo; 560 mac_addr[4] = (u8)(data_lo >> 8); 561 mac_addr[3] = (u8)(data_lo >> 16); 562 mac_addr[2] = (u8)(data_lo >> 24); 563 564 mac_addr[1] = (u8)data_hi; 565 mac_addr[0] = (u8)(data_hi >> 8); 566 rc = 0; 567 } 568 mutex_unlock(&dev->alu_mutex); 569 570 return rc; 571 } 572 573 static int ksz8_r_sta_mac_table(struct ksz_device *dev, u16 addr, 574 struct alu_struct *alu) 575 { 576 struct ksz8 *ksz8 = dev->priv; 577 u32 data_hi, data_lo; 578 const u8 *shifts; 579 const u32 *masks; 580 u64 data; 581 582 shifts = ksz8->shifts; 583 masks = ksz8->masks; 584 585 ksz8_r_table(dev, TABLE_STATIC_MAC, addr, &data); 586 data_hi = data >> 32; 587 data_lo = (u32)data; 588 if (data_hi & (masks[STATIC_MAC_TABLE_VALID] | 589 masks[STATIC_MAC_TABLE_OVERRIDE])) { 590 alu->mac[5] = (u8)data_lo; 591 alu->mac[4] = (u8)(data_lo >> 8); 592 alu->mac[3] = (u8)(data_lo >> 16); 593 alu->mac[2] = (u8)(data_lo >> 24); 594 alu->mac[1] = (u8)data_hi; 595 alu->mac[0] = (u8)(data_hi >> 8); 596 alu->port_forward = 597 (data_hi & masks[STATIC_MAC_TABLE_FWD_PORTS]) >> 598 shifts[STATIC_MAC_FWD_PORTS]; 599 alu->is_override = 600 (data_hi & masks[STATIC_MAC_TABLE_OVERRIDE]) ? 1 : 0; 601 data_hi >>= 1; 602 alu->is_static = true; 603 alu->is_use_fid = 604 (data_hi & masks[STATIC_MAC_TABLE_USE_FID]) ? 1 : 0; 605 alu->fid = (data_hi & masks[STATIC_MAC_TABLE_FID]) >> 606 shifts[STATIC_MAC_FID]; 607 return 0; 608 } 609 return -ENXIO; 610 } 611 612 static void ksz8_w_sta_mac_table(struct ksz_device *dev, u16 addr, 613 struct alu_struct *alu) 614 { 615 struct ksz8 *ksz8 = dev->priv; 616 u32 data_hi, data_lo; 617 const u8 *shifts; 618 const u32 *masks; 619 u64 data; 620 621 shifts = ksz8->shifts; 622 masks = ksz8->masks; 623 624 data_lo = ((u32)alu->mac[2] << 24) | 625 ((u32)alu->mac[3] << 16) | 626 ((u32)alu->mac[4] << 8) | alu->mac[5]; 627 data_hi = ((u32)alu->mac[0] << 8) | alu->mac[1]; 628 data_hi |= (u32)alu->port_forward << shifts[STATIC_MAC_FWD_PORTS]; 629 630 if (alu->is_override) 631 data_hi |= masks[STATIC_MAC_TABLE_OVERRIDE]; 632 if (alu->is_use_fid) { 633 data_hi |= masks[STATIC_MAC_TABLE_USE_FID]; 634 data_hi |= (u32)alu->fid << shifts[STATIC_MAC_FID]; 635 } 636 if (alu->is_static) 637 data_hi |= masks[STATIC_MAC_TABLE_VALID]; 638 else 639 data_hi &= ~masks[STATIC_MAC_TABLE_OVERRIDE]; 640 641 data = (u64)data_hi << 32 | data_lo; 642 ksz8_w_table(dev, TABLE_STATIC_MAC, addr, data); 643 } 644 645 static void ksz8_from_vlan(struct ksz_device *dev, u32 vlan, u8 *fid, 646 u8 *member, u8 *valid) 647 { 648 struct ksz8 *ksz8 = dev->priv; 649 const u8 *shifts; 650 const u32 *masks; 651 652 shifts = ksz8->shifts; 653 masks = ksz8->masks; 654 655 *fid = vlan & masks[VLAN_TABLE_FID]; 656 *member = (vlan & masks[VLAN_TABLE_MEMBERSHIP]) >> 657 shifts[VLAN_TABLE_MEMBERSHIP_S]; 658 *valid = !!(vlan & masks[VLAN_TABLE_VALID]); 659 } 660 661 static void ksz8_to_vlan(struct ksz_device *dev, u8 fid, u8 member, u8 valid, 662 u16 *vlan) 663 { 664 struct ksz8 *ksz8 = dev->priv; 665 const u8 *shifts; 666 const u32 *masks; 667 668 shifts = ksz8->shifts; 669 masks = ksz8->masks; 670 671 *vlan = fid; 672 *vlan |= (u16)member << shifts[VLAN_TABLE_MEMBERSHIP_S]; 673 if (valid) 674 *vlan |= masks[VLAN_TABLE_VALID]; 675 } 676 677 static void ksz8_r_vlan_entries(struct ksz_device *dev, u16 addr) 678 { 679 struct ksz8 *ksz8 = dev->priv; 680 const u8 *shifts; 681 u64 data; 682 int i; 683 684 shifts = ksz8->shifts; 685 686 ksz8_r_table(dev, TABLE_VLAN, addr, &data); 687 addr *= dev->phy_port_cnt; 688 for (i = 0; i < dev->phy_port_cnt; i++) { 689 dev->vlan_cache[addr + i].table[0] = (u16)data; 690 data >>= shifts[VLAN_TABLE]; 691 } 692 } 693 694 static void ksz8_r_vlan_table(struct ksz_device *dev, u16 vid, u16 *vlan) 695 { 696 int index; 697 u16 *data; 698 u16 addr; 699 u64 buf; 700 701 data = (u16 *)&buf; 702 addr = vid / dev->phy_port_cnt; 703 index = vid & 3; 704 ksz8_r_table(dev, TABLE_VLAN, addr, &buf); 705 *vlan = data[index]; 706 } 707 708 static void ksz8_w_vlan_table(struct ksz_device *dev, u16 vid, u16 vlan) 709 { 710 int index; 711 u16 *data; 712 u16 addr; 713 u64 buf; 714 715 data = (u16 *)&buf; 716 addr = vid / dev->phy_port_cnt; 717 index = vid & 3; 718 ksz8_r_table(dev, TABLE_VLAN, addr, &buf); 719 data[index] = vlan; 720 dev->vlan_cache[vid].table[0] = vlan; 721 ksz8_w_table(dev, TABLE_VLAN, addr, buf); 722 } 723 724 static void ksz8_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val) 725 { 726 struct ksz8 *ksz8 = dev->priv; 727 u8 restart, speed, ctrl, link; 728 const u8 *regs = ksz8->regs; 729 int processed = true; 730 u16 data = 0; 731 u8 p = phy; 732 733 switch (reg) { 734 case PHY_REG_CTRL: 735 ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart); 736 ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed); 737 ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl); 738 if (restart & PORT_PHY_LOOPBACK) 739 data |= PHY_LOOPBACK; 740 if (ctrl & PORT_FORCE_100_MBIT) 741 data |= PHY_SPEED_100MBIT; 742 if (ksz_is_ksz88x3(dev)) { 743 if ((ctrl & PORT_AUTO_NEG_ENABLE)) 744 data |= PHY_AUTO_NEG_ENABLE; 745 } else { 746 if (!(ctrl & PORT_AUTO_NEG_DISABLE)) 747 data |= PHY_AUTO_NEG_ENABLE; 748 } 749 if (restart & PORT_POWER_DOWN) 750 data |= PHY_POWER_DOWN; 751 if (restart & PORT_AUTO_NEG_RESTART) 752 data |= PHY_AUTO_NEG_RESTART; 753 if (ctrl & PORT_FORCE_FULL_DUPLEX) 754 data |= PHY_FULL_DUPLEX; 755 if (speed & PORT_HP_MDIX) 756 data |= PHY_HP_MDIX; 757 if (restart & PORT_FORCE_MDIX) 758 data |= PHY_FORCE_MDIX; 759 if (restart & PORT_AUTO_MDIX_DISABLE) 760 data |= PHY_AUTO_MDIX_DISABLE; 761 if (restart & PORT_TX_DISABLE) 762 data |= PHY_TRANSMIT_DISABLE; 763 if (restart & PORT_LED_OFF) 764 data |= PHY_LED_DISABLE; 765 break; 766 case PHY_REG_STATUS: 767 ksz_pread8(dev, p, regs[P_LINK_STATUS], &link); 768 data = PHY_100BTX_FD_CAPABLE | 769 PHY_100BTX_CAPABLE | 770 PHY_10BT_FD_CAPABLE | 771 PHY_10BT_CAPABLE | 772 PHY_AUTO_NEG_CAPABLE; 773 if (link & PORT_AUTO_NEG_COMPLETE) 774 data |= PHY_AUTO_NEG_ACKNOWLEDGE; 775 if (link & PORT_STAT_LINK_GOOD) 776 data |= PHY_LINK_STATUS; 777 break; 778 case PHY_REG_ID_1: 779 data = KSZ8795_ID_HI; 780 break; 781 case PHY_REG_ID_2: 782 if (ksz_is_ksz88x3(dev)) 783 data = KSZ8863_ID_LO; 784 else 785 data = KSZ8795_ID_LO; 786 break; 787 case PHY_REG_AUTO_NEGOTIATION: 788 ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl); 789 data = PHY_AUTO_NEG_802_3; 790 if (ctrl & PORT_AUTO_NEG_SYM_PAUSE) 791 data |= PHY_AUTO_NEG_SYM_PAUSE; 792 if (ctrl & PORT_AUTO_NEG_100BTX_FD) 793 data |= PHY_AUTO_NEG_100BTX_FD; 794 if (ctrl & PORT_AUTO_NEG_100BTX) 795 data |= PHY_AUTO_NEG_100BTX; 796 if (ctrl & PORT_AUTO_NEG_10BT_FD) 797 data |= PHY_AUTO_NEG_10BT_FD; 798 if (ctrl & PORT_AUTO_NEG_10BT) 799 data |= PHY_AUTO_NEG_10BT; 800 break; 801 case PHY_REG_REMOTE_CAPABILITY: 802 ksz_pread8(dev, p, regs[P_REMOTE_STATUS], &link); 803 data = PHY_AUTO_NEG_802_3; 804 if (link & PORT_REMOTE_SYM_PAUSE) 805 data |= PHY_AUTO_NEG_SYM_PAUSE; 806 if (link & PORT_REMOTE_100BTX_FD) 807 data |= PHY_AUTO_NEG_100BTX_FD; 808 if (link & PORT_REMOTE_100BTX) 809 data |= PHY_AUTO_NEG_100BTX; 810 if (link & PORT_REMOTE_10BT_FD) 811 data |= PHY_AUTO_NEG_10BT_FD; 812 if (link & PORT_REMOTE_10BT) 813 data |= PHY_AUTO_NEG_10BT; 814 if (data & ~PHY_AUTO_NEG_802_3) 815 data |= PHY_REMOTE_ACKNOWLEDGE_NOT; 816 break; 817 default: 818 processed = false; 819 break; 820 } 821 if (processed) 822 *val = data; 823 } 824 825 static void ksz8_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val) 826 { 827 struct ksz8 *ksz8 = dev->priv; 828 u8 restart, speed, ctrl, data; 829 const u8 *regs = ksz8->regs; 830 u8 p = phy; 831 832 switch (reg) { 833 case PHY_REG_CTRL: 834 835 /* Do not support PHY reset function. */ 836 if (val & PHY_RESET) 837 break; 838 ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed); 839 data = speed; 840 if (val & PHY_HP_MDIX) 841 data |= PORT_HP_MDIX; 842 else 843 data &= ~PORT_HP_MDIX; 844 if (data != speed) 845 ksz_pwrite8(dev, p, regs[P_SPEED_STATUS], data); 846 ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl); 847 data = ctrl; 848 if (ksz_is_ksz88x3(dev)) { 849 if ((val & PHY_AUTO_NEG_ENABLE)) 850 data |= PORT_AUTO_NEG_ENABLE; 851 else 852 data &= ~PORT_AUTO_NEG_ENABLE; 853 } else { 854 if (!(val & PHY_AUTO_NEG_ENABLE)) 855 data |= PORT_AUTO_NEG_DISABLE; 856 else 857 data &= ~PORT_AUTO_NEG_DISABLE; 858 859 /* Fiber port does not support auto-negotiation. */ 860 if (dev->ports[p].fiber) 861 data |= PORT_AUTO_NEG_DISABLE; 862 } 863 864 if (val & PHY_SPEED_100MBIT) 865 data |= PORT_FORCE_100_MBIT; 866 else 867 data &= ~PORT_FORCE_100_MBIT; 868 if (val & PHY_FULL_DUPLEX) 869 data |= PORT_FORCE_FULL_DUPLEX; 870 else 871 data &= ~PORT_FORCE_FULL_DUPLEX; 872 if (data != ctrl) 873 ksz_pwrite8(dev, p, regs[P_FORCE_CTRL], data); 874 ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart); 875 data = restart; 876 if (val & PHY_LED_DISABLE) 877 data |= PORT_LED_OFF; 878 else 879 data &= ~PORT_LED_OFF; 880 if (val & PHY_TRANSMIT_DISABLE) 881 data |= PORT_TX_DISABLE; 882 else 883 data &= ~PORT_TX_DISABLE; 884 if (val & PHY_AUTO_NEG_RESTART) 885 data |= PORT_AUTO_NEG_RESTART; 886 else 887 data &= ~(PORT_AUTO_NEG_RESTART); 888 if (val & PHY_POWER_DOWN) 889 data |= PORT_POWER_DOWN; 890 else 891 data &= ~PORT_POWER_DOWN; 892 if (val & PHY_AUTO_MDIX_DISABLE) 893 data |= PORT_AUTO_MDIX_DISABLE; 894 else 895 data &= ~PORT_AUTO_MDIX_DISABLE; 896 if (val & PHY_FORCE_MDIX) 897 data |= PORT_FORCE_MDIX; 898 else 899 data &= ~PORT_FORCE_MDIX; 900 if (val & PHY_LOOPBACK) 901 data |= PORT_PHY_LOOPBACK; 902 else 903 data &= ~PORT_PHY_LOOPBACK; 904 if (data != restart) 905 ksz_pwrite8(dev, p, regs[P_NEG_RESTART_CTRL], data); 906 break; 907 case PHY_REG_AUTO_NEGOTIATION: 908 ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl); 909 data = ctrl; 910 data &= ~(PORT_AUTO_NEG_SYM_PAUSE | 911 PORT_AUTO_NEG_100BTX_FD | 912 PORT_AUTO_NEG_100BTX | 913 PORT_AUTO_NEG_10BT_FD | 914 PORT_AUTO_NEG_10BT); 915 if (val & PHY_AUTO_NEG_SYM_PAUSE) 916 data |= PORT_AUTO_NEG_SYM_PAUSE; 917 if (val & PHY_AUTO_NEG_100BTX_FD) 918 data |= PORT_AUTO_NEG_100BTX_FD; 919 if (val & PHY_AUTO_NEG_100BTX) 920 data |= PORT_AUTO_NEG_100BTX; 921 if (val & PHY_AUTO_NEG_10BT_FD) 922 data |= PORT_AUTO_NEG_10BT_FD; 923 if (val & PHY_AUTO_NEG_10BT) 924 data |= PORT_AUTO_NEG_10BT; 925 if (data != ctrl) 926 ksz_pwrite8(dev, p, regs[P_LOCAL_CTRL], data); 927 break; 928 default: 929 break; 930 } 931 } 932 933 static enum dsa_tag_protocol ksz8_get_tag_protocol(struct dsa_switch *ds, 934 int port, 935 enum dsa_tag_protocol mp) 936 { 937 struct ksz_device *dev = ds->priv; 938 939 /* ksz88x3 uses the same tag schema as KSZ9893 */ 940 return ksz_is_ksz88x3(dev) ? 941 DSA_TAG_PROTO_KSZ9893 : DSA_TAG_PROTO_KSZ8795; 942 } 943 944 static void ksz8_get_strings(struct dsa_switch *ds, int port, 945 u32 stringset, uint8_t *buf) 946 { 947 struct ksz_device *dev = ds->priv; 948 int i; 949 950 for (i = 0; i < dev->mib_cnt; i++) { 951 memcpy(buf + i * ETH_GSTRING_LEN, 952 dev->mib_names[i].string, ETH_GSTRING_LEN); 953 } 954 } 955 956 static void ksz8_cfg_port_member(struct ksz_device *dev, int port, u8 member) 957 { 958 u8 data; 959 960 ksz_pread8(dev, port, P_MIRROR_CTRL, &data); 961 data &= ~PORT_VLAN_MEMBERSHIP; 962 data |= (member & dev->port_mask); 963 ksz_pwrite8(dev, port, P_MIRROR_CTRL, data); 964 dev->ports[port].member = member; 965 } 966 967 static void ksz8_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 968 { 969 struct ksz_device *dev = ds->priv; 970 int forward = dev->member; 971 struct ksz_port *p; 972 int member = -1; 973 u8 data; 974 975 p = &dev->ports[port]; 976 977 ksz_pread8(dev, port, P_STP_CTRL, &data); 978 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 979 980 switch (state) { 981 case BR_STATE_DISABLED: 982 data |= PORT_LEARN_DISABLE; 983 if (port < dev->phy_port_cnt) 984 member = 0; 985 break; 986 case BR_STATE_LISTENING: 987 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 988 if (port < dev->phy_port_cnt && 989 p->stp_state == BR_STATE_DISABLED) 990 member = dev->host_mask | p->vid_member; 991 break; 992 case BR_STATE_LEARNING: 993 data |= PORT_RX_ENABLE; 994 break; 995 case BR_STATE_FORWARDING: 996 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 997 998 /* This function is also used internally. */ 999 if (port == dev->cpu_port) 1000 break; 1001 1002 /* Port is a member of a bridge. */ 1003 if (dev->br_member & BIT(port)) { 1004 dev->member |= BIT(port); 1005 member = dev->member; 1006 } else { 1007 member = dev->host_mask | p->vid_member; 1008 } 1009 break; 1010 case BR_STATE_BLOCKING: 1011 data |= PORT_LEARN_DISABLE; 1012 if (port < dev->phy_port_cnt && 1013 p->stp_state == BR_STATE_DISABLED) 1014 member = dev->host_mask | p->vid_member; 1015 break; 1016 default: 1017 dev_err(ds->dev, "invalid STP state: %d\n", state); 1018 return; 1019 } 1020 1021 ksz_pwrite8(dev, port, P_STP_CTRL, data); 1022 p->stp_state = state; 1023 /* Port membership may share register with STP state. */ 1024 if (member >= 0 && member != p->member) 1025 ksz8_cfg_port_member(dev, port, (u8)member); 1026 1027 /* Check if forwarding needs to be updated. */ 1028 if (state != BR_STATE_FORWARDING) { 1029 if (dev->br_member & BIT(port)) 1030 dev->member &= ~BIT(port); 1031 } 1032 1033 /* When topology has changed the function ksz_update_port_member 1034 * should be called to modify port forwarding behavior. 1035 */ 1036 if (forward != dev->member) 1037 ksz_update_port_member(dev, port); 1038 } 1039 1040 static void ksz8_flush_dyn_mac_table(struct ksz_device *dev, int port) 1041 { 1042 u8 learn[DSA_MAX_PORTS]; 1043 int first, index, cnt; 1044 struct ksz_port *p; 1045 1046 if ((uint)port < dev->port_cnt) { 1047 first = port; 1048 cnt = port + 1; 1049 } else { 1050 /* Flush all ports. */ 1051 first = 0; 1052 cnt = dev->port_cnt; 1053 } 1054 for (index = first; index < cnt; index++) { 1055 p = &dev->ports[index]; 1056 if (!p->on) 1057 continue; 1058 ksz_pread8(dev, index, P_STP_CTRL, &learn[index]); 1059 if (!(learn[index] & PORT_LEARN_DISABLE)) 1060 ksz_pwrite8(dev, index, P_STP_CTRL, 1061 learn[index] | PORT_LEARN_DISABLE); 1062 } 1063 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 1064 for (index = first; index < cnt; index++) { 1065 p = &dev->ports[index]; 1066 if (!p->on) 1067 continue; 1068 if (!(learn[index] & PORT_LEARN_DISABLE)) 1069 ksz_pwrite8(dev, index, P_STP_CTRL, learn[index]); 1070 } 1071 } 1072 1073 static int ksz8_port_vlan_filtering(struct dsa_switch *ds, int port, bool flag, 1074 struct netlink_ext_ack *extack) 1075 { 1076 struct ksz_device *dev = ds->priv; 1077 1078 if (ksz_is_ksz88x3(dev)) 1079 return -ENOTSUPP; 1080 1081 ksz_cfg(dev, S_MIRROR_CTRL, SW_VLAN_ENABLE, flag); 1082 1083 return 0; 1084 } 1085 1086 static int ksz8_port_vlan_add(struct dsa_switch *ds, int port, 1087 const struct switchdev_obj_port_vlan *vlan, 1088 struct netlink_ext_ack *extack) 1089 { 1090 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1091 struct ksz_device *dev = ds->priv; 1092 u16 data, new_pvid = 0; 1093 u8 fid, member, valid; 1094 1095 if (ksz_is_ksz88x3(dev)) 1096 return -ENOTSUPP; 1097 1098 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged); 1099 1100 ksz8_r_vlan_table(dev, vlan->vid, &data); 1101 ksz8_from_vlan(dev, data, &fid, &member, &valid); 1102 1103 /* First time to setup the VLAN entry. */ 1104 if (!valid) { 1105 /* Need to find a way to map VID to FID. */ 1106 fid = 1; 1107 valid = 1; 1108 } 1109 member |= BIT(port); 1110 1111 ksz8_to_vlan(dev, fid, member, valid, &data); 1112 ksz8_w_vlan_table(dev, vlan->vid, data); 1113 1114 /* change PVID */ 1115 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 1116 new_pvid = vlan->vid; 1117 1118 if (new_pvid) { 1119 u16 vid; 1120 1121 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &vid); 1122 vid &= 0xfff; 1123 vid |= new_pvid; 1124 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, vid); 1125 } 1126 1127 return 0; 1128 } 1129 1130 static int ksz8_port_vlan_del(struct dsa_switch *ds, int port, 1131 const struct switchdev_obj_port_vlan *vlan) 1132 { 1133 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1134 struct ksz_device *dev = ds->priv; 1135 u16 data, pvid, new_pvid = 0; 1136 u8 fid, member, valid; 1137 1138 if (ksz_is_ksz88x3(dev)) 1139 return -ENOTSUPP; 1140 1141 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid); 1142 pvid = pvid & 0xFFF; 1143 1144 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged); 1145 1146 ksz8_r_vlan_table(dev, vlan->vid, &data); 1147 ksz8_from_vlan(dev, data, &fid, &member, &valid); 1148 1149 member &= ~BIT(port); 1150 1151 /* Invalidate the entry if no more member. */ 1152 if (!member) { 1153 fid = 0; 1154 valid = 0; 1155 } 1156 1157 if (pvid == vlan->vid) 1158 new_pvid = 1; 1159 1160 ksz8_to_vlan(dev, fid, member, valid, &data); 1161 ksz8_w_vlan_table(dev, vlan->vid, data); 1162 1163 if (new_pvid != pvid) 1164 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, pvid); 1165 1166 return 0; 1167 } 1168 1169 static int ksz8_port_mirror_add(struct dsa_switch *ds, int port, 1170 struct dsa_mall_mirror_tc_entry *mirror, 1171 bool ingress) 1172 { 1173 struct ksz_device *dev = ds->priv; 1174 1175 if (ingress) { 1176 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 1177 dev->mirror_rx |= BIT(port); 1178 } else { 1179 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 1180 dev->mirror_tx |= BIT(port); 1181 } 1182 1183 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false); 1184 1185 /* configure mirror port */ 1186 if (dev->mirror_rx || dev->mirror_tx) 1187 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1188 PORT_MIRROR_SNIFFER, true); 1189 1190 return 0; 1191 } 1192 1193 static void ksz8_port_mirror_del(struct dsa_switch *ds, int port, 1194 struct dsa_mall_mirror_tc_entry *mirror) 1195 { 1196 struct ksz_device *dev = ds->priv; 1197 u8 data; 1198 1199 if (mirror->ingress) { 1200 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 1201 dev->mirror_rx &= ~BIT(port); 1202 } else { 1203 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 1204 dev->mirror_tx &= ~BIT(port); 1205 } 1206 1207 ksz_pread8(dev, port, P_MIRROR_CTRL, &data); 1208 1209 if (!dev->mirror_rx && !dev->mirror_tx) 1210 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1211 PORT_MIRROR_SNIFFER, false); 1212 } 1213 1214 static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port) 1215 { 1216 struct ksz_port *p = &dev->ports[port]; 1217 u8 data8; 1218 1219 if (!p->interface && dev->compat_interface) { 1220 dev_warn(dev->dev, 1221 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 1222 "Please update your device tree.\n", 1223 port); 1224 p->interface = dev->compat_interface; 1225 } 1226 1227 /* Configure MII interface for proper network communication. */ 1228 ksz_read8(dev, REG_PORT_5_CTRL_6, &data8); 1229 data8 &= ~PORT_INTERFACE_TYPE; 1230 data8 &= ~PORT_GMII_1GPS_MODE; 1231 switch (p->interface) { 1232 case PHY_INTERFACE_MODE_MII: 1233 p->phydev.speed = SPEED_100; 1234 break; 1235 case PHY_INTERFACE_MODE_RMII: 1236 data8 |= PORT_INTERFACE_RMII; 1237 p->phydev.speed = SPEED_100; 1238 break; 1239 case PHY_INTERFACE_MODE_GMII: 1240 data8 |= PORT_GMII_1GPS_MODE; 1241 data8 |= PORT_INTERFACE_GMII; 1242 p->phydev.speed = SPEED_1000; 1243 break; 1244 default: 1245 data8 &= ~PORT_RGMII_ID_IN_ENABLE; 1246 data8 &= ~PORT_RGMII_ID_OUT_ENABLE; 1247 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1248 p->interface == PHY_INTERFACE_MODE_RGMII_RXID) 1249 data8 |= PORT_RGMII_ID_IN_ENABLE; 1250 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1251 p->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1252 data8 |= PORT_RGMII_ID_OUT_ENABLE; 1253 data8 |= PORT_GMII_1GPS_MODE; 1254 data8 |= PORT_INTERFACE_RGMII; 1255 p->phydev.speed = SPEED_1000; 1256 break; 1257 } 1258 ksz_write8(dev, REG_PORT_5_CTRL_6, data8); 1259 p->phydev.duplex = 1; 1260 } 1261 1262 static void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1263 { 1264 struct ksz_port *p = &dev->ports[port]; 1265 struct ksz8 *ksz8 = dev->priv; 1266 const u32 *masks; 1267 u8 member; 1268 1269 masks = ksz8->masks; 1270 1271 /* enable broadcast storm limit */ 1272 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 1273 1274 if (!ksz_is_ksz88x3(dev)) 1275 ksz8795_set_prio_queue(dev, port, 4); 1276 1277 /* disable DiffServ priority */ 1278 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_ENABLE, false); 1279 1280 /* replace priority */ 1281 ksz_port_cfg(dev, port, P_802_1P_CTRL, 1282 masks[PORT_802_1P_REMAPPING], false); 1283 1284 /* enable 802.1p priority */ 1285 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_ENABLE, true); 1286 1287 if (cpu_port) { 1288 if (!ksz_is_ksz88x3(dev)) 1289 ksz8795_cpu_interface_select(dev, port); 1290 1291 member = dev->port_mask; 1292 } else { 1293 member = dev->host_mask | p->vid_member; 1294 } 1295 ksz8_cfg_port_member(dev, port, member); 1296 } 1297 1298 static void ksz8_config_cpu_port(struct dsa_switch *ds) 1299 { 1300 struct ksz_device *dev = ds->priv; 1301 struct ksz8 *ksz8 = dev->priv; 1302 const u8 *regs = ksz8->regs; 1303 struct ksz_port *p; 1304 const u32 *masks; 1305 u8 remote; 1306 int i; 1307 1308 masks = ksz8->masks; 1309 1310 /* Switch marks the maximum frame with extra byte as oversize. */ 1311 ksz_cfg(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, true); 1312 ksz_cfg(dev, regs[S_TAIL_TAG_CTRL], masks[SW_TAIL_TAG_ENABLE], true); 1313 1314 p = &dev->ports[dev->cpu_port]; 1315 p->vid_member = dev->port_mask; 1316 p->on = 1; 1317 1318 ksz8_port_setup(dev, dev->cpu_port, true); 1319 dev->member = dev->host_mask; 1320 1321 for (i = 0; i < dev->phy_port_cnt; i++) { 1322 p = &dev->ports[i]; 1323 1324 /* Initialize to non-zero so that ksz_cfg_port_member() will 1325 * be called. 1326 */ 1327 p->vid_member = BIT(i); 1328 p->member = dev->port_mask; 1329 ksz8_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1330 1331 /* Last port may be disabled. */ 1332 if (i == dev->phy_port_cnt) 1333 break; 1334 p->on = 1; 1335 p->phy = 1; 1336 } 1337 for (i = 0; i < dev->phy_port_cnt; i++) { 1338 p = &dev->ports[i]; 1339 if (!p->on) 1340 continue; 1341 if (!ksz_is_ksz88x3(dev)) { 1342 ksz_pread8(dev, i, regs[P_REMOTE_STATUS], &remote); 1343 if (remote & PORT_FIBER_MODE) 1344 p->fiber = 1; 1345 } 1346 if (p->fiber) 1347 ksz_port_cfg(dev, i, P_STP_CTRL, PORT_FORCE_FLOW_CTRL, 1348 true); 1349 else 1350 ksz_port_cfg(dev, i, P_STP_CTRL, PORT_FORCE_FLOW_CTRL, 1351 false); 1352 } 1353 } 1354 1355 static int ksz8_setup(struct dsa_switch *ds) 1356 { 1357 struct ksz_device *dev = ds->priv; 1358 struct alu_struct alu; 1359 int i, ret = 0; 1360 1361 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 1362 dev->num_vlans, GFP_KERNEL); 1363 if (!dev->vlan_cache) 1364 return -ENOMEM; 1365 1366 ret = ksz8_reset_switch(dev); 1367 if (ret) { 1368 dev_err(ds->dev, "failed to reset switch\n"); 1369 return ret; 1370 } 1371 1372 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_FLOW_CTRL, true); 1373 1374 /* Enable automatic fast aging when link changed detected. */ 1375 ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true); 1376 1377 /* Enable aggressive back off algorithm in half duplex mode. */ 1378 regmap_update_bits(dev->regmap[0], REG_SW_CTRL_1, 1379 SW_AGGR_BACKOFF, SW_AGGR_BACKOFF); 1380 1381 /* 1382 * Make sure unicast VLAN boundary is set as default and 1383 * enable no excessive collision drop. 1384 */ 1385 regmap_update_bits(dev->regmap[0], REG_SW_CTRL_2, 1386 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP, 1387 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP); 1388 1389 ksz8_config_cpu_port(ds); 1390 1391 ksz_cfg(dev, REG_SW_CTRL_2, MULTICAST_STORM_DISABLE, true); 1392 1393 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false); 1394 1395 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 1396 1397 /* set broadcast storm protection 10% rate */ 1398 regmap_update_bits(dev->regmap[1], S_REPLACE_VID_CTRL, 1399 BROADCAST_STORM_RATE, 1400 (BROADCAST_STORM_VALUE * 1401 BROADCAST_STORM_PROT_RATE) / 100); 1402 1403 for (i = 0; i < (dev->num_vlans / 4); i++) 1404 ksz8_r_vlan_entries(dev, i); 1405 1406 /* Setup STP address for STP operation. */ 1407 memset(&alu, 0, sizeof(alu)); 1408 ether_addr_copy(alu.mac, eth_stp_addr); 1409 alu.is_static = true; 1410 alu.is_override = true; 1411 alu.port_forward = dev->host_mask; 1412 1413 ksz8_w_sta_mac_table(dev, 0, &alu); 1414 1415 ksz_init_mib_timer(dev); 1416 1417 ds->configure_vlan_while_not_filtering = false; 1418 1419 return 0; 1420 } 1421 1422 static const struct dsa_switch_ops ksz8_switch_ops = { 1423 .get_tag_protocol = ksz8_get_tag_protocol, 1424 .setup = ksz8_setup, 1425 .phy_read = ksz_phy_read16, 1426 .phy_write = ksz_phy_write16, 1427 .phylink_mac_link_down = ksz_mac_link_down, 1428 .port_enable = ksz_enable_port, 1429 .get_strings = ksz8_get_strings, 1430 .get_ethtool_stats = ksz_get_ethtool_stats, 1431 .get_sset_count = ksz_sset_count, 1432 .port_bridge_join = ksz_port_bridge_join, 1433 .port_bridge_leave = ksz_port_bridge_leave, 1434 .port_stp_state_set = ksz8_port_stp_state_set, 1435 .port_fast_age = ksz_port_fast_age, 1436 .port_vlan_filtering = ksz8_port_vlan_filtering, 1437 .port_vlan_add = ksz8_port_vlan_add, 1438 .port_vlan_del = ksz8_port_vlan_del, 1439 .port_fdb_dump = ksz_port_fdb_dump, 1440 .port_mdb_add = ksz_port_mdb_add, 1441 .port_mdb_del = ksz_port_mdb_del, 1442 .port_mirror_add = ksz8_port_mirror_add, 1443 .port_mirror_del = ksz8_port_mirror_del, 1444 }; 1445 1446 static u32 ksz8_get_port_addr(int port, int offset) 1447 { 1448 return PORT_CTRL_ADDR(port, offset); 1449 } 1450 1451 static int ksz8_switch_detect(struct ksz_device *dev) 1452 { 1453 u8 id1, id2; 1454 u16 id16; 1455 int ret; 1456 1457 /* read chip id */ 1458 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 1459 if (ret) 1460 return ret; 1461 1462 id1 = id16 >> 8; 1463 id2 = id16 & SW_CHIP_ID_M; 1464 1465 switch (id1) { 1466 case KSZ87_FAMILY_ID: 1467 if ((id2 != CHIP_ID_94 && id2 != CHIP_ID_95)) 1468 return -ENODEV; 1469 1470 if (id2 == CHIP_ID_95) { 1471 u8 val; 1472 1473 id2 = 0x95; 1474 ksz_read8(dev, REG_PORT_STATUS_0, &val); 1475 if (val & PORT_FIBER_MODE) 1476 id2 = 0x65; 1477 } else if (id2 == CHIP_ID_94) { 1478 id2 = 0x94; 1479 } 1480 break; 1481 case KSZ88_FAMILY_ID: 1482 if (id2 != CHIP_ID_63) 1483 return -ENODEV; 1484 break; 1485 default: 1486 dev_err(dev->dev, "invalid family id: %d\n", id1); 1487 return -ENODEV; 1488 } 1489 id16 &= ~0xff; 1490 id16 |= id2; 1491 dev->chip_id = id16; 1492 1493 return 0; 1494 } 1495 1496 struct ksz_chip_data { 1497 u16 chip_id; 1498 const char *dev_name; 1499 int num_vlans; 1500 int num_alus; 1501 int num_statics; 1502 int cpu_ports; 1503 int port_cnt; 1504 }; 1505 1506 static const struct ksz_chip_data ksz8_switch_chips[] = { 1507 { 1508 .chip_id = 0x8795, 1509 .dev_name = "KSZ8795", 1510 .num_vlans = 4096, 1511 .num_alus = 0, 1512 .num_statics = 8, 1513 .cpu_ports = 0x10, /* can be configured as cpu port */ 1514 .port_cnt = 5, /* total cpu and user ports */ 1515 }, 1516 { 1517 /* 1518 * WARNING 1519 * ======= 1520 * KSZ8794 is similar to KSZ8795, except the port map 1521 * contains a gap between external and CPU ports, the 1522 * port map is NOT continuous. The per-port register 1523 * map is shifted accordingly too, i.e. registers at 1524 * offset 0x40 are NOT used on KSZ8794 and they ARE 1525 * used on KSZ8795 for external port 3. 1526 * external cpu 1527 * KSZ8794 0,1,2 4 1528 * KSZ8795 0,1,2,3 4 1529 * KSZ8765 0,1,2,3 4 1530 */ 1531 .chip_id = 0x8794, 1532 .dev_name = "KSZ8794", 1533 .num_vlans = 4096, 1534 .num_alus = 0, 1535 .num_statics = 8, 1536 .cpu_ports = 0x10, /* can be configured as cpu port */ 1537 .port_cnt = 4, /* total cpu and user ports */ 1538 }, 1539 { 1540 .chip_id = 0x8765, 1541 .dev_name = "KSZ8765", 1542 .num_vlans = 4096, 1543 .num_alus = 0, 1544 .num_statics = 8, 1545 .cpu_ports = 0x10, /* can be configured as cpu port */ 1546 .port_cnt = 5, /* total cpu and user ports */ 1547 }, 1548 { 1549 .chip_id = 0x8830, 1550 .dev_name = "KSZ8863/KSZ8873", 1551 .num_vlans = 16, 1552 .num_alus = 0, 1553 .num_statics = 8, 1554 .cpu_ports = 0x4, /* can be configured as cpu port */ 1555 .port_cnt = 3, 1556 }, 1557 }; 1558 1559 static int ksz8_switch_init(struct ksz_device *dev) 1560 { 1561 struct ksz8 *ksz8 = dev->priv; 1562 int i; 1563 1564 dev->ds->ops = &ksz8_switch_ops; 1565 1566 for (i = 0; i < ARRAY_SIZE(ksz8_switch_chips); i++) { 1567 const struct ksz_chip_data *chip = &ksz8_switch_chips[i]; 1568 1569 if (dev->chip_id == chip->chip_id) { 1570 dev->name = chip->dev_name; 1571 dev->num_vlans = chip->num_vlans; 1572 dev->num_alus = chip->num_alus; 1573 dev->num_statics = chip->num_statics; 1574 dev->port_cnt = fls(chip->cpu_ports); 1575 dev->cpu_port = fls(chip->cpu_ports) - 1; 1576 dev->phy_port_cnt = dev->port_cnt - 1; 1577 dev->cpu_ports = chip->cpu_ports; 1578 dev->host_mask = chip->cpu_ports; 1579 dev->port_mask = (BIT(dev->phy_port_cnt) - 1) | 1580 chip->cpu_ports; 1581 break; 1582 } 1583 } 1584 1585 /* no switch found */ 1586 if (!dev->cpu_ports) 1587 return -ENODEV; 1588 1589 if (ksz_is_ksz88x3(dev)) { 1590 ksz8->regs = ksz8863_regs; 1591 ksz8->masks = ksz8863_masks; 1592 ksz8->shifts = ksz8863_shifts; 1593 dev->mib_cnt = ARRAY_SIZE(ksz88xx_mib_names); 1594 dev->mib_names = ksz88xx_mib_names; 1595 } else { 1596 ksz8->regs = ksz8795_regs; 1597 ksz8->masks = ksz8795_masks; 1598 ksz8->shifts = ksz8795_shifts; 1599 dev->mib_cnt = ARRAY_SIZE(ksz87xx_mib_names); 1600 dev->mib_names = ksz87xx_mib_names; 1601 } 1602 1603 dev->reg_mib_cnt = MIB_COUNTER_NUM; 1604 1605 dev->ports = devm_kzalloc(dev->dev, 1606 dev->port_cnt * sizeof(struct ksz_port), 1607 GFP_KERNEL); 1608 if (!dev->ports) 1609 return -ENOMEM; 1610 for (i = 0; i < dev->port_cnt; i++) { 1611 mutex_init(&dev->ports[i].mib.cnt_mutex); 1612 dev->ports[i].mib.counters = 1613 devm_kzalloc(dev->dev, 1614 sizeof(u64) * 1615 (dev->mib_cnt + 1), 1616 GFP_KERNEL); 1617 if (!dev->ports[i].mib.counters) 1618 return -ENOMEM; 1619 } 1620 1621 /* set the real number of ports */ 1622 dev->ds->num_ports = dev->port_cnt; 1623 1624 return 0; 1625 } 1626 1627 static void ksz8_switch_exit(struct ksz_device *dev) 1628 { 1629 ksz8_reset_switch(dev); 1630 } 1631 1632 static const struct ksz_dev_ops ksz8_dev_ops = { 1633 .get_port_addr = ksz8_get_port_addr, 1634 .cfg_port_member = ksz8_cfg_port_member, 1635 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 1636 .port_setup = ksz8_port_setup, 1637 .r_phy = ksz8_r_phy, 1638 .w_phy = ksz8_w_phy, 1639 .r_dyn_mac_table = ksz8_r_dyn_mac_table, 1640 .r_sta_mac_table = ksz8_r_sta_mac_table, 1641 .w_sta_mac_table = ksz8_w_sta_mac_table, 1642 .r_mib_cnt = ksz8_r_mib_cnt, 1643 .r_mib_pkt = ksz8_r_mib_pkt, 1644 .freeze_mib = ksz8_freeze_mib, 1645 .port_init_cnt = ksz8_port_init_cnt, 1646 .shutdown = ksz8_reset_switch, 1647 .detect = ksz8_switch_detect, 1648 .init = ksz8_switch_init, 1649 .exit = ksz8_switch_exit, 1650 }; 1651 1652 int ksz8_switch_register(struct ksz_device *dev) 1653 { 1654 return ksz_switch_register(dev, &ksz8_dev_ops); 1655 } 1656 EXPORT_SYMBOL(ksz8_switch_register); 1657 1658 MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>"); 1659 MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch DSA Driver"); 1660 MODULE_LICENSE("GPL"); 1661