1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ8795 switch driver 4 * 5 * Copyright (C) 2017 Microchip Technology Inc. 6 * Tristram Ha <Tristram.Ha@microchip.com> 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/delay.h> 11 #include <linux/export.h> 12 #include <linux/gpio.h> 13 #include <linux/if_vlan.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/platform_data/microchip-ksz.h> 17 #include <linux/phy.h> 18 #include <linux/etherdevice.h> 19 #include <linux/if_bridge.h> 20 #include <linux/micrel_phy.h> 21 #include <net/dsa.h> 22 #include <net/switchdev.h> 23 #include <linux/phylink.h> 24 25 #include "ksz_common.h" 26 #include "ksz8795_reg.h" 27 #include "ksz8.h" 28 29 static bool ksz_is_ksz88x3(struct ksz_device *dev) 30 { 31 return dev->chip_id == 0x8830; 32 } 33 34 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 35 { 36 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0); 37 } 38 39 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 40 bool set) 41 { 42 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset), 43 bits, set ? bits : 0); 44 } 45 46 static int ksz8_ind_write8(struct ksz_device *dev, u8 table, u16 addr, u8 data) 47 { 48 const u16 *regs; 49 u16 ctrl_addr; 50 int ret = 0; 51 52 regs = dev->info->regs; 53 54 mutex_lock(&dev->alu_mutex); 55 56 ctrl_addr = IND_ACC_TABLE(table) | addr; 57 ret = ksz_write8(dev, regs[REG_IND_BYTE], data); 58 if (!ret) 59 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 60 61 mutex_unlock(&dev->alu_mutex); 62 63 return ret; 64 } 65 66 int ksz8_reset_switch(struct ksz_device *dev) 67 { 68 if (ksz_is_ksz88x3(dev)) { 69 /* reset switch */ 70 ksz_cfg(dev, KSZ8863_REG_SW_RESET, 71 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, true); 72 ksz_cfg(dev, KSZ8863_REG_SW_RESET, 73 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, false); 74 } else { 75 /* reset switch */ 76 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 77 SW_SOFTWARE_POWER_DOWN << SW_POWER_MANAGEMENT_MODE_S); 78 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 0); 79 } 80 81 return 0; 82 } 83 84 static void ksz8795_set_prio_queue(struct ksz_device *dev, int port, int queue) 85 { 86 u8 hi, lo; 87 88 /* Number of queues can only be 1, 2, or 4. */ 89 switch (queue) { 90 case 4: 91 case 3: 92 queue = PORT_QUEUE_SPLIT_4; 93 break; 94 case 2: 95 queue = PORT_QUEUE_SPLIT_2; 96 break; 97 default: 98 queue = PORT_QUEUE_SPLIT_1; 99 } 100 ksz_pread8(dev, port, REG_PORT_CTRL_0, &lo); 101 ksz_pread8(dev, port, P_DROP_TAG_CTRL, &hi); 102 lo &= ~PORT_QUEUE_SPLIT_L; 103 if (queue & PORT_QUEUE_SPLIT_2) 104 lo |= PORT_QUEUE_SPLIT_L; 105 hi &= ~PORT_QUEUE_SPLIT_H; 106 if (queue & PORT_QUEUE_SPLIT_4) 107 hi |= PORT_QUEUE_SPLIT_H; 108 ksz_pwrite8(dev, port, REG_PORT_CTRL_0, lo); 109 ksz_pwrite8(dev, port, P_DROP_TAG_CTRL, hi); 110 111 /* Default is port based for egress rate limit. */ 112 if (queue != PORT_QUEUE_SPLIT_1) 113 ksz_cfg(dev, REG_SW_CTRL_19, SW_OUT_RATE_LIMIT_QUEUE_BASED, 114 true); 115 } 116 117 void ksz8_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt) 118 { 119 const u32 *masks; 120 const u16 *regs; 121 u16 ctrl_addr; 122 u32 data; 123 u8 check; 124 int loop; 125 126 masks = dev->info->masks; 127 regs = dev->info->regs; 128 129 ctrl_addr = addr + dev->info->reg_mib_cnt * port; 130 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 131 132 mutex_lock(&dev->alu_mutex); 133 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 134 135 /* It is almost guaranteed to always read the valid bit because of 136 * slow SPI speed. 137 */ 138 for (loop = 2; loop > 0; loop--) { 139 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check); 140 141 if (check & masks[MIB_COUNTER_VALID]) { 142 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 143 if (check & masks[MIB_COUNTER_OVERFLOW]) 144 *cnt += MIB_COUNTER_VALUE + 1; 145 *cnt += data & MIB_COUNTER_VALUE; 146 break; 147 } 148 } 149 mutex_unlock(&dev->alu_mutex); 150 } 151 152 static void ksz8795_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 153 u64 *dropped, u64 *cnt) 154 { 155 const u32 *masks; 156 const u16 *regs; 157 u16 ctrl_addr; 158 u32 data; 159 u8 check; 160 int loop; 161 162 masks = dev->info->masks; 163 regs = dev->info->regs; 164 165 addr -= dev->info->reg_mib_cnt; 166 ctrl_addr = (KSZ8795_MIB_TOTAL_RX_1 - KSZ8795_MIB_TOTAL_RX_0) * port; 167 ctrl_addr += addr + KSZ8795_MIB_TOTAL_RX_0; 168 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 169 170 mutex_lock(&dev->alu_mutex); 171 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 172 173 /* It is almost guaranteed to always read the valid bit because of 174 * slow SPI speed. 175 */ 176 for (loop = 2; loop > 0; loop--) { 177 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check); 178 179 if (check & masks[MIB_COUNTER_VALID]) { 180 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 181 if (addr < 2) { 182 u64 total; 183 184 total = check & MIB_TOTAL_BYTES_H; 185 total <<= 32; 186 *cnt += total; 187 *cnt += data; 188 if (check & masks[MIB_COUNTER_OVERFLOW]) { 189 total = MIB_TOTAL_BYTES_H + 1; 190 total <<= 32; 191 *cnt += total; 192 } 193 } else { 194 if (check & masks[MIB_COUNTER_OVERFLOW]) 195 *cnt += MIB_PACKET_DROPPED + 1; 196 *cnt += data & MIB_PACKET_DROPPED; 197 } 198 break; 199 } 200 } 201 mutex_unlock(&dev->alu_mutex); 202 } 203 204 static void ksz8863_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 205 u64 *dropped, u64 *cnt) 206 { 207 u32 *last = (u32 *)dropped; 208 const u16 *regs; 209 u16 ctrl_addr; 210 u32 data; 211 u32 cur; 212 213 regs = dev->info->regs; 214 215 addr -= dev->info->reg_mib_cnt; 216 ctrl_addr = addr ? KSZ8863_MIB_PACKET_DROPPED_TX_0 : 217 KSZ8863_MIB_PACKET_DROPPED_RX_0; 218 ctrl_addr += port; 219 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 220 221 mutex_lock(&dev->alu_mutex); 222 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 223 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 224 mutex_unlock(&dev->alu_mutex); 225 226 data &= MIB_PACKET_DROPPED; 227 cur = last[addr]; 228 if (data != cur) { 229 last[addr] = data; 230 if (data < cur) 231 data += MIB_PACKET_DROPPED + 1; 232 data -= cur; 233 *cnt += data; 234 } 235 } 236 237 void ksz8_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 238 u64 *dropped, u64 *cnt) 239 { 240 if (ksz_is_ksz88x3(dev)) 241 ksz8863_r_mib_pkt(dev, port, addr, dropped, cnt); 242 else 243 ksz8795_r_mib_pkt(dev, port, addr, dropped, cnt); 244 } 245 246 void ksz8_freeze_mib(struct ksz_device *dev, int port, bool freeze) 247 { 248 if (ksz_is_ksz88x3(dev)) 249 return; 250 251 /* enable the port for flush/freeze function */ 252 if (freeze) 253 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true); 254 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FREEZE, freeze); 255 256 /* disable the port after freeze is done */ 257 if (!freeze) 258 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false); 259 } 260 261 void ksz8_port_init_cnt(struct ksz_device *dev, int port) 262 { 263 struct ksz_port_mib *mib = &dev->ports[port].mib; 264 u64 *dropped; 265 266 if (!ksz_is_ksz88x3(dev)) { 267 /* flush all enabled port MIB counters */ 268 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true); 269 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FLUSH, true); 270 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false); 271 } 272 273 mib->cnt_ptr = 0; 274 275 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 276 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 277 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 278 &mib->counters[mib->cnt_ptr]); 279 ++mib->cnt_ptr; 280 } 281 282 /* last one in storage */ 283 dropped = &mib->counters[dev->info->mib_cnt]; 284 285 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 286 while (mib->cnt_ptr < dev->info->mib_cnt) { 287 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 288 dropped, &mib->counters[mib->cnt_ptr]); 289 ++mib->cnt_ptr; 290 } 291 } 292 293 static void ksz8_r_table(struct ksz_device *dev, int table, u16 addr, u64 *data) 294 { 295 const u16 *regs; 296 u16 ctrl_addr; 297 298 regs = dev->info->regs; 299 300 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr; 301 302 mutex_lock(&dev->alu_mutex); 303 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 304 ksz_read64(dev, regs[REG_IND_DATA_HI], data); 305 mutex_unlock(&dev->alu_mutex); 306 } 307 308 static void ksz8_w_table(struct ksz_device *dev, int table, u16 addr, u64 data) 309 { 310 const u16 *regs; 311 u16 ctrl_addr; 312 313 regs = dev->info->regs; 314 315 ctrl_addr = IND_ACC_TABLE(table) | addr; 316 317 mutex_lock(&dev->alu_mutex); 318 ksz_write64(dev, regs[REG_IND_DATA_HI], data); 319 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 320 mutex_unlock(&dev->alu_mutex); 321 } 322 323 static int ksz8_valid_dyn_entry(struct ksz_device *dev, u8 *data) 324 { 325 int timeout = 100; 326 const u32 *masks; 327 const u16 *regs; 328 329 masks = dev->info->masks; 330 regs = dev->info->regs; 331 332 do { 333 ksz_read8(dev, regs[REG_IND_DATA_CHECK], data); 334 timeout--; 335 } while ((*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) && timeout); 336 337 /* Entry is not ready for accessing. */ 338 if (*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) { 339 return -EAGAIN; 340 /* Entry is ready for accessing. */ 341 } else { 342 ksz_read8(dev, regs[REG_IND_DATA_8], data); 343 344 /* There is no valid entry in the table. */ 345 if (*data & masks[DYNAMIC_MAC_TABLE_MAC_EMPTY]) 346 return -ENXIO; 347 } 348 return 0; 349 } 350 351 int ksz8_r_dyn_mac_table(struct ksz_device *dev, u16 addr, u8 *mac_addr, 352 u8 *fid, u8 *src_port, u8 *timestamp, u16 *entries) 353 { 354 u32 data_hi, data_lo; 355 const u8 *shifts; 356 const u32 *masks; 357 const u16 *regs; 358 u16 ctrl_addr; 359 u8 data; 360 int rc; 361 362 shifts = dev->info->shifts; 363 masks = dev->info->masks; 364 regs = dev->info->regs; 365 366 ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr; 367 368 mutex_lock(&dev->alu_mutex); 369 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 370 371 rc = ksz8_valid_dyn_entry(dev, &data); 372 if (rc == -EAGAIN) { 373 if (addr == 0) 374 *entries = 0; 375 } else if (rc == -ENXIO) { 376 *entries = 0; 377 /* At least one valid entry in the table. */ 378 } else { 379 u64 buf = 0; 380 int cnt; 381 382 ksz_read64(dev, regs[REG_IND_DATA_HI], &buf); 383 data_hi = (u32)(buf >> 32); 384 data_lo = (u32)buf; 385 386 /* Check out how many valid entry in the table. */ 387 cnt = data & masks[DYNAMIC_MAC_TABLE_ENTRIES_H]; 388 cnt <<= shifts[DYNAMIC_MAC_ENTRIES_H]; 389 cnt |= (data_hi & masks[DYNAMIC_MAC_TABLE_ENTRIES]) >> 390 shifts[DYNAMIC_MAC_ENTRIES]; 391 *entries = cnt + 1; 392 393 *fid = (data_hi & masks[DYNAMIC_MAC_TABLE_FID]) >> 394 shifts[DYNAMIC_MAC_FID]; 395 *src_port = (data_hi & masks[DYNAMIC_MAC_TABLE_SRC_PORT]) >> 396 shifts[DYNAMIC_MAC_SRC_PORT]; 397 *timestamp = (data_hi & masks[DYNAMIC_MAC_TABLE_TIMESTAMP]) >> 398 shifts[DYNAMIC_MAC_TIMESTAMP]; 399 400 mac_addr[5] = (u8)data_lo; 401 mac_addr[4] = (u8)(data_lo >> 8); 402 mac_addr[3] = (u8)(data_lo >> 16); 403 mac_addr[2] = (u8)(data_lo >> 24); 404 405 mac_addr[1] = (u8)data_hi; 406 mac_addr[0] = (u8)(data_hi >> 8); 407 rc = 0; 408 } 409 mutex_unlock(&dev->alu_mutex); 410 411 return rc; 412 } 413 414 int ksz8_r_sta_mac_table(struct ksz_device *dev, u16 addr, 415 struct alu_struct *alu) 416 { 417 u32 data_hi, data_lo; 418 const u8 *shifts; 419 const u32 *masks; 420 u64 data; 421 422 shifts = dev->info->shifts; 423 masks = dev->info->masks; 424 425 ksz8_r_table(dev, TABLE_STATIC_MAC, addr, &data); 426 data_hi = data >> 32; 427 data_lo = (u32)data; 428 if (data_hi & (masks[STATIC_MAC_TABLE_VALID] | 429 masks[STATIC_MAC_TABLE_OVERRIDE])) { 430 alu->mac[5] = (u8)data_lo; 431 alu->mac[4] = (u8)(data_lo >> 8); 432 alu->mac[3] = (u8)(data_lo >> 16); 433 alu->mac[2] = (u8)(data_lo >> 24); 434 alu->mac[1] = (u8)data_hi; 435 alu->mac[0] = (u8)(data_hi >> 8); 436 alu->port_forward = 437 (data_hi & masks[STATIC_MAC_TABLE_FWD_PORTS]) >> 438 shifts[STATIC_MAC_FWD_PORTS]; 439 alu->is_override = 440 (data_hi & masks[STATIC_MAC_TABLE_OVERRIDE]) ? 1 : 0; 441 data_hi >>= 1; 442 alu->is_static = true; 443 alu->is_use_fid = 444 (data_hi & masks[STATIC_MAC_TABLE_USE_FID]) ? 1 : 0; 445 alu->fid = (data_hi & masks[STATIC_MAC_TABLE_FID]) >> 446 shifts[STATIC_MAC_FID]; 447 return 0; 448 } 449 return -ENXIO; 450 } 451 452 void ksz8_w_sta_mac_table(struct ksz_device *dev, u16 addr, 453 struct alu_struct *alu) 454 { 455 u32 data_hi, data_lo; 456 const u8 *shifts; 457 const u32 *masks; 458 u64 data; 459 460 shifts = dev->info->shifts; 461 masks = dev->info->masks; 462 463 data_lo = ((u32)alu->mac[2] << 24) | 464 ((u32)alu->mac[3] << 16) | 465 ((u32)alu->mac[4] << 8) | alu->mac[5]; 466 data_hi = ((u32)alu->mac[0] << 8) | alu->mac[1]; 467 data_hi |= (u32)alu->port_forward << shifts[STATIC_MAC_FWD_PORTS]; 468 469 if (alu->is_override) 470 data_hi |= masks[STATIC_MAC_TABLE_OVERRIDE]; 471 if (alu->is_use_fid) { 472 data_hi |= masks[STATIC_MAC_TABLE_USE_FID]; 473 data_hi |= (u32)alu->fid << shifts[STATIC_MAC_FID]; 474 } 475 if (alu->is_static) 476 data_hi |= masks[STATIC_MAC_TABLE_VALID]; 477 else 478 data_hi &= ~masks[STATIC_MAC_TABLE_OVERRIDE]; 479 480 data = (u64)data_hi << 32 | data_lo; 481 ksz8_w_table(dev, TABLE_STATIC_MAC, addr, data); 482 } 483 484 static void ksz8_from_vlan(struct ksz_device *dev, u32 vlan, u8 *fid, 485 u8 *member, u8 *valid) 486 { 487 const u8 *shifts; 488 const u32 *masks; 489 490 shifts = dev->info->shifts; 491 masks = dev->info->masks; 492 493 *fid = vlan & masks[VLAN_TABLE_FID]; 494 *member = (vlan & masks[VLAN_TABLE_MEMBERSHIP]) >> 495 shifts[VLAN_TABLE_MEMBERSHIP_S]; 496 *valid = !!(vlan & masks[VLAN_TABLE_VALID]); 497 } 498 499 static void ksz8_to_vlan(struct ksz_device *dev, u8 fid, u8 member, u8 valid, 500 u16 *vlan) 501 { 502 const u8 *shifts; 503 const u32 *masks; 504 505 shifts = dev->info->shifts; 506 masks = dev->info->masks; 507 508 *vlan = fid; 509 *vlan |= (u16)member << shifts[VLAN_TABLE_MEMBERSHIP_S]; 510 if (valid) 511 *vlan |= masks[VLAN_TABLE_VALID]; 512 } 513 514 static void ksz8_r_vlan_entries(struct ksz_device *dev, u16 addr) 515 { 516 const u8 *shifts; 517 u64 data; 518 int i; 519 520 shifts = dev->info->shifts; 521 522 ksz8_r_table(dev, TABLE_VLAN, addr, &data); 523 addr *= 4; 524 for (i = 0; i < 4; i++) { 525 dev->vlan_cache[addr + i].table[0] = (u16)data; 526 data >>= shifts[VLAN_TABLE]; 527 } 528 } 529 530 static void ksz8_r_vlan_table(struct ksz_device *dev, u16 vid, u16 *vlan) 531 { 532 int index; 533 u16 *data; 534 u16 addr; 535 u64 buf; 536 537 data = (u16 *)&buf; 538 addr = vid / 4; 539 index = vid & 3; 540 ksz8_r_table(dev, TABLE_VLAN, addr, &buf); 541 *vlan = data[index]; 542 } 543 544 static void ksz8_w_vlan_table(struct ksz_device *dev, u16 vid, u16 vlan) 545 { 546 int index; 547 u16 *data; 548 u16 addr; 549 u64 buf; 550 551 data = (u16 *)&buf; 552 addr = vid / 4; 553 index = vid & 3; 554 ksz8_r_table(dev, TABLE_VLAN, addr, &buf); 555 data[index] = vlan; 556 dev->vlan_cache[vid].table[0] = vlan; 557 ksz8_w_table(dev, TABLE_VLAN, addr, buf); 558 } 559 560 void ksz8_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val) 561 { 562 u8 restart, speed, ctrl, link; 563 int processed = true; 564 const u16 *regs; 565 u8 val1, val2; 566 u16 data = 0; 567 u8 p = phy; 568 569 regs = dev->info->regs; 570 571 switch (reg) { 572 case MII_BMCR: 573 ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart); 574 ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed); 575 ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl); 576 if (restart & PORT_PHY_LOOPBACK) 577 data |= BMCR_LOOPBACK; 578 if (ctrl & PORT_FORCE_100_MBIT) 579 data |= BMCR_SPEED100; 580 if (ksz_is_ksz88x3(dev)) { 581 if ((ctrl & PORT_AUTO_NEG_ENABLE)) 582 data |= BMCR_ANENABLE; 583 } else { 584 if (!(ctrl & PORT_AUTO_NEG_DISABLE)) 585 data |= BMCR_ANENABLE; 586 } 587 if (restart & PORT_POWER_DOWN) 588 data |= BMCR_PDOWN; 589 if (restart & PORT_AUTO_NEG_RESTART) 590 data |= BMCR_ANRESTART; 591 if (ctrl & PORT_FORCE_FULL_DUPLEX) 592 data |= BMCR_FULLDPLX; 593 if (speed & PORT_HP_MDIX) 594 data |= KSZ886X_BMCR_HP_MDIX; 595 if (restart & PORT_FORCE_MDIX) 596 data |= KSZ886X_BMCR_FORCE_MDI; 597 if (restart & PORT_AUTO_MDIX_DISABLE) 598 data |= KSZ886X_BMCR_DISABLE_AUTO_MDIX; 599 if (restart & PORT_TX_DISABLE) 600 data |= KSZ886X_BMCR_DISABLE_TRANSMIT; 601 if (restart & PORT_LED_OFF) 602 data |= KSZ886X_BMCR_DISABLE_LED; 603 break; 604 case MII_BMSR: 605 ksz_pread8(dev, p, regs[P_LINK_STATUS], &link); 606 data = BMSR_100FULL | 607 BMSR_100HALF | 608 BMSR_10FULL | 609 BMSR_10HALF | 610 BMSR_ANEGCAPABLE; 611 if (link & PORT_AUTO_NEG_COMPLETE) 612 data |= BMSR_ANEGCOMPLETE; 613 if (link & PORT_STAT_LINK_GOOD) 614 data |= BMSR_LSTATUS; 615 break; 616 case MII_PHYSID1: 617 data = KSZ8795_ID_HI; 618 break; 619 case MII_PHYSID2: 620 if (ksz_is_ksz88x3(dev)) 621 data = KSZ8863_ID_LO; 622 else 623 data = KSZ8795_ID_LO; 624 break; 625 case MII_ADVERTISE: 626 ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl); 627 data = ADVERTISE_CSMA; 628 if (ctrl & PORT_AUTO_NEG_SYM_PAUSE) 629 data |= ADVERTISE_PAUSE_CAP; 630 if (ctrl & PORT_AUTO_NEG_100BTX_FD) 631 data |= ADVERTISE_100FULL; 632 if (ctrl & PORT_AUTO_NEG_100BTX) 633 data |= ADVERTISE_100HALF; 634 if (ctrl & PORT_AUTO_NEG_10BT_FD) 635 data |= ADVERTISE_10FULL; 636 if (ctrl & PORT_AUTO_NEG_10BT) 637 data |= ADVERTISE_10HALF; 638 break; 639 case MII_LPA: 640 ksz_pread8(dev, p, regs[P_REMOTE_STATUS], &link); 641 data = LPA_SLCT; 642 if (link & PORT_REMOTE_SYM_PAUSE) 643 data |= LPA_PAUSE_CAP; 644 if (link & PORT_REMOTE_100BTX_FD) 645 data |= LPA_100FULL; 646 if (link & PORT_REMOTE_100BTX) 647 data |= LPA_100HALF; 648 if (link & PORT_REMOTE_10BT_FD) 649 data |= LPA_10FULL; 650 if (link & PORT_REMOTE_10BT) 651 data |= LPA_10HALF; 652 if (data & ~LPA_SLCT) 653 data |= LPA_LPACK; 654 break; 655 case PHY_REG_LINK_MD: 656 ksz_pread8(dev, p, REG_PORT_LINK_MD_CTRL, &val1); 657 ksz_pread8(dev, p, REG_PORT_LINK_MD_RESULT, &val2); 658 if (val1 & PORT_START_CABLE_DIAG) 659 data |= PHY_START_CABLE_DIAG; 660 661 if (val1 & PORT_CABLE_10M_SHORT) 662 data |= PHY_CABLE_10M_SHORT; 663 664 data |= FIELD_PREP(PHY_CABLE_DIAG_RESULT_M, 665 FIELD_GET(PORT_CABLE_DIAG_RESULT_M, val1)); 666 667 data |= FIELD_PREP(PHY_CABLE_FAULT_COUNTER_M, 668 (FIELD_GET(PORT_CABLE_FAULT_COUNTER_H, val1) << 8) | 669 FIELD_GET(PORT_CABLE_FAULT_COUNTER_L, val2)); 670 break; 671 case PHY_REG_PHY_CTRL: 672 ksz_pread8(dev, p, regs[P_LINK_STATUS], &link); 673 if (link & PORT_MDIX_STATUS) 674 data |= KSZ886X_CTRL_MDIX_STAT; 675 break; 676 default: 677 processed = false; 678 break; 679 } 680 if (processed) 681 *val = data; 682 } 683 684 void ksz8_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val) 685 { 686 u8 restart, speed, ctrl, data; 687 const u16 *regs; 688 u8 p = phy; 689 690 regs = dev->info->regs; 691 692 switch (reg) { 693 case MII_BMCR: 694 695 /* Do not support PHY reset function. */ 696 if (val & BMCR_RESET) 697 break; 698 ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed); 699 data = speed; 700 if (val & KSZ886X_BMCR_HP_MDIX) 701 data |= PORT_HP_MDIX; 702 else 703 data &= ~PORT_HP_MDIX; 704 if (data != speed) 705 ksz_pwrite8(dev, p, regs[P_SPEED_STATUS], data); 706 ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl); 707 data = ctrl; 708 if (ksz_is_ksz88x3(dev)) { 709 if ((val & BMCR_ANENABLE)) 710 data |= PORT_AUTO_NEG_ENABLE; 711 else 712 data &= ~PORT_AUTO_NEG_ENABLE; 713 } else { 714 if (!(val & BMCR_ANENABLE)) 715 data |= PORT_AUTO_NEG_DISABLE; 716 else 717 data &= ~PORT_AUTO_NEG_DISABLE; 718 719 /* Fiber port does not support auto-negotiation. */ 720 if (dev->ports[p].fiber) 721 data |= PORT_AUTO_NEG_DISABLE; 722 } 723 724 if (val & BMCR_SPEED100) 725 data |= PORT_FORCE_100_MBIT; 726 else 727 data &= ~PORT_FORCE_100_MBIT; 728 if (val & BMCR_FULLDPLX) 729 data |= PORT_FORCE_FULL_DUPLEX; 730 else 731 data &= ~PORT_FORCE_FULL_DUPLEX; 732 if (data != ctrl) 733 ksz_pwrite8(dev, p, regs[P_FORCE_CTRL], data); 734 ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart); 735 data = restart; 736 if (val & KSZ886X_BMCR_DISABLE_LED) 737 data |= PORT_LED_OFF; 738 else 739 data &= ~PORT_LED_OFF; 740 if (val & KSZ886X_BMCR_DISABLE_TRANSMIT) 741 data |= PORT_TX_DISABLE; 742 else 743 data &= ~PORT_TX_DISABLE; 744 if (val & BMCR_ANRESTART) 745 data |= PORT_AUTO_NEG_RESTART; 746 else 747 data &= ~(PORT_AUTO_NEG_RESTART); 748 if (val & BMCR_PDOWN) 749 data |= PORT_POWER_DOWN; 750 else 751 data &= ~PORT_POWER_DOWN; 752 if (val & KSZ886X_BMCR_DISABLE_AUTO_MDIX) 753 data |= PORT_AUTO_MDIX_DISABLE; 754 else 755 data &= ~PORT_AUTO_MDIX_DISABLE; 756 if (val & KSZ886X_BMCR_FORCE_MDI) 757 data |= PORT_FORCE_MDIX; 758 else 759 data &= ~PORT_FORCE_MDIX; 760 if (val & BMCR_LOOPBACK) 761 data |= PORT_PHY_LOOPBACK; 762 else 763 data &= ~PORT_PHY_LOOPBACK; 764 if (data != restart) 765 ksz_pwrite8(dev, p, regs[P_NEG_RESTART_CTRL], data); 766 break; 767 case MII_ADVERTISE: 768 ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl); 769 data = ctrl; 770 data &= ~(PORT_AUTO_NEG_SYM_PAUSE | 771 PORT_AUTO_NEG_100BTX_FD | 772 PORT_AUTO_NEG_100BTX | 773 PORT_AUTO_NEG_10BT_FD | 774 PORT_AUTO_NEG_10BT); 775 if (val & ADVERTISE_PAUSE_CAP) 776 data |= PORT_AUTO_NEG_SYM_PAUSE; 777 if (val & ADVERTISE_100FULL) 778 data |= PORT_AUTO_NEG_100BTX_FD; 779 if (val & ADVERTISE_100HALF) 780 data |= PORT_AUTO_NEG_100BTX; 781 if (val & ADVERTISE_10FULL) 782 data |= PORT_AUTO_NEG_10BT_FD; 783 if (val & ADVERTISE_10HALF) 784 data |= PORT_AUTO_NEG_10BT; 785 if (data != ctrl) 786 ksz_pwrite8(dev, p, regs[P_LOCAL_CTRL], data); 787 break; 788 case PHY_REG_LINK_MD: 789 if (val & PHY_START_CABLE_DIAG) 790 ksz_port_cfg(dev, p, REG_PORT_LINK_MD_CTRL, PORT_START_CABLE_DIAG, true); 791 break; 792 default: 793 break; 794 } 795 } 796 797 void ksz8_cfg_port_member(struct ksz_device *dev, int port, u8 member) 798 { 799 u8 data; 800 801 ksz_pread8(dev, port, P_MIRROR_CTRL, &data); 802 data &= ~PORT_VLAN_MEMBERSHIP; 803 data |= (member & dev->port_mask); 804 ksz_pwrite8(dev, port, P_MIRROR_CTRL, data); 805 } 806 807 void ksz8_flush_dyn_mac_table(struct ksz_device *dev, int port) 808 { 809 u8 learn[DSA_MAX_PORTS]; 810 int first, index, cnt; 811 struct ksz_port *p; 812 const u16 *regs; 813 814 regs = dev->info->regs; 815 816 if ((uint)port < dev->info->port_cnt) { 817 first = port; 818 cnt = port + 1; 819 } else { 820 /* Flush all ports. */ 821 first = 0; 822 cnt = dev->info->port_cnt; 823 } 824 for (index = first; index < cnt; index++) { 825 p = &dev->ports[index]; 826 if (!p->on) 827 continue; 828 ksz_pread8(dev, index, regs[P_STP_CTRL], &learn[index]); 829 if (!(learn[index] & PORT_LEARN_DISABLE)) 830 ksz_pwrite8(dev, index, regs[P_STP_CTRL], 831 learn[index] | PORT_LEARN_DISABLE); 832 } 833 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 834 for (index = first; index < cnt; index++) { 835 p = &dev->ports[index]; 836 if (!p->on) 837 continue; 838 if (!(learn[index] & PORT_LEARN_DISABLE)) 839 ksz_pwrite8(dev, index, regs[P_STP_CTRL], learn[index]); 840 } 841 } 842 843 int ksz8_fdb_dump(struct ksz_device *dev, int port, 844 dsa_fdb_dump_cb_t *cb, void *data) 845 { 846 int ret = 0; 847 u16 i = 0; 848 u16 entries = 0; 849 u8 timestamp = 0; 850 u8 fid; 851 u8 member; 852 struct alu_struct alu; 853 854 do { 855 alu.is_static = false; 856 ret = ksz8_r_dyn_mac_table(dev, i, alu.mac, &fid, &member, 857 ×tamp, &entries); 858 if (!ret && (member & BIT(port))) { 859 ret = cb(alu.mac, alu.fid, alu.is_static, data); 860 if (ret) 861 break; 862 } 863 i++; 864 } while (i < entries); 865 if (i >= entries) 866 ret = 0; 867 868 return ret; 869 } 870 871 int ksz8_mdb_add(struct ksz_device *dev, int port, 872 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 873 { 874 struct alu_struct alu; 875 int index; 876 int empty = 0; 877 878 alu.port_forward = 0; 879 for (index = 0; index < dev->info->num_statics; index++) { 880 if (!ksz8_r_sta_mac_table(dev, index, &alu)) { 881 /* Found one already in static MAC table. */ 882 if (!memcmp(alu.mac, mdb->addr, ETH_ALEN) && 883 alu.fid == mdb->vid) 884 break; 885 /* Remember the first empty entry. */ 886 } else if (!empty) { 887 empty = index + 1; 888 } 889 } 890 891 /* no available entry */ 892 if (index == dev->info->num_statics && !empty) 893 return -ENOSPC; 894 895 /* add entry */ 896 if (index == dev->info->num_statics) { 897 index = empty - 1; 898 memset(&alu, 0, sizeof(alu)); 899 memcpy(alu.mac, mdb->addr, ETH_ALEN); 900 alu.is_static = true; 901 } 902 alu.port_forward |= BIT(port); 903 if (mdb->vid) { 904 alu.is_use_fid = true; 905 906 /* Need a way to map VID to FID. */ 907 alu.fid = mdb->vid; 908 } 909 ksz8_w_sta_mac_table(dev, index, &alu); 910 911 return 0; 912 } 913 914 int ksz8_mdb_del(struct ksz_device *dev, int port, 915 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db) 916 { 917 struct alu_struct alu; 918 int index; 919 920 for (index = 0; index < dev->info->num_statics; index++) { 921 if (!ksz8_r_sta_mac_table(dev, index, &alu)) { 922 /* Found one already in static MAC table. */ 923 if (!memcmp(alu.mac, mdb->addr, ETH_ALEN) && 924 alu.fid == mdb->vid) 925 break; 926 } 927 } 928 929 /* no available entry */ 930 if (index == dev->info->num_statics) 931 goto exit; 932 933 /* clear port */ 934 alu.port_forward &= ~BIT(port); 935 if (!alu.port_forward) 936 alu.is_static = false; 937 ksz8_w_sta_mac_table(dev, index, &alu); 938 939 exit: 940 return 0; 941 } 942 943 int ksz8_port_vlan_filtering(struct ksz_device *dev, int port, bool flag, 944 struct netlink_ext_ack *extack) 945 { 946 if (ksz_is_ksz88x3(dev)) 947 return -ENOTSUPP; 948 949 /* Discard packets with VID not enabled on the switch */ 950 ksz_cfg(dev, S_MIRROR_CTRL, SW_VLAN_ENABLE, flag); 951 952 /* Discard packets with VID not enabled on the ingress port */ 953 for (port = 0; port < dev->phy_port_cnt; ++port) 954 ksz_port_cfg(dev, port, REG_PORT_CTRL_2, PORT_INGRESS_FILTER, 955 flag); 956 957 return 0; 958 } 959 960 static void ksz8_port_enable_pvid(struct ksz_device *dev, int port, bool state) 961 { 962 if (ksz_is_ksz88x3(dev)) { 963 ksz_cfg(dev, REG_SW_INSERT_SRC_PVID, 964 0x03 << (4 - 2 * port), state); 965 } else { 966 ksz_pwrite8(dev, port, REG_PORT_CTRL_12, state ? 0x0f : 0x00); 967 } 968 } 969 970 int ksz8_port_vlan_add(struct ksz_device *dev, int port, 971 const struct switchdev_obj_port_vlan *vlan, 972 struct netlink_ext_ack *extack) 973 { 974 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 975 struct ksz_port *p = &dev->ports[port]; 976 u16 data, new_pvid = 0; 977 u8 fid, member, valid; 978 979 if (ksz_is_ksz88x3(dev)) 980 return -ENOTSUPP; 981 982 /* If a VLAN is added with untagged flag different from the 983 * port's Remove Tag flag, we need to change the latter. 984 * Ignore VID 0, which is always untagged. 985 * Ignore CPU port, which will always be tagged. 986 */ 987 if (untagged != p->remove_tag && vlan->vid != 0 && 988 port != dev->cpu_port) { 989 unsigned int vid; 990 991 /* Reject attempts to add a VLAN that requires the 992 * Remove Tag flag to be changed, unless there are no 993 * other VLANs currently configured. 994 */ 995 for (vid = 1; vid < dev->info->num_vlans; ++vid) { 996 /* Skip the VID we are going to add or reconfigure */ 997 if (vid == vlan->vid) 998 continue; 999 1000 ksz8_from_vlan(dev, dev->vlan_cache[vid].table[0], 1001 &fid, &member, &valid); 1002 if (valid && (member & BIT(port))) 1003 return -EINVAL; 1004 } 1005 1006 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged); 1007 p->remove_tag = untagged; 1008 } 1009 1010 ksz8_r_vlan_table(dev, vlan->vid, &data); 1011 ksz8_from_vlan(dev, data, &fid, &member, &valid); 1012 1013 /* First time to setup the VLAN entry. */ 1014 if (!valid) { 1015 /* Need to find a way to map VID to FID. */ 1016 fid = 1; 1017 valid = 1; 1018 } 1019 member |= BIT(port); 1020 1021 ksz8_to_vlan(dev, fid, member, valid, &data); 1022 ksz8_w_vlan_table(dev, vlan->vid, data); 1023 1024 /* change PVID */ 1025 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 1026 new_pvid = vlan->vid; 1027 1028 if (new_pvid) { 1029 u16 vid; 1030 1031 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &vid); 1032 vid &= ~VLAN_VID_MASK; 1033 vid |= new_pvid; 1034 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, vid); 1035 1036 ksz8_port_enable_pvid(dev, port, true); 1037 } 1038 1039 return 0; 1040 } 1041 1042 int ksz8_port_vlan_del(struct ksz_device *dev, int port, 1043 const struct switchdev_obj_port_vlan *vlan) 1044 { 1045 u16 data, pvid; 1046 u8 fid, member, valid; 1047 1048 if (ksz_is_ksz88x3(dev)) 1049 return -ENOTSUPP; 1050 1051 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid); 1052 pvid = pvid & 0xFFF; 1053 1054 ksz8_r_vlan_table(dev, vlan->vid, &data); 1055 ksz8_from_vlan(dev, data, &fid, &member, &valid); 1056 1057 member &= ~BIT(port); 1058 1059 /* Invalidate the entry if no more member. */ 1060 if (!member) { 1061 fid = 0; 1062 valid = 0; 1063 } 1064 1065 ksz8_to_vlan(dev, fid, member, valid, &data); 1066 ksz8_w_vlan_table(dev, vlan->vid, data); 1067 1068 if (pvid == vlan->vid) 1069 ksz8_port_enable_pvid(dev, port, false); 1070 1071 return 0; 1072 } 1073 1074 int ksz8_port_mirror_add(struct ksz_device *dev, int port, 1075 struct dsa_mall_mirror_tc_entry *mirror, 1076 bool ingress, struct netlink_ext_ack *extack) 1077 { 1078 if (ingress) { 1079 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 1080 dev->mirror_rx |= BIT(port); 1081 } else { 1082 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 1083 dev->mirror_tx |= BIT(port); 1084 } 1085 1086 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false); 1087 1088 /* configure mirror port */ 1089 if (dev->mirror_rx || dev->mirror_tx) 1090 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1091 PORT_MIRROR_SNIFFER, true); 1092 1093 return 0; 1094 } 1095 1096 void ksz8_port_mirror_del(struct ksz_device *dev, int port, 1097 struct dsa_mall_mirror_tc_entry *mirror) 1098 { 1099 u8 data; 1100 1101 if (mirror->ingress) { 1102 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 1103 dev->mirror_rx &= ~BIT(port); 1104 } else { 1105 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 1106 dev->mirror_tx &= ~BIT(port); 1107 } 1108 1109 ksz_pread8(dev, port, P_MIRROR_CTRL, &data); 1110 1111 if (!dev->mirror_rx && !dev->mirror_tx) 1112 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1113 PORT_MIRROR_SNIFFER, false); 1114 } 1115 1116 static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port) 1117 { 1118 struct ksz_port *p = &dev->ports[port]; 1119 u8 data8; 1120 1121 if (!p->interface && dev->compat_interface) { 1122 dev_warn(dev->dev, 1123 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 1124 "Please update your device tree.\n", 1125 port); 1126 p->interface = dev->compat_interface; 1127 } 1128 1129 /* Configure MII interface for proper network communication. */ 1130 ksz_read8(dev, REG_PORT_5_CTRL_6, &data8); 1131 data8 &= ~PORT_INTERFACE_TYPE; 1132 data8 &= ~PORT_GMII_1GPS_MODE; 1133 switch (p->interface) { 1134 case PHY_INTERFACE_MODE_MII: 1135 p->phydev.speed = SPEED_100; 1136 break; 1137 case PHY_INTERFACE_MODE_RMII: 1138 data8 |= PORT_INTERFACE_RMII; 1139 p->phydev.speed = SPEED_100; 1140 break; 1141 case PHY_INTERFACE_MODE_GMII: 1142 data8 |= PORT_GMII_1GPS_MODE; 1143 data8 |= PORT_INTERFACE_GMII; 1144 p->phydev.speed = SPEED_1000; 1145 break; 1146 default: 1147 data8 &= ~PORT_RGMII_ID_IN_ENABLE; 1148 data8 &= ~PORT_RGMII_ID_OUT_ENABLE; 1149 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1150 p->interface == PHY_INTERFACE_MODE_RGMII_RXID) 1151 data8 |= PORT_RGMII_ID_IN_ENABLE; 1152 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1153 p->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1154 data8 |= PORT_RGMII_ID_OUT_ENABLE; 1155 data8 |= PORT_GMII_1GPS_MODE; 1156 data8 |= PORT_INTERFACE_RGMII; 1157 p->phydev.speed = SPEED_1000; 1158 break; 1159 } 1160 ksz_write8(dev, REG_PORT_5_CTRL_6, data8); 1161 p->phydev.duplex = 1; 1162 } 1163 1164 void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1165 { 1166 struct dsa_switch *ds = dev->ds; 1167 const u32 *masks; 1168 u8 member; 1169 1170 masks = dev->info->masks; 1171 1172 /* enable broadcast storm limit */ 1173 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 1174 1175 if (!ksz_is_ksz88x3(dev)) 1176 ksz8795_set_prio_queue(dev, port, 4); 1177 1178 /* disable DiffServ priority */ 1179 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_ENABLE, false); 1180 1181 /* replace priority */ 1182 ksz_port_cfg(dev, port, P_802_1P_CTRL, 1183 masks[PORT_802_1P_REMAPPING], false); 1184 1185 /* enable 802.1p priority */ 1186 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_ENABLE, true); 1187 1188 if (cpu_port) { 1189 if (!ksz_is_ksz88x3(dev)) 1190 ksz8795_cpu_interface_select(dev, port); 1191 1192 member = dsa_user_ports(ds); 1193 } else { 1194 member = BIT(dsa_upstream_port(ds, port)); 1195 } 1196 1197 ksz8_cfg_port_member(dev, port, member); 1198 } 1199 1200 void ksz8_config_cpu_port(struct dsa_switch *ds) 1201 { 1202 struct ksz_device *dev = ds->priv; 1203 struct ksz_port *p; 1204 const u32 *masks; 1205 const u16 *regs; 1206 u8 remote; 1207 int i; 1208 1209 masks = dev->info->masks; 1210 regs = dev->info->regs; 1211 1212 /* Switch marks the maximum frame with extra byte as oversize. */ 1213 ksz_cfg(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, true); 1214 ksz_cfg(dev, regs[S_TAIL_TAG_CTRL], masks[SW_TAIL_TAG_ENABLE], true); 1215 1216 p = &dev->ports[dev->cpu_port]; 1217 p->on = 1; 1218 1219 ksz8_port_setup(dev, dev->cpu_port, true); 1220 1221 for (i = 0; i < dev->phy_port_cnt; i++) { 1222 p = &dev->ports[i]; 1223 1224 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1225 1226 /* Last port may be disabled. */ 1227 if (i == dev->phy_port_cnt) 1228 break; 1229 p->on = 1; 1230 p->phy = 1; 1231 } 1232 for (i = 0; i < dev->phy_port_cnt; i++) { 1233 p = &dev->ports[i]; 1234 if (!p->on) 1235 continue; 1236 if (!ksz_is_ksz88x3(dev)) { 1237 ksz_pread8(dev, i, regs[P_REMOTE_STATUS], &remote); 1238 if (remote & KSZ8_PORT_FIBER_MODE) 1239 p->fiber = 1; 1240 } 1241 if (p->fiber) 1242 ksz_port_cfg(dev, i, regs[P_STP_CTRL], 1243 PORT_FORCE_FLOW_CTRL, true); 1244 else 1245 ksz_port_cfg(dev, i, regs[P_STP_CTRL], 1246 PORT_FORCE_FLOW_CTRL, false); 1247 } 1248 } 1249 1250 static int ksz8_handle_global_errata(struct dsa_switch *ds) 1251 { 1252 struct ksz_device *dev = ds->priv; 1253 int ret = 0; 1254 1255 /* KSZ87xx Errata DS80000687C. 1256 * Module 2: Link drops with some EEE link partners. 1257 * An issue with the EEE next page exchange between the 1258 * KSZ879x/KSZ877x/KSZ876x and some EEE link partners may result in 1259 * the link dropping. 1260 */ 1261 if (dev->info->ksz87xx_eee_link_erratum) 1262 ret = ksz8_ind_write8(dev, TABLE_EEE, REG_IND_EEE_GLOB2_HI, 0); 1263 1264 return ret; 1265 } 1266 1267 int ksz8_enable_stp_addr(struct ksz_device *dev) 1268 { 1269 struct alu_struct alu; 1270 1271 /* Setup STP address for STP operation. */ 1272 memset(&alu, 0, sizeof(alu)); 1273 ether_addr_copy(alu.mac, eth_stp_addr); 1274 alu.is_static = true; 1275 alu.is_override = true; 1276 alu.port_forward = dev->info->cpu_ports; 1277 1278 ksz8_w_sta_mac_table(dev, 0, &alu); 1279 1280 return 0; 1281 } 1282 1283 int ksz8_setup(struct dsa_switch *ds) 1284 { 1285 struct ksz_device *dev = ds->priv; 1286 int i; 1287 1288 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_FLOW_CTRL, true); 1289 1290 /* Enable automatic fast aging when link changed detected. */ 1291 ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true); 1292 1293 /* Enable aggressive back off algorithm in half duplex mode. */ 1294 regmap_update_bits(dev->regmap[0], REG_SW_CTRL_1, 1295 SW_AGGR_BACKOFF, SW_AGGR_BACKOFF); 1296 1297 /* 1298 * Make sure unicast VLAN boundary is set as default and 1299 * enable no excessive collision drop. 1300 */ 1301 regmap_update_bits(dev->regmap[0], REG_SW_CTRL_2, 1302 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP, 1303 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP); 1304 1305 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false); 1306 1307 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 1308 1309 if (!ksz_is_ksz88x3(dev)) 1310 ksz_cfg(dev, REG_SW_CTRL_19, SW_INS_TAG_ENABLE, true); 1311 1312 for (i = 0; i < (dev->info->num_vlans / 4); i++) 1313 ksz8_r_vlan_entries(dev, i); 1314 1315 return ksz8_handle_global_errata(ds); 1316 } 1317 1318 void ksz8_get_caps(struct ksz_device *dev, int port, 1319 struct phylink_config *config) 1320 { 1321 config->mac_capabilities = MAC_10 | MAC_100; 1322 1323 /* Silicon Errata Sheet (DS80000830A): 1324 * "Port 1 does not respond to received flow control PAUSE frames" 1325 * So, disable Pause support on "Port 1" (port == 0) for all ksz88x3 1326 * switches. 1327 */ 1328 if (!ksz_is_ksz88x3(dev) || port) 1329 config->mac_capabilities |= MAC_SYM_PAUSE; 1330 1331 /* Asym pause is not supported on KSZ8863 and KSZ8873 */ 1332 if (!ksz_is_ksz88x3(dev)) 1333 config->mac_capabilities |= MAC_ASYM_PAUSE; 1334 } 1335 1336 u32 ksz8_get_port_addr(int port, int offset) 1337 { 1338 return PORT_CTRL_ADDR(port, offset); 1339 } 1340 1341 int ksz8_switch_init(struct ksz_device *dev) 1342 { 1343 dev->cpu_port = fls(dev->info->cpu_ports) - 1; 1344 dev->phy_port_cnt = dev->info->port_cnt - 1; 1345 dev->port_mask = (BIT(dev->phy_port_cnt) - 1) | dev->info->cpu_ports; 1346 1347 /* We rely on software untagging on the CPU port, so that we 1348 * can support both tagged and untagged VLANs 1349 */ 1350 dev->ds->untag_bridge_pvid = true; 1351 1352 /* VLAN filtering is partly controlled by the global VLAN 1353 * Enable flag 1354 */ 1355 dev->ds->vlan_filtering_is_global = true; 1356 1357 return 0; 1358 } 1359 1360 void ksz8_switch_exit(struct ksz_device *dev) 1361 { 1362 ksz8_reset_switch(dev); 1363 } 1364 1365 MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>"); 1366 MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch DSA Driver"); 1367 MODULE_LICENSE("GPL"); 1368